Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date         : Wed Jul 15 02:37:33 2026
| Host         : 685a421e500f running 64-bit unknown
| Command      : report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
| Design       : fpga_top
| Device       : xc7a100t
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Control Set Information

Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Total control sets                                       |    80 |
|    Minimum number of control sets                        |    80 |
|    Addition due to synthesis replication                 |     0 |
|    Addition due to physical synthesis replication        |     0 |
| Unused register locations in slices containing registers |   110 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions


2. Histogram
------------

+--------------------+-------+
|       Fanout       | Count |
+--------------------+-------+
| Total control sets |    80 |
| >= 0 to < 4        |     2 |
| >= 4 to < 6        |     8 |
| >= 6 to < 8        |     2 |
| >= 8 to < 10       |     8 |
| >= 10 to < 12      |     5 |
| >= 12 to < 14      |     3 |
| >= 14 to < 16      |     0 |
| >= 16              |    52 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design


3. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |               9 |            6 |
| No           | No                    | Yes                    |              21 |           14 |
| No           | Yes                   | No                     |             148 |           66 |
| Yes          | No                    | No                     |             732 |          307 |
| Yes          | No                    | Yes                    |             260 |           76 |
| Yes          | Yes                   | No                     |             480 |          140 |
+--------------+-----------------------+------------------------+-----------------+--------------+


4. Detailed Control Set Information
-----------------------------------

+----------------+-------------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+
|  Clock Signal  |                              Enable Signal                              |                       Set/Reset Signal                       | Slice Load Count | Bel Load Count | Bels / Slice |
+----------------+-------------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+
|  clk_IBUF_BUFG |                                                                         |                                                              |                1 |              1 |         1.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                        | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_1_n_0             |                1 |              1 |         1.00 |
|  clk_core      | ptop/kronos_core_inst/u_id/u_hcu/core_reset_reg                         | ptop/kronos_core_inst/u_if/fetch_reg[ir][6]_0                |                1 |              4 |         4.00 |
|  clk_o_BUFG    | ResetBootSystem/counter                                                 |                                                              |                2 |              4 |         2.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_tx/E[0]                                   |                                                              |                1 |              4 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_rx/next_bit                               | ptop/u_Controller/Uart/i_uart_rx/bit_counter[3]_i_1__0_n_0   |                1 |              4 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_2__0_n_0              | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_1_n_0      |                1 |              4 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/return_state                              | ResetBootSystem/rst_o_reg_0                                  |                3 |              5 |         1.67 |
|  clk_core      | ptop/u_Controller/Interpreter/core_reset_reg_0[0]                       |                                                              |                2 |              5 |         2.50 |
|  clk_core      | ptop/kronos_core_inst/u_id/E[0]                                         |                                                              |                3 |              5 |         1.67 |
|  clk_core      | ptop/kronos_core_inst/u_ex/u_csr/FSM_onehot_state_reg[2]_0[0]           | ptop/u_Controller/Interpreter/rst_core                       |                2 |              7 |         3.50 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_tx/data_to_send[6]_i_1_n_0                | ResetBootSystem/rst_o_reg_0                                  |                2 |              7 |         3.50 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_rx/E[0]                                   | ResetBootSystem/rst_o_reg_0                                  |                2 |              8 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/uart_tx_en                                       | ResetBootSystem/rst_o_reg_0                                  |                1 |              8 |         8.00 |
|  clk_o_BUFG    |                                                                         |                                                              |                5 |              8 |         1.60 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_rx/recieved_data0                         | ptop/u_Controller/Uart/i_uart_rx/recieved_data[7]_i_1_n_0    |                2 |              8 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_rx/uart_rx_data[7]_i_1_n_0                | ResetBootSystem/rst_o_reg_0                                  |                2 |              8 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/counter                                   | ResetBootSystem/rst_o_reg_0                                  |                2 |              8 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/accumulator[7]_i_1_n_0                    | ResetBootSystem/rst_o_reg_0                                  |                2 |              8 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/tx_fifo/FSM_sequential_state_write_reg[2][0]     | ResetBootSystem/rst_o_reg_0                                  |                1 |              8 |         8.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                        | ResetBootSystem/SR[0]                                        |                3 |             10 |         3.33 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/i_uart_rx/cycle_counter0                         | ptop/u_Controller/Uart/i_uart_rx/cycle_counter[9]_i_1__0_n_0 |                3 |             10 |         3.33 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/tx_fifo/read_ptr[2]_i_1_n_0                      | ResetBootSystem/rst_o_reg_0                                  |                3 |             11 |         3.67 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/rx_fifo/read_ptr0                                | ResetBootSystem/rst_o_reg_0                                  |                3 |             11 |         3.67 |
|  clk_core      | ptop/u_Controller/Interpreter/E[0]                                      | ptop/kronos_core_inst/u_if/u_rf/immediate[11]_i_1_n_0        |                2 |             11 |         5.50 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/tx_fifo/memory_reg_0_7_0_5_i_1_n_0               |                                                              |                2 |             12 |         6.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/address[31]_i_1_n_0                       |                                                              |                6 |             12 |         2.00 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/rx_fifo/memory_reg_0_7_0_5_i_1__0_n_0            |                                                              |                2 |             12 |         6.00 |
|  clk_core      |                                                                         | ptop/u_Controller/Interpreter/rst_core                       |               14 |             21 |         1.50 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/num_of_cycles_to_pulse[23]_i_1_n_0        |                                                              |                9 |             24 |         2.67 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/memory_page_number[23]_i_2_n_0            | ptop/u_Controller/Interpreter/memory_page_number[23]_i_1_n_0 |                7 |             24 |         3.43 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/accumulator0                              | ResetBootSystem/rst_o_reg_0                                  |                4 |             24 |         6.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/num_of_pages                              | ResetBootSystem/rst_o_reg_0                                  |                6 |             24 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/timeout                                   | ResetBootSystem/rst_o_reg_0                                  |               10 |             24 |         2.40 |
|  clk_core      | ptop/kronos_core_inst/u_id/E[0]                                         | ptop/kronos_core_inst/u_ex/u_csr/mcause[30]_i_1_n_0          |                9 |             27 |         3.00 |
|  clk_core      | ptop/kronos_core_inst/u_ex/u_csr/trap_handle[31]_i_1_n_0                |                                                              |                9 |             30 |         3.33 |
|  clk_core      | ptop/kronos_core_inst/u_id/core_reset_reg_1[0]                          |                                                              |               14 |             30 |         2.14 |
|  clk_core      | ptop/kronos_core_inst/u_id/decode_reg[ir][20]_2[0]                      | ptop/u_Controller/Interpreter/rst_core                       |               10 |             30 |         3.00 |
|  clk_core      | ptop/kronos_core_inst/u_id/u_hcu/core_reset_reg                         | ptop/kronos_core_inst/u_if/fetch_reg[ir][3]_1                |               17 |             31 |         1.82 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/tx_fifo/E[0]                                     | ResetBootSystem/rst_o_reg_0                                  |                7 |             32 |         4.57 |
|  clk_o_BUFG    | ptop/u_Controller/Uart/rx_fifo/E[0]                                     | ResetBootSystem/rst_o_reg_0                                  |                5 |             32 |         6.40 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/timeout_counter                           | ResetBootSystem/rst_o_reg_0                                  |                6 |             32 |         5.33 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/communication_write_data[31]_i_1_n_0      |                                                              |               11 |             32 |         2.91 |
|  clk_o_BUFG    | ptop/u_Controller/ClkDivider/pulse_counter[0]_i_1_n_0                   | ResetBootSystem/rst_o_reg_0                                  |                8 |             32 |         4.00 |
|  clk_core      | ptop/kronos_core_inst/u_id/core_reset_reg_0[0]                          |                                                              |               15 |             32 |         2.13 |
|  clk_core      | ptop/kronos_core_inst/u_id/u_hcu/FSM_sequential_state_reg[0][0]         |                                                              |                9 |             32 |         3.56 |
|  clk_core      | ptop/kronos_core_inst/u_id/incr_high_reg                                | ptop/u_Controller/Interpreter/rst_core                       |                8 |             32 |         4.00 |
|  clk_core      | ptop/kronos_core_inst/u_id/sel                                          | ptop/u_Controller/Interpreter/rst_core                       |                8 |             32 |         4.00 |
|  clk_core      | ptop/kronos_core_inst/u_id/decode_reg[ir][27]_1[0]                      |                                                              |               12 |             32 |         2.67 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/read_buffer                               | ResetBootSystem/rst_o_reg_0                                  |               19 |             32 |         1.68 |
|  clk_core      | ptop/kronos_core_inst/u_id/u_hcu/decode_reg[regwr_alu]_0[0]             |                                                              |               28 |             32 |         1.14 |
|  clk_core      | ptop/kronos_core_inst/u_ex/u_csr/u_hpmcounter1/count_low[0]_i_1__0_n_0  | ptop/u_Controller/Interpreter/rst_core                       |                8 |             32 |         4.00 |
|  clk_core      | ptop/kronos_core_inst/u_ex/u_csr/u_hpmcounter0/count_high[0]_i_1__0_n_0 | ptop/u_Controller/Interpreter/rst_core                       |                8 |             32 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/communication_buffer[31]_i_1_n_0          | ResetBootSystem/rst_o_reg_0                                  |                7 |             32 |         4.57 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/write_data[31]_i_1_n_0                    |                                                              |               18 |             32 |         1.78 |
|  clk_core      | ptop/kronos_core_inst/u_if/u_rf/regrd_rs2[31]_i_1_n_0                   |                                                              |               14 |             32 |         2.29 |
|  clk_core      | ptop/kronos_core_inst/u_if/u_rf/regrd_rs1[31]_i_1_n_0                   |                                                              |               18 |             32 |         1.78 |
|  clk_core      | ptop/kronos_core_inst/u_ex/u_csr/u_hpmcounter1/E[0]                     |                                                              |               22 |             32 |         1.45 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/end_position[31]_i_1_n_0                  | ResetBootSystem/rst_o_reg_0                                  |                8 |             32 |         4.00 |
|  clk_core      | ptop/u_Controller/Interpreter/E[0]                                      |                                                              |               10 |             33 |         3.30 |
|  clk_core      | ptop/kronos_core_inst/u_id/FSM_onehot_state_reg[1]                      |                                                              |               16 |             36 |         2.25 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/num_of_positions[23]_i_1_n_0              |                                                              |               12 |             55 |         4.58 |
|  clk_core      | ptop/kronos_core_inst/u_if/pc                                           | ptop/u_Controller/Interpreter/rst_core                       |               24 |             63 |         2.62 |
|  clk_core      | ptop/kronos_core_inst/u_id/u_hcu/instr_ack_reg[0]                       |                                                              |               29 |             64 |         2.21 |
|  clk_o_BUFG    |                                                                         | ptop/instr_data[31]_i_1_n_0                                  |               32 |             64 |         2.00 |
|  clk_o_BUFG    |                                                                         | ResetBootSystem/rst_o_reg_0                                  |               34 |             84 |         2.47 |
|  clk_core      | ptop/kronos_core_inst/u_ex/regwr_en                                     |                                                              |               11 |             88 |         8.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/address_reg[31]_7                         |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/address_reg[11]_1                         |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/decode_reg[addr][10]                      |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/address_reg[10]_0                         |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/decode_reg[addr][10]_0                    |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/address_reg[31]_0                         |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/address_reg[31]_1                         |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/address_reg[31]_2                         |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/address_reg[31]_3                         |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/address_reg[31]_4                         |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/address_reg[31]_5                         |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG    | ptop/u_Controller/Interpreter/address_reg[31]_6                         |                                                              |               32 |            128 |         4.00 |
|  clk_core      | ptop/kronos_core_inst/u_id/u_hcu/core_reset_reg                         |                                                              |               47 |            142 |         3.02 |
+----------------+-------------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+


