DIRCjl<&jl<&!V@oQM8~ 0~~əLICENSEjl<&jl<&!VirIm /+VeXTProject/Components/ALU.vhdjl<&jl<&!VJ:Sa.խ(w9!Project/Components/EX_MEM_DIV.vhdjl<&jl<&!V#Mn*u>U}] Project/Components/ID_EX_DIV.vhdjl<&jl<&!V_,< =/8!ϼ Project/Components/IF_ID_DIV.vhdjl<&jl<&!V 6 JmJ.c!Project/Components/MEM_WB_DIV.vhdjl<&jl<&!VkLh+} ӱ XProject/Components/adder.vhdjl<V0jl<V0!VO8W-M;Z~P΅ԏ W!Project/Components/controller.vhdjl<V0jl<V0!VA/ ? HHProject/Components/datamem.vhdjl<V0jl<V0!V&;V zuOlm((Project/Components/datamem_interface.vhdjl<V0jl<V0!V(wXHG#S<Project/Components/datapath.vhdjl<V0jl<V0!Vw",.G:,1$Project/Components/flushing_unit.vhdjl<V0jl<V0!V 8+qX_kjLNJ./L&Project/Components/forwarding_unit.vhdjl<V0jl<V0!V9p0b 1|/ͯ^'Project/Components/jump_target_unit.vhdjl<V0jl<V0!V9Gms"ֺ\&Project/Components/microcontroller.vhdjl<V0jl<V0!Vb(G~y}ፈNProject/Components/mux_2_1.vhdjl<V0jl<V0!V2?=*>4O؛Project/Components/mux_32_1.vhdjl<V0jl<V0!VY 6kظ ? Project/Components/mux_3_1.vhdjl<V0jl<V0!V7n$z~ЮOProject/Components/mux_5_1.vhdjl<V0jl<V0!V>/ftʤp(Project/Components/progmem_interface.vhdjl<V0jl<V0!V =*%_ǐ'&Project/Components/program_counter.vhdjl<V0jl<V0!V=$:M~ ~D#-6JProject/Components/reg1b.vhdjl<V0jl<V0!VxfRRJ~>g7o!Project/Components/reg2b.vhdjl<V0jl<V0!VoKa>z? g Project/Components/reg32b.vhdjl<V0jl<V0!V'b 4V }WTd*Project/Components/reg32b_falling_edge.vhdjl<V0jl<V0!Vz_q=›{#*T4Project/Components/reg3b.vhdjl<V0jl<V0!V|w*`[Q-5.*Project/Components/reg4b.vhdjl<V0jl<V0!V~'7Ǟ.vZ%Project/Components/reg5b.vhdjl<V0jl<V0!V'_8T`<d{\$Project/Components/register_file.vhdjl<V0jl<V0!V!N2=z_eZ4Quartus/riscv_microcontroller/db/altsyncram_0ed1.tdfjl<V0jl<V0!V] xi&!3EC4Quartus/riscv_microcontroller/db/altsyncram_11h1.tdfjl<V0jl<V0!VqPͲU` Ǽ&ɂ׮4Quartus/riscv_microcontroller/db/altsyncram_3de1.tdfjl<V0jl<V0!V 76D8su4Quartus/riscv_microcontroller/db/altsyncram_5gs3.tdfjl<V0jl<V0!Vf d;y"u1־#4Quartus/riscv_microcontroller/db/altsyncram_66s3.tdfjl<V0jl<V0!V0[KUC-^o 4Quartus/riscv_microcontroller/db/altsyncram_a4d1.tdfjl<V0jl<V0!V'N~*..C㺔4Quartus/riscv_microcontroller/db/altsyncram_b2f1.tdfjl<V0jl<V0!Vt.#}Gμ4Quartus/riscv_microcontroller/db/altsyncram_d9h1.tdfjl<V0jl<V0!V(QCѤS$`@.9'4Quartus/riscv_microcontroller/db/altsyncram_mbe1.tdfjl<V0jl<V0!Vy x qdHbLVYML4Quartus/riscv_microcontroller/db/altsyncram_oig1.tdfjl<V0jl<V0!V }Q;Z}LI/Quartus/riscv_microcontroller/db/decode_eca.tdfjl<V0jl<V0!V v ۇLI /Quartus/riscv_microcontroller/db/decode_l0b.tdfjl<V0jl<V0!W⛲CK)wZS9Quartus/riscv_microcontroller/db/logic_util_heursitic.datjl<V0jl<V0!W'^1JQ"Tt,Quartus/riscv_microcontroller/db/mux_5rb.tdfjl<V0jl<V0!W jgzއ9*t,Quartus/riscv_microcontroller/db/mux_isb.tdfjl<:Ljl<:L!WZuh썁HnKHRjDQuartus/riscv_microcontroller/db/prev_cmp_riscv_microcontroller.qmsgjl<:Ljl<:L!W 2(vc$>Quartus/riscv_microcontroller/db/riscv_microcontroller.db_infojl<:Ljl<:L!W#Pw~ăKQuartus/riscv_microcontroller/db/riscv_microcontroller.sld_design_entry.scijl<:Ljl<:L!W{$ 0HwJQuartus/riscv_microcontroller/db/riscv_microcontroller_partition_pins.jsonjl<:Ljl<:L!WM^Y0MpqN6Quartus/riscv_microcontroller/greybox_tmp/cbx_args.txtjl<:Ljl<:L!W/BR:sRy1qY&rX1Quartus/riscv_microcontroller/microcontroller.vwfjl<:Ljl<:L!WȜ܉CX郙q`k6Quartus/riscv_microcontroller/microcontroller.vwf.tempjl<:Ljl<:L!W7s:.e@ ݍ)Quartus/riscv_microcontroller/progmem.cmpjl<:Ljl<:L![b%zwE0&R|gs2)Quartus/riscv_microcontroller/progmem.mifjl<:Ljl<:L!\~]h ۠Wk)Quartus/riscv_microcontroller/progmem.qipjl<:Ljl<:L!]T^?lw[/Sc o)Quartus/riscv_microcontroller/progmem.vhdjl<tpjl<tp!^3ǀ\ap9\Zs~7Quartus/riscv_microcontroller/riscv_microcontroller.pngjl<tpjl<tp!^v B@zK۩7Quartus/riscv_microcontroller/riscv_microcontroller.qpfjl<tpjl<tp!^emWkHk7Quartus/riscv_microcontroller/riscv_microcontroller.qsfjl<tpjl<tp!bR߃85W·*&7Quartus/riscv_microcontroller/riscv_microcontroller.qwsjl<tpjl<tp!b ׮c?}1+,|;KQuartus/riscv_microcontroller/riscv_microcontroller_assignment_defaults.qdfjl<tpjl<tp!b!gB \v{8˼MQuartus/riscv_microcontroller/riscv_microcontroller_nativelink_simulation.rptjl<tpjl<tp!b(;"ƐcOi4 4HQuartus/riscv_microcontroller/simulation/modelsim/microcontroller.vwf.dojl<tpjl<tp!b)1g#>0<9HQuartus/riscv_microcontroller/simulation/modelsim/microcontroller.vwf.vtjl<tpjl<tp!b**7)H I>my5?Ȓ>Quartus/riscv_microcontroller/simulation/modelsim/modelsim.inijl<tpjl<tp!b+>hoi \g.g,aAQuartus/riscv_microcontroller/simulation/modelsim/msim_transcriptjl<tpjl<tp!b,+ qڧliJQuartus/riscv_microcontroller/simulation/modelsim/riscv_microcontroller.vojl<3jl<3!b/@M7ޭim4r Kn [Quartus/riscv_microcontroller/simulation/modelsim/riscv_microcontroller_7_1200mv_0c_slow.vojl<2jl<2!b0$b&#XG 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C1\i柈aQuartus/riscv_microcontroller/simulation/modelsim/riscv_microcontroller_run_msim_rtl_vhdl.do.bak1jl< jl< !bH[Q0 C1\i柈aQuartus/riscv_microcontroller/simulation/modelsim/riscv_microcontroller_run_msim_rtl_vhdl.do.bak2jl< jl< !bQGs6&+yE<aQuartus/riscv_microcontroller/simulation/modelsim/riscv_microcontroller_run_msim_rtl_vhdl.do.bak3jl< jjl< j!bS$o>d:Ǥڶ>oNMQuartus/riscv_microcontroller/simulation/modelsim/riscv_microcontroller_v.sdojl< jjl< j!bUsqؓ?v]'-f$@Quartus/riscv_microcontroller/simulation/modelsim/rtl_work/_infojl< jjl< j!b[/~r?ޠYR^]AQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/_vmakejl< jjl< j!b`]xyIxEOQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/datamem/_primary.datjl< jjl< j!bc6Xa]qHcnd[HOQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/datamem/_primary.dbsjl< jjl< j!bdT܁D]OJQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/datamem/syn.datjl< jjl< j!be#l499ASք5%JQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/datamem/syn.dbsjl< jjl< j!bg^Et-3?zJQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/datamem/syn.prwjl< jjl< j!bi"BEʖz1w񯒹XJQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/datamem/syn.psmjl< jjl< j!bk;,JU'kO I$eQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/microcontroller_vlg_check_tst/_primary.datjl< jjl< j!blIPm WX&eQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/microcontroller_vlg_check_tst/_primary.dbsjl< jjl< j!bmcK "gwxeQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/microcontroller_vlg_check_tst/_primary.vhdjl< Wjl< W!bn>#gܰ-R$(dQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/microcontroller_vlg_check_tst/verilog.prwjl< jl< !bo+8[e`,-!dQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/microcontroller_vlg_check_tst/verilog.psmjl< jl< !bq&)ا2C<fQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/microcontroller_vlg_sample_tst/_primary.datjl< jl< !br[ ,+_&WfQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/microcontroller_vlg_sample_tst/_primary.dbsjl< jl< !bt w24zc•p]fQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/microcontroller_vlg_sample_tst/_primary.vhdjl< jl< !bvXoǮ!Ҥ$ f|aeQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/microcontroller_vlg_sample_tst/verilog.prwjl< jl< !bw07Aa3 **'&,U aeQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/microcontroller_vlg_sample_tst/verilog.psmjl< jl< !b{ J ݑ-I.Y1 cQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/microcontroller_vlg_vec_tst/_primary.datjl< jl< !b|R48zߟu[: K)cQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/microcontroller_vlg_vec_tst/_primary.dbsjl< jl< !b~rX8?U41\cQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/microcontroller_vlg_vec_tst/_primary.vhdjl< jl< !bÕU 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`m1%BPQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/reg1b/description.datjl< jl< !bCPL SȓnPQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/reg1b/description.dbsjl< jl< !b viny |PQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/reg1b/description.prwjl< jl< !bxI@A, &G-[PQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/reg1b/description.psmjl< jl< !b X8 8Hi{^Quartus/riscv_microcontroller/simulation/modelsim/rtl_work/reg32b_falling_edge/description.prwjl< jl< !b8yV\?T7,XK%^Quartus/riscv_microcontroller/simulation/modelsim/rtl_work/reg32b_falling_edge/description.psmjl< jl< !bsRwqB40yβMQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/reg3b/_primary.datjl< jl< !b/2R]*=S~GMQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/reg3b/_primary.dbsjl< jl< !bj1 T4twPQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/reg3b/description.datjl< jl< !bn%t㈅Н5{b7PQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/reg3b/description.dbsjl< jl< !b5GJ$em=W4(PQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/reg3b/description.prwjl< jl< !b8#T]؁ƈ~PQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/reg3b/description.psmjl< jl< !b8ēUz?GMQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/reg4b/_primary.datjl< jl< !b=bKo'?3n8MQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/reg4b/_primary.dbsjl< jl< !bk`+ἅ+X"ř683PQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/reg4b/description.datjl< jl< !b!Y99M3$uTPQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/reg4b/description.dbsjl< jl< !b5tA{#~ZT(fakPQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/reg4b/description.prwjl< jl< !bH}zOw/TMu HIoPQuartus/riscv_microcontroller/simulation/modelsim/rtl_work/reg4b/description.psmjl< jl< !bj:#۬ zNEuE;Quartus/riscv_microcontroller/simulation/modelsim/tcc/_infojl< jl< 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