Determining the location of the ModelSim executable...

Using: D:\Programs\Altera\Quartus\modelsim_ase\win32aloem

To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options
Note: if both ModelSim-Altera and ModelSim executables are available, ModelSim-Altera will be used.

**** Generating the ModelSim Testbench ****

quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off riscv_microcontroller -c riscv_microcontroller --vector_source="E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Quartus/riscv_microcontroller/microcontroller.vwf" --testbench_file="E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Quartus/riscv_microcontroller/simulation/qsim/microcontroller.vwf.vht"

Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
    Info: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
    Info: Copyright (C) 2018  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Wed Aug 14 17:17:42 2019
Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off riscv_microcontroller -c riscv_microcontroller --vector_source="E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Quartus/riscv_microcontroller/microcontroller.vwf" --testbench_file="E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Quartus/riscv_microcontroller/simulation/qsim/microcontroller.vwf.vht"
Info (119004): Automatically selected device EP4CGX150CF23C7 for design riscv_microcontroller
Info (119005): Fitting design with smaller device may be possible, but smaller device must be specified
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.

ut_1_ID_EX[12]" in vector source file when writing test bench files

Completed successfully. 

**** Generating the functional simulation netlist ****

quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Quartus/riscv_microcontroller/simulation/qsim/" riscv_microcontroller -c riscv_microcontroller

Info: *******************************************************************
Info: Running Quartus Prime EDA Netlist Writer
    Info: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
    Info: Copyright (C) 2018  Intel Corporation. All rights reserved.
    Info: Your use of Intel Corporation's design tools, logic functions 
    Info: and other software and tools, and its AMPP partner logic 
    Info: functions, and any output files from any of the foregoing 
    Info: (including device programming or simulation files), and any 
    Info: associated documentation or information are expressly subject 
    Info: to the terms and conditions of the Intel Program License 
    Info: Subscription Agreement, the Intel Quartus Prime License Agreement,
    Info: the Intel FPGA IP License Agreement, or other applicable license
    Info: agreement, including, without limitation, that your use is for
    Info: the sole purpose of programming logic devices manufactured by
    Info: Intel and sold by Intel or its authorized distributors.  Please
    Info: refer to the applicable agreement for further details.
    Info: Processing started: Wed Aug 14 17:17:44 2019
Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Quartus/riscv_microcontroller/simulation/qsim/" riscv_microcontroller -c riscv_microcontroller
Info (119004): Automatically selected device EP4CGX150CF23C7 for design riscv_microcontroller
Info (119005): Fitting design with smaller device may be possible, but smaller device must be specified
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
Info (204019): Generated file riscv_microcontroller.vho in folder "E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Quartus/riscv_microcontroller/simulation/qsim//" for EDA simulation tool
Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 4751 megabytes
    Info: Processing ended: Wed Aug 14 17:17:46 2019
    Info: Elapsed time: 00:00:02
    Info: Total CPU time (on all processors): 00:00:02

Completed successfully. 

**** Generating the ModelSim .do script ****

E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Quartus/riscv_microcontroller/simulation/qsim/riscv_microcontroller.do generated.

Completed successfully. 

**** Running the ModelSim simulation ****

D:/Programs/Altera/Quartus/modelsim_ase/win32aloem/vsim -c -do riscv_microcontroller.do

Reading D:/Programs/Altera/Quartus/modelsim_ase/tcl/vsim/pref.tcl 

# 10.1d

# do riscv_microcontroller.do 

# ** Warning: (vlib-34) Library already exists at "work".
# 
# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package VITAL_Timing
# -- Loading package VITAL_Primitives
# -- Loading package dffeas_pack
# -- Loading package altera_primitives_components

# -- Loading package cycloneiv_atom_pack
# -- Loading package cycloneiv_components
# -- Compiling entity microcontroller
# -- Compiling architecture structure of microcontroller

# Model Technology ModelSim ALTERA vcom 10.1d Compiler 2012.11 Nov  2 2012
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Compiling entity microcontroller_vhd_vec_tst

# -- Compiling architecture microcontroller_arch of microcontroller_vhd_vec_tst

# vsim -L cycloneiv -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim -c -t 1ps -novopt work.microcontroller_vhd_vec_tst 

# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading work.microcontroller_vhd_vec_tst(microcontroller_arch)
# Loading ieee.vital_timing(body)
# Loading ieee.vital_primitives(body)
# Loading altera.dffeas_pack
# Loading altera.altera_primitives_components
# Loading cycloneiv.cycloneiv_atom_pack(body)
# Loading cycloneiv.cycloneiv_components
# Loading work.microcontroller(structure)

# Loading ieee.std_logic_arith(body)
# Loading cycloneiv.cycloneiv_io_obuf(arch)
# Loading cycloneiv.cycloneiv_io_ibuf(arch)
# Loading altera.dffeas(vital_dffeas)
# Loading cycloneiv.cycloneiv_lcell_comb(vital_lcell_comb)
# Loading cycloneiv.cycloneiv_ram_block(block_arch)
# Loading cycloneiv.cycloneiv_ram_register(reg_arch)
# Loading cycloneiv.cycloneiv_ram_pulse_generator(pgen_arch)

# ** Warning: Design size of 4 instances exceeds ModelSim ALTERA recommended capacity.
# This may because you are loading cell libraries which are not recommended with
# the ModelSim Altera version. Expect performance to be adversely affected.
# after#35

# Simulation time: 0 ps 

# Simulation time: 0 ps 

# Simulation time: 0 ps 

# Simulation time: 0 ps 

# Simulation time: 0 ps 

# Simulation time: 0 ps 

# Simulation time: 0 ps 

# Simulation time: 0 ps 

# Simulation time: 435000 ps 

# Simulation time: 435000 ps 

# Simulation time: 435000 ps 

# Simulation time: 435000 ps 

# Simulation time: 435000 ps 

# Simulation time: 435000 ps 

# Simulation time: 435000 ps 

# Simulation time: 435000 ps 

# Simulation time: 795000 ps 

# Simulation time: 795000 ps 

# Simulation time: 795000 ps 

Completed successfully. 

**** Converting ModelSim VCD to vector waveform ****

Reading E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Quartus/riscv_microcontroller/microcontroller.vwf...

Reading E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Quartus/riscv_microcontroller/simulation/qsim/riscv_microcontroller.msim.vcd...

Processing channel transitions... 

Writing the resulting VWF to E:/Documents-bkp/UFRN/TCC - with debug signals - Copy/Quartus/riscv_microcontroller/simulation/qsim/riscv_microcontroller_20190814171845.sim.vwf

Finished VCD to VWF conversion.

Completed successfully. 

All completed.