# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 13:04:35  April 24, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		riscv_microcontroller_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
#    file is updated automatically by the Quartus II software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone IV GX"
set_global_assignment -name DEVICE AUTO
set_global_assignment -name TOP_LEVEL_ENTITY microcontroller
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:04:35  APRIL 24, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "18.1.0 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS COMMAND_MACRO_MODE -section_id eda_simulation
set_global_assignment -name EDA_SIMULATION_RUN_SCRIPT simulation/modelsim/riscv_microcontroller_run_msim_rtl_vhdl.do -section_id eda_simulation
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "E:/Documents-bkp/UFRN/TCC - with debug signals/Quartus/riscv_microcontroller/microcontroller.vwf"
set_global_assignment -name MIF_FILE progmem.mif
set_global_assignment -name VHDL_FILE ../../Project/Components/datamem.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/mux_5_1.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/jump_target_unit.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/flushing_unit.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/adder.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/reg32b_falling_edge.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/IF_ID_DIV.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/forwarding_unit.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/reg4b.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/reg3b.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/reg2b.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/reg1b.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/MEM_WB_DIV.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/ID_EX_DIV.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/EX_MEM_DIV.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/register_file.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/reg32b.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/program_counter.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/progmem_interface.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/mux_32_1.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/mux_2_1.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/microcontroller.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/datapath.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/datamem_interface.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/controller.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/ALU.vhd
set_global_assignment -name VECTOR_WAVEFORM_FILE microcontroller.vwf
set_global_assignment -name VHDL_FILE ../../Project/Components/mux_3_1.vhd
set_global_assignment -name VHDL_FILE ../../Project/Components/reg5b.vhd
set_global_assignment -name QIP_FILE progmem.qip
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top