Started by timer [Pipeline] Start of Pipeline [Pipeline] node Running on Jenkins in /var/jenkins_home/workspace/mmRISC-1 [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -rf mmRISC-1 [Pipeline] sh + git clone --recursive --depth=1 https://github.com/munetomo-maruyama/mmRISC-1 mmRISC-1 Cloning into 'mmRISC-1'... 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[Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Simulation) [Pipeline] dir Running in /var/jenkins_home/workspace/mmRISC-1/mmRISC-1 [Pipeline] { [Pipeline] echo simulation not supported for mixed VHDL and Verilog files [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Utilities) [Pipeline] dir Running in /var/jenkins_home/workspace/mmRISC-1/mmRISC-1 [Pipeline] { [Pipeline] sh + pwd + python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/mmRISC-1/mmRISC-1 -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels.json WARNING: Error writing to JSON file: [Errno 2] No such file or directory: '/jenkins/processor_ci_utils/labels.json' Trying to read file: /var/jenkins_home/workspace/mmRISC-1/mmRISC-1/fpga/PLL.v Trying to read file: /var/jenkins_home/workspace/mmRISC-1/mmRISC-1/fpga/PLL.v Trying to read file: /var/jenkins_home/workspace/mmRISC-1/mmRISC-1/fpga/PLL_bb.v Trying to read file: /var/jenkins_home/workspace/mmRISC-1/mmRISC-1/fpga/RAM128KB_DP.v [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Build Pipeline) [Pipeline] parallel [Pipeline] { (Branch: colorlight_i9) [Pipeline] { (Branch: digilent_nexys4_ddr) [Pipeline] stage [Pipeline] { (colorlight_i9) [Pipeline] stage [Pipeline] { (digilent_nexys4_ddr) [Pipeline] lock Trying to acquire lock on [Resource: colorlight_i9] Resource [colorlight_i9] did not exist. Created. Lock acquired on [Resource: colorlight_i9] [Pipeline] { [Pipeline] lock Trying to acquire lock on [Resource: digilent_nexys4_ddr] Resource [digilent_nexys4_ddr] did not exist. Created. Lock acquired on [Resource: digilent_nexys4_ddr] [Pipeline] { [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] dir Running in /var/jenkins_home/workspace/mmRISC-1/mmRISC-1 [Pipeline] { [Pipeline] dir Running in /var/jenkins_home/workspace/mmRISC-1/mmRISC-1 [Pipeline] { [Pipeline] echo Starting synthesis for FPGA colorlight_i9. [Pipeline] sh [Pipeline] echo Starting synthesis for FPGA digilent_nexys4_ddr. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p mmRISC-1 -b colorlight_i9 Final configuration file generated at /var/jenkins_home/workspace/mmRISC-1/mmRISC-1/build_colorlight_i9.tcl Error executing Makefile. /var/jenkins_home/workspace/mmRISC-1/mmRISC-1/fpga/PLL_bb.v:35: ERROR: Re-definition of module `\PLL'! make: *** [/eda/processor_ci/makefiles/colorlight_i9.mk:12: colorlight_i9.json] Error 1 Traceback (most recent call last): File "/eda/processor_ci/main.py", line 135, in <module> main( File "/eda/processor_ci/main.py", line 82, in main build(build_file_path, board_name, toolchain_path) File "/eda/processor_ci/core/fpga.py", line 218, in build raise subprocess.CalledProcessError(process.returncode, 'make') subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2. + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p mmRISC-1 -b digilent_nexys4_ddr [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash colorlight_i9) Stage "Flash colorlight_i9" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test colorlight_i9) Stage "Test colorlight_i9" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: colorlight_i9] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } Failed in branch colorlight_i9 Final configuration file generated at /var/jenkins_home/workspace/mmRISC-1/mmRISC-1/build_digilent_nexys4_ddr.tcl Error executing Makefile. ERROR: [Synth 8-9263] cannot open include file 'defines_chip.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/chip/chip_top.v:198] ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/chip/chip_top.v:199] ERROR: [Synth 8-9263] cannot open include file 'defines_chip.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/chip/chip_top_wrap.v:196] ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/chip/chip_top_wrap.v:197] ERROR: [Synth 8-9263] cannot open include file 'defines_chip.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cjtag/cjtag_2_jtag.v:83] ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cjtag/cjtag_2_jtag.v:84] ERROR: [Synth 8-9263] cannot open include file 'defines_chip.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cjtag/cjtag_adapter.v:13] ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cjtag/cjtag_adapter.v:14] ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_csr.v:163] ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_csr_dbg.v:77] ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_csr_int.v:45] ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_datapath.v:13] ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_debug.v:13] ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_fetch.v:123] ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_fpu32.v:79] ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_pipeline.v:75] ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/cpu/cpu_top.v:15] ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/debug/debug_dm.v:94] ERROR: [Synth 8-9263] cannot open include file 'defines_core.v' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/debug/debug_dtm_jtag.v:28] ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:45] ERROR: [Synth 8-2716] syntax error near ''' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:71] ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:59] ERROR: [Synth 8-2716] syntax error near ''' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:91] ERROR: [Synth 8-2716] syntax error near ''' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:92] ERROR: [Synth 8-2716] syntax error near ''' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:97] ERROR: [Synth 8-2716] syntax error near ''' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:101] ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:88] ERROR: [Synth 8-2716] syntax error near ''' [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:142] ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:125] ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:173] ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:193] ERROR: [Synth 8-9917] port 'ARB_PRIORITY' must not be declared to be an array [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:27] ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:237] ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:254] ERROR: [Synth 8-10632] declarations are not allowed in an unnamed block [/var/jenkins_home/workspace/mmRISC-1/mmRISC-1/verilog/ahb_matrix/ahb_arb.v:269] ERROR: [Synth 8-439] module 'Controller' not found [/eda/processor_ci/rtl/mmRISC-1.v:48] ERROR: [Synth 8-6156] failed synthesizing module 'processorci_top' [/eda/processor_ci/rtl/mmRISC-1.v:1] ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details make: *** [/eda/processor_ci/makefiles/digilent_nexys4_ddr.mk:12: digilent_nexys4_ddr.bit] Error 1 Traceback (most recent call last): File "/eda/processor_ci/main.py", line 135, in <module> main( File "/eda/processor_ci/main.py", line 82, in main build(build_file_path, board_name, toolchain_path) File "/eda/processor_ci/core/fpga.py", line 218, in build raise subprocess.CalledProcessError(process.returncode, 'make') subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2. [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash digilent_nexys4_ddr) Stage "Flash digilent_nexys4_ddr" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test digilent_nexys4_ddr) Stage "Test digilent_nexys4_ddr" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: digilent_nexys4_ddr] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } Failed in branch digilent_nexys4_ddr [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Declarative: Post Actions) [Pipeline] junit Recording test results No test report files were found. Configuration error? Error when executing always post condition: Also: org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: 7b588bad-b899-40a9-a567-595752f9caea hudson.AbortException: No test report files were found. Configuration error? at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253) at hudson.FilePath.act(FilePath.java:1234) at hudson.FilePath.act(FilePath.java:1217) at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27) at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:47) at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source) at java.base/java.util.concurrent.FutureTask.run(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source) at java.base/java.lang.Thread.run(Unknown Source) [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline ERROR: script returned exit code 1 Finished: FAILURE