-work work
-sv
+incdir+../../../verilog/common
+incdir+../../../verilog/ahb_sdram/model
+incdir+../../../verilog/i2c/i2c/trunk/rtl/verilog
-timescale=1ns/100ps
+define+RISCV_TESTS
+define+SIMULATION
+define+den512mb
+define+sg75
+define+x16
../../../verilog/chip/chip_top_wrap.v  \
../../../verilog/chip/chip_top.v       \
../../../verilog/cjtag/cjtag_2_jtag.v  \
../../../verilog/cjtag/cjtag_adapter.v \
../../../verilog/int_gen/int_gen.v
../../../verilog/ram/ram.v
../../../verilog/port/port.v
../../../verilog/uart/uart.v
../../../verilog/uart/sasc/trunk/rtl/verilog/sasc_top.v
../../../verilog/uart/sasc/trunk/rtl/verilog/sasc_fifo4.v
../../../verilog/uart/sasc/trunk/rtl/verilog/sasc_brg.v
../../../verilog/i2c/i2c.v
../../../verilog/i2c/i2c/trunk/rtl/verilog/i2c_master_top.v
../../../verilog/i2c/i2c/trunk/rtl/verilog/i2c_master_bit_ctrl.v
../../../verilog/i2c/i2c/trunk/rtl/verilog/i2c_master_byte_ctrl.v
../../../verilog/i2c/i2c_slave_model.v
../../../verilog/spi/spi.v
../../../verilog/spi/simple_spi/trunk/rtl/verilog/simple_spi_top.v
../../../verilog/spi/simple_spi/trunk/rtl/verilog/fifo4.v
../../../verilog/mmRISC/mmRISC.v
../../../verilog/mmRISC/bus_m_ahb.v
../../../verilog/mmRISC/csr_mtime.v
../../../verilog/cpu/cpu_top.v
../../../verilog/cpu/cpu_fetch.v
../../../verilog/cpu/cpu_datapath.v
../../../verilog/cpu/cpu_pipeline.v
../../../verilog/cpu/cpu_fpu32.v
../../../verilog/cpu/cpu_csr.v
../../../verilog/cpu/cpu_csr_int.v
../../../verilog/cpu/cpu_csr_dbg.v
../../../verilog/cpu/cpu_debug.v
../../../verilog/debug/debug_top.v
../../../verilog/debug/debug_dtm_jtag.v
../../../verilog/debug/debug_cdc.v
../../../verilog/debug/debug_dm.v
../../../verilog/ahb_matrix/ahb_top.v
../../../verilog/ahb_matrix/ahb_master_port.v
../../../verilog/ahb_matrix/ahb_slave_port.v
../../../verilog/ahb_matrix/ahb_interconnect.v
../../../verilog/ahb_matrix/ahb_arb.v
../../../verilog/ahb_sdram/logic/ahb_lite_sdram.v
../../../verilog/ahb_sdram/model/sdr.v
./tb_TOP.v
