Workspace

	.git
	.Xil
	doc
	fpga
	openocd
	simulation/modelsim
	tools
	verilog
	workspace
	build_digilent_arty_a7_100t.tcl	Apr 15, 2026, 5:19:27 AM	3.05 KiB
	LICENSE	Apr 15, 2026, 5:19:19 AM	1.30 KiB
	processor_ci_defines.vh	Apr 15, 2026, 5:19:27 AM	300 B
	README.md	Apr 15, 2026, 5:19:19 AM	10.77 KiB
(all files in zip)