read_verilog -sv /eda/processor_ci/rtl/neorv32-verilog.sv
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_application_image.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_boot_rom.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_bootloader_image.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_bus.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_cache.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_cfs.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_clockgate.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_cpu.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_cpu_alu.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_cpu_control.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_cpu_cp_bitmanip.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_cpu_cp_cfu.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_cpu_cp_cond.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_cpu_cp_crypto.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_cpu_cp_fpu.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_cpu_cp_muldiv.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_cpu_cp_shifter.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_cpu_decompressor.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_cpu_lsu.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_cpu_pmp.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_cpu_regfile.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_crc.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_debug_auth.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_debug_dm.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_debug_dtm.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_dma.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_dmem.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_fifo.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_gpio.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_gptmr.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_imem.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_mtime.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_neoled.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_onewire.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_package.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_pwm.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_sdi.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_slink.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_spi.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_sys.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_sysinfo.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_top.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_trng.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_twd.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_twi.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_uart.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_wdt.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_xbus.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_xip.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/core/neorv32_xirq.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/processor_templates/neorv32_ProcessorTop_Minimal.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/processor_templates/neorv32_ProcessorTop_MinimalBoot.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/processor_templates/neorv32_ProcessorTop_UP5KDemo.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/system_integration/neorv32_litex_core_complex.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/system_integration/neorv32_vivado_ip.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/system_integration/xbus2ahblite_bridge.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/neorv32/rtl/system_integration/xbus2axi4lite_bridge.vhd
read_vhdl -vhdl2008 /var/jenkins_home/workspace/neorv32-verilog/neorv32-verilog/src/neorv32_verilog_wrapper.vhd
read_verilog -sv /eda/processor-ci-controller/modules/uart.sv
read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v

#read_verilog -sv /eda/processor-ci-controller/modules/spi.sv;
#read_verilog -sv /eda/processor-ci-controller/modules/SPI-Slave/rtl/spi_slave.sv;

read_verilog -sv /eda/processor_ci/internal/ahblite_to_wishbone.sv
read_verilog -sv /eda/processor_ci/internal/axi4_to_wishbone.sv
read_verilog -sv /eda/processor_ci/internal/axi4lite_to_wishbone.sv
read_verilog -sv /eda/processor-ci-controller/rtl/fifo.sv
read_verilog -sv /eda/processor-ci-controller/rtl/reset.sv
read_verilog -sv /eda/processor-ci-controller/rtl/clk_divider.sv
read_verilog -sv /eda/processor-ci-controller/rtl/memory.sv
read_verilog -sv /eda/processor-ci-controller/rtl/interpreter.sv
read_verilog -sv /eda/processor-ci-controller/rtl/controller.sv
read_verilog -sv /eda/processor-ci-controller/rtl/timer.sv
read_verilog -sv /eda/processor_ci/internal/fpga_top.sv

set_param general.maxThreads 16

read_xdc "/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc"
set_property PROCESSING_ORDER EARLY [get_files /eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]

# synth
synth_design -top "fpga_top" -part "xc7a100tcsg324-1"

# place and route
opt_design
place_design

report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt
report_utilization               -file digilent_arty_a7_utilization_place.rpt
report_io                        -file digilent_arty_a7_io.rpt
report_control_sets -verbose     -file digilent_arty_a7_control_sets.rpt
report_clock_utilization         -file digilent_arty_a7_clock_utilization.rpt


route_design

report_timing_summary -no_header -no_detailed_paths
report_route_status                            -file digilent_arty_a7_route_status.rpt
report_drc                                     -file digilent_arty_a7_drc.rpt
report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt
report_power                                   -file digilent_arty_a7_power.rpt


# write bitstream
write_bitstream -force "digilent_arty_a7_100t.bit"

exit