:sectnums:
=== Instruction Sets and Extensions

The NEORV32 CPU provides several optional RISC-V-compliant and custom/user-defined ISA extensions.
The extensions can be enabled/configured via the according <<_processor_top_entity_generics>>.
This chapter gives a brief overview of all available ISA extensions.

.NEORV32 Instruction Set Extensions
[cols="<2,<5,<3"]
[options="header",grid="rows"]
|=======================
| Name | Description | <<_processor_top_entity_generics, Enabled by Generic>>
| <<_a_isa_extension,`A`>>               | Atomic memory instructions                                   | _Implicitly_ enabled
| <<_b_isa_extension,`B`>>               | Bit manipulation instructions                                | _Implicitly_ enabled
| <<_c_isa_extension,`C`>>               | Compressed (16-bit) instructions                             | <<_processor_top_entity_generics, `RISCV_ISA_C`>>
| <<_e_isa_extension,`E`>>               | Embedded CPU extension (reduced register file size)          | <<_processor_top_entity_generics, `RISCV_ISA_E`>>
| <<_i_isa_extension,`I`>>               | Integer base ISA                                             | Enabled if `RISCV_ISA_E` is **not** enabled
| <<_m_isa_extension,`M`>>               | Integer multiplication and division instructions             | <<_processor_top_entity_generics, `RISCV_ISA_M`>>
| <<_u_isa_extension,`U`>>               | Less-privileged _user_ mode extension                        | <<_processor_top_entity_generics, `RISCV_ISA_U`>>
| <<_x_isa_extension,`X`>>               | Platform-specific / NEORV32-specific extension               | Always enabled
| <<_zaamo_isa_extension,`Zaamo`>>       | Atomic read-modify-write memory operations                   | <<_processor_top_entity_generics, `RISCV_ISA_Zaamo`>>
| <<_zalrsc_isa_extension,`Zalrsc`>>     | Atomic reservation-set memory operations                     | <<_processor_top_entity_generics, `RISCV_ISA_Zalrsc`>>
| `Zca` (_just an alias_)                | Compressed instruction without floating-point operations     | Implicitly enabled via <<_processor_top_entity_generics, `RISCV_ISA_C`>>
| <<_zba_isa_extension,`Zba`>>           | Shifted-add bit manipulation instructions                    | <<_processor_top_entity_generics, `RISCV_ISA_Zba`>>
| <<_zbb_isa_extension,`Zbb`>>           | Basic bit manipulation instructions                          | <<_processor_top_entity_generics, `RISCV_ISA_Zbb`>>
| <<_zbkb_isa_extension,`Zbkb`>>         | Scalar cryptography bit manipulation instructions            | <<_processor_top_entity_generics, `RISCV_ISA_Zbkb`>>
| <<_zbkc_isa_extension,`Zbkc`>>         | Scalar cryptography carry-less multiplication instructions   | <<_processor_top_entity_generics, `RISCV_ISA_Zbkc`>>
| <<_zbkx_isa_extension,`Zbkx`>>         | Scalar cryptography crossbar permutation instructions        | <<_processor_top_entity_generics, `RISCV_ISA_Zbkx`>>
| <<_zbs_isa_extension,`Zbs`>>           | Single-bit bit manipulation instructions                     | <<_processor_top_entity_generics, `RISCV_ISA_Zbs`>>
| <<_zcb_isa_extension,`Zcb`>>           | Additional code size reduction instructions (build upon `C`) | <<_processor_top_entity_generics, `RISCV_ISA_Zcb`>>
| <<_zfinx_isa_extension,`Zfinx`>>       | Floating-point instructions using integer registers          | <<_processor_top_entity_generics, `RISCV_ISA_Zfinx`>>
| <<_zifencei_isa_extension,`Zifencei`>> | Instruction stream synchronization instruction               | Always enabled
| <<_zibi_isa_extension,`Zibi`>>         | Branches with immediate-comparison                           | <<_processor_top_entity_generics, `RISCV_ISA_Zibi`>>
| <<_zicntr_isa_extension,`Zicntr`>>     | Base counters extension                                      | <<_processor_top_entity_generics, `RISCV_ISA_Zicntr`>>
| <<_zicond_isa_extension,`Zicond`>>     | Integer conditional operations                               | <<_processor_top_entity_generics, `RISCV_ISA_Zicond`>>
| <<_zicsr_isa_extension,`Zicsr`>>       | Control and status register access instructions              | Always enabled
| <<_zihpm_isa_extension,`Zihpm`>>       | Hardware performance monitors extension                      | <<_processor_top_entity_generics, `RISCV_ISA_Zihpm`>>
| <<_zimop_isa_extension,`Zimop`>>       | May-be-operations                                            | <<_processor_top_entity_generics, `RISCV_ISA_Zimop`>>
| <<_zkn_isa_extension,`Zkn`>>           | Scalar cryptography NIST algorithm suite                     | _Implicitly_ enabled
| <<_zknd_isa_extension,`Zknd`>>         | Scalar cryptography NIST AES decryption instructions         | <<_processor_top_entity_generics, `RISCV_ISA_Zknd`>>
| <<_zkne_isa_extension,`Zkne`>>         | Scalar cryptography NIST AES encryption instructions         | <<_processor_top_entity_generics, `RISCV_ISA_Zkne`>>
| <<_zknh_isa_extension,`Zknh`>>         | Scalar cryptography NIST hash function instructions          | <<_processor_top_entity_generics, `RISCV_ISA_Zknh`>>
| <<_zkt_isa_extension,`Zkt`>>           | Data independent execution time (of cryptography operations) | _Implicitly_ enabled
| <<_zks_isa_extension,`Zks`>>           | Scalar cryptography ShangMi algorithm suite                  | _Implicitly_ enabled
| <<_zksed_isa_extension,`Zksed`>>       | Scalar cryptography ShangMi block cypher instructions        | <<_processor_top_entity_generics, `RISCV_ISA_Zksed`>>
| <<_zksh_isa_extension,`Zksh`>>         | Scalar cryptography ShangMi hash instructions                | <<_processor_top_entity_generics, `RISCV_ISA_Zksh`>>
| <<_zmmul_isa_extension,`Zmmul`>>       | Integer multiplication-only instructions                     | <<_processor_top_entity_generics, `RISCV_ISA_Zmmul`>>
| <<_zxcfu_isa_extension,`Zcfu`>>        | Custom / user-defined instructions                           | <<_processor_top_entity_generics, `RISCV_ISA_Zxcfu`>>
| <<_smpmp_isa_extension,`Smpmp`>>       | Physical memory protection (PMP) extension                   | <<_processor_top_entity_generics, `RISCV_ISA_Smpmp`>>
| <<_sdext_isa_extension,`Sdext`>>       | External debug support extension (on-chip debugger)          | <<_processor_top_entity_generics, `OCD_EN`>>
| <<_sdtrig_isa_extension,`Sdtrig`>>     | Debug trigger module extension (hardware breakpoint)         | <<_processor_top_entity_generics, `OCD_NUM_HW_TRIGGERS`>>
|=======================

.RISC-V ISA Specification
[TIP]
For more information regarding the RISC-V ISA extensions please refer to the "RISC-V Instruction Set Manual - Volume
I: Unprivileged ISA" and "The RISC-V Instruction Set Manual Volume II: Privileged Architecture". A copy of these
documents can be found in the projects `docs/references` folder.

.Discovering ISA Extensions
[TIP]
Software can discover available ISA extensions via the <<_misa>> and <<_mxisa>> CSRs or by executing an instruction
and checking for an illegal instruction exception (i.e. <<_full_virtualization>>).


==== Latency Definitions

This chapter shows the CPI values (cycles per instruction) for each individual instruction/type. For some instructions
a placeholder variable from the table below is used. Note that the provided values reflect _optimal bus accesses_
(i.e. no congestion/wait states due to dual-core or DMA accesses) and no pipeline wait cycles. To benchmark a certain
processor configuration for its setup-specific CPI value please refer to the `sw/example/performance_tests` test programs.

[cols="<1,<9"]
[options="header", grid="rows"]
|=======================
| Alias | Description
| `T_shift_latency` | 1 if <<_cpu_fast_shift_en>> is `true`; otherwise `T_shift_latency` equals the shift offset
| `T_data_latency` | 1 for accessing the default processor-internal memories; +
1 if accessing the data cache results in a hit; +
2 for accessing the default processor-internal peripherals; +
uncached accesses via the <<_processor_external_bus_interface_xbus>> may have additional wait states
| `T_inst_latency` | 1 for accessing the default processor-internal memories; +
1 if accessing the instruction cache results in a hit; +
2 for accessing the default processor-internal peripherals; +
uncached accesses via the <<_processor_external_bus_interface_xbus>> may have additional wait states; +
branches to an unaligned address require additional `2 x T_inst_latency` cycles
| `T_mul_latency` | 1 if <<_cpu_fast_mul_en>> is `true`; 32 otherwise
| `T_cust_latency` | latency is defined by the custom <<_custom_functions_unit_cfu>> logic; +
however, the minimum is 1 and the maximum is 512
|=======================


==== `A` ISA Extension

The `A` ISA extension adds instructions and mechanisms for atomic memory operations hat can be used to
manage mutually-exclusive access to shared resources. Note that this ISA extension cannot be enabled by
a specific generic. Instead, it is enabled if a specific set of sub-extensions is enabled. The `A`
extension is shorthand for the following set of other extensions:

* <<_zaamo_isa_extension>> - Atomic read-modify-write instructions.
* <<_zalrsc_isa_extension>> - Atomic reservation-set instructions.

.Atomic Variable in C Languages
[NOTE]
The C `_Atomic` specifier should be used for atomic variables.
See section <<_coherence_example>> for more information.

.`A` ISA Extension Exceptions
[NOTE]
Note that load and load-reserved instructions generate load exceptions,
whereas store, store-conditional, and AMO instructions generate store exceptions.


==== `B` ISA Extension

The `B` ISA extension adds instructions for bit-manipulation operations.
This ISA extension cannot be enabled by a specific generic. Instead, it is enabled if a specific set of
sub-extensions is enabled. The `B` extension is shorthand for the following set of other extensions:

* <<_zba_isa_extension>> - Address-generation / shifted-add instructions.
* <<_zbb_isa_extension>> - Basic bit manipulation instructions.
* <<_zbs_isa_extension>> - Single-bit operations.

A processor configuration which implements `B` must implement all of the above extensions.


==== `C` ISA Extension

The "compressed" ISA extension provides 16-bit encodings of commonly used instructions to reduce code size.

.Instructions and Timing
[cols="<2,<5,<4"]
[options="header", grid="rows"]
|=======================
| Class | Instructions | Execution cycles
| ALU        | `c.addi4spn` `c.nop` `c.add[i]` `c.li` `c.addi16sp` `c.lui` `c.and[i]` `c.sub` `c.xor` `c.or` `c.mv` | 2
| ALU shifts | `c.srli` `c.srai` `c.slli`                                                                           | 2 + `T_shift_latency`
| Branch     | `c.beqz` `c.bnez`                                                                                    | not taken: 3 +
taken: 5 + `T_inst_latency`
| Jump/call  | `c.jal[r]` `c.j` `c.jr`                                                                              | 5 + `T_inst_latency`
| Load/store | `c.lw` `c.sw` `c.lwsp` `c.swsp`                                                                      | 4 + `T_data_latency`
| System     | `c.break`                                                                                            | 7 + `T_inst_latency`
|=======================

Note that the NEORV32 `C` ISA extension only includes the `Zca` instructions; i.e. all instructions from `C`
excluding the single-precision (`F`) and double-precision (`D`) floating-point instructions.


==== `E` ISA Extension

The "embedded" ISA extensions reduces the size of the general purpose register file from 32 entries
to 16 entries to shrink hardware size. It provides the same instructions as the base `I` ISA extension.
Due to the reduced register file size an alternate toolchain ABI (`ilp32e*`) is required.


==== `I` ISA Extension

The `I` ISA extensions is the base RISC-V integer ISA that is always enabled.

.Instructions and Timing
[cols="<2,<5,<4"]
[options="header", grid="rows"]
|=======================
| Class | Instructions | Execution cycles
| ALU            | `add[i]` `slt[i]` `slt[i]u` `xor[i]` `or[i]` `and[i]` `sub` `lui` `auipc` | 2
| ALU shifts     | `sll[i]` `srl[i]` `sra[i]`                                                | 3 + `T_shift_latency`
| Branch         | `beq` `bne` `blt` `bge` `bltu` `bgeu`                                     | not taken: 3 +
taken: 5 + `T_inst_latency`
| Jump/call      | `jal[r]`                                                                  | 5 + `T_inst_latency`
| Load/store     | `lb` `lh` `lw` `lbu` `lhu` `sb` `sh` `sw`                                 | 4 + `T_data_latency`
| Data fence     | `fence`                                                                   | 2
| System         | `ecall` `ebreak` `mret`                                                   | 7 + `T_inst_latency`
| System         | `wfi`                                                                     | 3
|=======================

.`fence` Instruction
[NOTE]
Analogous to the `fence.i` instruction (<<_zifencei_isa_extension>>) the `fence` instruction triggers
a load/store memory synchronization operation by flushing the CPU's data cache. See section
<<_memory_coherence>> for more information. NEORV32 ignores the predecessor and successor fields and
always executes a conservative fence on all operations.

.`wfi` Instruction
[NOTE]
The `wfi` instruction is used to enter CPU <<_sleep_mode>>.


==== `M` ISA Extension

Hardware-accelerated integer multiplication and division operations are available via the RISC-V `M` ISA extension.
This ISA extension is implemented as multi-cycle ALU co-process (`rtl/core/neorv32_cpu_cp_muldiv.vhd`).

.Instructions and Timing
[cols="<2,<5,<4"]
[options="header", grid="rows"]
|=======================
| Class | Instructions | Execution cycles
| Multiplication | `mul` `mulh` `mulhsu` `mulhu` | 3 + `T_mul_latency`
| Division       | `div` `divu` `rem` `remu`     | 3 + 32
|=======================

.Multiplication Tuning Options
[TIP]
The physical implementation of the multiplier can be tuned for certain design goals like area or throughput.
See section <<_cpu_tuning_options>> for more information.


==== `U` ISA Extension

In addition to the highest-privileged machine-mode, the user-mode ISA extensions adds a second **less-privileged**
operation mode. Code executed in user-mode has reduced CSR access rights. Furthermore, user-mode accesses to the address space
(like peripheral/IO devices) can be constrained via the physical memory protection.
Any kind of privilege rights violation will raise an exception to allow <<_full_virtualization>>.


==== `X` ISA Extension

The NEORV32-specific ISA extensions `X` is always enabled. The most important points of the NEORV32-specific extensions are:
* The CPU provides 16 _fast interrupt_ interrupts (`FIRQ`), which are controlled via custom bits in the <<_mie>>
and <<_mip>> CSRs. These extensions are mapped to CSR bits, that are available for custom use according to the
RISC-V specs. Also, custom trap codes for <<_mcause>> are implemented.
* All undefined/unimplemented/malformed/illegal instructions do raise an illegal instruction exception (see <<_full_virtualization>>).
* Additional <<_neorv32_specific_csrs>>.


==== `Zaamo` ISA Extension

The `Zaamo` ISA extension is a sub-extension of the RISC-V <<_a_isa_extension>> and compromises
instructions for atomic read-modify-write operations. It is enabled by the top's
<<_processor_top_entity_generics, `RISCV_ISA_Zaamo`>> generic. Atomic read-modify-write operations
are handled by the processor's <<_atomic_memory_operations_controller>>.

.Instructions and Timing
[cols="<2,<5,<4"]
[options="header", grid="rows"]
|=======================
| Class | Instructions | Execution cycles
| Atomic read-modify-write | `amoswap.w` `amoadd.w` `amoand.w` `amoor.w` `amoxor.w` `amomax[u].w` `amomin[u].w` | 4 + 2x `T_data_latency` + 1
|=======================

.`aq` and `rl` Bits
[NOTE]
The instruction word's `aq` and `lr` memory ordering bits are not evaluated by the hardware at all.


==== `Zalrsc` ISA Extension

The `Zalrsc` ISA extension is a sub-extension of the RISC-V <<_a_isa_extension>> and compromises
instructions for reservation-set operations. It is enabled by the top's
<<_processor_top_entity_generics, `RISCV_ISA_Zalrsc`>> generic. Atomic reservation-set operations
are handled by the processor's <<_atomic_reservation_set_controller>>.

.Instructions and Timing
[cols="<2,<5,<4"]
[options="header", grid="rows"]
|=======================
| Class | Instructions | Execution cycles
| Atomic reservation-set | `lr.w` `sc.w` | 4 + `T_data_latency`
|=======================

.`aq` and `rl` Bits
[NOTE]
The instruction word's `aq` and `lr` memory ordering bits are not evaluated by the hardware at all.


==== `Zcb` ISA Extension

This ISA extension is part of the "code size reduction" ISA extension `Zc*` and adds additional
compressed instruction for common operation. `Zcb` requires the <<_c_isa_extension>> to be enabled.
Some instructions may require additional ISA (sub-) extensions.

.Instructions and Timing
[cols="<2,<4,<3,<3"]
[options="header", grid="rows"]
|=======================
| Class | Instructions | Depends on ISA Ext. | Execution cycles
| Memory     | `c.lbu` `c.lh` `c.lhu` `c.sb` `c.sh` | -              | 4 + `T_data_latency`
| Logic      | `c.not` `c.zext.b`                   | -              | 2
| Logic      | `c.sext.b` `c.zext.h` `c.zext.h`     | `B` or `Zbb`   | 3
| Arithmetic | `c.mul`                              | `M` or `Zmmul` | 3 + `T_mul_latency`
|=======================

.RISC-V GCC ISA String
[IMPORTANT]
Technically, `Zbc` required the `Zca` extension which is `C` but excluding the floating-point operations.
Therefore, `Zca` and `Zbc` must be contained in the ISA string so that the compiler generates `Zbc` instructions..
Example: `MARCH=rv32imc_zca_zcb_...`


==== `Zifencei` ISA Extension

This instruction is the only standard mechanism to ensure that stores visible to a hart will also be visible to its
instruction fetches. When executed, the CPU flushes the instruction prefetch buffer and reloads the CPU's
instruction cache (if enabled). See section <<_memory_coherence>> for more information.

.Instructions and Timing
[cols="<2,<5,<4"]
[options="header", grid="rows"]
|=======================
| Class | Instructions | Execution cycles
| Instruction fence | `fence.i` | 2
|=======================


==== `Zfinx` ISA Extension

The `Zfinx` floating-point extension is an _alternative_ of the standard `F` floating-point ISA extension.
It also uses the integer register file `x` to store and operate on floating-point data
instead of a dedicated floating-point register file. Thus, the `Zfinx` extension requires
less hardware resources and features faster context changes. This also implies that there are NO dedicated `f`
register file-related load/store or move instructions. The `Zfinx` extension'S floating-point unit is controlled
via dedicated <<_floating_point_csrs>>.
This ISA extension is implemented as multi-cycle ALU co-process (`rtl/core/neorv32_cpu_cp_fpu.vhd`).

.Fused / Multiply-Add and Division / Square Root Instructions
[WARNING]
Fused multiply-add instructions `f[n]m[add/sub].s` and division `fdiv.s` and square root `fsqrt.s` instructions
are not supported yet. are not supported. Special GCC flags are used to prevent the compiler from emitting these
operations (see <<_default_compiler_flags>>).

.Subnormal Numbers
[WARNING]
Subnormal numbers ("de-normalized" numbers, i.e. exponent = 0) are not supported by the NEORV32 FPU.
Subnormal numbers are _flushed to zero_ setting them to +/- 0 before being processed by **any** FPU operation.
If a computational instruction generates a subnormal result it is also flushed to zero during normalization.

.Instructions and Timing
[cols="<3,<4,<2"]
[options="header", grid="rows"]
|=======================
| Class | Instructions | Execution cycles
| Add/sub                | `fadd.s` `fsub.s`                         | 21
| Multiply               | `fmul.s`                                  | 13
| Compare                | `fmin.s` `fmax.s` `feq.s` `flt.s` `fle.s` | 5
| Convert (float -> int) | `fcvt.w.s` `fcvt.wu.s`                    | 10
| Convert (int -> float) | `fcvt.s.w` `fcvt.s.wu`                    | 42
| Sign-injection         | `fsgnj.s` `fsgnjn.s` `fsgnjx.s`           | 4
| Classify               | `fclass.s`                                | 4
|=======================


==== `Zibi` ISA Extension

The RISC-V `Zibi` ISA extension adds two new "branch with immediate" instructions. The instruction
word's `rs2` bit-field selects one out of 32 pre-defined immediate values which is used for the
actual comparison.

.Non-Ratified ISA Extension
[WARNING]
The RISC-V `Zibi` ISA extension has not been ratified yet!

.Instructions and Timing
[cols="<3,<2,<5"]
[options="header", grid="rows"]
|=======================
| Class | Instructions | Execution cycles
| Branch with immediate | `beqi` `bnei` | not taken: 3 +
taken: 5 + `T_inst_latency`
|=======================


==== `Zicntr` ISA Extension

The `Zicntr` ISA extension adds the basic <<_cycleh>>, <<_mcycleh>>, <<_instreth>> and <<_minstreth>>
counter CSRs. Section <<_machine_counter_and_timer_csrs>> shows a list of all `Zicntr`-related CSRs.

.Time CSRs
[NOTE]
The user-mode `time[h]` CSRs are **not implemented**. Any access will trap allowing the trap handler to
retrieve system time from the <<_core_local_interruptor_clint>>.

.Constrained Access
[TIP]
User-level access to the counter CSRs can be constrained by the <<_mcounteren>> CSR.


==== `Zicond` ISA Extension

The `Zicond` ISA extension adds integer conditional move primitives that allow to implement branch-less
control flows. It is enabled by the top's <<_processor_top_entity_generics, `RISCV_ISA_Zicond`>> generic.
This ISA extension is implemented as multi-cycle ALU co-processor (`rtl/core/neorv32_cpu_cp_cond.vhd`).

.Instructions and Timing
[cols="<2,<5,<4"]
[options="header", grid="rows"]
|=======================
| Class | Instructions | Execution cycles
| Conditional | `czero.eqz` `czero.nez` | 3
|=======================


==== `Zicsr` ISA Extension

This ISA extensions provides instructions for accessing the <<_control_and_status_registers_csrs>> as well as further
privileged-architecture extensions. This extension is mandatory and cannot be disabled. Hence, there is no generic
for enabling/disabling this ISA extension.

.Side-Effects if Destination is Zero-Register
[NOTE]
If `rd=x0` for the `csrrw[i]` instructions there will be no actual read access to the according CSR.
However, access privileges are still enforced so these instruction variants _do_ cause side-effects
(the RISC-V spec. state that these combinations "shall" not cause any side-effects).

.Instructions and Timing
[cols="<2,<5,<4"]
[options="header", grid="rows"]
|=======================
| Class | Instructions | Execution cycles
| System | `csrrw[i]` `csrrs[i]` `csrrc[i]` | 3
|=======================


==== `Zihpm` ISA Extension

In additions to the base counters the NEORV32 CPU provides up to 13 hardware performance monitors (HPM 3..15),
which can be used to benchmark applications. Each HPM consists of an N-bit wide counter (split in a high-word 32-bit
CSR and a low-word 32-bit CSR), where N is defined via the top's `HPM_CNT_WIDTH` generic and a corresponding event
configuration CSR.

The event configuration CSR defines the architectural events that lead to an increment of the associated HPM counter.
See section <<_hardware_performance_monitors_hpm_csrs>> for a list of all HPM-related CSRs and event configurations.

.Machine-Mode HPMs Only
[NOTE]
Note that only the machine-mode hardware performance counter CSR are available (`mhpmcounter*[h]`).
Accessing any user-mode HPM CSR (`hpmcounter*[h]`) will raise an illegal instruction exception.

.Increment Inhibit
[TIP]
The event-driven increment of the HPMs can be deactivated individually via the <<_mcountinhibit>> CSR.


==== `Zimop` ISA Extension

The `Zimop` ISA extension introduces the concept of instructions that may be operations (MOPs). MOPs are initially
defined to simply write zero to the destination register, but are designed to be redefined by later extensions to
perform some other system/environment-class actions. NEORV32 can implement this ISA extension for software compatibility.
Without the `Zimop` extension, any `mop.r*` instruction will raise an illegal instruction exception.

.Instructions and Timing
[cols="<2,<5,<4"]
[options="header", grid="rows"]
|=======================
| Class | Instructions | Execution cycles
| System | `mop.r.[0..31]` `mop.rr.[0..7]` | 3
|=======================


==== `Zba` ISA Extension

The `Zba` sub-extension is part of the _RISC-V bit manipulation_ ISA specification (<<_b_isa_extension>>)
and adds shifted-add / address-generation instructions. It is enabled by the top's
<<_processor_top_entity_generics, `RISCV_ISA_Zba`>> generic. This ISA extension is implemented as multi-cycle
ALU co-processor (`rtl/core/neorv32_cpu_cp_bitmanip.vhd`).

.Instructions and Timing
[cols="<2,<5,<4"]
[options="header", grid="rows"]
|=======================
| Class | Instructions | Execution cycles
| Shifted-add | `sh1add` `sh2add` `sh3add` | 4
|=======================


==== `Zbb` ISA Extension

The `Zbb` sub-extension is part of the _RISC-V bit manipulation_ ISA specification (<<_b_isa_extension>>)
and adds the basic bit manipulation instructions. It is enabled by the top's <<_processor_top_entity_generics, `RISCV_ISA_Zbb`>>
generic. This ISA extension is implemented as multi-cycle ALU co-processor (`rtl/core/neorv32_cpu_cp_bitmanip.vhd`).

.Instructions and Timing
[cols="<2,<5,<4"]
[options="header", grid="rows"]
|=======================
| Class | Instructions | Execution cycles
| Logic with negate       | `andn` `orn` `xnor`      | 4
| Bit count               | `clz` `ctz` `cpop`       | 4 + `T_shift_latency`
| Integer maximum/minimum | `min[u]` `max[u]`        | 4
| Sign/zero extension     | `sext.b` `sext.h` `zext` | 4
| Bitwise rotation        | `rol` `ror[i]`           | 4 + `T_shift_latency`
| OR-combine              | `orc.b`                  | 4
| Byte-reverse            | `rev8`                   | 4
|=======================

.shifter Tuning Options
[TIP]
The physical implementation of the bit-shifter can be tuned for certain design goals like area or throughput.
See section <<_cpu_tuning_options>> for more information.


==== `Zbs` ISA Extension

The `Zbs` sub-extension is part of the _RISC-V bit manipulation_ ISA specification (<<_b_isa_extension>>)
and adds single-bit operations. It is enabled by the top's <<_processor_top_entity_generics, `RISCV_ISA_Zbs`>> generic.
This ISA extension is implemented as multi-cycle ALU co-processor (`rtl/core/neorv32_cpu_cp_bitmanip.vhd`).

.Instructions and Timing
[cols="<2,<5,<4"]
[options="header", grid="rows"]
|=======================
| Class | Instructions | Execution cycles
| Single-bit | `sbset[i]` `sbclr[i]` `sbinv[i]` `sbext[i]` | 4
|=======================


==== `Zbkb` ISA Extension

The `Zbkb` sub-extension is part of the _RISC-V scalar cryptography_ ISA specification and extends the _RISC-V bit manipulation_
ISA extension with additional instructions. It is enabled by the top's <<_processor_top_entity_generics, `RISCV_ISA_Zbkb`>> generic.
Note that enabling this extension will also enable the `Zbb` basic bit-manipulation ISA extension (which is extended by `Zknb`).
This ISA extension is implemented as multi-cycle ALU co-processor (`rtl/core/neorv32_cpu_cp_bitmanip.vhd`).

.Instructions and Timing (in addition to `Zbb`)
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|=======================
| Class | Instructions | Execution cycles
| Packing                | `pack` `packh` | 4
| Interleaving           | `zip` `unzip`  | 4
| Byte-wise bit reversal | `brev8`        | 4
|=======================


==== `Zbkc` ISA Extension

The `Zbkc` sub-extension is part of the _RISC-V scalar cryptography_ ISA extension and adds carry-less multiplication instruction.
ISA extension with additional instructions. It is enabled by the top's <<_processor_top_entity_generics, `RISCV_ISA_Zbkc`>> generic.
This ISA extension is implemented as multi-cycle ALU co-processor (`rtl/core/neorv32_cpu_cp_bitmanip.vhd`).

.Instructions and Timing
[cols="<2,<5,<4"]
[options="header", grid="rows"]
|=======================
| Class | Instructions | Execution cycles
| Carry-less multiply | `clmul` `clmulh` | 4 + 32
|=======================


==== `Zbkx` ISA Extension

The `Zbkx` sub-extension is part of the _RISC-V scalar cryptography_ ISA specification and adds crossbar permutation instructions.
It is enabled by the top's <<_processor_top_entity_generics, `RISCV_ISA_Zbkx`>> generic.
This ISA extension is implemented as multi-cycle ALU co-processor (`rtl/core/neorv32_cpu_cp_crypto.vhd`).

.Instructions and Timing
[cols="<2,<5,<4"]
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|=======================
| Class | Instructions | Execution cycles
| Crossbar permutation | `xperm8` `xperm4` | 4
|=======================


==== `Zkn` ISA Extension

The `Zkn` ISA extension is part of the _RISC-V scalar cryptography_ ISA specification and defines the "NIST algorithm suite".
This ISA extension cannot be enabled by a specific generic. Instead, it is enabled if a specific set of cryptography-related
sub-extensions is enabled.

The `Zkn` extension is shorthand for the following set of other extensions:

* <<_zbkb_isa_extension>> - Bit manipulation instructions for cryptography.
* <<_zbkc_isa_extension>> - Carry-less multiply instructions.
* <<_zbkx_isa_extension>> - Cross-bar permutation instructions.
* <<_zkne_isa_extension>> - AES encryption instructions.
* <<_zknd_isa_extension>> - AES decryption instructions.
* <<_zknh_isa_extension>> - SHA2 hash function instructions.

A processor configuration which implements `Zkn` must implement all of the above extensions.


==== `Zknd` ISA Extension

The `Zknd` sub-extension is part of the _RISC-V scalar cryptography_ ISA specification and adds NIST AES decryption instructions.
It is enabled by the top's <<_processor_top_entity_generics, `RISCV_ISA_Zknd`>> generic.
This ISA extension is implemented as multi-cycle ALU co-processor (`rtl/core/neorv32_cpu_cp_crypto.vhd`).

.Instructions and Timing
[cols="<2,<5,<4"]
[options="header", grid="rows"]
|=======================
| Class | Instructions | Execution cycles
| AES decryption | `aes32dsi` `aes32dsmi` | 6
|=======================


==== `Zkne` ISA Extension

The `Zkne` sub-extension is part of the _RISC-V scalar cryptography_ ISA specification and adds NIST AES encryption instructions.
It is enabled by the top's <<_processor_top_entity_generics, `RISCV_ISA_Zkne`>> generic.
This ISA extension is implemented as multi-cycle ALU co-processor (`rtl/core/neorv32_cpu_cp_crypto.vhd`).

.Instructions and Timing
[cols="<2,<5,<4"]
[options="header", grid="rows"]
|=======================
| Class | Instructions | Execution cycles
| AES decryption | `aes32esi` `aes32esmi` | 6
|=======================


==== `Zknh` ISA Extension

The `Zknh` sub-extension is part of the _RISC-V scalar cryptography_ ISA specification and adds NIST hash function instructions.
It is enabled by the top's <<_processor_top_entity_generics, `RISCV_ISA_Zknh`>> generic.
This ISA extension is implemented as multi-cycle ALU co-processor (`rtl/core/neorv32_cpu_cp_crypto.vhd`).

.Instructions and Timing
[cols="<2,<5,<4"]
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|=======================
| Class | Instructions | Execution cycles
| sha256 | `sha256sig0` `sha256sig1` `sha256sum0` `sha256sum1`                                 | 4
| sha512 | `sha512sig0h` `sha512sig0l` `sha512sig1h` `sha512sig1l` `sha512sum0r` `sha512sum1r` | 4
|=======================


==== `Zks` ISA Extension

The `Zks` ISA extension is part of the _RISC-V scalar cryptography_ ISA specification and defines the "ShangMi algorithm suite".
This ISA extension cannot be enabled by a specific generic. Instead, it is enabled if a specific set of cryptography-related
sub-extensions is enabled.

The `Zks` extension is shorthand for the following set of other extensions:

* <<_zbkb_isa_extension>> - Bit manipulation instructions for cryptography.
* <<_zbkc_isa_extension>> - Carry-less multiply instructions.
* <<_zbkx_isa_extension>> - Cross-bar permutation instructions.
* <<_zksed_isa_extension>> - SM4 block cipher instructions.
* <<_zksh_isa_extension>> - SM3 hash function instructions.

A processor configuration which implements `Zks` must implement all of the above extensions.


==== `Zksed` ISA Extension

The `Zksed` sub-extension is part of the _RISC-V scalar cryptography_ ISA specification and adds ShangMi block cypher
and key schedule instructions. It is enabled by the top's <<_processor_top_entity_generics, `RISCV_ISA_Zksed`>> generic.
This ISA extension is implemented as multi-cycle ALU co-processor (`rtl/core/neorv32_cpu_cp_crypto.vhd`).

.Instructions and Timing
[cols="<2,<5,<4"]
[options="header", grid="rows"]
|=======================
| Class | Instructions | Execution cycles
| Block cyphers | `sm4ed` | 6
| Key schedule  | `sm4ks` | 6
|=======================


==== `Zksh` ISA Extension

The `Zksh` sub-extension is part of the _RISC-V scalar cryptography_ ISA specification and adds ShangMi hash function instructions.
It is enabled by the top's <<_processor_top_entity_generics, `RISCV_ISA_Zksh`>> generic.
This ISA extension is implemented as multi-cycle ALU co-processor (`rtl/core/neorv32_cpu_cp_crypto.vhd`).

.Instructions and Timing
[cols="<2,<5,<4"]
[options="header", grid="rows"]
|=======================
| Class | Instructions | Execution cycles
| Hash | `sm3p0` `sm3p1` | 6
|=======================


==== `Zkt` ISA Extension

The `Zkt` sub-extension is part of the _RISC-V scalar cryptography_ ISA specification and guarantees data independent execution
times of cryptography and cryptography-related instructions. The ISA extension cannot be enabled by a specific generic.
Instead, it is enabled implicitly by certain CPU configurations.

The RISC-V `Zkt` specifications provides a list of instructions that are included within this specification.
However, not all instructions are required to be implemented. Rather, every one of these instructions that the
core does implement must adhere to the requirements of `Zkt`.

.`Zkt` instruction listing
[cols="<2,<4,<4"]
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|=======================
| Parent extension | Instructions | Data independent execution time?
.2+<| `RVI` <| `lui` `auipc` `add[i]` `slt[i][u]` `xor[i]` `or[i]` `and[i]` `sub` <| yes
            <| `sll[i]` `srl[i]` `sra[i]` <| yes if `CPU_FAST_SHIFT_EN` enabled
| `RVM` | `mul[h]` `mulh[s]u` | yes
.2+<| `RVC` <| `c.nop` `c.addi` `c.lui` `c.andi` `c.sub` `c.xor` `c.and` `c.mv` `c.add` <| yes
            <| `c.srli` `c.srai` `c.slli` <| yes if `CPU_FAST_SHIFT_EN` enabled
.2+<| `Zcb` <| `c.mul`, `c.not`, `c.zext.b` <| yes
| `RVK` | `aes32ds[m]i` `aes32es[m]i` `sha256sig*` `sha512sig*` `sha512sum*` `sm3p0` `sm3p1` `sm4ed` `sm4ks` | yes
.2+<| `RVB` <| `xperm4` `xperm8` `andn` `orn` `xnor` `pack[h]` `brev8` `rev8` <| yes
            <| `ror[i]` `rol` <| yes if `CPU_FAST_SHIFT_EN` enabled
|=======================

.Data-Independent Timing of Branches
[TIP]
To further reduce the possibility of timing side-channel attacks, conditional branches can be executed with constant time
(i.e. data-independent execution times). See the <<_cpu_constt_br_en>> <<_cpu_tuning_options>> for more information.


==== `Zmmul` - ISA Extension

This is a sub-extension of the <<_m_isa_extension>> ISA extension. It implements only the multiplication operations
of the `M` extensions and is intended for size-constrained setups that require hardware-based
integer multiplications but not hardware-based divisions, which will be computed entirely in software.
Note that the <<_zmmul_isa_extension>> and <<_m_isa_extension>> are mutually exclusive.


==== `Zxcfu` ISA Extension

The `Zxcfu` presents a NEORV32-specific ISA extension. It adds the <<_custom_functions_unit_cfu>> to
the CPU core, which allows to add custom RISC-V instructions to the processor core.
For detailed information regarding the CFU, its hardware and the according software interface
see section <<_custom_functions_unit_cfu>>.

Software can utilize the custom instructions by using _intrinsics_, which are basically inline assembly functions that
behave like regular C functions but that evaluate to a single custom instruction word (no calling overhead at all).

.CFU Execution Time
[NOTE]
The actual CFU execution time depends on the logic being implemented. The CPU architecture requires a minimal execution
time of 3 cycles (purely combinatorial CFU operation) and automatically terminates execution after 512 cycles if the CFU
does not complete operation within this time window.

.Instructions and Timing
[cols="<2,<5,<4"]
[options="header", grid="rows"]
|=======================
| Class | Instructions | Execution cycles
| Custom instructions | Instruction words with `custom-0` or `custom-1` opcode | 3 + `T_cust_latency`
|=======================


==== `Smpmp` ISA Extension

The NEORV32 physical memory protection (PMP) provides an elementary memory protection mechanism that can be used
to configure read/write(execute permission of arbitrary memory regions. In general, the PMP can **grant permissions
to user mode**, which by default has none, and can **revoke permissions from M-mode**, which by default has full
permissions. The NEORV32 PMP is fully compatible to the RISC-V Privileged Architecture Specifications and is
configured via several CSRs (<<_machine_physical_memory_protection_csrs>>). Several <<_processor_top_entity_generics>>
are provided to adjust the CPU's PMP capabilities according to the application requirements (pre-synthesis):

. `PMP_NUM_REGIONS` defines the number of implemented PMP regions (0..16); setting this generic to zero will
result in absolutely no PMP logic being implemented
. `PMP_MIN_GRANULARITY` defines the minimal granularity of each region (has to be a power of 2, minimal
granularity = 4 bytes); note that a smaller granularity will lead to wider comparators and thus, to higher area footprint
and longer critical path
. `PMP_TOR_MODE_EN` controls the implementation of the top-of-region (TOR) mode (default = true); disabling this mode
will reduce area footprint
. `PMP_NAP_MODE_EN` controls the implementation of the naturally-aligned-power-of-two (NA4 and NAPOT) modes (default =
true); disabling this mode will reduce area footprint and critical path length

.PMP Permissions when in Debug Mode
[NOTE]
When in debug-mode all PMP rules are bypassed/ignored granting the debugger maximum access permissions.

.PMP Time-Multiplex
[NOTE]
Instructions are executed in a multi-cycle manner. Hence, data access (load/store) and instruction fetch cannot occur
at the same time. Therefore, the PMP hardware uses only a single set of comparators for memory access permissions checks
that are switched in an iterative, time-multiplex style reducing hardware footprint by approx. 50% while maintaining
full security features and RISC-V compatibility.

.PMP Memory Accesses
[IMPORTANT]
Load/store accesses for which there are insufficient access permission do not trigger any memory/bus accesses at all.
In contrast, instruction accesses for which there are insufficient access permission nevertheless lead to a memory/bus
access (causing potential side effects on the memory side=. However, the fetched instruction will be discarded and the
corresponding exception will still be triggered precisely.


==== `Sdext` ISA Extension

This ISA extension enables the RISC-V-compatible "external debug support" by implementing
the CPU "debug mode", which is required for the on-chip debugger.
See section <<_on_chip_debugger_ocd>> / <<_cpu_debug_mode>> for more information.

.Instructions and Timing
[cols="<2,<5,<4"]
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|=======================
| Class | Instructions | Execution cycles
| System | `dret` | 5
|=======================

==== `Sdtrig` ISA Extension

This ISA extension implements the RISC-V-compatible "trigger module" which provides support for
hardware breakpoints for the on-chip-debugger.
See section <<_on_chip_debugger_ocd>> / <<_trigger_module>> for more information.
