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==== System Configuration Information Memory (SYSINFO)

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|=======================
| Hardware source files:  | neorv32_sysinfo.vhd |
| Software driver files:  | neorv32_sysinfo.h   | link:https://stnolting.github.io/neorv32/sw/neorv32__sysinfo_8h.html[Online software reference (Doxygen)]
| Top entity ports:       | none                |
| Configuration generics: | all                 | most of the top's configuration generics
| CPU interrupts:         | none                |
|=======================

**Key Features**

* Provides detailed SoC configuration information


**Overview**

The SYSINFO module allows the application software to determine the setting of most of the <<_processor_top_entity_generics>>
that are related to CPU and processor/SoC configuration. This device is always implemented - regardless of the actual hardware
configuration since the NEORV32 software framework requires information from this device for correct operation.
However, advanced users that do not want to use the default NEORV32 software framework can choose to disable the
entire SYSINFO module. This might also be suitable for setups that use the processor just as wrapper for a CPU-only
configuration.


**Register Map**

All registers of this module are read-only except for the `CLK` register. Upon reset, the `CLK` registers is initialized
from the `CLOCK_FREQUENCY` top entity generic. Application software can override this default value in order, for example,
to take into account a dynamic frequency scaling of the processor.

.SYSINFO register map (`struct NEORV32_SYSINFO`)
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|=======================
| Address | Name [C] | R/W | Description
| `0xfffe0000` | `CLK`     | r/w | clock frequency in Hz (initialized from top's `CLOCK_FREQUENCY` generic)
| `0xfffe0004` | `MISC[4]` | r/- | miscellaneous system configurations (see <<_sysinfo_miscellaneous_configuration>>)
| `0xfffe0008` | `SOC`     | r/- | specific SoC configuration (see <<_sysinfo_soc_configuration>>)
| `0xfffe000c` | `CACHE`   | r/- | cache configuration information (see <<_sysinfo_cache_configuration>>)
|=======================


===== SYSINFO - Miscellaneous Configuration

.SYSINFO `MEM` Bits
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|=======================
| Byte | Name [C] | Description
| `7:0`   | `SYSINFO_MISC_IMEM_MBS : SYSINFO_MISC_IMEM_LSB` | _log2_(internal IMEM size in bytes), via top's `IMEM_SIZE` generic
| `15:8`  | `SYSINFO_MISC_DMEM_MSB : SYSINFO_MISC_DMEM_LSB` | _log2_(internal DMEM size in bytes), via top's `DMEM_SIZE` generic
| `19:16` | `SYSINFO_MISC_HART_MSB : SYSINFO_MISC_HART_LSB` | number of physical CPU cores ("harts")
| `21:20` | `SYSINFO_MISC_BOOT_MSB : SYSINFO_MISC_BOOT_LSB` | boot mode configuration, via top's `BOOT_MODE_SELECT` generic (see <<_boot_configuration>>))
| `26:22` | `SYSINFO_MISC_ITMO_MSB : SYSINFO_MISC_ITMO_LSB` | _log2_(internal bus timeout cycles), see <<_bus_monitor_and_timeout>>
| `31:27` | `SYSINFO_MISC_ETMO_MSB : SYSINFO_MISC_ETMO_LSB` | _log2_(external bus timeout cycles), see <<_bus_monitor_and_timeout>>
|=======================


===== SYSINFO - SoC Configuration

.SYSINFO `SOC` Bits
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|=======================
| Bit | Name [C] | Description
| `0`  | `SYSINFO_SOC_BOOTLOADER` | set if processor-internal <<_bootloader>> is implemented (via top's `BOOT_MODE_SELECT` generic; see <<_boot_configuration>>)
| `1`  | `SYSINFO_SOC_XBUS`       | set if <<_processor_external_bus_interface_xbus>> is implemented (via top's `XBUS_EN` generic)
| `2`  | `SYSINFO_SOC_IMEM`       | set if processor-internal <<_instruction_memory_imem>> is implemented (via top's `IMEM_EN` generic)
| `3`  | `SYSINFO_SOC_DMEM`       | set if processor-internal <<_data_memory_dmem>> is implemented (via top's `DMEM_EN` generic)
| `4`  | `SYSINFO_SOC_OCD`        | set if <<_on_chip_debugger_ocd>> is implemented (via top's `OCD_EN` generic)
| `5`  | `SYSINFO_SOC_ICACHE`     | set if <<_instruction_cache_icache>> is implemented (via top's `ICACHE_EN` generic)
| `6`  | `SYSINFO_SOC_DCACHE`     | set if <<_data_cache_dcache>> is implemented (via top's `DCACHE_EN` generic)
| `7`  | `SYSINFO_SOC_SMC`        | set if <<_serial_memory_controller_smc>> is implemented (via top's `SMC_EN` generic)
| `8`  | -                        | _reserved_, read as zero
| `9`  | -                        | _reserved_, read as zero
| `10` | -                        | _reserved_, read as zero
| `11` | `SYSINFO_SOC_OCD_AUTH`   | set if on-chip debugger <<_debug_authentication>> is implemented (via top's `OCD_AUTHENTICATION` generic)
| `12` | `SYSINFO_SOC_IMEM_ROM`   | set if processor-internal <<_instruction_memory_imem>> is implemented as pre-initialized ROM (via top's `BOOT_MODE_SELECT` generic; see <<_boot_configuration>>)
| `13` | `SYSINFO_SOC_IO_TWD`     | set if <<_two_wire_serial_device_controller_twd>> is implemented (via top's `IO_TWD_EN` generic)
| `14` | `SYSINFO_SOC_IO_DMA`     | set if <<_direct_memory_access_controller_dma>> is implemented (via top's `IO_DMA_EN` generic)
| `15` | `SYSINFO_SOC_IO_GPIO`    | set if <<_general_purpose_input_and_output_port_gpio>> is implemented (via top's `IO_GPIO_EN` generic)
| `16` | `SYSINFO_SOC_IO_CLINT`   | set if <<_core_local_interruptor_clint>> is implemented (via top's `IO_CLINT_EN` generic)
| `17` | `SYSINFO_SOC_IO_UART0`   | set if <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> is implemented (via top's `IO_UART0_EN` generic)
| `18` | `SYSINFO_SOC_IO_SPI`     | set if <<_serial_peripheral_interface_controller_spi>> is implemented (via top's `IO_SPI_EN` generic)
| `19` | `SYSINFO_SOC_IO_TWI`     | set if <<_two_wire_serial_interface_controller_twi>> is implemented (via top's `IO_TWI_EN` generic)
| `20` | `SYSINFO_SOC_IO_PWM`     | set if <<_pulse_width_modulation_controller_pwm>> is implemented (via top's `IO_PWM_NUM` generic)
| `21` | `SYSINFO_SOC_IO_WDT`     | set if <<_watchdog_timer_wdt>> is implemented (via top's `IO_WDT_EN` generic)
| `22` | `SYSINFO_SOC_IO_CFS`     | set if <<_custom_functions_subsystem_cfs>> is implemented (via top's `IO_CFS_EN` generic)
| `23` | `SYSINFO_SOC_IO_TRNG`    | set if <<_true_random_number_generator_trng>> is implemented (via top's `IO_TRNG_EN` generic)
| `24` | `SYSINFO_SOC_IO_SDI`     | set if <<_serial_data_interface_controller_sdi>> is implemented (via top's `IO_SDI_EN` generic)
| `25` | `SYSINFO_SOC_IO_UART1`   | set if <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1>> is implemented (via top's `IO_UART1_EN` generic)
| `26` | `SYSINFO_SOC_IO_NEOLED`  | set if <<_smart_led_interface_neoled>> is implemented (via top's `IO_NEOLED_EN` generic)
| `27` | `SYSINFO_SOC_IO_TRACER`  | set if <<_execution_trace_buffer_tracer>> is implemented (via top's `IO_TRACER_EN` generic)
| `28` | `SYSINFO_SOC_IO_GPTMR`   | set if <<_general_purpose_timer_gptmr>> is implemented (via top's `IO_GPTMR_NUM` generic)
| `29` | `SYSINFO_SOC_IO_SLINK`   | set if <<_stream_link_interface_slink>> is implemented (via top's `IO_SLINK_EN` generic)
| `30` | `SYSINFO_SOC_IO_ONEWIRE` | set if <<_one_wire_serial_interface_controller_onewire>> interface is implemented (via top's `IO_ONEWIRE_EN` generic)
| `31` | `SYSINFO_SOC_SIM`        | set if NEORV32 is being simulated
|=======================


===== SYSINFO - Cache Configuration

The SYSINFO cache register provides information about the configuration of the processor caches:

* <<_instruction_cache_icache>>
* <<_data_cache_dcache>>

.SYSINFO `CACHE` Bits
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|=======================
| Bit     | Name [C] | Description
| `3:0`   | `SYSINFO_CACHE_BLOCK_SIZE_3 : SYSINFO_CACHE_BLOCK_SIZE_0`     | _log2_(cache block size in bytes), via top's `CACHE_BLOCK_SIZE` generic
| `7:4`   | `SYSINFO_CACHE_I_NUM_BLOCKS_3 : SYSINFO_CACHE_I_NUM_BLOCKS_0` | _log2_(i-cache number of cache blocks), via top's `ICACHE_NUM_BLOCKS` generic
| `11:8`  | `SYSINFO_CACHE_D_NUM_BLOCKS_3 : SYSINFO_CACHE_D_NUM_BLOCKS_0` | _log2_(d-cache number of cache blocks), via top's `DCACHE_NUM_BLOCKS` generic
| `15:12` | `SYSINFO_CACHE_UC_BEGIN_3 : SYSINFO_CACHE_UC_BEGIN_0`         | start of non-cached address space, 256MB page, via top's `CACHE_UC_BASE` generic
| `16`    | `SYSINFO_CACHE_BURSTS_EN`                                     | cache burst transfers enabled, via top's `CACHE_BURSTS_EN` generic
| `31:17` | -                                                             | _reserved_, read as zero
|=======================
