<<<
:sectnums:
== Overview

The NEORV32 RISC-V Processor is an open-source RISC-V compatible processor system that is intended as
*ready-to-go* auxiliary processor within a larger SoC designs or as stand-alone custom / customizable
microcontroller.

The system is highly configurable and provides optional common peripherals like embedded memories,
timers, serial interfaces, general purpose IO ports and an external bus interface to connect custom IP like
memories, NoCs and other peripherals. On-line and in-system debugging is supported by an OpenOCD/gdb
compatible on-chip debugger accessible via JTAG.

Special focus is paid on **execution safety** to provide defined and predictable behavior at any time.
Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions
are executed. Whenever an unexpected situation occurs, the application code is informed via hardware exceptions.

The software framework of the processor comes with application makefiles, software libraries for all CPU
and processor features, a bootloader, a runtime environment and several example programs - including a port
of the CoreMark MCU benchmark and the official RISC-V architecture test suite. RISC-V GCC is used as
default toolchain.

Check out the processor's **https://stnolting.github.io/neorv32/ug[online User Guide]**
that provides hands-on tutorials to get you started.


**Structure**

[start=2]
. <<_neorv32_processor_soc>>
. <<_neorv32_central_processing_unit_cpu>>
. <<_software_framework>>
. <<_on_chip_debugger_ocd>>
. <<_legal>>


<<<
// ####################################################################################################################
:sectnums:
=== Project Key Features

**Project**

* all-in-one package: **CPU** + **SoC** + **Software Framework & Tooling**
* completely described in behavioral, platform-independent VHDL - no vendor- or technology-specific primitives, attributes, macros, libraries, etc. are used at all
* all-Verilog "version" available (auto-generated by GHDL)
* extensive configuration options for adapting the processor to the requirements of the application
* highly extensible hardware - on CPU, SoC and system level
* aims to be as small as possible while being as RISC-V-compliant as possible - with a reasonable area-vs-performance trade-off
* FPGA friendly (e.g. all internal memories can be mapped to block RAM - including the register file)
* optimized for high clock frequencies to ease timing closure and integration
* from zero to _"hello world!"_ - completely open source and documented
* easy to use even for FPGA/RISC-V starters – intended to _work out of the box_

**NEORV32 CPU (the core)**

* 32-bit RISC-V CPU
* official RISC-V open source architecture ID
* fully compatible to the RISC-V ISA specs. - checked by the official RISC-V architecture compatibility tests
* base ISA + privileged ISA + several optional standard and custom ISA extensions
* option to add user-defined RISC-V instructions as custom ISA extension
* rich set of customization options (ISA extensions, design goal: performance / area / energy, tuning options, ...)
* <<_full_virtualization>> capabilities to increase execution safety
* full execution tracing; compatible to the RISC-V formal interface spec (RVFI)

**NEORV32 Processor (the SoC)**

* highly-configurable full-scale microcontroller-like processor system
* based on the NEORV32 CPU
* optional standard serial interfaces (UART, TWI, SPI (host and device), 1-Wire)
* optional timers and counters (watchdog, system timer)
* optional general purpose IO and PWM; a native NeoPixel(c)-compatible smart LED interface
* optional embedded memories and caches for data, instructions and bootloader
* optional serial memory interface controller (supporting XIP)
* optional external memory interface for custom connectivity
* optional DMA controller for CPU-independent data transfers
* on-chip debugger compatible with OpenOCD and GDB including hardware trigger module and optional authentication

**Software framework**

* written in C and based on GCC
* internal bootloader with serial user interface (via UART)
* core libraries and HAL for high-level usage of the provided functions and peripherals
* processor-specific runtime environment and several example programs
* Doxygen-based documentation of the software framework; a deployed version is available at https://stnolting.github.io/neorv32/sw/files.html
* Ada support at https://github.com/GNAT-Academic-Program/neorv32-hal

**OS Support**

* FreeRTOS port: https://github.com/stnolting/neorv32-freertos
* Upstream Zephyr support: https://docs.zephyrproject.org/latest/boards/others/neorv32/doc/index.html
* MicroPython port: https://github.com/stnolting/neorv32-micropython

**Extensibility and Customization**

The NEORV32 processor is designed to ease customization and extensibility and provides several options for adding
application-specific custom hardware modules and accelerators. The three most common options for adding custom
on-chip modules are listed below.

* <<_processor_external_bus_interface_xbus>> to attach processor-external IP modules (memories and peripherals)
* <<_custom_functions_subsystem_cfs>> for tightly-coupled processor-internal co-processors
* <<_custom_functions_unit_cfu>> for custom RISC-V instructions

[TIP]
A more detailed comparison of the extension/customization options can be found in section
https://stnolting.github.io/neorv32/ug/#_adding_custom_hardware_modules[Adding Custom Hardware Modules]
of the user guide.


<<<
// ####################################################################################################################
:sectnums:
=== Project Folder Structure

The root directory of the repository is considered the NEORV32 base or home folder (i.e. `neorv32/`).

.Folder Structure
...................................
neorv32                   - Project home folder
│
├─ docs                   - Documentation
│  ├─ datasheet           - AsciiDoc sources for the NEORV32 data sheet
│  ├─ figures             - Figures and logos
│  └─ userguide           - AsciiDoc sources for the NEORV32 user guide
│
├─ rtl                    - HDL sources
│  ├─ core                - Core sources of the CPU & SoC
│  ├─ system_integration  - System wrappers and bridges for advanced SoC connectivity
│  ├─ test_setups         - Minimal test setup "SoCs" used in the User Guide
│  └─ verilog             - Scripts and examples for converting NEORV32 to Verilog
│
├─ sim                    - Simulation files
│
└─ sw                     - Software framework
   ├─ bootloader          - Sources of the default builtin bootloader
   ├─ common              - Linker script, crt0.S start-up code and central makefile
   ├─ example             - Example programs for the core and the SoC modules
   │  ├─ eclipse          - Pre-configured Eclipse IDE project
   │  └─ ...              - Several example programs
   ├─ image_gen           - Helper program to generate executables & memory images
   ├─ lib                 - NEORV32 core library
   ├─ ocd_firmware        - Firmware for the on-chip debugger "park loop"
   ├─ openocd             - OpenOCD configuration files
   └─ svd                 - Processor system view description file (CMSIS-SVD)
...................................



<<<
// ####################################################################################################################
:sectnums:
=== VHDL File Hierarchy

All required VHDL hardware source files are located in the project's `rtl/core` folder.

.VHDL Library
[IMPORTANT]
All core VHDL files from the list below have to be assigned to a **new library** named `neorv32`.

.Compilation Order
[NOTE]
See section <<_file_list_file>> for more information.

.Replacing Modules for Customization or Optimization (Especially Memory Modules)
[TIP]
Any module of the core can be replaced for customization purpose.
For ASIC implementations (and for some FPGA implementations), this is particularly recommended for
the underlying memories. Therefore, all (larger) memories are encapsulated as easily replaceable IP
wrappers (i.e. `*_ram.vhd` and `*_rom.vhd` files). By default, these wrappers use a generic memory
description that should infer blockRAM on most FPGA platforms.

.RTL File List (in alphabetical order)
...................................
rtl/core
│
├─ neorv32_bootrom.vhd           - Bootloader ROM
├─ neorv32_bootrom_image.vhd     - Bootloader ROM initialization image
├─ neorv32_bus.vhd               - SoC bus infrastructure modules
├─ neorv32_cache.vhd             - Generic cache module
├─ neorv32_cache_ram.vhd         - Cache tag and data RAM
├─ neorv32_cfs.vhd               - Custom functions subsystem
├─ neorv32_clint.vhd             - Core local interruptor
├─ neorv32_cpu.vhd               - NEORV32 CPU TOP ENTITY
├─ neorv32_cpu_alu.vhd           - Arithmetic/logic unit
├─ neorv32_cpu_control.vhd       - CPU control, exception system and CSRs
├─ neorv32_cpu_counters.vhd      - Hardware counters (Zicntr & Zihpm ext.)
├─ neorv32_cpu_alu_bitmanip.vhd  - Bit-manipulation unit (B ext.)
├─ neorv32_cpu_alu_cfu.vhd       - Custom instructions unit (Xcfu ext.)
├─ neorv32_cpu_alu_cond.vhd      - Integer conditional unit (Zicond ext.)
├─ neorv32_cpu_alu_crypto.vhd    - Scalar cryptography unit (Zk*/Zbk* ext.)
├─ neorv32_cpu_alu_fpu.vhd       - Floating-point unit (Zfinx ext.)
├─ neorv32_cpu_alu_muldiv.vhd    - Integer MUL/DIV unit (M ext.)
├─ neorv32_cpu_alu_shifter.vhd   - Bit-shift unit (base ISA)
├─ neorv32_cpu_decompressor.vhd  - Compressed instructions decoder (C ext.)
├─ neorv32_cpu_frontend.vhd      - Instruction fetch and issue
├─ neorv32_cpu_hwtrig.vhd        - Hardware trigger module (Sdtrig ext.)
├─ neorv32_cpu_lsu.vhd           - Load/store unit
├─ neorv32_cpu_pmp.vhd           - Physical memory protection unit (Smpmp ext.)
├─ neorv32_cpu_regfile.vhd       - Data register file
├─ neorv32_cpu_trace.vhd         - Trace generator
├─ neorv32_debug_auth.vhd        - On-chip debugger: authentication module
├─ neorv32_debug_dm.vhd          - On-chip debugger: debug module
├─ neorv32_debug_dtm.vhd         - On-chip debugger: debug transfer module
├─ neorv32_dma.vhd               - Direct memory access controller
├─ neorv32_dmem.vhd              - Data memory
├─ neorv32_gpio.vhd              - General purpose input/output port unit
├─ neorv32_gptmr.vhd             - General purpose 32-bit timer
├─ neorv32_imem.vhd              - Instruction memory
├─ neorv32_imem_image.vhd        - Instruction memory initialization image
├─ neorv32_neoled.vhd            - NeoPixel (TM) compatible smart LED interface
├─ neorv32_onewire.vhd           - One-Wire serial interface controller
├─ neorv32_package.vhd           - Main VHDL package file
├─ neorv32_prim.vhd              - Generic RTL primitives
├─ neorv32_pwm.vhd               - Pulse-width modulation controller
├─ neorv32_sdi.vhd               - Serial data interface controller (SPI device)
├─ neorv32_slink.vhd             - Stream link interface
├─ neorv32_smc.vhd               - Serial memory controller
├─ neorv32_spi.vhd               - Serial peripheral interface controller (SPI host)
├─ neorv32_sys.vhd               - System infrastructure modules
├─ neorv32_sysinfo.vhd           - System configuration information memory
├─ neorv32_top.vhd               - NEORV32 PROCESSOR/SOC TOP ENTITY
├─ neorv32_tracer.vhd            - Instruction trace buffer
├─ neorv32_trng.vhd              - True random number generator
├─ neorv32_twd.vhd               - Two wire serial device controller
├─ neorv32_twi.vhd               - Two wire serial interface controller
├─ neorv32_uart.vhd              - Universal async. receiver/transmitter
├─ neorv32_wdt.vhd               - Watchdog timer
└─ neorv32_xbus.vhd              - External bus interface gateway
...................................


:sectnums:
==== File-List File

Most of the RTL sources use **entity instantiation**. Hence, the RTL compile order might be relevant (depending on
the synthesis/simulation tool. Therefore, a file-list file is provided in the `rtl` folder that list all required
HDL files for the entire processor and also represent their recommended compile order. Note that
this file lists the architecture "bottom-up" - the according top entity is listed in the very last line.
The file-list file can be consumed by EDA tools to simplify project setup.

* `file_list_core.f` - HDL files and compile order for the entire processor/SoC; top module: `neorv32_top`

A simple bash script `file_list_regenerate.sh` is provided for regenerating the file-list (using GHDL's _elaborate_ command).
This script can also be invoked using the default application makefile (see <<_makefile_targets>>).

By default, the file-list file includes a **placeholder** (`$NEORV32_HOME`) in the path of each included hardware
source file. These placeholders need to be replaced/substituted by the actual path before being used. Example:

* default: `$NEORV32_HOME/rtl/core/neorv32_package.vhd`
* substituted: `path/to/neorv32/rtl/core/neorv32_package.vhd`


**Example: Makefile**

.Processing the File-List Files in a Makefile
[source,makefile]
----
NEORV32_HOME  ?= path/to/neorv32 <1>
NEORV32_FFILE := $(shell cat $(NEORV32_HOME)/rtl/file_list_core.f) <2>
NEORV32_SRCS  := $(subst $$NEORV32_HOME,$(NEORV32_HOME),$(NEORV32_FFILE)) <3>
----
<1> Path to the NEORV32 home folder (i.e. the root folder of the GitHub repository).
<2> Load the content of the `file_list_core.f` file-list into a variable `NEORV32_SOC_FILE`.
<3> Substitute the file-list file's path placeholder "`$NEORV32_HOME`" by the actual path and store to `NEORV32_SRCS` variable.

**Example: TCL**

.Processing the File-List Files in a TCL Script
[source,tcl]
----
set neorv32_home path/to/neorv32 <1>
set file_list_file [read [open "$neorv32_home/rtl/file_list_core.f" r]] <2>
set file_list [string map [list {$NEORV32_HOME} $neorv32_home] $file_list_file] <3>
----
<1> Path to the NEORV32 home folder (i.e. the root folder of the GitHub repository).
<2> Load the content of the `file_list_core.f` file-list into a variable `file_list_file`.
<3> Substitute the file-list file's path placeholder "`$NEORV32_HOME`" by the actual path and store to `file_list` variable.

**Example: Bash**

.Processing the File-List Files in a Bash Script
[source,bash]
----
neorv32/rtl$ export NEORV32_HOME=path/to/neorv32 <1>
neorv32/rtl$ envsubst < file_list_core.f > file_list.f <2>
----
<1> Set path to the NEORV32 home folder (i.e. the root folder of the GitHub repository) as environment variable.
<2> Substitute `$NEORV32_HOME` by the content of the according environment variable and store to `file_list.f` file.


<<<
// ####################################################################################################################
:sectnums:
=== VHDL Coding Style

* The entire processor, including the CPU core, is written in platform-/technology-independent VHDL.
The code makes minimal use of VHDL 2008 features in order to remain compatible with older EDA tools.
* A specific VHDL library `neorv32` is used for all sources.
* All registers in the control path use an asynchronous reset. The registers in the data path do not
have a dedicated reset if their state is gated by a "valid" signal. This allows using of smaller FFs
and relaxes the reset routing.
* The entire setup uses a single clock domain. External "clock" signals are synchronized into this
clock domain using 2-stage shift registers.
* A single package/library file (`neorv32_package.vhd`) is used to provide global definitions and auxiliary functions.
The user-defined configuration is done entirely via the generics of the top entity.
* Internally, all generics are checked to ensure correct configuration.
Asserts are used to inform the user about the actual processor configuration and possible invalid settings.
* The code uses entity instantiation for all internal modules. However, if multiple submodules are specified within the
same source file, component instantiation is used for them. * When instantiating the top-level processor module
(`neorv32_top.vhd`) in a user-defined design, either entity instantiation or component instantiation can be used,
as the NEORV32 package file/library file already provides a corresponding component declaration.
* Certain modules are explicitly designed to be replaced by external (Verilog) IP.
See section <<_replaceable_modules>> for more information.


<<<
// ####################################################################################################################
:sectnums:
=== Verilog-Only and Mixed-Language Setups

NEORV32 is developed in VHDL. However, the project also supports Verilog-based and mixed-language
tool flows for users who cannot (or do not want to) work with VHDL directly.
There are two main approaches to integrate NEORV32 into a Verilog design:

[start=1]
. **Mixed-language design:** If your EDA toolchain supports mixed VHDL/Verilog designs, you can instantiate the
NEORV32 processor top entity directly from your Verilog project. No conversion is required in this case.
. **All-Verilog design:** If your EDA toolchain does *not* support mixed-language designs, NEORV32 provides a
GHDL-based conversion flow that generates a plain-Verilog version of the entire processor. See section
<<_convert_to_verilog>> for a detailed description of this flow.

Additionally, certain SoC modules (for example the processor-internal instruction and data memories) are specifically
designed so that they can be replaced by external, custom (Verilog) modules — for example to integrate
technology-specific memory IP. This mechanism works independently of the full all-Verilog conversion flow.
All modules that can be replaced by external IP are listed in section <<_replaceable_modules>>.


:sectnums:
==== Convert to Verilog

The free and open **GHDL** can be used to generate an **all-Verilog** version of NEORV32. GHDL's synthesis feature
is used to convert a pre-configured NEORV32 setup - including all peripherals, memories and memory images - into
a single plain-Verilog module. A pre-defined conversion setup is provided in `rtl/verilog`.

.GHDL Synthesis
[TIP]
More information regarding GHDL's synthesis option can be found at https://ghdl.github.io/ghdl/using/Synthesis.html.

An intermediate VHDL wrapper (`rtl/verilog/neorv32_verilog_wrapper.vhd`) is used to configure the SoC
(using VHDL generics) and to customize the interface ports. After conversion, a single Verilog file is generated
(`rtl/verilog/neorv32_verilog_wrapper.v`) that contains the entire NEORV32 processor.

The actual conversion is conducted by a single Makefile (`rtl/verilog/Makefile`), which analyzes all the processor's
sources and finally calls GHDL `synth` to create the final Verilog code. After conversion, the interface of the resulting
`neorv32_verilog_wrapper` Verilog module is shown in the console which can be used as instantiation template.

[source,bash]
----
neorv32/rtl/verilog$ make convert
Converting to Verilog: neorv32_verilog_wrapper.vhd -> neorv32_verilog_wrapper.v

...

-----------------------------------------------
Verilog instantiation prototype
-----------------------------------------------
module neorv32_verilog_wrapper
  (input  clk_i,
   input  rstn_i,
   input  uart0_rxd_i,
   output uart0_txd_o);
-----------------------------------------------
----

.Replace NEORV32 Components by Verilog Modules
[TIP]
The pre-defined conversion setup also allows to replace certain VHDL modules of the core by according
Verilog modules for simulation. See the Readme in `rtl/verilog` for more information. A list of all
SoC modules that can be replaced by Verilog modules is provided in section <<_replaceable_modules>>.

**Conversion Notes**

* GHDL synthesis generates an un-optimized plain Verilog code without any (technology-specific) primitives.
However, optimizations will be performed later by the technology-specific synthesis tool.
* The output of the GHDL synthesis is a _post-elaboration_ result. Therefore, all the processor's configuration
options (i.e. VHDL generics) are resolved **before** the actual output is generated. Hence, the entity of the
conversion wrapper must not have any generics.
* The interface of the resulting Verilog module lists all inputs first followed by all outputs.
* The original module hierarchy is preserved as well as all module interface names.
* VHDL records are collapsed into linear arrays.
* Modules that follow the component-instantiation conventions described in
<<Replacing SoC Modules with External Components>> convert cleanly into this flow, since their black-box,
late-binding-compatible interfaces are already restricted to simple, statically-sized `std_ulogic` /
`std_ulogic_vector` ports.


<<<
// ####################################################################################################################
:sectnums:
=== Performance

**Area Utilization**

The NEORV32 processor is optimized for minimal size. However, the actual size (silicon area or FPGA resources)
depends on the specific configuration. For example, an RTOS-capable setup based on a `rv32imc_Zicsr_Zicntr` CPU
configuration including peripheral and memories requires about 2300 LUTs and 1000 FFs and can run at up to 130 MHz
(implementation results for an Altera Cyclone IV E `EP4CE22F17C6` FPGA).

.NEORV32 Setups
[TIP]
The processor has been successfully ported to AMD, Altera, Lattice, Microchip, Gowin, Cologne Chip
and NanoXplore FPGAs. Some pre-configured example setup are available online: https://github.com/stnolting/neorv32-setups

**Processing Speed**

The computational performance of the NEORV32 is evaluated using https://www.eembc.org/coremark/[Core Mark CPU benchmark].
The NEORV32 CoreMark port can be found in a separate repository: https://github.com/stnolting/neorv32-coremark[neorv32-coremark]

.CoreMark Results
[cols="<6,^2,^2"]
[options="header",grid="rows"]
|=======================
| CPU Configuration                                        | CoreMark Score | CoreMarks/MHz
| _small_ (`rv32i_Zicsr_Zifencei`)                         |          33.89 | **0.33**
| _medium_ (`rv32imc_Zicsr_Zifencei`)                      |          62.50 | **0.62**
| _performance_ (`rv32imc_Zicsr_Zifencei` + perf. options) |          95.23 | **0.95**
| _dual-core_ (`rv32imc_Zicsr_Zifencei` + perf. options)   |         190.47 | **1.90**
|=======================

Performance can be further improved by enabling additional ISA extensions. Note that the compiler
also needs to support these extensions (make sure to use a `multilib` GCC configuration for optimal
code results).

The NEORV32 CPU is based on a multi-cycle architecture. Each instruction is executed in a sequence of
several consecutive micro operations. The average CPI (cycles per instruction) depends on the instruction
mix of a specific applications and also on the available CPU extensions, tuning options and memory latency.


// ####################################################################################################################
:sectnums:
=== RISC-V Compatibility

The NEORV32 CPU passes the official **RISC-V Architectural Certification Tests (ACTs)** to "_certify it faithfully
implements the RISC-V specification_". The NEORV32 port of this test framework is available at
https://github.com/stnolting/neorv32-riscv-act.

++++
<details>
<summary><b>ACT Results</b> for NEORV32 v1.13.3.1, 24th of July, 2026 (click to expand)</summary>
<pre>
RESULT: All 301 tests passed.
priv/ExceptionsSm/ExceptionsSm-00.log              RVCP-SUMMARY: TEST PASSED - Test File "ExceptionsSm-00.S"
priv/ExceptionsU/ExceptionsU-00.log                RVCP-SUMMARY: TEST PASSED - Test File "ExceptionsU-00.S"
priv/ExceptionsZaamo/ExceptionsZaamo-00.log        RVCP-SUMMARY: TEST PASSED - Test File "ExceptionsZaamo-00.S"
priv/ExceptionsZalrsc/ExceptionsZalrsc-00.log      RVCP-SUMMARY: TEST PASSED - Test File "ExceptionsZalrsc-00.S"
priv/ExceptionsZc/ExceptionsZc-00.log              RVCP-SUMMARY: TEST PASSED - Test File "ExceptionsZc-00.S"
priv/ExceptionsZicboU/ExceptionsZicboU-00.log      RVCP-SUMMARY: TEST PASSED - Test File "ExceptionsZicboU-00.S"
priv/InterruptsSm/InterruptsSm-00.log              RVCP-SUMMARY: TEST PASSED - Test File "InterruptsSm-00.S"
priv/InterruptsU/InterruptsU-00.log                RVCP-SUMMARY: TEST PASSED - Test File "InterruptsU-00.S"
priv/SsstrictSm/SsstrictSm-12.log                  RVCP-SUMMARY: TEST PASSED - Test File "SsstrictSm-12.S"
priv/SsstrictSm/SsstrictSm-13.log                  RVCP-SUMMARY: TEST PASSED - Test File "SsstrictSm-13.S"
priv/SsstrictSm/SsstrictSm-14.log                  RVCP-SUMMARY: TEST PASSED - Test File "SsstrictSm-14.S"
priv/U/U-00.log                                    RVCP-SUMMARY: TEST PASSED - Test File "U-00.S"
priv/ZicntrU/ZicntrU-00.log                        RVCP-SUMMARY: TEST PASSED - Test File "ZicntrU-00.S"
priv/pmp/pmp32/PMPSm/pmpsm_all_entries_check.log   RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_all_entries_check.S"
priv/pmp/pmp32/PMPSm/pmpsm_cfg_A_all.log           RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_cfg_A_all.S"
priv/pmp/pmp32/PMPSm/pmpsm_cfg_A_off_all.log       RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_cfg_A_off_all.S"
priv/pmp/pmp32/PMPSm/pmpsm_cfg_A_tor_bot.log       RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_cfg_A_tor_bot.S"
priv/pmp/pmp32/PMPSm/pmpsm_cfg_A_tor_zero.log      RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_cfg_A_tor_zero.S"
priv/pmp/pmp32/PMPSm/pmpsm_cfg_L_access_all.log    RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_cfg_L_access_all.S"
priv/pmp/pmp32/PMPSm/pmpsm_cfg_L_modify_napot.log  RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_cfg_L_modify_napot.S"
priv/pmp/pmp32/PMPSm/pmpsm_cfg_L_modify_off.log    RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_cfg_L_modify_off.S"
priv/pmp/pmp32/PMPSm/pmpsm_cfg_L_modify_tor.log    RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_cfg_L_modify_tor.S"
priv/pmp/pmp32/PMPSm/pmpsm_cfg_XWR_all-01.log      RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_cfg_XWR_all-01.S"
priv/pmp/pmp32/PMPSm/pmpsm_cfg_XWR_all-02.log      RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_cfg_XWR_all-02.S"
priv/pmp/pmp32/PMPSm/pmpsm_cfg_XWR_all-03.log      RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_cfg_XWR_all-03.S"
priv/pmp/pmp32/PMPSm/pmpsm_cfg_XWR_all-04.log      RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_cfg_XWR_all-04.S"
priv/pmp/pmp32/PMPSm/pmpsm_cfg_na4_all.log         RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_cfg_na4_all.S"
priv/pmp/pmp32/PMPSm/pmpsm_cfg_napot_all.log       RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_cfg_napot_all.S"
priv/pmp/pmp32/PMPSm/pmpsm_cfg_tor_all.log         RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_cfg_tor_all.S"
priv/pmp/pmp32/PMPSm/pmpsm_cfg_tor_check-01.log    RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_cfg_tor_check-01.S"
priv/pmp/pmp32/PMPSm/pmpsm_cfg_tor_check-02.log    RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_cfg_tor_check-02.S"
priv/pmp/pmp32/PMPSm/pmpsm_cfg_tor_check-03.log    RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_cfg_tor_check-03.S"
priv/pmp/pmp32/PMPSm/pmpsm_csr_walk-1.log          RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_csr_walk-01.S"
priv/pmp/pmp32/PMPSm/pmpsm_csr_walk-10.log         RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_csr_walk-10.S"
priv/pmp/pmp32/PMPSm/pmpsm_csr_walk-2.log          RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_csr_walk-02.S"
priv/pmp/pmp32/PMPSm/pmpsm_csr_walk-3.log          RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_csr_walk-03.S"
priv/pmp/pmp32/PMPSm/pmpsm_csr_walk-4.log          RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_csr_walk-04.S"
priv/pmp/pmp32/PMPSm/pmpsm_csr_walk-5.log          RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_csr_walk-05.S"
priv/pmp/pmp32/PMPSm/pmpsm_csr_walk-6.log          RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_csr_walk-06.S"
priv/pmp/pmp32/PMPSm/pmpsm_csr_walk-7.log          RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_csr_walk-07.S"
priv/pmp/pmp32/PMPSm/pmpsm_csr_walk-8.log          RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_csr_walk-08.S"
priv/pmp/pmp32/PMPSm/pmpsm_csr_walk-9.log          RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_csr_walk-09.S"
priv/pmp/pmp32/PMPSm/pmpsm_grain.log               RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_grain.S"
priv/pmp/pmp32/PMPSm/pmpsm_grain_check.log         RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_grain_check.S"
priv/pmp/pmp32/PMPSm/pmpsm_na4_legal_lwxr.log      RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_cfg_napot_all.S"
priv/pmp/pmp32/PMPSm/pmpsm_napot_legal_lwxr.log    RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_napot_legal_lwxr.S"
priv/pmp/pmp32/PMPSm/pmpsm_priority.log            RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_priority.S"
priv/pmp/pmp32/PMPSm/pmpsm_priority_off.log        RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_priority_off.S"
priv/pmp/pmp32/PMPSm/pmpsm_tor_legal_lwxr-01.log   RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_tor_legal_lwxr.S"
priv/pmp/pmp32/PMPSm/pmpsm_tor_legal_lwxr-02.log   RVCP-SUMMARY: TEST PASSED - Test File "pmpsm_tor_legal_lwxr.S"
priv/pmp/pmp32/PMPU/pmpu_cfg_A_off.log             RVCP-SUMMARY: TEST PASSED - Test File "pmpu_cfg_A_all.S"
priv/pmp/pmp32/PMPU/pmpu_cfg_XWR.log               RVCP-SUMMARY: TEST PASSED - Test File "pmpu_cfg_XWR.S"
priv/pmp/pmp32/PMPU/pmpu_cfg_XWR_unlocked.log      RVCP-SUMMARY: TEST PASSED - Test File "pmpu_cfg_XWR_unlocked.S"
priv/pmp/pmp32/PMPU/pmpu_csr_access.log            RVCP-SUMMARY: TEST PASSED - Test File "pmpu_csr_access.S"
priv/pmp/pmp32/PMPU/pmpu_mprv_check-01.log         RVCP-SUMMARY: TEST PASSED - Test File "pmpu_mprv_check-01.S"
priv/pmp/pmp32/PMPU/pmpu_mprv_check-02.log         RVCP-SUMMARY: TEST PASSED - Test File "pmpu_mprv_check-02.S"
priv/pmp/pmp32/PMPU/pmpu_napot_legal_lxwr-01.log   RVCP-SUMMARY: TEST PASSED - Test File "pmpu_napot_legal_lxwr.S"
priv/pmp/pmp32/PMPU/pmpu_napot_legal_lxwr-02.log   RVCP-SUMMARY: TEST PASSED - Test File "pmps_napot_legal_lxwr.S"
priv/pmp/pmp32/PMPU/pmpu_tor_legal_lxwr-01.log     RVCP-SUMMARY: TEST PASSED - Test File "pmpu_tor_legal_lxwr.S"
priv/pmp/pmp32/PMPU/pmpu_tor_legal_lxwr-02.log     RVCP-SUMMARY: TEST PASSED - Test File "pmpu_tor_legal_lxwr.S"
priv/pmp/pmp32/PMPZaamo/pmpzaamo_cfg_wr.log        RVCP-SUMMARY: TEST PASSED - Test File "pmpzaamo_cfg_wr.S"
priv/pmp/pmp32/PMPZalrsc/pmpzalrsc_cfg_wr.log      RVCP-SUMMARY: TEST PASSED - Test File "pmpzalrsc_cfg_wrS"
priv/pmp/pmp32/PMPZca/pmpzca_aligned_na4.log       RVCP-SUMMARY: TEST PASSED - Test File "pmpzca_aligned_na4.S"
priv/pmp/pmp32/PMPZca/pmpzca_aligned_napot.log     RVCP-SUMMARY: TEST PASSED - Test File "pmpzca_aligned_napot.S"
priv/pmp/pmp32/PMPZca/pmpzca_aligned_off.log       RVCP-SUMMARY: TEST PASSED - Test File "pmpzca_aligned_off.S"
priv/pmp/pmp32/PMPZca/pmpzca_aligned_tor.log       RVCP-SUMMARY: TEST PASSED - Test File "pmpzca_aligned_tor.S"
priv/pmp/pmp32/PMPZca/pmpzca_cret_na4.log          RVCP-SUMMARY: TEST PASSED - Test File "pmpzca_cret_napot.S"
priv/pmp/pmp32/PMPZca/pmpzca_cret_napot.log        RVCP-SUMMARY: TEST PASSED - Test File "pmpzca_cret_napot.S"
priv/pmp/pmp32/PMPZca/pmpzca_cret_tor.log          RVCP-SUMMARY: TEST PASSED - Test File "pmpzca_cret_napot.S"
priv/pmp/pmp32/PMPZca/pmpzca_legal_lwrx.log        RVCP-SUMMARY: TEST PASSED - Test File "pmpzca_legal_lxwr.S"
priv/pmp/pmp32/PMPZca/pmpzca_misaligned_na4.log    RVCP-SUMMARY: TEST PASSED - Test File "pmpzca_aligned_na4.S"
priv/pmp/pmp32/PMPZca/pmpzca_misaligned_napot.log  RVCP-SUMMARY: TEST PASSED - Test File "pmpzca_misaligned_napot.S"
priv/pmp/pmp32/PMPZca/pmpzca_misaligned_off.log    RVCP-SUMMARY: TEST PASSED - Test File "pmpzca_misaligned_off.S"
priv/pmp/pmp32/PMPZca/pmpzca_misaligned_tor.log    RVCP-SUMMARY: TEST PASSED - Test File "pmpzca_misaligned_tor.S"
priv/pmp/pmp32/PMPZca/pmpzcb_legal_lxwr.log        RVCP-SUMMARY: TEST PASSED - Test File "pmpzcb_legal_lwxr.S"
rv32i/I/I-add-00.log                               RVCP-SUMMARY: TEST PASSED - Test File "I-add-00.S"
rv32i/I/I-addi-00.log                              RVCP-SUMMARY: TEST PASSED - Test File "I-addi-00.S"
rv32i/I/I-and-00.log                               RVCP-SUMMARY: TEST PASSED - Test File "I-and-00.S"
rv32i/I/I-andi-00.log                              RVCP-SUMMARY: TEST PASSED - Test File "I-andi-00.S"
rv32i/I/I-auipc-00.log                             RVCP-SUMMARY: TEST PASSED - Test File "I-auipc-00.S"
rv32i/I/I-beq-00.log                               RVCP-SUMMARY: TEST PASSED - Test File "I-beq-00.S"
rv32i/I/I-bge-00.log                               RVCP-SUMMARY: TEST PASSED - Test File "I-bge-00.S"
rv32i/I/I-bgeu-00.log                              RVCP-SUMMARY: TEST PASSED - Test File "I-bgeu-00.S"
rv32i/I/I-blt-00.log                               RVCP-SUMMARY: TEST PASSED - Test File "I-blt-00.S"
rv32i/I/I-bltu-00.log                              RVCP-SUMMARY: TEST PASSED - Test File "I-bltu-00.S"
rv32i/I/I-bne-00.log                               RVCP-SUMMARY: TEST PASSED - Test File "I-bne-00.S"
rv32i/I/I-fence-00.log                             RVCP-SUMMARY: TEST PASSED - Test File "I-fence-00.S"
rv32i/I/I-jal-00.log                               RVCP-SUMMARY: TEST PASSED - Test File "I-jal-00.S"
rv32i/I/I-jalr-00.log                              RVCP-SUMMARY: TEST PASSED - Test File "I-jalr-00.S"
rv32i/I/I-lb-00.log                                RVCP-SUMMARY: TEST PASSED - Test File "I-lb-00.S"
rv32i/I/I-lbu-00.log                               RVCP-SUMMARY: TEST PASSED - Test File "I-lbu-00.S"
rv32i/I/I-lh-00.log                                RVCP-SUMMARY: TEST PASSED - Test File "I-lh-00.S"
rv32i/I/I-lhu-00.log                               RVCP-SUMMARY: TEST PASSED - Test File "I-lhu-00.S"
rv32i/I/I-lui-00.log                               RVCP-SUMMARY: TEST PASSED - Test File "I-lui-00.S"
rv32i/I/I-lw-00.log                                RVCP-SUMMARY: TEST PASSED - Test File "I-lw-00.S"
rv32i/I/I-nop-00.log                               RVCP-SUMMARY: TEST PASSED - Test File "I-nop-00.S"
rv32i/I/I-or-00.log                                RVCP-SUMMARY: TEST PASSED - Test File "I-or-00.S"
rv32i/I/I-ori-00.log                               RVCP-SUMMARY: TEST PASSED - Test File "I-ori-00.S"
rv32i/I/I-sb-00.log                                RVCP-SUMMARY: TEST PASSED - Test File "I-sb-00.S"
rv32i/I/I-sh-00.log                                RVCP-SUMMARY: TEST PASSED - Test File "I-sh-00.S"
rv32i/I/I-sll-00.log                               RVCP-SUMMARY: TEST PASSED - Test File "I-sll-00.S"
rv32i/I/I-slli-00.log                              RVCP-SUMMARY: TEST PASSED - Test File "I-slli-00.S"
rv32i/I/I-slt-00.log                               RVCP-SUMMARY: TEST PASSED - Test File "I-slt-00.S"
rv32i/I/I-slti-00.log                              RVCP-SUMMARY: TEST PASSED - Test File "I-slti-00.S"
rv32i/I/I-sltiu-00.log                             RVCP-SUMMARY: TEST PASSED - Test File "I-sltiu-00.S"
rv32i/I/I-sltu-00.log                              RVCP-SUMMARY: TEST PASSED - Test File "I-sltu-00.S"
rv32i/I/I-sra-00.log                               RVCP-SUMMARY: TEST PASSED - Test File "I-sra-00.S"
rv32i/I/I-srai-00.log                              RVCP-SUMMARY: TEST PASSED - Test File "I-srai-00.S"
rv32i/I/I-srl-00.log                               RVCP-SUMMARY: TEST PASSED - Test File "I-srl-00.S"
rv32i/I/I-srli-00.log                              RVCP-SUMMARY: TEST PASSED - Test File "I-srli-00.S"
rv32i/I/I-sub-00.log                               RVCP-SUMMARY: TEST PASSED - Test File "I-sub-00.S"
rv32i/I/I-sw-00.log                                RVCP-SUMMARY: TEST PASSED - Test File "I-sw-00.S"
rv32i/I/I-xor-00.log                               RVCP-SUMMARY: TEST PASSED - Test File "I-xor-00.S"
rv32i/I/I-xori-00.log                              RVCP-SUMMARY: TEST PASSED - Test File "I-xori-00.S"
rv32i/M/M-div-00.log                               RVCP-SUMMARY: TEST PASSED - Test File "M-div-00.S"
rv32i/M/M-divu-00.log                              RVCP-SUMMARY: TEST PASSED - Test File "M-divu-00.S"
rv32i/M/M-mul-00.log                               RVCP-SUMMARY: TEST PASSED - Test File "M-mul-00.S"
rv32i/M/M-mulh-00.log                              RVCP-SUMMARY: TEST PASSED - Test File "M-mulh-00.S"
rv32i/M/M-mulhsu-00.log                            RVCP-SUMMARY: TEST PASSED - Test File "M-mulhsu-00.S"
rv32i/M/M-mulhu-00.log                             RVCP-SUMMARY: TEST PASSED - Test File "M-mulhu-00.S"
rv32i/M/M-rem-00.log                               RVCP-SUMMARY: TEST PASSED - Test File "M-rem-00.S"
rv32i/M/M-remu-00.log                              RVCP-SUMMARY: TEST PASSED - Test File "M-remu-00.S"
rv32i/Zaamo/Zaamo-amoadd.w-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zaamo-amoadd.w-00.S"
rv32i/Zaamo/Zaamo-amoand.w-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zaamo-amoand.w-00.S"
rv32i/Zaamo/Zaamo-amomax.w-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zaamo-amomax.w-00.S"
rv32i/Zaamo/Zaamo-amomaxu.w-00.log                 RVCP-SUMMARY: TEST PASSED - Test File "Zaamo-amomaxu.w-00.S"
rv32i/Zaamo/Zaamo-amomin.w-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zaamo-amomin.w-00.S"
rv32i/Zaamo/Zaamo-amominu.w-00.log                 RVCP-SUMMARY: TEST PASSED - Test File "Zaamo-amominu.w-00.S"
rv32i/Zaamo/Zaamo-amoor.w-00.log                   RVCP-SUMMARY: TEST PASSED - Test File "Zaamo-amoor.w-00.S"
rv32i/Zaamo/Zaamo-amoswap.w-00.log                 RVCP-SUMMARY: TEST PASSED - Test File "Zaamo-amoswap.w-00.S"
rv32i/Zaamo/Zaamo-amoxor.w-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zaamo-amoxor.w-00.S"
rv32i/Zalrsc/Zalrsc-lr.w-00.log                    RVCP-SUMMARY: TEST PASSED - Test File "Zalrsc-lr.w-00.S"
rv32i/Zalrsc/Zalrsc-sc.w-00.log                    RVCP-SUMMARY: TEST PASSED - Test File "Zalrsc-sc.w-00.S"
rv32i/Zba/Zba-sh1add-00.log                        RVCP-SUMMARY: TEST PASSED - Test File "Zba-sh1add-00.S"
rv32i/Zba/Zba-sh2add-00.log                        RVCP-SUMMARY: TEST PASSED - Test File "Zba-sh2add-00.S"
rv32i/Zba/Zba-sh3add-00.log                        RVCP-SUMMARY: TEST PASSED - Test File "Zba-sh3add-00.S"
rv32i/Zbb/Zbb-andn-00.log                          RVCP-SUMMARY: TEST PASSED - Test File "Zbb-andn-00.S"
rv32i/Zbb/Zbb-clz-00.log                           RVCP-SUMMARY: TEST PASSED - Test File "Zbb-clz-00.S"
rv32i/Zbb/Zbb-cpop-00.log                          RVCP-SUMMARY: TEST PASSED - Test File "Zbb-cpop-00.S"
rv32i/Zbb/Zbb-ctz-00.log                           RVCP-SUMMARY: TEST PASSED - Test File "Zbb-ctz-00.S"
rv32i/Zbb/Zbb-max-00.log                           RVCP-SUMMARY: TEST PASSED - Test File "Zbb-max-00.S"
rv32i/Zbb/Zbb-maxu-00.log                          RVCP-SUMMARY: TEST PASSED - Test File "Zbb-maxu-00.S"
rv32i/Zbb/Zbb-min-00.log                           RVCP-SUMMARY: TEST PASSED - Test File "Zbb-min-00.S"
rv32i/Zbb/Zbb-minu-00.log                          RVCP-SUMMARY: TEST PASSED - Test File "Zbb-minu-00.S"
rv32i/Zbb/Zbb-orc.b-00.log                         RVCP-SUMMARY: TEST PASSED - Test File "Zbb-orc.b-00.S"
rv32i/Zbb/Zbb-orn-00.log                           RVCP-SUMMARY: TEST PASSED - Test File "Zbb-orn-00.S"
rv32i/Zbb/Zbb-rev8-00.log                          RVCP-SUMMARY: TEST PASSED - Test File "Zbb-rev8-00.S"
rv32i/Zbb/Zbb-rol-00.log                           RVCP-SUMMARY: TEST PASSED - Test File "Zbb-rol-00.S"
rv32i/Zbb/Zbb-ror-00.log                           RVCP-SUMMARY: TEST PASSED - Test File "Zbb-ror-00.S"
rv32i/Zbb/Zbb-rori-00.log                          RVCP-SUMMARY: TEST PASSED - Test File "Zbb-rori-00.S"
rv32i/Zbb/Zbb-sext.b-00.log                        RVCP-SUMMARY: TEST PASSED - Test File "Zbb-sext.b-00.S"
rv32i/Zbb/Zbb-sext.h-00.log                        RVCP-SUMMARY: TEST PASSED - Test File "Zbb-sext.h-00.S"
rv32i/Zbb/Zbb-xnor-00.log                          RVCP-SUMMARY: TEST PASSED - Test File "Zbb-xnor-00.S"
rv32i/Zbb/Zbb-zext.h-00.log                        RVCP-SUMMARY: TEST PASSED - Test File "Zbb-zext.h-00.S"
rv32i/Zbc/Zbc-clmul-00.log                         RVCP-SUMMARY: TEST PASSED - Test File "Zbc-clmul-00.S"
rv32i/Zbc/Zbc-clmulh-00.log                        RVCP-SUMMARY: TEST PASSED - Test File "Zbc-clmulh-00.S"
rv32i/Zbc/Zbc-clmulr-00.log                        RVCP-SUMMARY: TEST PASSED - Test File "Zbc-clmulr-00.S"
rv32i/Zbkb/Zbkb-andn-00.log                        RVCP-SUMMARY: TEST PASSED - Test File "Zbkb-andn-00.S"
rv32i/Zbkb/Zbkb-brev8-00.log                       RVCP-SUMMARY: TEST PASSED - Test File "Zbkb-brev8-00.S"
rv32i/Zbkb/Zbkb-orn-00.log                         RVCP-SUMMARY: TEST PASSED - Test File "Zbkb-orn-00.S"
rv32i/Zbkb/Zbkb-pack-00.log                        RVCP-SUMMARY: TEST PASSED - Test File "Zbkb-pack-00.S"
rv32i/Zbkb/Zbkb-packh-00.log                       RVCP-SUMMARY: TEST PASSED - Test File "Zbkb-packh-00.S"
rv32i/Zbkb/Zbkb-rev8-00.log                        RVCP-SUMMARY: TEST PASSED - Test File "Zbkb-rev8-00.S"
rv32i/Zbkb/Zbkb-rol-00.log                         RVCP-SUMMARY: TEST PASSED - Test File "Zbkb-rol-00.S"
rv32i/Zbkb/Zbkb-ror-00.log                         RVCP-SUMMARY: TEST PASSED - Test File "Zbkb-ror-00.S"
rv32i/Zbkb/Zbkb-rori-00.log                        RVCP-SUMMARY: TEST PASSED - Test File "Zbkb-rori-00.S"
rv32i/Zbkb/Zbkb-unzip-00.log                       RVCP-SUMMARY: TEST PASSED - Test File "Zbkb-unzip-00.S"
rv32i/Zbkb/Zbkb-xnor-00.log                        RVCP-SUMMARY: TEST PASSED - Test File "Zbkb-xnor-00.S"
rv32i/Zbkb/Zbkb-zip-00.log                         RVCP-SUMMARY: TEST PASSED - Test File "Zbkb-zip-00.S"
rv32i/Zbkc/Zbkc-clmul-00.log                       RVCP-SUMMARY: TEST PASSED - Test File "Zbkc-clmul-00.S"
rv32i/Zbkc/Zbkc-clmulh-00.log                      RVCP-SUMMARY: TEST PASSED - Test File "Zbkc-clmulh-00.S"
rv32i/Zbkx/Zbkx-xperm4-00.log                      RVCP-SUMMARY: TEST PASSED - Test File "Zbkx-xperm4-00.S"
rv32i/Zbkx/Zbkx-xperm8-00.log                      RVCP-SUMMARY: TEST PASSED - Test File "Zbkx-xperm8-00.S"
rv32i/Zbs/Zbs-bclr-00.log                          RVCP-SUMMARY: TEST PASSED - Test File "Zbs-bclr-00.S"
rv32i/Zbs/Zbs-bclri-00.log                         RVCP-SUMMARY: TEST PASSED - Test File "Zbs-bclri-00.S"
rv32i/Zbs/Zbs-bext-00.log                          RVCP-SUMMARY: TEST PASSED - Test File "Zbs-bext-00.S"
rv32i/Zbs/Zbs-bexti-00.log                         RVCP-SUMMARY: TEST PASSED - Test File "Zbs-bexti-00.S"
rv32i/Zbs/Zbs-binv-00.log                          RVCP-SUMMARY: TEST PASSED - Test File "Zbs-binv-00.S"
rv32i/Zbs/Zbs-binvi-00.log                         RVCP-SUMMARY: TEST PASSED - Test File "Zbs-binvi-00.S"
rv32i/Zbs/Zbs-bset-00.log                          RVCP-SUMMARY: TEST PASSED - Test File "Zbs-bset-00.S"
rv32i/Zbs/Zbs-bseti-00.log                         RVCP-SUMMARY: TEST PASSED - Test File "Zbs-bseti-00.S"
rv32i/Zca/Zca-c.add-00.log                         RVCP-SUMMARY: TEST PASSED - Test File "Zca-c.add-00.S"
rv32i/Zca/Zca-c.addi-00.log                        RVCP-SUMMARY: TEST PASSED - Test File "Zca-c.addi-00.S"
rv32i/Zca/Zca-c.addi16sp-00.log                    RVCP-SUMMARY: TEST PASSED - Test File "Zca-c.addi16sp-00.S"
rv32i/Zca/Zca-c.addi4spn-00.log                    RVCP-SUMMARY: TEST PASSED - Test File "Zca-c.addi4spn-00.S"
rv32i/Zca/Zca-c.and-00.log                         RVCP-SUMMARY: TEST PASSED - Test File "Zca-c.and-00.S"
rv32i/Zca/Zca-c.andi-00.log                        RVCP-SUMMARY: TEST PASSED - Test File "Zca-c.andi-00.S"
rv32i/Zca/Zca-c.beqz-00.log                        RVCP-SUMMARY: TEST PASSED - Test File "Zca-c.beqz-00.S"
rv32i/Zca/Zca-c.bnez-00.log                        RVCP-SUMMARY: TEST PASSED - Test File "Zca-c.bnez-00.S"
rv32i/Zca/Zca-c.j-00.log                           RVCP-SUMMARY: TEST PASSED - Test File "Zca-c.j-00.S"
rv32i/Zca/Zca-c.jal-00.log                         RVCP-SUMMARY: TEST PASSED - Test File "Zca-c.jal-00.S"
rv32i/Zca/Zca-c.jalr-00.log                        RVCP-SUMMARY: TEST PASSED - Test File "Zca-c.jalr-00.S"
rv32i/Zca/Zca-c.jr-00.log                          RVCP-SUMMARY: TEST PASSED - Test File "Zca-c.jr-00.S"
rv32i/Zca/Zca-c.li-00.log                          RVCP-SUMMARY: TEST PASSED - Test File "Zca-c.li-00.S"
rv32i/Zca/Zca-c.lui-00.log                         RVCP-SUMMARY: TEST PASSED - Test File "Zca-c.lui-00.S"
rv32i/Zca/Zca-c.lw-00.log                          RVCP-SUMMARY: TEST PASSED - Test File "Zca-c.lw-00.S"
rv32i/Zca/Zca-c.lwsp-00.log                        RVCP-SUMMARY: TEST PASSED - Test File "Zca-c.lwsp-00.S"
rv32i/Zca/Zca-c.mv-00.log                          RVCP-SUMMARY: TEST PASSED - Test File "Zca-c.mv-00.S"
rv32i/Zca/Zca-c.nop-00.log                         RVCP-SUMMARY: TEST PASSED - Test File "Zca-c.nop-00.S"
rv32i/Zca/Zca-c.or-00.log                          RVCP-SUMMARY: TEST PASSED - Test File "Zca-c.or-00.S"
rv32i/Zca/Zca-c.slli-00.log                        RVCP-SUMMARY: TEST PASSED - Test File "Zca-c.slli-00.S"
rv32i/Zca/Zca-c.srai-00.log                        RVCP-SUMMARY: TEST PASSED - Test File "Zca-c.srai-00.S"
rv32i/Zca/Zca-c.srli-00.log                        RVCP-SUMMARY: TEST PASSED - Test File "Zca-c.srli-00.S"
rv32i/Zca/Zca-c.sub-00.log                         RVCP-SUMMARY: TEST PASSED - Test File "Zca-c.sub-00.S"
rv32i/Zca/Zca-c.sw-00.log                          RVCP-SUMMARY: TEST PASSED - Test File "Zca-c.sw-00.S"
rv32i/Zca/Zca-c.swsp-00.log                        RVCP-SUMMARY: TEST PASSED - Test File "Zca-c.swsp-00.S"
rv32i/Zca/Zca-c.xor-00.log                         RVCP-SUMMARY: TEST PASSED - Test File "Zca-c.xor-00.S"
rv32i/Zcb/Zcb-c.lbu-00.log                         RVCP-SUMMARY: TEST PASSED - Test File "Zcb-c.lbu-00.S"
rv32i/Zcb/Zcb-c.lh-00.log                          RVCP-SUMMARY: TEST PASSED - Test File "Zcb-c.lh-00.S"
rv32i/Zcb/Zcb-c.lhu-00.log                         RVCP-SUMMARY: TEST PASSED - Test File "Zcb-c.lhu-00.S"
rv32i/Zcb/Zcb-c.not-00.log                         RVCP-SUMMARY: TEST PASSED - Test File "Zcb-c.not-00.S"
rv32i/Zcb/Zcb-c.sb-00.log                          RVCP-SUMMARY: TEST PASSED - Test File "Zcb-c.sb-00.S"
rv32i/Zcb/Zcb-c.sh-00.log                          RVCP-SUMMARY: TEST PASSED - Test File "Zcb-c.sh-00.S"
rv32i/Zcb/Zcb-c.zext.b-00.log                      RVCP-SUMMARY: TEST PASSED - Test File "Zcb-c.zext.b-00.S"
rv32i/ZcbM/ZcbM-c.mul-00.log                       RVCP-SUMMARY: TEST PASSED - Test File "ZcbM-c.mul-00.S"
rv32i/ZcbZbb/ZcbZbb-c.sext.b-00.log                RVCP-SUMMARY: TEST PASSED - Test File "ZcbZbb-c.sext.b-00.S"
rv32i/ZcbZbb/ZcbZbb-c.sext.h-00.log                RVCP-SUMMARY: TEST PASSED - Test File "ZcbZbb-c.sext.h-00.S"
rv32i/ZcbZbb/ZcbZbb-c.zext.h-00.log                RVCP-SUMMARY: TEST PASSED - Test File "ZcbZbb-c.zext.h-00.S"
rv32i/Zcmop/Zcmop-c.mop.1-00.log                   RVCP-SUMMARY: TEST PASSED - Test File "Zcmop-c.mop.1-00.S"
rv32i/Zcmop/Zcmop-c.mop.11-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zcmop-c.mop.11-00.S"
rv32i/Zcmop/Zcmop-c.mop.13-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zcmop-c.mop.13-00.S"
rv32i/Zcmop/Zcmop-c.mop.15-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zcmop-c.mop.15-00.S"
rv32i/Zcmop/Zcmop-c.mop.3-00.log                   RVCP-SUMMARY: TEST PASSED - Test File "Zcmop-c.mop.3-00.S"
rv32i/Zcmop/Zcmop-c.mop.5-00.log                   RVCP-SUMMARY: TEST PASSED - Test File "Zcmop-c.mop.5-00.S"
rv32i/Zcmop/Zcmop-c.mop.7-00.log                   RVCP-SUMMARY: TEST PASSED - Test File "Zcmop-c.mop.7-00.S"
rv32i/Zcmop/Zcmop-c.mop.9-00.log                   RVCP-SUMMARY: TEST PASSED - Test File "Zcmop-c.mop.9-00.S"
rv32i/Zicntr/Zicntr-csrrc-00.log                   RVCP-SUMMARY: TEST PASSED - Test File "Zicntr-csrrc-00.S"
rv32i/Zicntr/Zicntr-csrrs-00.log                   RVCP-SUMMARY: TEST PASSED - Test File "Zicntr-csrrs-00.S"
rv32i/Zicond/Zicond-czero.eqz-00.log               RVCP-SUMMARY: TEST PASSED - Test File "Zicond-czero.eqz-00.S"
rv32i/Zicond/Zicond-czero.nez-00.log               RVCP-SUMMARY: TEST PASSED - Test File "Zicond-czero.nez-00.S"
rv32i/Zicsr/Zicsr-csrrc-00.log                     RVCP-SUMMARY: TEST PASSED - Test File "Zicsr-csrrc-00.S"
rv32i/Zicsr/Zicsr-csrrci-00.log                    RVCP-SUMMARY: TEST PASSED - Test File "Zicsr-csrrci-00.S"
rv32i/Zicsr/Zicsr-csrrs-00.log                     RVCP-SUMMARY: TEST PASSED - Test File "Zicsr-csrrs-00.S"
rv32i/Zicsr/Zicsr-csrrsi-00.log                    RVCP-SUMMARY: TEST PASSED - Test File "Zicsr-csrrsi-00.S"
rv32i/Zicsr/Zicsr-csrrw-00.log                     RVCP-SUMMARY: TEST PASSED - Test File "Zicsr-csrrw-00.S"
rv32i/Zicsr/Zicsr-csrrwi-00.log                    RVCP-SUMMARY: TEST PASSED - Test File "Zicsr-csrrwi-00.S"
rv32i/Zifencei/Zifencei-fence.i-00.log             RVCP-SUMMARY: TEST PASSED - Test File "Zifencei-fence.i-00.S"
rv32i/Zihpm/Zihpm-csrrc-00.log                     RVCP-SUMMARY: TEST PASSED - Test File "Zihpm-csrrc-00.S"
rv32i/Zihpm/Zihpm-csrrs-00.log                     RVCP-SUMMARY: TEST PASSED - Test File "Zihpm-csrrs-00.S"
rv32i/Zimop/Zimop-mop.r.0-00.log                   RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.0-00.S"
rv32i/Zimop/Zimop-mop.r.1-00.log                   RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.1-00.S"
rv32i/Zimop/Zimop-mop.r.10-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.10-00.S"
rv32i/Zimop/Zimop-mop.r.11-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.11-00.S"
rv32i/Zimop/Zimop-mop.r.12-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.12-00.S"
rv32i/Zimop/Zimop-mop.r.13-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.13-00.S"
rv32i/Zimop/Zimop-mop.r.14-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.14-00.S"
rv32i/Zimop/Zimop-mop.r.15-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.15-00.S"
rv32i/Zimop/Zimop-mop.r.16-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.16-00.S"
rv32i/Zimop/Zimop-mop.r.17-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.17-00.S"
rv32i/Zimop/Zimop-mop.r.18-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.18-00.S"
rv32i/Zimop/Zimop-mop.r.19-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.19-00.S"
rv32i/Zimop/Zimop-mop.r.2-00.log                   RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.2-00.S"
rv32i/Zimop/Zimop-mop.r.20-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.20-00.S"
rv32i/Zimop/Zimop-mop.r.21-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.21-00.S"
rv32i/Zimop/Zimop-mop.r.22-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.22-00.S"
rv32i/Zimop/Zimop-mop.r.23-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.23-00.S"
rv32i/Zimop/Zimop-mop.r.24-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.24-00.S"
rv32i/Zimop/Zimop-mop.r.25-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.25-00.S"
rv32i/Zimop/Zimop-mop.r.26-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.26-00.S"
rv32i/Zimop/Zimop-mop.r.27-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.27-00.S"
rv32i/Zimop/Zimop-mop.r.28-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.28-00.S"
rv32i/Zimop/Zimop-mop.r.29-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.29-00.S"
rv32i/Zimop/Zimop-mop.r.3-00.log                   RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.3-00.S"
rv32i/Zimop/Zimop-mop.r.30-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.30-00.S"
rv32i/Zimop/Zimop-mop.r.31-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.31-00.S"
rv32i/Zimop/Zimop-mop.r.4-00.log                   RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.4-00.S"
rv32i/Zimop/Zimop-mop.r.5-00.log                   RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.5-00.S"
rv32i/Zimop/Zimop-mop.r.6-00.log                   RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.6-00.S"
rv32i/Zimop/Zimop-mop.r.7-00.log                   RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.7-00.S"
rv32i/Zimop/Zimop-mop.r.8-00.log                   RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.8-00.S"
rv32i/Zimop/Zimop-mop.r.9-00.log                   RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.r.9-00.S"
rv32i/Zimop/Zimop-mop.rr.0-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.rr.0-00.S"
rv32i/Zimop/Zimop-mop.rr.1-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.rr.1-00.S"
rv32i/Zimop/Zimop-mop.rr.2-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.rr.2-00.S"
rv32i/Zimop/Zimop-mop.rr.3-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.rr.3-00.S"
rv32i/Zimop/Zimop-mop.rr.4-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.rr.4-00.S"
rv32i/Zimop/Zimop-mop.rr.5-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.rr.5-00.S"
rv32i/Zimop/Zimop-mop.rr.6-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.rr.6-00.S"
rv32i/Zimop/Zimop-mop.rr.7-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zimop-mop.rr.7-00.S"
rv32i/Zknd/Zknd-aes32dsi-00.log                    RVCP-SUMMARY: TEST PASSED - Test File "Zknd-aes32dsi-00.S"
rv32i/Zknd/Zknd-aes32dsmi-00.log                   RVCP-SUMMARY: TEST PASSED - Test File "Zknd-aes32dsmi-00.S"
rv32i/Zkne/Zkne-aes32esi-00.log                    RVCP-SUMMARY: TEST PASSED - Test File "Zkne-aes32esi-00.S"
rv32i/Zkne/Zkne-aes32esmi-00.log                   RVCP-SUMMARY: TEST PASSED - Test File "Zkne-aes32esmi-00.S"
rv32i/Zknh/Zknh-sha256sig0-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zknh-sha256sig0-00.S"
rv32i/Zknh/Zknh-sha256sig1-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zknh-sha256sig1-00.S"
rv32i/Zknh/Zknh-sha256sum0-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zknh-sha256sum0-00.S"
rv32i/Zknh/Zknh-sha256sum1-00.log                  RVCP-SUMMARY: TEST PASSED - Test File "Zknh-sha256sum1-00.S"
rv32i/Zknh/Zknh-sha512sig0h-00.log                 RVCP-SUMMARY: TEST PASSED - Test File "Zknh-sha512sig0h-00.S"
rv32i/Zknh/Zknh-sha512sig0l-00.log                 RVCP-SUMMARY: TEST PASSED - Test File "Zknh-sha512sig0l-00.S"
rv32i/Zknh/Zknh-sha512sig1h-00.log                 RVCP-SUMMARY: TEST PASSED - Test File "Zknh-sha512sig1h-00.S"
rv32i/Zknh/Zknh-sha512sig1l-00.log                 RVCP-SUMMARY: TEST PASSED - Test File "Zknh-sha512sig1l-00.S"
rv32i/Zknh/Zknh-sha512sum0r-00.log                 RVCP-SUMMARY: TEST PASSED - Test File "Zknh-sha512sum0r-00.S"
rv32i/Zknh/Zknh-sha512sum1r-00.log                 RVCP-SUMMARY: TEST PASSED - Test File "Zknh-sha512sum1r-00.S"
rv32i/Zksed/Zksed-sm4ed-00.log                     RVCP-SUMMARY: TEST PASSED - Test File "Zksed-sm4ed-00.S"
rv32i/Zksed/Zksed-sm4ks-00.log                     RVCP-SUMMARY: TEST PASSED - Test File "Zksed-sm4ks-00.S"
rv32i/Zksh/Zksh-sm3p0-00.log                       RVCP-SUMMARY: TEST PASSED - Test File "Zksh-sm3p0-00.S"
rv32i/Zksh/Zksh-sm3p1-00.log                       RVCP-SUMMARY: TEST PASSED - Test File "Zksh-sm3p1-00.S"
rv32i/Zmmul/Zmmul-mul-00.log                       RVCP-SUMMARY: TEST PASSED - Test File "Zmmul-mul-00.S"
rv32i/Zmmul/Zmmul-mulh-00.log                      RVCP-SUMMARY: TEST PASSED - Test File "Zmmul-mulh-00.S"
rv32i/Zmmul/Zmmul-mulhsu-00.log                    RVCP-SUMMARY: TEST PASSED - Test File "Zmmul-mulhsu-00.S"
rv32i/Zmmul/Zmmul-mulhu-00.log                     RVCP-SUMMARY: TEST PASSED - Test File "Zmmul-mulhu-00.S"
</pre>
</details>
++++


.Unsupported/Unavailable ISA Extensions and Illegal Instruction
[TIP]
Executing instructions or accessing CSRs from unsupported ISA extensions will raise a precise illegal
instruction exception allowing full software emulation (see section <<_full_virtualization>>).


// ####################################################################################################################
:sectnums:
=== RISC-V Documentation

The ratified RISC-V specifications (ISA specs, frameworks, ABI, etc.) are available online at riscv.org:

* **https://docs.riscv.org/reference/home**

Additional resources and specs currently under development are available on GitHub:

* ISA Specifications: https://github.com/riscv)
* Non-ISA Specifications: https://github.com/riscv-non-isa
* RISC-V Software: https://github.com/riscv-software-src

Elementary software references:

* RISC-V C API: https://github.com/riscv-non-isa/riscv-c-api-doc
* RISC-V ELF psABI: https://github.com/riscv-non-isa/riscv-elf-psabi-doc
