#  NERV -- Naive Educational RISC-V Processor
#
#  Copyright (C) 2020  Claire Xenia Wolf <claire@yosyshq.com>
#
#  Permission to use, copy, modify, and/or distribute this software for any
#  purpose with or without fee is hereby granted, provided that the above
#  copyright notice and this permission notice appear in all copies.
#
#  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
#  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
#  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
#  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
#  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
#  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
#  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

[options]
isa rv32ib
nbus 2
# csr_spec 1.12

[depth]
insn            10
reg        5    10
pc_fwd     5    10
pc_bwd     5    10
unique     1  5 10
causal     5    10
cover      1    10
ill             10
csrw            10
csr_ill         10

bus_imem            1    10
bus_imem_fault      1    10
bus_dmem            1    10
bus_dmem_fault      1    10
csrc_zero  1    5
csrc_any   1    5
csrc_inc   1    5
csrc_const 1    5
csrc_upcnt 1    10
csrc_hpm   1    10

[sort]
reg_ch0
bus_[id]mem(_fault)?_ch0
insn_[ls][bhw]u?_ch0
csrc_upcnt_(.*)_ch0

[csrs]
mcycle          upcnt
minstret        upcnt
mhpmcounter5    inc
mhpmevent5      hpm=1
mhpmevent9      hpm=2
mhpmevent3      hpm=3
mstatus

[custom_csrs]
fc0     m       custom_ro       const="32'h dead_beef"
bc0     mu      custom          any

[illegal_csrs]
fff     msu     rw
f11     m       w

[defines]
`define YOSYS // Hotfix for older Tabby CAD Releases
`define NERV_RVFI
`define NERV_FAULT
`define RISCV_FORMAL_ALIGNED_MEM
`define RISCV_FORMAL_MEM_FAULT


[defines liveness]
`define NERV_FAIRNESS

[verilog-files]
@basedir@/cores/@core@/wrapper.sv
@basedir@/cores/@core@/@core@.sv

[cover]
always @* if (!reset) cover (channel[0].cnt_insns == 2);
always @* if (!reset) cover (rvfi_csr_mstatus_rdata[3] != 0 && rvfi_valid == 1);