[*]
[*] GTKWave Analyzer v3.3.108 (w)1999-2020 BSI
[*] Tue Nov  3 15:34:10 2020
[*]
[dumpfile] "/home/matt/work/symbiotic/riscv-formal/cores/nerv/examples/icebreaker/testbench.vcd"
[dumpfile_mtime] "Tue Nov  3 15:33:50 2020"
[dumpfile_size] 472777
[savefile] "/home/matt/work/symbiotic/riscv-formal/cores/nerv/examples/icebreaker/testbench.gtkw"
[timestart] 0
[size] 1920 1015
[pos] -1 -1
*-11.000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] testbench.
[treeopen] testbench.dut.
[treeopen] testbench.dut.soc.
[sst_width] 240
[signals_width] 286
[sst_expanded] 1
[sst_vpaned_height] 289
@28
testbench.LEDR_N
testbench.LEDG_N
testbench.LED1
testbench.LED2
testbench.LED3
testbench.LED4
testbench.LED5
@201
-
@28
testbench.clock
@22
testbench.cycles[31:0]
@200
-
@28
testbench.dut.soc.clock
@22
testbench.dut.soc.dmem_addr[31:0]
testbench.dut.soc.dmem_rdata[31:0]
@28
testbench.dut.soc.dmem_valid
@22
testbench.dut.soc.dmem_wdata[31:0]
testbench.dut.soc.dmem_wstrb[3:0]
testbench.dut.soc.imem_addr[31:0]
testbench.dut.soc.imem_data[31:0]
testbench.dut.soc.leds[31:0]
@28
testbench.dut.soc.reset
testbench.dut.soc.stall
testbench.dut.soc.trap
[pattern_trace] 1
[pattern_trace] 0