#  NERV -- Naive Educational RISC-V Processor
#
#  Copyright (C) 2020  Claire Xenia Wolf <claire@yosyshq.com>
#  Copyright (C) 2023  Jannis Harder <jix@yosyshq.com> <me@jix.one>
#
#  Permission to use, copy, modify, and/or distribute this software for any
#  purpose with or without fee is hereby granted, provided that the above
#  copyright notice and this permission notice appear in all copies.
#
#  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
#  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
#  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
#  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
#  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
#  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
#  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

[options]
isa rv32i
nbus 3
buslen 256
mode bmc
solver boolector

[depth]
bus_imem            1    14
bus_imem_fault      1    14
bus_dmem            1    14
bus_dmem_fault      1    14

[csrs]
mcause

[defines]
`define YOSYS // Hotfix for older Tabby CAD Releases
`define NERV_RVFI
`define NERV_FAULT
`define RISCV_FORMAL_ALIGNED_MEM
`define RISCV_FORMAL_MEM_FAULT

[defines liveness]
`define NERV_FAIRNESS

[verilog-files]
@basedir@/cores/@core@/axi_cache/wrapper_internal.sv
@basedir@/cores/@core@/@core@.sv
@basedir@/cores/@core@/axi_cache/nerv_axi_cache_icache.sv
@basedir@/cores/@core@/axi_cache/nerv_axi_cache_dcache.sv