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Report generated on 2022-03-18 19:48 GMT by riscof v

## Environment

Riscof Version | 1.23.4
Riscv-arch-test Version/Commit Id | 2.7.1
DUT | nox
Reference | sail c simulator
ISA | RV32I
User Spec Version | 2.3
Privilege Spec Version | 1.11

## Yaml

Name
/test/riscof_compliance/riscof_work/nox_isa_checked.yaml
hart_ids: [0] hart0: ISA: RV32I physical_addr_sz: 32 User_Spec_Version: '2.3' Privilege_Spec_Version: '1.11' hw_data_misaligned_support: false supported_xlen: - 32 misa: reset-val: 0x40000100 rv32: accessible: true mxl: implemented: true type: warl: dependency_fields: [] legal: - mxl[1:0] in [0x1] wr_illegal: - Unchanged description: Encodes the native base integer ISA width. shadow: shadow_type: rw msb: 31 lsb: 30 extensions: implemented: true type: warl: dependency_fields: [] legal: - extensions[25:0] bitmask [0x0001104, 0x0000000] wr_illegal: - Unchanged description: Encodes the presence of the standard extensions, with a single bit per letter of the alphabet. shadow: shadow_type: rw msb: 25 lsb: 0 fields: - extensions - mxl - - - 26 - 29 description: misa is a read-write register reporting the ISA supported by the hart. address: 769 priv_mode: M rv64: accessible: false pmp_granularity: 0 custom_exceptions: custom_interrupts: mstatus: rv32: accessible: true fields: - uie - sie - mie - upie - spie - mpie - spp - mpp - fs - xs - mprv - sum - mxr - tvm - tw - tsr - sd - - - 2 - - 6 - - 9 - 10 - - 23 - 30 uie: implemented: false description: Stores the state of the user mode interrupts. shadow: shadow_type: rw msb: 0 lsb: 0 sie: implemented: false description: Stores the state of the supervisor mode interrupts. shadow: shadow_type: rw msb: 1 lsb: 1 mie: implemented: true description: Stores the state of the machine mode interrupts. shadow: shadow_type: rw msb: 3 lsb: 3 type: wlrl: - 0:1 upie: implemented: false description: Stores the state of the user mode interrupts prior to the trap. shadow: shadow_type: rw msb: 4 lsb: 4 spie: implemented: false description: Stores the state of the supervisor mode interrupts prior to the trap. shadow: shadow_type: rw msb: 5 lsb: 5 mpie: implemented: true description: Stores the state of the machine mode interrupts prior to the trap. shadow: shadow_type: rw msb: 7 lsb: 7 type: wlrl: - 0:1 spp: implemented: false description: Stores the previous priority mode for supervisor. shadow: shadow_type: rw msb: 8 lsb: 8 mpp: implemented: true description: Stores the previous priority mode for machine. shadow: shadow_type: rw msb: 12 lsb: 11 type: {ro_constant: 0} fs: implemented: false description: Encodes the status of the floating-point unit, including the CSR fcsr and floating-point data registers. shadow: shadow_type: rw msb: 14 lsb: 13 xs: implemented: false description: Encodes the status of additional user-mode extensions and associated state. shadow: shadow_type: rw msb: 16 lsb: 15 mprv: implemented: false description: Modifies the privilege level at which loads and stores execute in all privilege modes. shadow: shadow_type: rw msb: 17 lsb: 17 sum: implemented: false description: Modifies the privilege with which S-mode loads and stores access virtual memory. shadow: shadow_type: rw msb: 18 lsb: 18 mxr: implemented: false description: Modifies the privilege with which loads access virtual memory. shadow: shadow_type: rw msb: 19 lsb: 19 tvm: implemented: false description: Supports intercepting supervisor virtual-memory management operations. shadow: shadow_type: rw msb: 20 lsb: 20 tw: implemented: false description: Supports intercepting the WFI instruction. shadow: shadow_type: rw msb: 21 lsb: 21 tsr: implemented: false description: Supports intercepting the supervisor exception return instruction. shadow: shadow_type: rw msb: 22 lsb: 22 sd: implemented: false description: Read-only bit that summarizes whether either the FS field or XS field signals the presence of some dirty state. shadow: shadow_type: rw msb: 31 lsb: 31 rv64: accessible: false description: The mstatus register keeps track of and controls the hart’s current operating state. address: 768 priv_mode: M reset-val: 0 mstatush: rv32: accessible: true fields: - sbe - mbe - gva - mpv - - - 0 - 3 - - 8 - 31 mpv: implemented: false description: Stores the state of the user mode interrupts. shadow: shadow_type: rw msb: 7 lsb: 7 gva: implemented: false description: Stores the state of the supervisor mode interrupts. shadow: shadow_type: rw msb: 6 lsb: 6 mbe: implemented: false description: control the endianness of memory accesses other than instruction fetches for machine mode shadow: shadow_type: rw msb: 5 lsb: 5 sbe: implemented: false description: control the endianness of memory accesses other than instruction fetches for supervisor mode shadow: shadow_type: rw msb: 4 lsb: 4 rv64: accessible: false description: The mstatush register keeps track of and controls the hart’s current operating state. address: 768 priv_mode: M reset-val: 0 mvendorid: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: ro_constant: 0 rv64: accessible: false description: 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core. address: 3857 priv_mode: M reset-val: 0 marchid: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: ro_constant: 0 rv64: accessible: false description: MXLEN-bit read-only register encoding the base microarchitecture of the hart. address: 3858 priv_mode: M reset-val: 0 mimpid: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: ro_constant: 0 rv64: accessible: false description: Provides a unique encoding of the version of the processor implementation. address: 3859 priv_mode: M reset-val: 0 mhartid: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: ro_constant: 0 rv64: accessible: false description: MXLEN-bit read-only register containing the integer ID of the hardware thread running the code. address: 3860 priv_mode: M reset-val: 0 mtvec: rv32: accessible: true fields: - mode - base base: implemented: true description: Vector base address. shadow: shadow_type: rw msb: 31 lsb: 2 type: warl: dependency_fields: [] legal: - base[29:0] bitmask [0x3FFFFFFF, 0x00000000] wr_illegal: - Unchanged mode: implemented: true description: Vector mode. shadow: shadow_type: rw msb: 1 lsb: 0 type: warl: dependency_fields: [] legal: - mode[1:0] in [0x0,0x1] wr_illegal: - Unchanged rv64: accessible: false description: MXLEN-bit read/write register that holds trap vector configuration. address: 773 priv_mode: M reset-val: 0 mideleg: rv32: accessible: false rv64: accessible: false description: Machine Interrupt delegation Register. address: 771 priv_mode: M reset-val: 0 medeleg: rv32: accessible: false rv64: accessible: false description: Machine Exception delegation Register. address: 770 priv_mode: M reset-val: 0 mip: rv32: accessible: true fields: - usip - ssip - vssip - msip - utip - stip - vstip - mtip - ueip - seip - vseip - meip - sgeip - - - 13 - 31 usip: implemented: false description: User Software Interrupt Pending. shadow: shadow_type: rw msb: 0 lsb: 0 ssip: implemented: false description: Supervisor Software Interrupt Pending. shadow: shadow_type: rw msb: 1 lsb: 1 vssip: implemented: false description: VS-level Software Interrupt Pending. shadow: shadow_type: rw msb: 2 lsb: 2 msip: implemented: true description: Machine Software Interrupt Pending. shadow: shadow_type: rw msb: 3 lsb: 3 type: ro_variable: true utip: implemented: false description: User Timer Interrupt Pending. shadow: shadow_type: rw msb: 4 lsb: 4 stip: implemented: false description: Supervisor Timer Interrupt Pending. shadow: shadow_type: rw msb: 5 lsb: 5 vstip: implemented: false description: VS-level Timer Interrupt Pending. shadow: shadow_type: rw msb: 6 lsb: 6 mtip: implemented: true description: Machine Timer Interrupt Pending. shadow: shadow_type: rw msb: 7 lsb: 7 type: ro_variable: true ueip: implemented: false description: User External Interrupt Pending. shadow: shadow_type: rw msb: 8 lsb: 8 seip: implemented: false description: Supervisor External Interrupt Pending. shadow: shadow_type: rw msb: 9 lsb: 9 vseip: implemented: false description: VS-level External Interrupt Pending. shadow: shadow_type: rw msb: 10 lsb: 10 meip: implemented: true description: Machine External Interrupt Pending. shadow: shadow_type: rw msb: 11 lsb: 11 type: ro_variable: true sgeip: implemented: false description: HS-level External Interrupt Pending. shadow: shadow_type: rw msb: 12 lsb: 12 rv64: accessible: false description: The mip register is an MXLEN-bit read/write register containing information on pending interrupts. address: 836 priv_mode: M reset-val: 0 hie: rv32: accessible: false rv64: accessible: false description: The hie register is an HSXLEN-bit read/write register containing interrupt enable bits. address: 0x604 priv_mode: H reset-val: 0 mie: rv32: accessible: true fields: - usie - ssie - vssie - msie - utie - stie - vstie - mtie - ueie - seie - vseie - meie - sgeie - - - 13 - 31 usie: implemented: false description: User Software Interrupt enable. shadow: shadow_type: rw msb: 0 lsb: 0 ssie: implemented: false description: Supervisor Software Interrupt enable. shadow: shadow_type: rw msb: 1 lsb: 1 vssie: implemented: false description: VS-level Software Interrupt enable. shadow: shadow_type: rw msb: 2 lsb: 2 msie: implemented: true description: Machine Software Interrupt enable. shadow: shadow_type: rw msb: 3 lsb: 3 type: wlrl: - 0x0:0x1 utie: implemented: false description: User Timer Interrupt enable. shadow: shadow_type: rw msb: 4 lsb: 4 stie: implemented: false description: Supervisor Timer Interrupt enable. shadow: shadow_type: rw msb: 5 lsb: 5 vstie: implemented: false description: VS-level Timer Interrupt enable. shadow: shadow_type: rw msb: 6 lsb: 6 mtie: implemented: true description: Machine Timer Interrupt enable. shadow: shadow_type: rw msb: 7 lsb: 7 type: wlrl: - 0:1 ueie: implemented: false description: User External Interrupt enable. shadow: shadow_type: rw msb: 8 lsb: 8 seie: implemented: false description: Supervisor External Interrupt enable. shadow: shadow_type: rw msb: 9 lsb: 9 vseie: implemented: false description: VS-level External Interrupt enable. shadow: shadow_type: rw msb: 10 lsb: 10 meie: implemented: true description: Machine External Interrupt enable. shadow: shadow_type: rw msb: 11 lsb: 11 type: wlrl: - 0:1 sgeie: implemented: false description: HS-level External Interrupt enable. shadow: shadow_type: rw msb: 12 lsb: 12 rv64: accessible: false description: The mie register is an MXLEN-bit read/write register containing interrupt enable bits. address: 772 priv_mode: M reset-val: 0 mscratch: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: warl: dependency_fields: [] legal: - mscratch[31:0] in [0x00000000:0xFFFFFFFF] wr_illegal: - unchanged rv64: accessible: false description: The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode. address: 832 priv_mode: M reset-val: 0 mepc: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: warl: dependency_fields: [] legal: - mepc[31:0] in [0x00000000:0xFFFFFFFF] wr_illegal: - unchanged rv64: accessible: false description: The mepc is a warl register that must be able to hold all valid physical and virtual addresses. address: 0x341 priv_mode: M reset-val: 0 mtval: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: warl: dependency_fields: [] legal: - mtval[31:0] in [0x00000000:0xFFFFFFFF] wr_illegal: - unchanged rv64: accessible: false description: The mtval is a warl register that holds the address of the instruction which caused the exception. address: 835 priv_mode: M reset-val: 0 mcause: rv32: accessible: true fields: - exception_code - interrupt interrupt: implemented: true description: Indicates whether the trap was due to an interrupt. shadow: shadow_type: rw msb: 31 lsb: 31 type: wlrl: - 0x0:0x1 exception_code: implemented: true description: Encodes the exception code. shadow: shadow_type: rw msb: 30 lsb: 0 type: wlrl: - 0:15 rv64: accessible: false description: The mcause register stores the information regarding the trap. address: 834 priv_mode: M reset-val: 0 pmpcfg0: rv32: accessible: false rv64: accessible: false description: PMP configuration register address: 0x3A0 priv_mode: M reset-val: 0 pmpcfg1: rv32: accessible: false rv64: accessible: false description: PMP configuration register address: 0x3A1 priv_mode: M reset-val: 0 pmpcfg2: rv32: accessible: false rv64: accessible: false description: PMP configuration register address: 0x3A2 priv_mode: M reset-val: 0 pmpcfg3: rv32: accessible: false rv64: accessible: false description: PMP configuration register address: 0x3A3 priv_mode: M reset-val: 0 pmpcfg4: rv32: accessible: false rv64: accessible: false description: PMP configuration register address: 0x3A4 priv_mode: M reset-val: 0 pmpcfg5: rv32: accessible: false rv64: accessible: false description: PMP configuration register address: 0x3A5 priv_mode: M reset-val: 0 pmpcfg6: rv32: accessible: false rv64: accessible: false description: PMP configuration register address: 0x3A6 priv_mode: M reset-val: 0 pmpcfg7: rv32: accessible: false rv64: accessible: false description: PMP configuration register address: 0x3A7 priv_mode: M reset-val: 0 pmpcfg8: rv32: accessible: false rv64: accessible: false description: PMP configuration register address: 0x3A8 priv_mode: M reset-val: 0 pmpcfg9: rv32: accessible: false rv64: accessible: false description: PMP configuration register address: 0x3A9 priv_mode: M reset-val: 0 pmpcfg10: rv32: accessible: false rv64: accessible: false description: PMP configuration register address: 0x3AA priv_mode: M reset-val: 0 pmpcfg11: rv32: accessible: false rv64: accessible: false description: PMP configuration register address: 0x3AB priv_mode: M reset-val: 0 pmpcfg12: rv32: accessible: false rv64: accessible: false description: PMP configuration register address: 0x3AC priv_mode: M reset-val: 0 pmpcfg13: rv32: accessible: false rv64: accessible: false description: PMP configuration register address: 0x3AD priv_mode: M reset-val: 0 pmpcfg14: rv32: accessible: false rv64: accessible: false description: PMP configuration register address: 0x3AE priv_mode: M reset-val: 0 pmpcfg15: rv32: accessible: false rv64: accessible: false description: PMP configuration register address: 0x3AF priv_mode: M reset-val: 0 pmpaddr0: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3B0 priv_mode: M reset-val: 0 pmpaddr1: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3B1 priv_mode: M reset-val: 0 pmpaddr2: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3B2 priv_mode: M reset-val: 0 pmpaddr3: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3B3 priv_mode: M reset-val: 0 pmpaddr4: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3B4 priv_mode: M reset-val: 0 pmpaddr5: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3B5 priv_mode: M reset-val: 0 pmpaddr6: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3B6 priv_mode: M reset-val: 0 pmpaddr7: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3B7 priv_mode: M reset-val: 0 pmpaddr8: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3B8 priv_mode: M reset-val: 0 pmpaddr9: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3B9 priv_mode: M reset-val: 0 pmpaddr10: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3BA priv_mode: M reset-val: 0 pmpaddr11: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3BB priv_mode: M reset-val: 0 pmpaddr12: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3BC priv_mode: M reset-val: 0 pmpaddr13: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3BD priv_mode: M reset-val: 0 pmpaddr14: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3BE priv_mode: M reset-val: 0 pmpaddr15: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3BF priv_mode: M reset-val: 0 pmpaddr16: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3C0 priv_mode: M reset-val: 0 pmpaddr17: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3C1 priv_mode: M reset-val: 0 pmpaddr18: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3C2 priv_mode: M reset-val: 0 pmpaddr19: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3C3 priv_mode: M reset-val: 0 pmpaddr20: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3C4 priv_mode: M reset-val: 0 pmpaddr21: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3C5 priv_mode: M reset-val: 0 pmpaddr22: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3C6 priv_mode: M reset-val: 0 pmpaddr23: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3C7 priv_mode: M reset-val: 0 pmpaddr24: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3C8 priv_mode: M reset-val: 0 pmpaddr25: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3C9 priv_mode: M reset-val: 0 pmpaddr26: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3CA priv_mode: M reset-val: 0 pmpaddr27: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3CB priv_mode: M reset-val: 0 pmpaddr28: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3CC priv_mode: M reset-val: 0 pmpaddr29: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3CD priv_mode: M reset-val: 0 pmpaddr30: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3CE priv_mode: M reset-val: 0 pmpaddr31: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3CF priv_mode: M reset-val: 0 pmpaddr32: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3D0 priv_mode: M reset-val: 0 pmpaddr33: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3D1 priv_mode: M reset-val: 0 pmpaddr34: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3D2 priv_mode: M reset-val: 0 pmpaddr35: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3D3 priv_mode: M reset-val: 0 pmpaddr36: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3D4 priv_mode: M reset-val: 0 pmpaddr37: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3D5 priv_mode: M reset-val: 0 pmpaddr38: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3D6 priv_mode: M reset-val: 0 pmpaddr39: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3D7 priv_mode: M reset-val: 0 pmpaddr40: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3D8 priv_mode: M reset-val: 0 pmpaddr41: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3D9 priv_mode: M reset-val: 0 pmpaddr42: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3DA priv_mode: M reset-val: 0 pmpaddr43: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3DB priv_mode: M reset-val: 0 pmpaddr44: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3DC priv_mode: M reset-val: 0 pmpaddr45: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3DD priv_mode: M reset-val: 0 pmpaddr46: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3DE priv_mode: M reset-val: 0 pmpaddr47: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3DF priv_mode: M reset-val: 0 pmpaddr48: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3E0 priv_mode: M reset-val: 0 pmpaddr49: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3E1 priv_mode: M reset-val: 0 pmpaddr50: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3E2 priv_mode: M reset-val: 0 pmpaddr51: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3E3 priv_mode: M reset-val: 0 pmpaddr52: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3E4 priv_mode: M reset-val: 0 pmpaddr53: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3E5 priv_mode: M reset-val: 0 pmpaddr54: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3E6 priv_mode: M reset-val: 0 pmpaddr55: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3E7 priv_mode: M reset-val: 0 pmpaddr56: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3E8 priv_mode: M reset-val: 0 pmpaddr57: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3E9 priv_mode: M reset-val: 0 pmpaddr58: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3EA priv_mode: M reset-val: 0 pmpaddr59: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3EB priv_mode: M reset-val: 0 pmpaddr60: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3EC priv_mode: M reset-val: 0 pmpaddr61: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3ED priv_mode: M reset-val: 0 pmpaddr62: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3EE priv_mode: M reset-val: 0 pmpaddr63: rv32: accessible: false rv64: accessible: false description: Physical memory protection address register address: 0x3EF priv_mode: M reset-val: 0 mcounteren: rv32: accessible: false rv64: accessible: false description: The mcounteren is a 32-bit register that controls the availability of the hardware performance-monitoring counters to the next-lowest privileged mode. address: 0x306 priv_mode: M reset-val: 0 mcountinhibit: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: {ro_constant: 0} rv64: accessible: false description: The mcountinhibit is a 32-bit WARL register that controls which of the hardware performance-monitoring counters increment. address: 0x320 priv_mode: M reset-val: 0 mcycle: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: warl: dependency_fields: [] legal: - mcycle[31:0] in [0x00000000:0xFFFFFFFF] wr_illegal: - unchanged rv64: accessible: false description: Counts the number of clock cycles executed from an arbitrary point in time. address: 0xB00 priv_mode: M reset-val: 0 mcycleh: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: warl: dependency_fields: [] legal: - mcycleh[31:0] in [0x00000000:0xFFFFFFFF] wr_illegal: - unchanged rv64: accessible: false description: upper 32 bits of mcycle address: 0xB80 priv_mode: M reset-val: 0 minstret: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: warl: dependency_fields: [] legal: - minstret[31:0] in [0x00000000:0xFFFFFFFF] wr_illegal: - unchanged rv64: accessible: false description: Counts the number of instructions completed from an arbitrary point in time. address: 0xB02 priv_mode: M reset-val: 0 minstreth: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: warl: dependency_fields: [] legal: - minstreth[31:0] in [0x00000000:0xFFFFFFFF] wr_illegal: - unchanged rv64: accessible: false description: Upper 32 bits of minstret. address: 0xB82 priv_mode: M reset-val: 0 mhpmevent3: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: &id001 ro_constant: 0 rv64: accessible: false description: The mhpmevent3 is a MXLEN-bit event register which controls mhpmcounter3. address: 0x323 priv_mode: M reset-val: 0 mhpmcounter3: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter3 is a 64-bit counter. Returns lower 32 bits in RV32I mode. address: 0xB03 priv_mode: M reset-val: 0 mhpmcounter3h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: &id002 ro_constant: 0 rv64: accessible: false description: The mhpmcounter3h returns the upper half word in RV32I systems. address: 0xB83 priv_mode: M reset-val: 0 mhpmevent4: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent4 is a MXLEN-bit event register which controls mhpmcounter4. address: 0x324 priv_mode: M reset-val: 0 mhpmcounter4: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter4 is a 64-bit counter. Returns lower 42 bits in RV42I mode. address: 0xB04 priv_mode: M reset-val: 0 mhpmcounter4h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter4h returns the upper half word in RV42I systems. address: 0xB84 priv_mode: M reset-val: 0 mhpmevent5: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent5 is a MXLEN-bit event register which controls mhpmcounter5. address: 0x325 priv_mode: M reset-val: 0 mhpmcounter5: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter5 is a 64-bit counter. Returns lower 52 bits in RV52I mode. address: 0xB05 priv_mode: M reset-val: 0 mhpmcounter5h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter5h returns the upper half word in RV52I systems. address: 0xB85 priv_mode: M reset-val: 0 mhpmevent6: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent6 is a MXLEN-bit event register which controls mhpmcounter6. address: 0x326 priv_mode: M reset-val: 0 mhpmcounter6: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter6 is a 64-bit counter. Returns lower 62 bits in RV62I mode. address: 0xB06 priv_mode: M reset-val: 0 mhpmcounter6h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter6h returns the upper half word in RV62I systems. address: 0xB86 priv_mode: M reset-val: 0 mhpmevent7: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent7 is a MXLEN-bit event register which controls mhpmcounter7. address: 0x327 priv_mode: M reset-val: 0 mhpmcounter7: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter7 is a 64-bit counter. Returns lower 72 bits in RV72I mode. address: 0xB07 priv_mode: M reset-val: 0 mhpmcounter7h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter7h returns the upper half word in RV72I systems. address: 0xB87 priv_mode: M reset-val: 0 mhpmevent8: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent8 is a MXLEN-bit event register which controls mhpmcounter8. address: 0x328 priv_mode: M reset-val: 0 mhpmcounter8: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter8 is a 64-bit counter. Returns lower 82 bits in RV82I mode. address: 0xB08 priv_mode: M reset-val: 0 mhpmcounter8h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter8h returns the upper half word in RV82I systems. address: 0xB88 priv_mode: M reset-val: 0 mhpmevent9: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent9 is a MXLEN-bit event register which controls mhpmcounter9. address: 0x329 priv_mode: M reset-val: 0 mhpmcounter9: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter9 is a 64-bit counter. Returns lower 32 bits in RV32I mode. address: 0xB09 priv_mode: M reset-val: 0 mhpmcounter9h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter9h returns the upper half word in RV32I systems. address: 0xB89 priv_mode: M reset-val: 0 mhpmevent10: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent10 is a MXLEN-bit event register which controls mhpmcounter10. address: 0x32a priv_mode: M reset-val: 0 mhpmcounter10: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter10 is a 64-bit counter. Returns lower 102 bits in RV102I mode. address: 0xB0A priv_mode: M reset-val: 0 mhpmcounter10h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter10h returns the upper half word in RV102I systems. address: 0xB8A priv_mode: M reset-val: 0 mhpmevent11: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent11 is a MXLEN-bit event register which controls mhpmcounter11. address: 0x32b priv_mode: M reset-val: 0 mhpmcounter11: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter11 is a 64-bit counter. Returns lower 112 bits in RV112I mode. address: 0xB0B priv_mode: M reset-val: 0 mhpmcounter11h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter11h returns the upper half word in RV112I systems. address: 0xB8B priv_mode: M reset-val: 0 mhpmevent12: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent12 is a MXLEN-bit event register which controls mhpmcounter12. address: 0x32c priv_mode: M reset-val: 0 mhpmcounter12: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter12 is a 64-bit counter. Returns lower 122 bits in RV122I mode. address: 0xB0C priv_mode: M reset-val: 0 mhpmcounter12h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter12h returns the upper half word in RV122I systems. address: 0xB8C priv_mode: M reset-val: 0 mhpmevent13: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent13 is a MXLEN-bit event register which controls mhpmcounter13. address: 0x32d priv_mode: M reset-val: 0 mhpmcounter13: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter13 is a 64-bit counter. Returns lower 132 bits in RV132I mode. address: 0xB0D priv_mode: M reset-val: 0 mhpmcounter13h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter13h returns the upper half word in RV132I systems. address: 0xB8D priv_mode: M reset-val: 0 mhpmevent14: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent14 is a MXLEN-bit event register which controls mhpmcounter14. address: 0x32e priv_mode: M reset-val: 0 mhpmcounter14: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter14 is a 64-bit counter. Returns lower 142 bits in RV142I mode. address: 0xB0E priv_mode: M reset-val: 0 mhpmcounter14h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter14h returns the upper half word in RV142I systems. address: 0xB8E priv_mode: M reset-val: 0 mhpmevent15: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent15 is a MXLEN-bit event register which controls mhpmcounter15. address: 0x32f priv_mode: M reset-val: 0 mhpmcounter15: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter15 is a 64-bit counter. Returns lower 152 bits in RV152I mode. address: 0xB0F priv_mode: M reset-val: 0 mhpmcounter15h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter15h returns the upper half word in RV152I systems. address: 0xB8F priv_mode: M reset-val: 0 mhpmevent16: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent16 is a MXLEN-bit event register which controls mhpmcounter16. address: 0x330 priv_mode: M reset-val: 0 mhpmcounter16: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter16 is a 64-bit counter. Returns lower 162 bits in RV162I mode. address: 0xB10 priv_mode: M reset-val: 0 mhpmcounter16h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter16h returns the upper half word in RV162I systems. address: 0xB90 priv_mode: M reset-val: 0 mhpmevent17: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent17 is a MXLEN-bit event register which controls mhpmcounter17. address: 0x331 priv_mode: M reset-val: 0 mhpmcounter17: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter17 is a 64-bit counter. Returns lower 172 bits in RV172I mode. address: 0xB11 priv_mode: M reset-val: 0 mhpmcounter17h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter17h returns the upper half word in RV172I systems. address: 0xB91 priv_mode: M reset-val: 0 mhpmevent18: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent18 is a MXLEN-bit event register which controls mhpmcounter18. address: 0x332 priv_mode: M reset-val: 0 mhpmcounter18: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter18 is a 64-bit counter. Returns lower 182 bits in RV182I mode. address: 0xB12 priv_mode: M reset-val: 0 mhpmcounter18h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter18h returns the upper half word in RV182I systems. address: 0xB92 priv_mode: M reset-val: 0 mhpmevent19: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent19 is a MXLEN-bit event register which controls mhpmcounter19. address: 0x333 priv_mode: M reset-val: 0 mhpmcounter19: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter19 is a 64-bit counter. Returns lower 32 bits in RV32I mode. address: 0xB13 priv_mode: M reset-val: 0 mhpmcounter19h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter19h returns the upper half word in RV32I systems. address: 0xB93 priv_mode: M reset-val: 0 mhpmevent20: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent20 is a MXLEN-bit event register which controls mhpmcounter20. address: 0x334 priv_mode: M reset-val: 0 mhpmcounter20: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter20 is a 64-bit counter. Returns lower 202 bits in RV202I mode. address: 0xB14 priv_mode: M reset-val: 0 mhpmcounter20h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter20h returns the upper half word in RV202I systems. address: 0xB94 priv_mode: M reset-val: 0 mhpmevent21: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent21 is a MXLEN-bit event register which controls mhpmcounter21. address: 0x335 priv_mode: M reset-val: 0 mhpmcounter21: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter21 is a 64-bit counter. Returns lower 212 bits in RV212I mode. address: 0xB15 priv_mode: M reset-val: 0 mhpmcounter21h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter21h returns the upper half word in RV212I systems. address: 0xB95 priv_mode: M reset-val: 0 mhpmevent22: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent22 is a MXLEN-bit event register which controls mhpmcounter22. address: 0x336 priv_mode: M reset-val: 0 mhpmcounter22: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter22 is a 64-bit counter. Returns lower 222 bits in RV222I mode. address: 0xB16 priv_mode: M reset-val: 0 mhpmcounter22h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter22h returns the upper half word in RV222I systems. address: 0xB96 priv_mode: M reset-val: 0 mhpmevent23: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent23 is a MXLEN-bit event register which controls mhpmcounter23. address: 0x337 priv_mode: M reset-val: 0 mhpmcounter23: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter23 is a 64-bit counter. Returns lower 232 bits in RV232I mode. address: 0xB17 priv_mode: M reset-val: 0 mhpmcounter23h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter23h returns the upper half word in RV232I systems. address: 0xB97 priv_mode: M reset-val: 0 mhpmevent24: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent24 is a MXLEN-bit event register which controls mhpmcounter24. address: 0x338 priv_mode: M reset-val: 0 mhpmcounter24: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter24 is a 64-bit counter. Returns lower 242 bits in RV242I mode. address: 0xB18 priv_mode: M reset-val: 0 mhpmcounter24h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter24h returns the upper half word in RV242I systems. address: 0xB98 priv_mode: M reset-val: 0 mhpmevent25: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent25 is a MXLEN-bit event register which controls mhpmcounter25. address: 0x339 priv_mode: M reset-val: 0 mhpmcounter25: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter25 is a 64-bit counter. Returns lower 252 bits in RV252I mode. address: 0xB19 priv_mode: M reset-val: 0 mhpmcounter25h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter25h returns the upper half word in RV252I systems. address: 0xB99 priv_mode: M reset-val: 0 mhpmevent26: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent26 is a MXLEN-bit event register which controls mhpmcounter26. address: 0x33a priv_mode: M reset-val: 0 mhpmcounter26: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter26 is a 64-bit counter. Returns lower 262 bits in RV262I mode. address: 0xB1A priv_mode: M reset-val: 0 mhpmcounter26h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter26h returns the upper half word in RV262I systems. address: 0xB9A priv_mode: M reset-val: 0 mhpmevent27: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent27 is a MXLEN-bit event register which controls mhpmcounter27. address: 0x33b priv_mode: M reset-val: 0 mhpmcounter27: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter27 is a 64-bit counter. Returns lower 272 bits in RV272I mode. address: 0xB1B priv_mode: M reset-val: 0 mhpmcounter27h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter27h returns the upper half word in RV272I systems. address: 0xB9B priv_mode: M reset-val: 0 mhpmevent28: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent28 is a MXLEN-bit event register which controls mhpmcounter28. address: 0x33c priv_mode: M reset-val: 0 mhpmcounter28: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter28 is a 64-bit counter. Returns lower 282 bits in RV282I mode. address: 0xB1C priv_mode: M reset-val: 0 mhpmcounter28h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter28h returns the upper half word in RV282I systems. address: 0xB9C priv_mode: M reset-val: 0 mhpmevent29: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent29 is a MXLEN-bit event register which controls mhpmcounter29. address: 0x33d priv_mode: M reset-val: 0 mhpmcounter29: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter29 is a 64-bit counter. Returns lower 32 bits in RV32I mode. address: 0xB1D priv_mode: M reset-val: 0 mhpmcounter29h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter29h returns the upper half word in RV32I systems. address: 0xB9D priv_mode: M reset-val: 0 mhpmevent30: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent30 is a MXLEN-bit event register which controls mhpmcounter30. address: 0x33e priv_mode: M reset-val: 0 mhpmcounter30: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter30 is a 64-bit counter. Returns lower 302 bits in RV302I mode. address: 0xB1E priv_mode: M reset-val: 0 mhpmcounter30h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter30h returns the upper half word in RV302I systems. address: 0xB9E priv_mode: M reset-val: 0 mhpmevent31: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmevent31 is a MXLEN-bit event register which controls mhpmcounter31. address: 0x33f priv_mode: M reset-val: 0 mhpmcounter31: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id001 rv64: accessible: false description: The mhpmcounter31 is a 64-bit counter. Returns lower 312 bits in RV312I mode. address: 0xB1F priv_mode: M reset-val: 0 mhpmcounter31h: rv32: accessible: true fields: [] shadow: shadow_type: rw msb: 31 lsb: 0 type: *id002 rv64: accessible: false description: The mhpmcounter31h returns the upper half word in RV312I systems. address: 0xB9F priv_mode: M reset-val: 0 sedeleg: rv32: accessible: false rv64: accessible: false description: sedeleg address: 258 priv_mode: S reset-val: 0 sideleg: rv32: accessible: false rv64: accessible: false description: sideleg priv_mode: S address: 259 reset-val: 0 fflags: rv32: accessible: false rv64: accessible: false description: 32-bit register to hold floating point accrued exceptions. address: 001 priv_mode: U reset-val: 0 frm: rv32: accessible: false rv64: accessible: false description: 32-bit register to hold Floating-Point Dynamic Rounding Mode. address: 002 priv_mode: U reset-val: 0 fcsr: rv32: accessible: false rv64: accessible: false description: 32-bit register to hold Floating-Point Control and Status Register. address: 003 priv_mode: U reset-val: 0 cycle: rv32: accessible: false rv64: accessible: false description: Captures the number of cycles executed from an arbitrary point in time. priv_mode: U address: 0xC00 reset-val: 0 cycleh: rv32: accessible: false rv64: accessible: false description: Upper 32-bits of the mcycle counter; only for rv32. address: 0xC80 priv_mode: U reset-val: 0 time: rv32: accessible: false rv64: accessible: false description: Timer for RDTIME instruction and RTC in the processor. priv_mode: U address: 0xC01 reset-val: 0 timeh: rv32: accessible: false rv64: accessible: false description: Upper 32-bits of the Timer for RDTIME instruction and RTC in the processor; only for rv32. address: 0xC81 priv_mode: U reset-val: 0 instret: rv32: accessible: false rv64: accessible: false description: Captures the number of instructions executed from an arbitrary point in time. priv_mode: U address: 0xC02 reset-val: 0 instreth: rv32: accessible: false rv64: accessible: false description: Upper 32-bits of the minstret counter; only for rv32. address: 0xC82 priv_mode: U reset-val: 0 hpmcounter3: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter3 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC03 hpmcounter4: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter4 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC04 hpmcounter5: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter5 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC05 hpmcounter6: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter6 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC06 hpmcounter7: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter7 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC07 hpmcounter8: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter8 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC08 hpmcounter9: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter9 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC09 hpmcounter10: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter10 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC0A hpmcounter11: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter11 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC0B hpmcounter12: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter12 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC0C hpmcounter13: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter13 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC0D hpmcounter14: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter14 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC0E hpmcounter15: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter15 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC0F hpmcounter16: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter16 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC10 hpmcounter17: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter17 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC11 hpmcounter18: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter18 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC12 hpmcounter19: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter19 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC13 hpmcounter20: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter20 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC14 hpmcounter21: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter21 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC15 hpmcounter22: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter22 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC16 hpmcounter23: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter23 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC17 hpmcounter24: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter24 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC18 hpmcounter25: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter25 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC19 hpmcounter26: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter26 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC1A hpmcounter27: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter27 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC1B hpmcounter28: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter28 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC1C hpmcounter29: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter29 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC1D hpmcounter30: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter30 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC1E hpmcounter31: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter31 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC1F hpmcounter3h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter3h returns the upper half word in RV32I systems. address: 0xC83 hpmcounter4h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter4h returns the upper half word in RV32I systems. address: 0xC84 hpmcounter5h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter5h returns the upper half word in RV32I systems. address: 0xC85 hpmcounter6h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter6h returns the upper half word in RV32I systems. address: 0xC86 hpmcounter7h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter7h returns the upper half word in RV32I systems. address: 0xC87 hpmcounter8h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter8h returns the upper half word in RV32I systems. address: 0xC88 hpmcounter9h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter9h returns the upper half word in RV32I systems. address: 0xC89 hpmcounter10h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter10h returns the upper half word in RV32I systems. address: 0xC8A hpmcounter11h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter11h returns the upper half word in RV32I systems. address: 0xC8B hpmcounter12h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter12h returns the upper half word in RV32I systems. address: 0xC8C hpmcounter13h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter13h returns the upper half word in RV32I systems. address: 0xC8D hpmcounter14h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter14h returns the upper half word in RV32I systems. address: 0xC8E hpmcounter15h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter15h returns the upper half word in RV32I systems. address: 0xC8F hpmcounter16h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter16h returns the upper half word in RV32I systems. address: 0xC90 hpmcounter17h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter17h returns the upper half word in RV32I systems. address: 0xC91 hpmcounter18h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter18h returns the upper half word in RV32I systems. address: 0xC92 hpmcounter19h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter19h returns the upper half word in RV32I systems. address: 0xC93 hpmcounter20h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter20h returns the upper half word in RV32I systems. address: 0xC94 hpmcounter21h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter21h returns the upper half word in RV32I systems. address: 0xC95 hpmcounter22h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter22h returns the upper half word in RV32I systems. address: 0xC96 hpmcounter23h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter23h returns the upper half word in RV32I systems. address: 0xC97 hpmcounter24h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter24h returns the upper half word in RV32I systems. address: 0xC98 hpmcounter25h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter25h returns the upper half word in RV32I systems. address: 0xC99 hpmcounter26h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter26h returns the upper half word in RV32I systems. address: 0xC9A hpmcounter27h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter27h returns the upper half word in RV32I systems. address: 0xC9B hpmcounter28h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter28h returns the upper half word in RV32I systems. address: 0xC9C hpmcounter29h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter29h returns the upper half word in RV32I systems. address: 0xC9D hpmcounter30h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter30h returns the upper half word in RV32I systems. address: 0xC9E hpmcounter31h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter31h returns the upper half word in RV32I systems. address: 0xC9F sstatus: rv32: accessible: false rv64: accessible: false description: The sstatus register keeps track of the processor’s current operating state. address: 0x100 priv_mode: S reset-val: 0 sie: rv32: accessible: false rv64: accessible: false description: The sie register is an SXLEN-bit read/write register containing interrupt enable bits. address: 0x104 priv_mode: S reset-val: 0 sip: rv32: accessible: false rv64: accessible: false description: The sip register is an SXLEN-bit read/write register containing interrupt pending bits. address: 0x144 priv_mode: S reset-val: 0 sscratch: rv32: accessible: false rv64: accessible: false description: The sscratch register is an MXLEN-bit read/write register dedicated for use by machine mode. address: 0x140 priv_mode: S reset-val: 0 sepc: rv32: accessible: false rv64: accessible: false description: The sepc is a warl register that must be able to hold all valid physical and virtual addresses. address: 0x141 priv_mode: S reset-val: 0 stval: rv32: accessible: false rv64: accessible: false description: The stval is a warl register that holds the address of the instruction which caused the exception. address: 0x143 priv_mode: S reset-val: 0 scause: rv32: accessible: false rv64: accessible: false description: The scause register stores the information regarding the trap. address: 0x142 priv_mode: S reset-val: 0 stvec: rv32: accessible: false rv64: accessible: false description: SXLEN-bit read/write register that holds trap vector configuration. address: 0x105 priv_mode: S reset-val: 0 satp: rv32: accessible: false rv64: accessible: false description: SXLEN-bit register which controls supervisor-mode address translation and protection address: 0x180 priv_mode: S reset-val: 0 ustatus: rv32: accessible: false rv64: accessible: false description: The ustatus register keeps track of the processor’s current operating state. address: 0x000 priv_mode: U reset-val: 0 uie: rv32: accessible: false rv64: accessible: false description: The uie register is an UXLEN-bit read/write register containing interrupt enable bits. address: 0x004 priv_mode: U reset-val: 0 uip: rv32: accessible: false rv64: accessible: false description: The uip register is an UXLEN-bit read/write register containing interrupt pending bits. address: 0x044 priv_mode: U reset-val: 0 uscratch: rv32: accessible: false rv64: accessible: false description: The uscratch register is an UXLEN-bit read/write register dedicated for use by machine mode. address: 0x040 priv_mode: U reset-val: 0 uepc: rv32: accessible: false rv64: accessible: false description: The uepc is a warl register that must be able to hold all valid physical and virtual addresses. address: 0x041 priv_mode: U reset-val: 0 utval: rv32: accessible: false rv64: accessible: false description: The utval is a warl register that holds the address of the instruction which caused the exception. address: 0x043 priv_mode: U reset-val: 0 ucause: rv32: accessible: false rv64: accessible: false description: The ucause register stores the information regarding the trap. address: 0x042 priv_mode: U reset-val: 0 utvec: rv32: accessible: false rv64: accessible: false description: UXLEN-bit read/write register that holds trap vector configuration. address: 0x005 priv_mode: U reset-val: 0 scounteren: rv32: accessible: false rv64: accessible: false description: The scounteren is a 32-bit register that controls the availability of the hardware performance-monitoring counters to the next-lowest privileged mode. address: 0x106 priv_mode: S reset-val: 0 hstatus: rv32: accessible: false rv64: accessible: false description: The hstatus register keeps track of and controls the hart’s current operating state. address: 1536 priv_mode: H reset-val: 0 hideleg: rv32: accessible: false rv64: accessible: false description: Hypervisor Interrupt delegation Register. address: 1539 priv_mode: H reset-val: 0 hedeleg: rv32: accessible: false rv64: accessible: false description: Hypervisor Exception delegation Register. address: 1538 priv_mode: H reset-val: 0 hip: rv32: accessible: false rv64: accessible: false description: The hip register is an HXLEN-bit read/write register containing information on pending interrupts. address: 1604 priv_mode: H reset-val: 0 hvip: rv32: accessible: false rv64: accessible: false description: The hvip register is an HSXLEN-bit read/write register that a hypervisor can write to indicate virtual interrupts intended for VS-mode. address: 1605 priv_mode: H reset-val: 0 hgeip: rv32: accessible: false rv64: accessible: false description: The hgeip register is an HSXLEN-bit read-only register that indicates pending guest external interrupts for this hart. address: 0xE12 priv_mode: H reset-val: 0 hgeie: rv32: accessible: false rv64: accessible: false description: The hgeie register is an HSXLEN-bit read/write register that contains enable bits for the guest external interrupts at this hart. address: 0x607 priv_mode: H reset-val: 0 htval: rv32: accessible: false rv64: accessible: false description: The htval is a warl register that holds the address of the instruction which caused the exception. address: 0x643 priv_mode: H reset-val: 0 htinst: rv32: accessible: false rv64: accessible: false description: The htinst is a warl register that need only be able to hold the values that the implementation may automatically write to it on a trap. address: 0x64A priv_mode: H reset-val: 0 mtval2: rv32: accessible: false rv64: accessible: false description: When a trap is taken into M-mode, mtval2 is written with additional exception-specific information to assist software in handling the trap. address: 0x34B priv_mode: M reset-val: 0 mtinst: rv32: accessible: false rv64: accessible: false description: The mtinst is a warl register that need only be able to hold the values that the implementation may automatically write to it on a trap. address: 0x34A priv_mode: M reset-val: 0 hgatp: rv32: accessible: false rv64: accessible: false description: HSXLEN-bit register which controls G-stage address translation and protection address: 0x680 priv_mode: H reset-val: 0 hcounteren: rv32: accessible: false rv64: accessible: false description: The hcounteren is a 32-bit register that controls the availability of the hardware performance-monitoring counters to the next-lowest privileged mode. address: 0x606 priv_mode: H reset-val: 0 htimedelta: rv32: accessible: false rv64: accessible: false description: The htimedelta CSR is a read/write register that contains the delta between the value of the time CSR and the value returned in VS-mode or VU-mode. priv_mode: H address: 0x605 reset-val: 0 htimedeltah: rv32: accessible: false rv64: accessible: false description: Upper 32-bits of htimedelta address: 0x615 priv_mode: H reset-val: 0 vsstatus: rv32: accessible: false rv64: accessible: false description: The vsstatus register keeps track of the processor’s current operating state. address: 0x200 priv_mode: S reset-val: 0 vsie: rv32: accessible: false rv64: accessible: false description: The vsie register is an VSXLEN-bit read/write register containing interrupt enable bits. address: 0x204 priv_mode: S reset-val: 0 vsip: rv32: accessible: false rv64: accessible: false description: The vsip register is an VSXLEN-bit read/write register containing interrupt pending bits. address: 0x244 priv_mode: S reset-val: 0 vsscratch: rv32: accessible: false rv64: accessible: false description: The vsscratch register is an VSXLEN-bit read/write register dedicated for use by machine mode. address: 0x240 priv_mode: S reset-val: 0 vsepc: rv32: accessible: false rv64: accessible: false description: The vsepc is a warl register that must be able to hold all valid physical and virtual addresses. address: 0x241 priv_mode: S reset-val: 0 vstval: rv32: accessible: false rv64: accessible: false description: The vstval is a warl register that holds the address of the instruction which caused the exception. address: 0x243 priv_mode: S reset-val: 0 vscause: rv32: accessible: false rv64: accessible: false description: The scause register stores the information regarding the trap. address: 0x242 priv_mode: S reset-val: 0 vstvec: rv32: accessible: false rv64: accessible: false description: SXLEN-bit read/write register that holds trap vector configuration. address: 0x205 priv_mode: S reset-val: 0 vsatp: rv32: accessible: false rv64: accessible: false description: VSXLEN-bit register which controls supervisor-mode address translation and protection address: 0x280 priv_mode: S reset-val: 0
/test/riscof_compliance/riscof_work/nox_platform_checked.yaml
mtime: implemented: true address: 0xbff8 mtimecmp: implemented: false nmi: label: nmi_vector reset: label: reset_vector mtval_condition_writes: implemented: false scause_non_standard: implemented: false stval_condition_writes: implemented: false

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## Summary

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39Passed, 0Failed

## Results

Test | Result | Path
--- | --- | ---
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/add-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/add-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/addi-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/addi-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/and-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/and-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/andi-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/andi-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/auipc-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/auipc-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/beq-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/beq-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bge-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/bge-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bgeu-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/bgeu-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/blt-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/blt-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bltu-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/bltu-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/bne-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/bne-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/fence-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/fence-01.S
commit_id:ff9358edda915263426801f485b5be24f788862c MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/jal-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/jal-01.S
commit_id:ff9358edda915263426801f485b5be24f788862c MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/jalr-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/jalr-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lb-align-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/lb-align-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lbu-align-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/lbu-align-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lh-align-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/lh-align-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lhu-align-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/lhu-align-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lui-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/lui-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/lw-align-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/lw-align-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/or-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/or-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/ori-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/ori-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sb-align-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/sb-align-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sh-align-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/sh-align-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sll-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/sll-01.S
commit_id:7f99888d992294a61b2a6bc8da4d8e3a9db0a3b8 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/slli-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/slli-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/slt-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/slt-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/slti-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/slti-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sltiu-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/sltiu-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sltu-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/sltu-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sra-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/sra-01.S
commit_id:7f99888d992294a61b2a6bc8da4d8e3a9db0a3b8 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/srai-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/srai-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/srl-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/srl-01.S
commit_id:7f99888d992294a61b2a6bc8da4d8e3a9db0a3b8 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/srli-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/srli-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sub-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/sub-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/sw-align-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/sw-align-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/xor-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/xor-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/I/src/xori-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/I/src/xori-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: TEST_CASE_1=True XLEN=32
/test/riscof_compliance/riscv-arch-test/riscv-test-suite/rv32i_m/privilege/src/misalign1-jalr-01.S | Passed | /test/riscof_compliance/riscof_work/rv32i_m/privilege/src/misalign1-jalr-01.S
commit_id:6ba8712973dade81eaf1182d1050e5799a7ef2a0 MACROS: rvtest_mtrap_routine=True TEST_CASE_1=True XLEN=32