Workspace
| .git | ||||
| .Xil | ||||
| ci | ||||
| doc | ||||
| fpga | ||||
| ips | ||||
| rtl | ||||
| sw | ||||
| tb | ||||
| vsim | ||||
| .gitignore | Jul 6, 2026, 4:18:29 AM | 34 B | ||
| .gitlab-ci.yml | Jul 6, 2026, 4:18:29 AM | 2.53 KiB | ||
| build_digilent_arty_a7_100t.tcl | Jul 6, 2026, 4:25:36 AM | 5.17 KiB | ||
| create-archive.py | Jul 6, 2026, 4:18:29 AM | 1.54 KiB | ||
| generate-scripts.py | Jul 6, 2026, 4:18:29 AM | 2.37 KiB | ||
| ips_list.yml | Jul 6, 2026, 4:18:29 AM | 1.24 KiB | ||
| LICENSE | Jul 6, 2026, 4:18:29 AM | 10.15 KiB | ||
| processor_ci_defines.vh | Jul 6, 2026, 4:25:36 AM | 300 B | ||
| README.md | Jul 6, 2026, 4:18:29 AM | 7.75 KiB | ||
| update-ips.py | Jul 6, 2026, 4:18:29 AM | 2.87 KiB | ||
