Skip to content

Workspace

/ pulpino /
.git
.Xil
ci
doc
fpga
ips
rtl
sw
tb
vsim
.gitignoreMay 18, 2026, 4:18:42 AM34 B
.gitlab-ci.ymlMay 18, 2026, 4:18:42 AM2.53 KiB
build_digilent_arty_a7_100t.tclMay 18, 2026, 4:25:55 AM5.17 KiB
clockInfo.txtMay 18, 2026, 4:26:53 AM375 B
create-archive.pyMay 18, 2026, 4:18:42 AM1.54 KiB
digilent_arty_a7_100t.bitMay 18, 2026, 4:27:47 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptMay 18, 2026, 4:26:57 AM16.56 KiB
digilent_arty_a7_control_sets.rptMay 18, 2026, 4:26:57 AM12.95 KiB
digilent_arty_a7_drc.rptMay 18, 2026, 4:27:29 AM2.34 KiB
digilent_arty_a7_io.rptMay 18, 2026, 4:26:57 AM96.81 KiB
digilent_arty_a7_power.rptMay 18, 2026, 4:27:29 AM8.59 KiB
digilent_arty_a7_route_status.rptMay 18, 2026, 4:27:28 AM651 B
digilent_arty_a7_timing.rptMay 18, 2026, 4:27:29 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptMay 18, 2026, 4:26:57 AM3.22 KiB
digilent_arty_a7_utilization_place.rptMay 18, 2026, 4:26:57 AM10.57 KiB
generate-scripts.pyMay 18, 2026, 4:18:42 AM2.37 KiB
ips_list.ymlMay 18, 2026, 4:18:42 AM1.24 KiB
LICENSEMay 18, 2026, 4:18:42 AM10.15 KiB
processor_ci_defines.vhMay 18, 2026, 4:25:55 AM300 B
README.mdMay 18, 2026, 4:18:42 AM7.75 KiB
update-ips.pyMay 18, 2026, 4:18:42 AM2.87 KiB