Skip to content

Workspace

/ pulpino /
.git
.Xil
ci
doc
fpga
ips
rtl
sw
tb
vsim
.gitignoreAug 27, 2026, 4:18:30 AM34 B
.gitlab-ci.ymlAug 27, 2026, 4:18:30 AM2.53 KiB
build_digilent_arty_a7_100t.tclAug 27, 2026, 4:25:40 AM5.17 KiB
clockInfo.txtAug 27, 2026, 4:26:39 AM375 B
create-archive.pyAug 27, 2026, 4:18:30 AM1.54 KiB
digilent_arty_a7_100t.bitAug 27, 2026, 4:27:41 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptAug 27, 2026, 4:26:45 AM16.56 KiB
digilent_arty_a7_control_sets.rptAug 27, 2026, 4:26:45 AM12.95 KiB
digilent_arty_a7_drc.rptAug 27, 2026, 4:27:22 AM2.34 KiB
digilent_arty_a7_io.rptAug 27, 2026, 4:26:44 AM96.81 KiB
digilent_arty_a7_power.rptAug 27, 2026, 4:27:22 AM8.59 KiB
digilent_arty_a7_route_status.rptAug 27, 2026, 4:27:21 AM651 B
digilent_arty_a7_timing.rptAug 27, 2026, 4:27:22 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptAug 27, 2026, 4:26:44 AM3.22 KiB
digilent_arty_a7_utilization_place.rptAug 27, 2026, 4:26:44 AM10.57 KiB
generate-scripts.pyAug 27, 2026, 4:18:30 AM2.37 KiB
ips_list.ymlAug 27, 2026, 4:18:30 AM1.24 KiB
LICENSEAug 27, 2026, 4:18:30 AM10.15 KiB
processor_ci_defines.vhAug 27, 2026, 4:25:40 AM300 B
README.mdAug 27, 2026, 4:18:30 AM7.75 KiB
update-ips.pyAug 27, 2026, 4:18:30 AM2.87 KiB