Skip to content
[Jenkins]Jenkins
log in

Workspace

/ pulpino /
.git
.Xil
ci
doc
fpga
ips
rtl
sw
tb
vsim
.gitignoreJul 6, 2026, 4:18:29 AM34 B
.gitlab-ci.ymlJul 6, 2026, 4:18:29 AM2.53 KiB
build_digilent_arty_a7_100t.tclJul 6, 2026, 4:25:36 AM5.17 KiB
clockInfo.txtJul 6, 2026, 4:26:35 AM375 B
create-archive.pyJul 6, 2026, 4:18:29 AM1.54 KiB
digilent_arty_a7_100t.bitJul 6, 2026, 4:27:29 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptJul 6, 2026, 4:26:39 AM16.56 KiB
digilent_arty_a7_control_sets.rptJul 6, 2026, 4:26:39 AM12.95 KiB
digilent_arty_a7_drc.rptJul 6, 2026, 4:27:10 AM2.34 KiB
digilent_arty_a7_io.rptJul 6, 2026, 4:26:39 AM96.81 KiB
digilent_arty_a7_power.rptJul 6, 2026, 4:27:11 AM8.59 KiB
digilent_arty_a7_route_status.rptJul 6, 2026, 4:27:09 AM651 B
digilent_arty_a7_timing.rptJul 6, 2026, 4:27:11 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptJul 6, 2026, 4:26:39 AM3.22 KiB
digilent_arty_a7_utilization_place.rptJul 6, 2026, 4:26:39 AM10.57 KiB
generate-scripts.pyJul 6, 2026, 4:18:29 AM2.37 KiB
ips_list.ymlJul 6, 2026, 4:18:29 AM1.24 KiB
LICENSEJul 6, 2026, 4:18:29 AM10.15 KiB
processor_ci_defines.vhJul 6, 2026, 4:25:36 AM300 B
README.mdJul 6, 2026, 4:18:29 AM7.75 KiB
update-ips.pyJul 6, 2026, 4:18:29 AM2.87 KiB