| .git |
| .Xil |
| ci |
| doc |
| fpga |
| ips |
| rtl |
| sw |
| tb |
| vsim |
| .gitignore | Jun 22, 2026, 4:19:26 AM | 34 B | |
| .gitlab-ci.yml | Jun 22, 2026, 4:19:26 AM | 2.53 KiB | |
| build_digilent_arty_a7_100t.tcl | Jun 22, 2026, 4:26:34 AM | 5.17 KiB | |
| clockInfo.txt | Jun 22, 2026, 4:27:31 AM | 375 B | |
| create-archive.py | Jun 22, 2026, 4:19:26 AM | 1.54 KiB | |
| digilent_arty_a7_100t.bit | Jun 22, 2026, 4:28:25 AM | 3.65 MiB | |
| digilent_arty_a7_clock_utilization.rpt | Jun 22, 2026, 4:27:35 AM | 16.56 KiB | |
| digilent_arty_a7_control_sets.rpt | Jun 22, 2026, 4:27:35 AM | 12.95 KiB | |
| digilent_arty_a7_drc.rpt | Jun 22, 2026, 4:28:07 AM | 2.34 KiB | |
| digilent_arty_a7_io.rpt | Jun 22, 2026, 4:27:35 AM | 96.81 KiB | |
| digilent_arty_a7_power.rpt | Jun 22, 2026, 4:28:07 AM | 8.59 KiB | |
| digilent_arty_a7_route_status.rpt | Jun 22, 2026, 4:28:06 AM | 651 B | |
| digilent_arty_a7_timing.rpt | Jun 22, 2026, 4:28:07 AM | 18.47 KiB | |
| digilent_arty_a7_utilization_hierarchical_place.rpt | Jun 22, 2026, 4:27:35 AM | 3.22 KiB | |
| digilent_arty_a7_utilization_place.rpt | Jun 22, 2026, 4:27:35 AM | 10.57 KiB | |
| generate-scripts.py | Jun 22, 2026, 4:19:26 AM | 2.37 KiB | |
| ips_list.yml | Jun 22, 2026, 4:19:26 AM | 1.24 KiB | |
| LICENSE | Jun 22, 2026, 4:19:26 AM | 10.15 KiB | |
| processor_ci_defines.vh | Jun 22, 2026, 4:26:34 AM | 300 B | |
| README.md | Jun 22, 2026, 4:19:26 AM | 7.75 KiB | |
| update-ips.py | Jun 22, 2026, 4:19:26 AM | 2.87 KiB | |
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