Skip to content
[Jenkins]Jenkins
log in

Workspace

/ pulpino /
.git
.Xil
ci
doc
fpga
ips
rtl
sw
tb
vsim
.gitignoreJun 30, 2026, 4:19:44 AM34 B
.gitlab-ci.ymlJun 30, 2026, 4:19:44 AM2.53 KiB
build_digilent_arty_a7_100t.tclJun 30, 2026, 4:37:37 AM5.17 KiB
clockInfo.txtJun 30, 2026, 4:40:20 AM375 B
create-archive.pyJun 30, 2026, 4:19:44 AM1.54 KiB
digilent_arty_a7_100t.bitJun 30, 2026, 4:43:14 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptJun 30, 2026, 4:41:22 AM16.56 KiB
digilent_arty_a7_control_sets.rptJun 30, 2026, 4:41:21 AM12.95 KiB
digilent_arty_a7_drc.rptJun 30, 2026, 4:42:45 AM2.34 KiB
digilent_arty_a7_io.rptJun 30, 2026, 4:41:21 AM96.81 KiB
digilent_arty_a7_power.rptJun 30, 2026, 4:42:46 AM8.59 KiB
digilent_arty_a7_route_status.rptJun 30, 2026, 4:42:42 AM651 B
digilent_arty_a7_timing.rptJun 30, 2026, 4:42:45 AM18.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptJun 30, 2026, 4:41:20 AM3.22 KiB
digilent_arty_a7_utilization_place.rptJun 30, 2026, 4:41:20 AM10.57 KiB
generate-scripts.pyJun 30, 2026, 4:19:44 AM2.37 KiB
ips_list.ymlJun 30, 2026, 4:19:44 AM1.24 KiB
LICENSEJun 30, 2026, 4:19:44 AM10.15 KiB
processor_ci_defines.vhJun 30, 2026, 4:37:37 AM300 B
README.mdJun 30, 2026, 4:19:44 AM7.75 KiB
update-ips.pyJun 30, 2026, 4:19:44 AM2.87 KiB