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Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/jenkins_home/workspace/riscado-v
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf riscado-v
[Pipeline] sh
+ git clone --recursive --depth=1 https://github.com/zxmarcos/riscado-v riscado-v
Cloning into 'riscado-v'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/jenkins_home/workspace/riscado-v/riscado-v
[Pipeline] {
[Pipeline] sh
+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s RISCV alu.v control_unit.v program_counter.v register_file.v riscv.v load_store.v
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Utilities)
[Pipeline] dir
Running in /var/jenkins_home/workspace/riscado-v/riscado-v
[Pipeline] {
[Pipeline] sh
+ pwd
+ python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/riscado-v/riscado-v -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels.json
WARNING: Error writing to JSON file: [Errno 2] No such file or directory: '/jenkins/processor_ci_utils/labels.json'
Trying to read file: /var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_nexys4_ddr)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_nexys4_ddr)
[Pipeline] lock
Trying to acquire lock on [Resource: colorlight_i9]
The resource [colorlight_i9] is locked by build RISC-V Steel #264 #264 since Feb 19, 2025, 2:53 AM.
[Resource: colorlight_i9] is not free, waiting for execution ...
[Required resources: [colorlight_i9]] added into queue at position 0
[Pipeline] lock
Trying to acquire lock on [Resource: digilent_nexys4_ddr]
Resource [digilent_nexys4_ddr] did not exist. Created.
Lock acquired on [Resource: digilent_nexys4_ddr]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] dir
Running in /var/jenkins_home/workspace/riscado-v/riscado-v
[Pipeline] {
[Pipeline] echo
Starting synthesis for FPGA digilent_nexys4_ddr.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p riscado-v -b digilent_nexys4_ddr
Final configuration file generated at /var/jenkins_home/workspace/riscado-v/riscado-v/build_digilent_nexys4_ddr.tcl
Error executing Makefile.
ERROR: [Common 17-55] 'set_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
make: *** [/eda/processor_ci/makefiles/digilent_nexys4_ddr.mk:12: digilent_nexys4_ddr.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 135, in <module>
    main(
  File "/eda/processor_ci/main.py", line 82, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 215, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_nexys4_ddr)
Stage "Flash digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test digilent_nexys4_ddr)
Stage "Test digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_nexys4_ddr]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch digilent_nexys4_ddr
Lock acquired on [Resource: colorlight_i9]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] dir
Running in /var/jenkins_home/workspace/riscado-v/riscado-v
[Pipeline] {
[Pipeline] echo
Starting synthesis for FPGA colorlight_i9.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p riscado-v -b colorlight_i9
Final configuration file generated at /var/jenkins_home/workspace/riscado-v/riscado-v/build_colorlight_i9.tcl
Makefile executed successfully.
Makefile output:
/eda/oss-cad-suite/bin/yosys -c /var/jenkins_home/workspace/riscado-v/riscado-v/build_colorlight_i9.tcl -DID=0x6a6a6a6a -DCLOCK_FREQ=25000000 -DMEMORY_SIZE=4096

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.45+139 (git sha1 4d581a97d, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3)

-- Running command `read -define ID=0x6a6a6a6a CLOCK_FREQ=25000000 MEMORY_SIZE=4096' --

1. Executing Verilog-2005 frontend: /eda/processor_ci/rtl/riscado-v.v
Parsing Verilog input from `/eda/processor_ci/rtl/riscado-v.v' to AST representation.
Generating RTLIL representation for module `\processorci_top'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/riscado-v/riscado-v/alu.v
Parsing Verilog input from `/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v' to AST representation.
Generating RTLIL representation for module `\ALU'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v
Parsing Verilog input from `/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v' to AST representation.
Generating RTLIL representation for module `\ControlUnit'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v
Parsing Verilog input from `/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v' to AST representation.
Generating RTLIL representation for module `\ProgramCounter'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v
Parsing Verilog input from `/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v' to AST representation.
Generating RTLIL representation for module `\RegisterFile'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v
Parsing Verilog input from `/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v' to AST representation.
Generating RTLIL representation for module `\RISCV'.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v
Parsing Verilog input from `/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v' to AST representation.
Lexer warning: The SystemVerilog keyword `byte' (at /var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:14) is not recognized unless read_verilog is called with -sv!
Lexer warning: The SystemVerilog keyword `byte' (at /var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:18) is not recognized unless read_verilog is called with -sv!
Lexer warning: The SystemVerilog keyword `byte' (at /var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:18) is not recognized unless read_verilog is called with -sv!
Lexer warning: The SystemVerilog keyword `byte' (at /var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:18) is not recognized unless read_verilog is called with -sv!
Generating RTLIL representation for module `\ByteReader'.
Generating RTLIL representation for module `\HalfReader'.
Generating RTLIL representation for module `\ByteWriter'.
Generating RTLIL representation for module `\HalfWriter'.
Generating RTLIL representation for module `\LoadStore'.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/uart.v
Parsing Verilog input from `/eda/processor-ci-controller/modules/uart.v' to AST representation.
Generating RTLIL representation for module `\UART'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v' to AST representation.
Generating RTLIL representation for module `\uart_rx'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v
Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v' to AST representation.
Generating RTLIL representation for module `\uart_tx'.
Successfully finished Verilog frontend.

11. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/fifo.v
Parsing Verilog input from `/eda/processor-ci-controller/src/fifo.v' to AST representation.
Generating RTLIL representation for module `\FIFO'.
Successfully finished Verilog frontend.

12. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/reset.v
Parsing Verilog input from `/eda/processor-ci-controller/src/reset.v' to AST representation.
Generating RTLIL representation for module `\ResetBootSystem'.
Successfully finished Verilog frontend.

13. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/clk_divider.v
Parsing Verilog input from `/eda/processor-ci-controller/src/clk_divider.v' to AST representation.
Generating RTLIL representation for module `\ClkDivider'.
Successfully finished Verilog frontend.

14. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/memory.v
Parsing Verilog input from `/eda/processor-ci-controller/src/memory.v' to AST representation.
Generating RTLIL representation for module `\Memory'.
Successfully finished Verilog frontend.

15. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/interpreter.v
Parsing Verilog input from `/eda/processor-ci-controller/src/interpreter.v' to AST representation.
Generating RTLIL representation for module `\Interpreter'.
Successfully finished Verilog frontend.

16. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/controller.v
Parsing Verilog input from `/eda/processor-ci-controller/src/controller.v' to AST representation.
Generating RTLIL representation for module `\Controller'.
Successfully finished Verilog frontend.

17. Executing SYNTH_ECP5 pass.

17.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\DP16KD'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

17.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCUA'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Successfully finished Verilog frontend.

17.3. Executing HIERARCHY pass (managing design hierarchy).

17.3.1. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     \ResetBootSystem
Used module:     \RISCV
Used module:         \ALU
Used module:         \ProgramCounter
Used module:         \RegisterFile
Used module:         \LoadStore
Used module:             \HalfReader
Used module:             \ByteReader
Used module:             \HalfWriter
Used module:             \ByteWriter
Used module:         \ControlUnit
Used module:     \Controller
Used module:         \Memory
Used module:         \UART
Used module:             \uart_tx
Used module:             \uart_rx
Used module:             \FIFO
Used module:         \Interpreter
Used module:         \ClkDivider
Parameter \CYCLES = 20

17.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'.
Parameter \CYCLES = 20
Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \WORD_SIZE_BY = 4
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

17.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Controller'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \WORD_SIZE_BY = 4
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

17.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4

17.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4
Generating RTLIL representation for module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 12
Parameter \BUS_WIDTH = 32
Parameter \ID = 1
Parameter \RESET_CLK_CYCLES = 20

17.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 12
Parameter \BUS_WIDTH = 32
Parameter \ID = 1
Parameter \RESET_CLK_CYCLES = 20
Generating RTLIL representation for module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 12

17.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 12
Generating RTLIL representation for module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

17.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

17.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8

17.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

17.3.11. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     \RISCV
Used module:         \ALU
Used module:         \ProgramCounter
Used module:         \RegisterFile
Used module:         \LoadStore
Used module:             \HalfReader
Used module:             \ByteReader
Used module:             \HalfWriter
Used module:             \ByteWriter
Used module:         \ControlUnit
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         \Memory
Used module:         \UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \Interpreter
Used module:         \ClkDivider
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4

17.3.12. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4
Generating RTLIL representation for module `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20

17.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20
Generating RTLIL representation for module `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 32

17.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 32
Generating RTLIL representation for module `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider'.

17.3.15. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     \RISCV
Used module:         \ALU
Used module:         \ProgramCounter
Used module:         \RegisterFile
Used module:         \LoadStore
Used module:             \HalfReader
Used module:             \ByteReader
Used module:             \HalfWriter
Used module:             \ByteWriter
Used module:         \ControlUnit
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory
Used module:         $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART
Used module:             \uart_tx
Used module:             \uart_rx
Used module:             \FIFO
Used module:         $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter
Used module:         $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

17.3.16. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

17.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

17.3.18. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     \RISCV
Used module:         \ALU
Used module:         \ProgramCounter
Used module:         \RegisterFile
Used module:         \LoadStore
Used module:             \HalfReader
Used module:             \ByteReader
Used module:             \HalfWriter
Used module:             \ByteWriter
Used module:         \ControlUnit
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory
Used module:         $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter
Used module:         $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider

17.3.19. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     \RISCV
Used module:         \ALU
Used module:         \ProgramCounter
Used module:         \RegisterFile
Used module:         \LoadStore
Used module:             \HalfReader
Used module:             \ByteReader
Used module:             \HalfWriter
Used module:             \ByteWriter
Used module:         \ControlUnit
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory
Used module:         $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter
Used module:         $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'.
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'.
Removing unused module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'.
Removing unused module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'.
Removing unused module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'.
Removing unused module `\Controller'.
Removing unused module `\Interpreter'.
Removing unused module `\Memory'.
Removing unused module `\ClkDivider'.
Removing unused module `\ResetBootSystem'.
Removing unused module `\FIFO'.
Removing unused module `\uart_tx'.
Removing unused module `\uart_rx'.
Removing unused module `\UART'.
Removed 14 unused modules.
Module RISCV directly or indirectly displays text -> setting "keep" attribute.
Module ControlUnit directly or indirectly displays text -> setting "keep" attribute.
Module processorci_top directly or indirectly displays text -> setting "keep" attribute.

17.4. Executing PROC pass (convert processes to netlists).

17.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$634'.
Found and cleaned up 1 empty switch in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$816'.
Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$816'.
Cleaned up 2 empty switches.

17.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$741 in module TRELLIS_FF.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$693 in module DPR16X4C.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$635 in module TRELLIS_DPR16X4.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:36$996 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:25$988 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1189 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1187 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1179 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1176 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1170 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1165 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1160 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1151 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1138 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1136 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1128 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1114 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1108 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1103 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:57$1090 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:36$1081 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
Marked 15 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/interpreter.v:116$1045 in module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.
Removed 1 dead cases from process $proc$/eda/processor-ci-controller/modules/uart.v:203$1037 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:203$1037 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:187$1032 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:132$1027 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:74$1022 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/memory.v:36$805 in module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/controller.v:113$794 in module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.
Marked 5 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/reset.v:25$744 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:23$100 in module RegisterFile.
Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:17$63 in module ProgramCounter.
Marked 25 switch rules as full_case in process $proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16 in module ControlUnit.
Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:16$1 in module ALU.
Removed a total of 1 dead cases.

17.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 4 redundant assignments.
Promoted 124 assignments to connections.

17.4.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$742'.
  Set init value: \Q = 1'0
Found init rule in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1021'.
  Set init value: \read_ptr = 6'000000
  Set init value: \write_ptr = 6'000000
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1191'.
  Set init value: \i = 0
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1144'.
  Set init value: \i = 0
Found init rule in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1096'.
  Set init value: \clk_o_auto = 1'0
  Set init value: \clk_counter = 0
  Set init value: \pulse_counter = 0
Found init rule in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1074'.
  Set init value: \state = 8'00000000
  Set init value: \counter = 8'00000000
  Set init value: \read_buffer = 0
  Set init value: \timeout = 0
  Set init value: \accumulator = 64'0000000000000000000000000000000000000000000000000000000000000000
Found init rule in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1044'.
  Set init value: \read_response = 1'0
  Set init value: \write_response = 1'0
  Set init value: \read_data = 0
  Set init value: \uart_tx_en = 1'0
  Set init value: \tx_fifo_read = 1'0
  Set init value: \tx_fifo_write = 1'0
  Set init value: \rx_fifo_read = 1'0
  Set init value: \rx_fifo_write = 1'0
  Set init value: \uart_tx_data = 8'00000000
  Set init value: \tx_fifo_write_data = 8'00000000
  Set init value: \rx_fifo_write_data = 8'00000000
  Set init value: \counter_write = 3'000
  Set init value: \counter_read = 3'000
  Set init value: \state_read = 4'0000
  Set init value: \state_write = 4'0000
Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$751'.
  Set init value: \reset_o = 1'0
  Set init value: \state = 2'01
  Set init value: \counter = 6'000000
Found init rule in `\RISCV.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:16$206'.
  Set init value: \ir = 0
Found init rule in `\ProgramCounter.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:15$65'.
  Set init value: \pc = 0
Found init rule in `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:41$62'.
  Set init value: \branchTestTrue = 1'0

17.4.5. Executing PROC_ARST pass (detect async resets in processes).

17.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~129 debug messages>

17.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$742'.
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$741'.
     1/1: $0\Q[0:0]
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$716'.
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$693'.
     1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$692_EN[3:0]$699
     2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$692_DATA[3:0]$698
     3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$692_ADDR[3:0]$697
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$659'.
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$635'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$633_EN[3:0]$641
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$633_DATA[3:0]$640
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$633_ADDR[3:0]$639
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$634'.
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1021'.
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$996'.
     1/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$1008
     2/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_DATA[7:0]$1007
     3/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_ADDR[5:0]$1006
     4/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$1002
     5/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_DATA[7:0]$1001
     6/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_ADDR[5:0]$1000
     7/7: $0\write_ptr[5:0]
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$988'.
     1/2: $0\read_ptr[5:0]
     2/2: $0\read_data[7:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1191'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1189'.
     1/2: $0\rxd_reg_0[0:0]
     2/2: $0\rxd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1187'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1179'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1176'.
     1/1: $0\bit_sample[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1170'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1165'.
     1/11: $3\i[31:0]
     2/11: $0\recieved_data[7:0] [1]
     3/11: $0\recieved_data[7:0] [0]
     4/11: $0\recieved_data[7:0] [2]
     5/11: $0\recieved_data[7:0] [3]
     6/11: $0\recieved_data[7:0] [4]
     7/11: $0\recieved_data[7:0] [5]
     8/11: $0\recieved_data[7:0] [6]
     9/11: $0\recieved_data[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1160'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1151'.
     1/1: $0\uart_rx_data[7:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1144'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1138'.
     1/1: $0\txd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1136'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1128'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1114'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1108'.
     1/11: $3\i[31:0]
     2/11: $0\data_to_send[7:0] [1]
     3/11: $0\data_to_send[7:0] [0]
     4/11: $0\data_to_send[7:0] [2]
     5/11: $0\data_to_send[7:0] [3]
     6/11: $0\data_to_send[7:0] [4]
     7/11: $0\data_to_send[7:0] [5]
     8/11: $0\data_to_send[7:0] [6]
     9/11: $0\data_to_send[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1103'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1096'.
Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1090'.
     1/1: $0\pulse_counter[31:0]
Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1081'.
     1/2: $0\clk_counter[31:0]
     2/2: $0\clk_o_auto[0:0]
Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1074'.
Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
     1/28: $0\state[7:0]
     2/28: $0\reset_bus[0:0]
     3/28: $0\memory_write[0:0]
     4/28: $0\memory_read[0:0]
     5/28: $0\write_pulse[0:0]
     6/28: $0\core_reset[0:0]
     7/28: $0\communication_write[0:0]
     8/28: $0\communication_read[0:0]
     9/28: $0\temp_buffer[63:0]
    10/28: $0\accumulator[63:0]
    11/28: $0\timeout_counter[31:0]
    12/28: $0\timeout[31:0]
    13/28: $0\read_buffer[31:0]
    14/28: $0\communication_buffer[31:0]
    15/28: $0\num_of_positions[23:0]
    16/28: $0\num_of_pages[23:0]
    17/28: $0\return_state[7:0]
    18/28: $0\memory_page_number[23:0]
    19/28: $0\memory_mux_selector[0:0]
    20/28: $0\end_position[31:0]
    21/28: $0\memory_page_size[23:0]
    22/28: $0\bus_mode[0:0]
    23/28: $0\num_of_cycles_to_pulse[31:0]
    24/28: $0\core_clk_enable[0:0]
    25/28: $0\communication_write_data[31:0]
    26/28: $0\counter[7:0]
    27/28: $0\write_data[31:0]
    28/28: $0\address[31:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1044'.
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1037'.
     1/4: $0\tx_fifo_read[0:0]
     2/4: $0\uart_tx_en[0:0]
     3/4: $0\tx_fifo_read_state[1:0]
     4/4: $0\uart_tx_data[7:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1032'.
     1/2: $0\rx_fifo_write[0:0]
     2/2: $0\rx_fifo_write_data[7:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1027'.
     1/6: $0\tx_fifo_write[0:0]
     2/6: $0\write_response[0:0]
     3/6: $0\state_write[3:0]
     4/6: $0\counter_write[2:0]
     5/6: $0\write_data_buffer[31:0]
     6/6: $0\tx_fifo_write_data[7:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1022'.
     1/5: $0\read_response[0:0]
     2/5: $0\rx_fifo_read[0:0]
     3/5: $0\state_read[3:0]
     4/5: $0\counter_read[2:0]
     5/5: $0\read_data[31:0]
Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$815'.
Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$805'.
     1/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$814
     2/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_DATA[31:0]$813
     3/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_ADDR[31:0]$812
     4/4: $0\read_sync[31:0]
Creating decoders for process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$794'.
     1/1: $0\finish_execution[0:0]
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$751'.
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$744'.
     1/3: $0\counter[5:0]
     2/3: $0\state[1:0]
     3/3: $0\reset_o[0:0]
Creating decoders for process `\RISCV.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:16$206'.
Creating decoders for process `\RISCV.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:40$181'.
     1/1: $0\ir[31:0]
Creating decoders for process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
Creating decoders for process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:23$100'.
     1/3: $1$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$108
     2/3: $1$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_DATA[31:0]$107
     3/3: $1$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_ADDR[4:0]$106
Creating decoders for process `\ProgramCounter.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:15$65'.
Creating decoders for process `\ProgramCounter.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:17$63'.
     1/2: $0\pc[31:0]
     2/2: $0\prevPc[31:0]
Creating decoders for process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:41$62'.
Creating decoders for process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'.
     1/26: $display$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:317$61_EN
     2/26: $display$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:221$50_EN
     3/26: $display$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:198$47_EN
     4/26: $display$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:154$37_EN
     5/26: $display$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:135$31_EN
     6/26: $display$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:116$27_EN
     7/26: $display$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:104$25_EN
     8/26: $display$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:94$23_EN
     9/26: $display$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:90$21_EN
    10/26: $display$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:83$20_EN
    11/26: $display$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:63$18_EN
    12/26: $0\branchTestTrue[0:0]
    13/26: $0\state[2:0]
    14/26: $0\readSignExtend[0:0]
    15/26: $0\writeLen[1:0]
    16/26: $0\readLen[1:0]
    17/26: $0\aluOperation[3:0]
    18/26: $0\aluSrcB[2:0]
    19/26: $0\aluSrcA[1:0]
    20/26: $0\pcWriteEnable[0:0]
    21/26: $0\regWriteEnable[0:0]
    22/26: $0\regDataSrc[1:0]
    23/26: $0\incrementPc[0:0]
    24/26: $0\addressIsPc[0:0]
    25/26: $0\irWriteEnable[0:0]
    26/26: $0\writeEnable[0:0]
Creating decoders for process `\ALU.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:16$1'.
     1/1: $1\res[31:0]

17.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1160'.
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1103'.
No latch inferred for signal `\RegisterFile.\i' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$67_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$68_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$69_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$70_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$71_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$72_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$73_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$74_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$75_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$76_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$77_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$78_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$79_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$80_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$81_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$82_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$83_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$84_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$85_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$86_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$87_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$88_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$89_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$90_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$91_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$92_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$93_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$94_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$95_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$96_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$97_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$98_EN' from process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
No latch inferred for signal `\ALU.\res' from process `\ALU.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:16$1'.

17.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$741'.
  created $dff cell `$procdff$3477' with positive edge clock.
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$716'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$677_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$716'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$678_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$716'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$679_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$716'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$680_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$716'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$681_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$716'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$682_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$716'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$683_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$716'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$684_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$716'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$685_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$716'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$686_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$716'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$687_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$716'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$688_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$716'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$689_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$716'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$690_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$716'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$691_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$716'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$692_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$693'.
  created $dff cell `$procdff$3478' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$692_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$693'.
  created $dff cell `$procdff$3479' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$692_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$693'.
  created $dff cell `$procdff$3480' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$659'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$617_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$659'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$618_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$659'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$619_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$659'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$620_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$659'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$621_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$659'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$622_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$659'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$623_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$659'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$624_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$659'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$625_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$659'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$626_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$659'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$627_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$659'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$628_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$659'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$629_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$659'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$630_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$659'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$631_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$659'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$632_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$659'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$633_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$635'.
  created $dff cell `$procdff$3481' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$633_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$635'.
  created $dff cell `$procdff$3482' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$633_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$635'.
  created $dff cell `$procdff$3483' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$634'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\write_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$996'.
  created $dff cell `$procdff$3484' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_ADDR' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$996'.
  created $dff cell `$procdff$3485' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_DATA' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$996'.
  created $dff cell `$procdff$3486' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$996'.
  created $dff cell `$procdff$3487' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_data' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$988'.
  created $dff cell `$procdff$3488' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$988'.
  created $dff cell `$procdff$3489' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1189'.
  created $dff cell `$procdff$3490' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1189'.
  created $dff cell `$procdff$3491' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1187'.
  created $dff cell `$procdff$3492' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1179'.
  created $dff cell `$procdff$3493' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1176'.
  created $dff cell `$procdff$3494' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1170'.
  created $dff cell `$procdff$3495' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1165'.
  created $dff cell `$procdff$3496' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1165'.
  created $dff cell `$procdff$3497' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1151'.
  created $dff cell `$procdff$3498' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1138'.
  created $dff cell `$procdff$3499' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1136'.
  created $dff cell `$procdff$3500' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1128'.
  created $dff cell `$procdff$3501' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1114'.
  created $dff cell `$procdff$3502' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1108'.
  created $dff cell `$procdff$3503' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1108'.
  created $dff cell `$procdff$3504' with positive edge clock.
Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\pulse_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1090'.
  created $dff cell `$procdff$3505' with positive edge clock.
Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_o_auto' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1081'.
  created $dff cell `$procdff$3506' with positive edge clock.
Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1081'.
  created $dff cell `$procdff$3507' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3508' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\address' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3509' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3510' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3511' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3512' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3513' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3514' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3515' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3516' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3517' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_clk_enable' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3518' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_reset' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3519' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_cycles_to_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3520' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\reset_bus' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3521' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\bus_mode' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3522' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_size' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3523' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\end_position' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3524' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_mux_selector' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3525' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_number' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3526' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\return_state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3527' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_pages' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3528' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_positions' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3529' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3530' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\read_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3531' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3532' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout_counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3533' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\accumulator' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3534' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\temp_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
  created $dff cell `$procdff$3535' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_en' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1037'.
  created $dff cell `$procdff$3536' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1037'.
  created $dff cell `$procdff$3537' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1037'.
  created $dff cell `$procdff$3538' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read_state' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1037'.
  created $dff cell `$procdff$3539' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1032'.
  created $dff cell `$procdff$3540' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1032'.
  created $dff cell `$procdff$3541' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1027'.
  created $dff cell `$procdff$3542' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1027'.
  created $dff cell `$procdff$3543' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1027'.
  created $dff cell `$procdff$3544' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_data_buffer' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1027'.
  created $dff cell `$procdff$3545' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1027'.
  created $dff cell `$procdff$3546' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1027'.
  created $dff cell `$procdff$3547' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1022'.
  created $dff cell `$procdff$3548' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1022'.
  created $dff cell `$procdff$3549' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1022'.
  created $dff cell `$procdff$3550' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1022'.
  created $dff cell `$procdff$3551' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1022'.
  created $dff cell `$procdff$3552' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_write_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$815'.
  created $dff cell `$procdff$3553' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_read_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$815'.
  created $dff cell `$procdff$3554' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\read_sync' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$805'.
  created $dff cell `$procdff$3555' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_ADDR' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$805'.
  created $dff cell `$procdff$3556' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_DATA' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$805'.
  created $dff cell `$procdff$3557' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$805'.
  created $dff cell `$procdff$3558' with positive edge clock.
Creating register for signal `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.\finish_execution' using process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$794'.
  created $dff cell `$procdff$3559' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$744'.
  created $dff cell `$procdff$3560' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$744'.
  created $dff cell `$procdff$3561' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$744'.
  created $dff cell `$procdff$3562' with positive edge clock.
Creating register for signal `\RISCV.\ir' using process `\RISCV.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:40$181'.
  created $dff cell `$procdff$3563' with positive edge clock.
Creating register for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_ADDR' using process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:23$100'.
  created $dff cell `$procdff$3564' with positive edge clock.
Creating register for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_DATA' using process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:23$100'.
  created $dff cell `$procdff$3565' with positive edge clock.
Creating register for signal `\RegisterFile.$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN' using process `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:23$100'.
  created $dff cell `$procdff$3566' with positive edge clock.
Creating register for signal `\ProgramCounter.\prevPc' using process `\ProgramCounter.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:17$63'.
  created $dff cell `$procdff$3567' with positive edge clock.
Creating register for signal `\ProgramCounter.\pc' using process `\ProgramCounter.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:17$63'.
  created $dff cell `$procdff$3568' with positive edge clock.
Creating register for signal `\ControlUnit.\writeEnable' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'.
  created $dff cell `$procdff$3569' with positive edge clock.
Creating register for signal `\ControlUnit.\irWriteEnable' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'.
  created $dff cell `$procdff$3570' with positive edge clock.
Creating register for signal `\ControlUnit.\addressIsPc' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'.
  created $dff cell `$procdff$3571' with positive edge clock.
Creating register for signal `\ControlUnit.\incrementPc' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'.
  created $dff cell `$procdff$3572' with positive edge clock.
Creating register for signal `\ControlUnit.\regDataSrc' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'.
  created $dff cell `$procdff$3573' with positive edge clock.
Creating register for signal `\ControlUnit.\regWriteEnable' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'.
  created $dff cell `$procdff$3574' with positive edge clock.
Creating register for signal `\ControlUnit.\pcWriteEnable' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'.
  created $dff cell `$procdff$3575' with positive edge clock.
Creating register for signal `\ControlUnit.\aluSrcA' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'.
  created $dff cell `$procdff$3576' with positive edge clock.
Creating register for signal `\ControlUnit.\aluSrcB' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'.
  created $dff cell `$procdff$3577' with positive edge clock.
Creating register for signal `\ControlUnit.\aluOperation' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'.
  created $dff cell `$procdff$3578' with positive edge clock.
Creating register for signal `\ControlUnit.\readLen' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'.
  created $dff cell `$procdff$3579' with positive edge clock.
Creating register for signal `\ControlUnit.\writeLen' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'.
  created $dff cell `$procdff$3580' with positive edge clock.
Creating register for signal `\ControlUnit.\readSignExtend' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'.
  created $dff cell `$procdff$3581' with positive edge clock.
Creating register for signal `\ControlUnit.\state' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'.
  created $dff cell `$procdff$3582' with positive edge clock.
Creating register for signal `\ControlUnit.\branchTestTrue' using process `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'.
  created $dff cell `$procdff$3583' with positive edge clock.

17.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

17.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$742'.
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$741'.
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$741'.
Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$716'.
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$693'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$659'.
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$635'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$634'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1021'.
Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$996'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$996'.
Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$988'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$988'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1191'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1189'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1189'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1187'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1187'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1179'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1179'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1176'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1176'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1170'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1170'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1165'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1165'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1160'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1160'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1151'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1151'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1144'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1138'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1138'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1136'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1136'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1128'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1128'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1114'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1114'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1108'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1108'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1103'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1103'.
Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1096'.
Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1090'.
Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1090'.
Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1081'.
Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1081'.
Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1074'.
Found and cleaned up 15 empty switches in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1045'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1044'.
Found and cleaned up 3 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1037'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1037'.
Found and cleaned up 2 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1032'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1032'.
Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1027'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1027'.
Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1022'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1022'.
Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$815'.
Found and cleaned up 2 empty switches in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$805'.
Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$805'.
Found and cleaned up 4 empty switches in `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$794'.
Removing empty process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$794'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$751'.
Found and cleaned up 6 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$744'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$744'.
Removing empty process `RISCV.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:16$206'.
Found and cleaned up 1 empty switch in `\RISCV.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:40$181'.
Removing empty process `RISCV.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:40$181'.
Removing empty process `RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:0$147'.
Found and cleaned up 1 empty switch in `\RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:23$100'.
Removing empty process `RegisterFile.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:23$100'.
Removing empty process `ProgramCounter.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:15$65'.
Found and cleaned up 3 empty switches in `\ProgramCounter.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:17$63'.
Removing empty process `ProgramCounter.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:17$63'.
Removing empty process `ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:41$62'.
Found and cleaned up 30 empty switches in `\ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'.
Removing empty process `ControlUnit.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:43$16'.
Found and cleaned up 1 empty switch in `\ALU.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:16$1'.
Removing empty process `ALU.$proc$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:16$1'.
Cleaned up 129 empty switches.

17.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
<suppressed ~5 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
<suppressed ~21 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
<suppressed ~19 debug messages>
Optimizing module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
<suppressed ~9 debug messages>
Optimizing module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.
<suppressed ~15 debug messages>
Optimizing module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
<suppressed ~24 debug messages>
Optimizing module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.
<suppressed ~3 debug messages>
Optimizing module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.
<suppressed ~26 debug messages>
Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
<suppressed ~8 debug messages>
Optimizing module LoadStore.
<suppressed ~2 debug messages>
Optimizing module HalfWriter.
<suppressed ~1 debug messages>
Optimizing module ByteWriter.
<suppressed ~1 debug messages>
Optimizing module HalfReader.
<suppressed ~1 debug messages>
Optimizing module ByteReader.
<suppressed ~1 debug messages>
Optimizing module RISCV.
<suppressed ~3 debug messages>
Optimizing module RegisterFile.
<suppressed ~3 debug messages>
Optimizing module ProgramCounter.
Optimizing module ControlUnit.
<suppressed ~7 debug messages>
Optimizing module ALU.
<suppressed ~1 debug messages>
Optimizing module processorci_top.

17.5. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Deleting now unused module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
Deleting now unused module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.
Deleting now unused module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Deleting now unused module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.
Deleting now unused module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.
Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Deleting now unused module LoadStore.
Deleting now unused module HalfWriter.
Deleting now unused module ByteWriter.
Deleting now unused module HalfReader.
Deleting now unused module ByteReader.
Deleting now unused module RISCV.
Deleting now unused module RegisterFile.
Deleting now unused module ProgramCounter.
Deleting now unused module ControlUnit.
Deleting now unused module ALU.
<suppressed ~21 debug messages>

17.6. Executing TRIBUF pass.

17.7. Executing DEMINOUT pass (demote inout ports to input or output).

17.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~50 debug messages>

17.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 82 unused cells and 1002 unused wires.
<suppressed ~102 debug messages>

17.10. Executing CHECK pass (checking for obvious problems).
Checking module processorci_top...
Warning: Wire processorci_top.\miso is used but has no driver.
Warning: Wire processorci_top.\intr is used but has no driver.
Warning: Wire processorci_top.\ResetBootSystem.start is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [31] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [30] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [29] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [28] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [27] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [26] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [25] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [24] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [23] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [22] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [21] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [20] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [19] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [18] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [17] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [16] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [15] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [14] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [13] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [12] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [11] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [10] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [9] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [8] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [7] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [6] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [5] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [4] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [3] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [2] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [1] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [0] is used but has no driver.
Found and reported 35 problems.

17.11. Executing OPT pass (performing simple optimizations).

17.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

17.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~567 debug messages>
Removed a total of 189 cells.

17.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1219.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1225.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1231.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1219.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1225.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1231.
Removed 6 multiplexer ports.
<suppressed ~148 debug messages>

17.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1880: { $auto$opt_reduce.cc:134:opt_pmux$3611 $auto$opt_reduce.cc:134:opt_pmux$3609 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1949: $auto$opt_reduce.cc:134:opt_pmux$3613
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1974: { $flatten\Controller.\Interpreter.$procmux$1595_CMP $auto$opt_reduce.cc:134:opt_pmux$3615 $flatten\Controller.\Interpreter.$procmux$1585_CMP }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Data_Memory.$procmux$2465:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0]
      New connections: $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [31:1] = { $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2002: { $flatten\Controller.\Interpreter.$procmux$1581_CMP $flatten\Controller.\Interpreter.$procmux$1574_CMP $flatten\Controller.\Interpreter.$procmux$1563_CMP $flatten\Controller.\Interpreter.$procmux$1557_CMP $auto$opt_reduce.cc:134:opt_pmux$3617 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2034: { $auto$opt_reduce.cc:134:opt_pmux$3621 $auto$opt_reduce.cc:134:opt_pmux$3619 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2116: { $flatten\Controller.\Interpreter.$procmux$1575_CMP $auto$opt_reduce.cc:134:opt_pmux$3623 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2127: { $flatten\Controller.\Interpreter.$procmux$1716_CMP $flatten\Controller.\Interpreter.$procmux$1615_CMP $auto$opt_reduce.cc:134:opt_pmux$3625 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2137: { $flatten\Controller.\Interpreter.$procmux$1614_CMP $auto$opt_reduce.cc:134:opt_pmux$3629 $auto$opt_reduce.cc:134:opt_pmux$3627 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2213: { $auto$opt_reduce.cc:134:opt_pmux$3631 $flatten\Controller.\Interpreter.$procmux$1614_CMP }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1555: { $flatten\Controller.\Interpreter.$procmux$1649_CMP $flatten\Controller.\Interpreter.$procmux$1645_CMP $flatten\Controller.\Interpreter.$procmux$1641_CMP $flatten\Controller.\Interpreter.$procmux$1615_CMP $flatten\Controller.\Interpreter.$procmux$1614_CMP $flatten\Controller.\Interpreter.$procmux$1610_CMP $flatten\Controller.\Interpreter.$procmux$1609_CMP $flatten\Controller.\Interpreter.$procmux$1605_CMP $flatten\Controller.\Interpreter.$procmux$1595_CMP $flatten\Controller.\Interpreter.$procmux$1591_CMP $auto$opt_reduce.cc:134:opt_pmux$3639 $flatten\Controller.\Interpreter.$procmux$1586_CMP $flatten\Controller.\Interpreter.$procmux$1585_CMP $auto$opt_reduce.cc:134:opt_pmux$3637 $flatten\Controller.\Interpreter.$procmux$1580_CMP $flatten\Controller.\Interpreter.$procmux$1579_CMP $flatten\Controller.\Interpreter.$procmux$1574_CMP $flatten\Controller.\Interpreter.$procmux$1570_CMP $flatten\Controller.\Interpreter.$procmux$1569_CMP $auto$opt_reduce.cc:134:opt_pmux$3635 $flatten\Controller.\Interpreter.$procmux$1563_CMP $flatten\Controller.\Interpreter.$procmux$1562_CMP $flatten\Controller.\Interpreter.$procmux$1561_CMP $auto$opt_reduce.cc:134:opt_pmux$3633 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2237: { $flatten\Controller.\Interpreter.$procmux$1682_CMP $flatten\Controller.\Interpreter.$procmux$1681_CMP $auto$opt_reduce.cc:134:opt_pmux$3641 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2263: { $auto$opt_reduce.cc:134:opt_pmux$3643 $flatten\Controller.\Interpreter.$procmux$1681_CMP $flatten\Controller.\Interpreter.$procmux$1600_CMP $flatten\Controller.\Interpreter.$procmux$1595_CMP $flatten\Controller.\Interpreter.$procmux$1585_CMP }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Memory.$procmux$2465:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0]
      New connections: $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [31:1] = { $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_EN[31:0]$808 [0] }
    New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2333: $auto$opt_reduce.cc:134:opt_pmux$3645
    New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2397: $auto$opt_reduce.cc:134:opt_pmux$3647
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1216:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1216_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1216_Y [0]
      New connections: $flatten\Controller.\Uart.\RX_FIFO.$procmux$1216_Y [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$procmux$1216_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1216_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1216_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1216_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1216_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1216_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1216_Y [0] }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1827: { $flatten\Controller.\Interpreter.$procmux$1595_CMP $auto$opt_reduce.cc:134:opt_pmux$3649 $flatten\Controller.\Interpreter.$procmux$1585_CMP }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1216:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1216_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1216_Y [0]
      New connections: $flatten\Controller.\Uart.\TX_FIFO.$procmux$1216_Y [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$procmux$1216_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1216_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1216_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1216_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1216_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1216_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1216_Y [0] }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1655: $auto$opt_reduce.cc:134:opt_pmux$3651
    New ctrl vector for $pmux cell $flatten\Riscado_V.\ctrlUnit.$procmux$2763: $auto$opt_reduce.cc:134:opt_pmux$3653
    New ctrl vector for $pmux cell $flatten\Riscado_V.\ctrlUnit.$procmux$2875: $auto$opt_reduce.cc:134:opt_pmux$3655
    New ctrl vector for $pmux cell $flatten\Riscado_V.\ctrlUnit.$procmux$2972: { $flatten\Riscado_V.\ctrlUnit.$procmux$2918_CMP $auto$opt_reduce.cc:134:opt_pmux$3659 $auto$opt_reduce.cc:134:opt_pmux$3657 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1679: $auto$opt_reduce.cc:134:opt_pmux$3661
    New ctrl vector for $pmux cell $flatten\Riscado_V.\ctrlUnit.$procmux$3045: { $auto$opt_reduce.cc:134:opt_pmux$3665 $auto$opt_reduce.cc:134:opt_pmux$3663 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1701: $auto$opt_reduce.cc:134:opt_pmux$3667
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1712: $auto$opt_reduce.cc:134:opt_pmux$3669
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1760: $auto$opt_reduce.cc:134:opt_pmux$3671
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1802: $auto$opt_reduce.cc:134:opt_pmux$3673
    Consolidated identical input bits for $mux cell $flatten\Riscado_V.\registerFile.$procmux$2528:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103
      New ports: A=1'0, B=1'1, Y=$flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0]
      New connections: $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [31:1] = { $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] $flatten\Riscado_V.\registerFile.$0$memwr$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:26$99_EN[31:0]$103 [0] }
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1234:
      Old ports: A=$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$1008, B=8'00000000, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999
      New ports: A=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1216_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0]
      New connections: $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1234:
      Old ports: A=$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$1008, B=8'00000000, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999
      New ports: A=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1216_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0]
      New connections: $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_EN[7:0]$999 [0] }
  Optimizing cells in module \processorci_top.
Performed a total of 32 changes.

17.11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~60 debug messages>
Removed a total of 20 cells.

17.11.6. Executing OPT_DFF pass (perform DFF optimizations).

17.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 227 unused wires.
<suppressed ~13 debug messages>

17.11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

17.11.9. Rerunning OPT passes. (Maybe there is more to do..)

17.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~157 debug messages>

17.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1827: { $auto$opt_reduce.cc:134:opt_pmux$3615 $auto$opt_reduce.cc:134:opt_pmux$3675 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1974: { $auto$opt_reduce.cc:134:opt_pmux$3615 $auto$opt_reduce.cc:134:opt_pmux$3677 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2263: { $auto$opt_reduce.cc:134:opt_pmux$3643 $flatten\Controller.\Interpreter.$procmux$1681_CMP $flatten\Controller.\Interpreter.$procmux$1600_CMP $auto$opt_reduce.cc:134:opt_pmux$3679 }
  Optimizing cells in module \processorci_top.
Performed a total of 3 changes.

17.11.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

17.11.13. Executing OPT_DFF pass (perform DFF optimizations).

17.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 2 unused wires.
<suppressed ~1 debug messages>

17.11.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

17.11.16. Rerunning OPT passes. (Maybe there is more to do..)

17.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~157 debug messages>

17.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

17.11.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

17.11.20. Executing OPT_DFF pass (perform DFF optimizations).

17.11.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

17.11.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

17.11.23. Finished OPT passes. (There is nothing left to do.)

17.12. Executing FSM pass (extract and optimize FSM).

17.12.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking processorci_top.Controller.Interpreter.return_state as FSM state register:
    Users of register don't seem to benefit from recoding.
Found FSM state register processorci_top.Controller.Uart.i_uart_rx.fsm_state.
Not marking processorci_top.Controller.Uart.i_uart_tx.fsm_state as FSM state register:
    Users of register don't seem to benefit from recoding.
Not marking processorci_top.Controller.Uart.state_read as FSM state register:
    Register has an initialization value.
Not marking processorci_top.Controller.Uart.state_write as FSM state register:
    Register has an initialization value.
Found FSM state register processorci_top.Controller.Uart.tx_fifo_read_state.
Not marking processorci_top.ResetBootSystem.state as FSM state register:
    Register has an initialization value.
    Circuit seems to be self-resetting.
Found FSM state register processorci_top.Riscado_V.ctrlUnit.aluOperation.
Found FSM state register processorci_top.Riscado_V.ctrlUnit.aluSrcA.
Found FSM state register processorci_top.Riscado_V.ctrlUnit.aluSrcB.
Found FSM state register processorci_top.Riscado_V.ctrlUnit.readLen.
Found FSM state register processorci_top.Riscado_V.ctrlUnit.regDataSrc.
Found FSM state register processorci_top.Riscado_V.ctrlUnit.state.
Found FSM state register processorci_top.Riscado_V.ctrlUnit.writeLen.

17.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\Controller.Uart.i_uart_rx.fsm_state' from module `\processorci_top'.
  found $dff cell for state register: $flatten\Controller.\Uart.\i_uart_rx.$procdff$3492
  root of input selection tree: $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1155_Y
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1168_Y
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1181_Y
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1167_Y
  found state code: 3'000
  found ctrl input: \Controller.Uart.i_uart_rx.next_bit
  found state code: 3'011
  found ctrl input: \Controller.Uart.i_uart_rx.payload_done
  found state code: 3'010
  found state code: 3'001
  found ctrl input: \Controller.Uart.i_uart_rx.rxd_reg
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1181_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1172_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1168_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1167_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1155_Y
  ctrl inputs: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.rxd_reg \Controller.Uart.i_uart_rx.next_bit \Controller.Uart.i_uart_rx.payload_done }
  ctrl outputs: { $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1155_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1167_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1168_Y $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1172_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1181_Y $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] }
  transition:      3'000 4'00-- ->      3'001 8'01010001
  transition:      3'000 4'01-- ->      3'000 8'01010000
  transition:      3'000 4'1--- ->      3'000 8'01010000
  transition:      3'010 4'0--0 ->      3'010 8'00100010
  transition:      3'010 4'0--1 ->      3'011 8'00100011
  transition:      3'010 4'1--- ->      3'000 8'00100000
  transition:      3'001 4'0-0- ->      3'001 8'00011001
  transition:      3'001 4'0-1- ->      3'010 8'00011010
  transition:      3'001 4'1--- ->      3'000 8'00011000
  transition:      3'011 4'0-0- ->      3'011 8'10010011
  transition:      3'011 4'0-1- ->      3'000 8'10010000
  transition:      3'011 4'1--- ->      3'000 8'10010000
Extracting FSM `\Controller.Uart.tx_fifo_read_state' from module `\processorci_top'.
  found $dff cell for state register: $flatten\Controller.\Uart.$procdff$3539
  root of input selection tree: $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0]
  found reset state: 2'00 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\Controller.\Uart.$procmux$2294_CMP
  found ctrl input: $flatten\Controller.\Uart.$procmux$2289_CMP
  found ctrl input: $flatten\Controller.\Uart.$procmux$2296_CMP
  found ctrl input: $flatten\Controller.\Uart.$procmux$2283_CMP
  found state code: 2'00
  found state code: 2'11
  found state code: 2'10
  found ctrl input: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1041_Y
  found state code: 2'01
  found ctrl output: $flatten\Controller.\Uart.$procmux$2283_CMP
  found ctrl output: $flatten\Controller.\Uart.$procmux$2289_CMP
  found ctrl output: $flatten\Controller.\Uart.$procmux$2294_CMP
  found ctrl output: $flatten\Controller.\Uart.$procmux$2296_CMP
  ctrl inputs: { \ResetBootSystem.reset_o $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1041_Y }
  ctrl outputs: { $flatten\Controller.\Uart.$procmux$2296_CMP $flatten\Controller.\Uart.$procmux$2294_CMP $flatten\Controller.\Uart.$procmux$2289_CMP $flatten\Controller.\Uart.$procmux$2283_CMP $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] }
  transition:       2'00 2'00 ->       2'00 6'000100
  transition:       2'00 2'01 ->       2'01 6'000101
  transition:       2'00 2'1- ->       2'00 6'000100
  transition:       2'10 2'0- ->       2'11 6'001011
  transition:       2'10 2'1- ->       2'00 6'001000
  transition:       2'01 2'0- ->       2'10 6'100010
  transition:       2'01 2'1- ->       2'00 6'100000
  transition:       2'11 2'0- ->       2'00 6'010000
  transition:       2'11 2'1- ->       2'00 6'010000
Extracting FSM `\Riscado_V.ctrlUnit.aluOperation' from module `\processorci_top'.
  found $dff cell for state register: $flatten\Riscado_V.\ctrlUnit.$procdff$3578
  root of input selection tree: $flatten\Riscado_V.\ctrlUnit.$0\aluOperation[3:0]
  found ctrl input: \Controller.Interpreter.core_reset
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y
  found state code: 4'0000
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y
  found ctrl input: $auto$opt_reduce.cc:134:opt_pmux$3663
  found ctrl input: $auto$opt_reduce.cc:134:opt_pmux$3665
  found state code: 4'1100
  found state code: 4'0011
  found state code: 4'0010
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$procmux$3046_CMP
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$procmux$2764_CMP
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$procmux$2973_CMP
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$procmux$2765_CMP
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$procmux$3060_CMP
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$procmux$2918_CMP
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$procmux$2876_CMP
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$procmux$2766_CMP
  found state code: 4'0111
  found state code: 4'0110
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:123$28_Y
  found state code: 4'0101
  found state code: 4'1101
  found state code: 4'0100
  found state code: 4'0001
  found state code: 4'1000
  found state code: 4'1010
  found state code: 4'1001
  found ctrl output: $flatten\Riscado_V.\alu.$procmux$3465_CMP
  found ctrl output: $flatten\Riscado_V.\alu.$procmux$3466_CMP
  found ctrl output: $flatten\Riscado_V.\alu.$procmux$3467_CMP
  found ctrl output: $flatten\Riscado_V.\alu.$procmux$3468_CMP
  found ctrl output: $flatten\Riscado_V.\alu.$procmux$3469_CMP
  found ctrl output: $flatten\Riscado_V.\alu.$procmux$3470_CMP
  found ctrl output: $flatten\Riscado_V.\alu.$procmux$3471_CMP
  found ctrl output: $flatten\Riscado_V.\alu.$procmux$3472_CMP
  found ctrl output: $flatten\Riscado_V.\alu.$procmux$3473_CMP
  found ctrl output: $flatten\Riscado_V.\alu.$procmux$3474_CMP
  found ctrl output: $flatten\Riscado_V.\alu.$procmux$3475_CMP
  found ctrl output: $flatten\Riscado_V.\alu.$procmux$3476_CMP
  ctrl inputs: { $flatten\Riscado_V.\ctrlUnit.$procmux$3060_CMP $flatten\Riscado_V.\ctrlUnit.$procmux$3046_CMP $flatten\Riscado_V.\ctrlUnit.$procmux$2973_CMP $flatten\Riscado_V.\ctrlUnit.$procmux$2918_CMP $flatten\Riscado_V.\ctrlUnit.$procmux$2876_CMP $flatten\Riscado_V.\ctrlUnit.$procmux$2766_CMP $flatten\Riscado_V.\ctrlUnit.$procmux$2765_CMP $flatten\Riscado_V.\ctrlUnit.$procmux$2764_CMP $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:123$28_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y $auto$opt_reduce.cc:134:opt_pmux$3665 $auto$opt_reduce.cc:134:opt_pmux$3663 \Controller.Interpreter.core_reset }
  ctrl outputs: { $flatten\Riscado_V.\ctrlUnit.$0\aluOperation[3:0] $flatten\Riscado_V.\alu.$procmux$3476_CMP $flatten\Riscado_V.\alu.$procmux$3475_CMP $flatten\Riscado_V.\alu.$procmux$3474_CMP $flatten\Riscado_V.\alu.$procmux$3473_CMP $flatten\Riscado_V.\alu.$procmux$3472_CMP $flatten\Riscado_V.\alu.$procmux$3471_CMP $flatten\Riscado_V.\alu.$procmux$3470_CMP $flatten\Riscado_V.\alu.$procmux$3469_CMP $flatten\Riscado_V.\alu.$procmux$3465_CMP $flatten\Riscado_V.\alu.$procmux$3466_CMP $flatten\Riscado_V.\alu.$procmux$3467_CMP $flatten\Riscado_V.\alu.$procmux$3468_CMP }
  transition:     4'0000 25'--------0000--00-00000--0 ->     4'0000 16'0000100000000000
  transition:     4'0000 25'--------1000-000-00000--0 ->     4'0000 16'0000100000000000
  transition:     4'0000 25'--------1000-100-00000--0 ->     4'0000 16'0000100000000000
  transition:     4'0000 25'---------100-000-00000--0 ->     4'0000 16'0000100000000000
  transition:     4'0000 25'---------100-100-00000--0 ->     4'0000 16'0000100000000000
  transition:     4'0000 25'----------10-000-00000--0 ->     4'0000 16'0000100000000000
  transition:     4'0000 25'----------10-100-00000--0 ->     4'0000 16'0000100000000000
  transition:     4'0000 25'-----------1-000-00000--0 ->     4'0000 16'0000100000000000
  transition:     4'0000 25'-----------1-100-00000--0 ->     4'0000 16'0000100000000000
  transition:     4'0000 25'------------0010-00000--0 ->     4'0000 16'0000100000000000
  transition:     4'0000 25'------------1010-00000--0 ->     4'0000 16'0000100000000000
  transition:     4'0000 25'-------------110-00000000 ->     4'1100 16'1100100000000000
  transition:     4'0000 25'-------------110-000001-0 ->     4'0010 16'0010100000000000
  transition:     4'0000 25'-------------110-00000-10 ->     4'0011 16'0011100000000000
  transition:     4'0000 25'00000000-------1-00000--0 -> INVALID_STATE(4'x) 16'xxxx100000000000  <ignored invalid transition!>
  transition:     4'0000 25'-----1---------1000000--0 ->     4'0000 16'0000100000000000
  transition:     4'0000 25'-----1---------1100000--0 ->     4'1000 16'1000100000000000
  transition:     4'0000 25'----1----------1-00000--0 ->     4'0001 16'0001100000000000
  transition:     4'0000 25'---1-----------1-00000--0 ->     4'0010 16'0010100000000000
  transition:     4'0000 25'1--------------1-00000--0 ->     4'0011 16'0011100000000000
  transition:     4'0000 25'------1--------1-00000--0 ->     4'0100 16'0100100000000000
  transition:     4'0000 25'--1------------1000000--0 ->     4'0101 16'0101100000000000
  transition:     4'0000 25'--1------------1100000--0 ->     4'1101 16'1101100000000000
  transition:     4'0000 25'-------1-------1-00000--0 ->     4'0110 16'0110100000000000
  transition:     4'0000 25'-1-------------1-00000--0 ->     4'0111 16'0111100000000000
  transition:     4'0000 25'00000000---------10000--0 -> INVALID_STATE(4'x) 16'xxxx100000000000  <ignored invalid transition!>
  transition:     4'0000 25'-----1-----------10000--0 ->     4'0000 16'0000100000000000
  transition:     4'0000 25'----1------------10000--0 ->     4'0001 16'0001100000000000
  transition:     4'0000 25'---1-------------10000--0 ->     4'0010 16'0010100000000000
  transition:     4'0000 25'1----------------10000--0 ->     4'0011 16'0011100000000000
  transition:     4'0000 25'------1----------10000--0 ->     4'0100 16'0100100000000000
  transition:     4'0000 25'--1-------------010000--0 ->     4'0101 16'0101100000000000
  transition:     4'0000 25'--1-------------110000--0 ->     4'1101 16'1101100000000000
  transition:     4'0000 25'-------1---------10000--0 ->     4'0110 16'0110100000000000
  transition:     4'0000 25'-1---------------10000--0 ->     4'0111 16'0111100000000000
  transition:     4'0000 25'------------------1000--0 ->     4'0000 16'0000100000000000
  transition:     4'0000 25'-------------------100--0 ->     4'1010 16'1010100000000000
  transition:     4'0000 25'--------------------10--0 ->     4'0000 16'0000100000000000
  transition:     4'0000 25'---------------------1--0 ->     4'1001 16'1001100000000000
  transition:     4'0000 25'------------------------1 ->     4'0000 16'0000100000000000
  transition:     4'1000 25'--------0000--00-00000--0 ->     4'1000 16'1000000000000001
  transition:     4'1000 25'--------1000-000-00000--0 ->     4'1000 16'1000000000000001
  transition:     4'1000 25'--------1000-100-00000--0 ->     4'0000 16'0000000000000001
  transition:     4'1000 25'---------100-000-00000--0 ->     4'1000 16'1000000000000001
  transition:     4'1000 25'---------100-100-00000--0 ->     4'0000 16'0000000000000001
  transition:     4'1000 25'----------10-000-00000--0 ->     4'1000 16'1000000000000001
  transition:     4'1000 25'----------10-100-00000--0 ->     4'0000 16'0000000000000001
  transition:     4'1000 25'-----------1-000-00000--0 ->     4'1000 16'1000000000000001
  transition:     4'1000 25'-----------1-100-00000--0 ->     4'0000 16'0000000000000001
  transition:     4'1000 25'------------0010-00000--0 ->     4'1000 16'1000000000000001
  transition:     4'1000 25'------------1010-00000--0 ->     4'0000 16'0000000000000001
  transition:     4'1000 25'-------------110-00000000 ->     4'1100 16'1100000000000001
  transition:     4'1000 25'-------------110-000001-0 ->     4'0010 16'0010000000000001
  transition:     4'1000 25'-------------110-00000-10 ->     4'0011 16'0011000000000001
  transition:     4'1000 25'00000000-------1-00000--0 -> INVALID_STATE(4'x) 16'xxxx000000000001  <ignored invalid transition!>
  transition:     4'1000 25'-----1---------1000000--0 ->     4'0000 16'0000000000000001
  transition:     4'1000 25'-----1---------1100000--0 ->     4'1000 16'1000000000000001
  transition:     4'1000 25'----1----------1-00000--0 ->     4'0001 16'0001000000000001
  transition:     4'1000 25'---1-----------1-00000--0 ->     4'0010 16'0010000000000001
  transition:     4'1000 25'1--------------1-00000--0 ->     4'0011 16'0011000000000001
  transition:     4'1000 25'------1--------1-00000--0 ->     4'0100 16'0100000000000001
  transition:     4'1000 25'--1------------1000000--0 ->     4'0101 16'0101000000000001
  transition:     4'1000 25'--1------------1100000--0 ->     4'1101 16'1101000000000001
  transition:     4'1000 25'-------1-------1-00000--0 ->     4'0110 16'0110000000000001
  transition:     4'1000 25'-1-------------1-00000--0 ->     4'0111 16'0111000000000001
  transition:     4'1000 25'00000000---------10000--0 -> INVALID_STATE(4'x) 16'xxxx000000000001  <ignored invalid transition!>
  transition:     4'1000 25'-----1-----------10000--0 ->     4'0000 16'0000000000000001
  transition:     4'1000 25'----1------------10000--0 ->     4'0001 16'0001000000000001
  transition:     4'1000 25'---1-------------10000--0 ->     4'0010 16'0010000000000001
  transition:     4'1000 25'1----------------10000--0 ->     4'0011 16'0011000000000001
  transition:     4'1000 25'------1----------10000--0 ->     4'0100 16'0100000000000001
  transition:     4'1000 25'--1-------------010000--0 ->     4'0101 16'0101000000000001
  transition:     4'1000 25'--1-------------110000--0 ->     4'1101 16'1101000000000001
  transition:     4'1000 25'-------1---------10000--0 ->     4'0110 16'0110000000000001
  transition:     4'1000 25'-1---------------10000--0 ->     4'0111 16'0111000000000001
  transition:     4'1000 25'------------------1000--0 ->     4'0000 16'0000000000000001
  transition:     4'1000 25'-------------------100--0 ->     4'1010 16'1010000000000001
  transition:     4'1000 25'--------------------10--0 ->     4'1000 16'1000000000000001
  transition:     4'1000 25'---------------------1--0 ->     4'1001 16'1001000000000001
  transition:     4'1000 25'------------------------1 ->     4'1000 16'1000000000000001
  transition:     4'0100 25'--------0000--00-00000--0 ->     4'0100 16'0100000010000000
  transition:     4'0100 25'--------1000-000-00000--0 ->     4'0100 16'0100000010000000
  transition:     4'0100 25'--------1000-100-00000--0 ->     4'0000 16'0000000010000000
  transition:     4'0100 25'---------100-000-00000--0 ->     4'0100 16'0100000010000000
  transition:     4'0100 25'---------100-100-00000--0 ->     4'0000 16'0000000010000000
  transition:     4'0100 25'----------10-000-00000--0 ->     4'0100 16'0100000010000000
  transition:     4'0100 25'----------10-100-00000--0 ->     4'0000 16'0000000010000000
  transition:     4'0100 25'-----------1-000-00000--0 ->     4'0100 16'0100000010000000
  transition:     4'0100 25'-----------1-100-00000--0 ->     4'0000 16'0000000010000000
  transition:     4'0100 25'------------0010-00000--0 ->     4'0100 16'0100000010000000
  transition:     4'0100 25'------------1010-00000--0 ->     4'0000 16'0000000010000000
  transition:     4'0100 25'-------------110-00000000 ->     4'1100 16'1100000010000000
  transition:     4'0100 25'-------------110-000001-0 ->     4'0010 16'0010000010000000
  transition:     4'0100 25'-------------110-00000-10 ->     4'0011 16'0011000010000000
  transition:     4'0100 25'00000000-------1-00000--0 -> INVALID_STATE(4'x) 16'xxxx000010000000  <ignored invalid transition!>
  transition:     4'0100 25'-----1---------1000000--0 ->     4'0000 16'0000000010000000
  transition:     4'0100 25'-----1---------1100000--0 ->     4'1000 16'1000000010000000
  transition:     4'0100 25'----1----------1-00000--0 ->     4'0001 16'0001000010000000
  transition:     4'0100 25'---1-----------1-00000--0 ->     4'0010 16'0010000010000000
  transition:     4'0100 25'1--------------1-00000--0 ->     4'0011 16'0011000010000000
  transition:     4'0100 25'------1--------1-00000--0 ->     4'0100 16'0100000010000000
  transition:     4'0100 25'--1------------1000000--0 ->     4'0101 16'0101000010000000
  transition:     4'0100 25'--1------------1100000--0 ->     4'1101 16'1101000010000000
  transition:     4'0100 25'-------1-------1-00000--0 ->     4'0110 16'0110000010000000
  transition:     4'0100 25'-1-------------1-00000--0 ->     4'0111 16'0111000010000000
  transition:     4'0100 25'00000000---------10000--0 -> INVALID_STATE(4'x) 16'xxxx000010000000  <ignored invalid transition!>
  transition:     4'0100 25'-----1-----------10000--0 ->     4'0000 16'0000000010000000
  transition:     4'0100 25'----1------------10000--0 ->     4'0001 16'0001000010000000
  transition:     4'0100 25'---1-------------10000--0 ->     4'0010 16'0010000010000000
  transition:     4'0100 25'1----------------10000--0 ->     4'0011 16'0011000010000000
  transition:     4'0100 25'------1----------10000--0 ->     4'0100 16'0100000010000000
  transition:     4'0100 25'--1-------------010000--0 ->     4'0101 16'0101000010000000
  transition:     4'0100 25'--1-------------110000--0 ->     4'1101 16'1101000010000000
  transition:     4'0100 25'-------1---------10000--0 ->     4'0110 16'0110000010000000
  transition:     4'0100 25'-1---------------10000--0 ->     4'0111 16'0111000010000000
  transition:     4'0100 25'------------------1000--0 ->     4'0000 16'0000000010000000
  transition:     4'0100 25'-------------------100--0 ->     4'1010 16'1010000010000000
  transition:     4'0100 25'--------------------10--0 ->     4'0100 16'0100000010000000
  transition:     4'0100 25'---------------------1--0 ->     4'1001 16'1001000010000000
  transition:     4'0100 25'------------------------1 ->     4'0100 16'0100000010000000
  transition:     4'1100 25'--------0000--00-00000--0 ->     4'1100 16'1100000000001000
  transition:     4'1100 25'--------1000-000-00000--0 ->     4'1100 16'1100000000001000
  transition:     4'1100 25'--------1000-100-00000--0 ->     4'0000 16'0000000000001000
  transition:     4'1100 25'---------100-000-00000--0 ->     4'1100 16'1100000000001000
  transition:     4'1100 25'---------100-100-00000--0 ->     4'0000 16'0000000000001000
  transition:     4'1100 25'----------10-000-00000--0 ->     4'1100 16'1100000000001000
  transition:     4'1100 25'----------10-100-00000--0 ->     4'0000 16'0000000000001000
  transition:     4'1100 25'-----------1-000-00000--0 ->     4'1100 16'1100000000001000
  transition:     4'1100 25'-----------1-100-00000--0 ->     4'0000 16'0000000000001000
  transition:     4'1100 25'------------0010-00000--0 ->     4'1100 16'1100000000001000
  transition:     4'1100 25'------------1010-00000--0 ->     4'0000 16'0000000000001000
  transition:     4'1100 25'-------------110-00000000 ->     4'1100 16'1100000000001000
  transition:     4'1100 25'-------------110-000001-0 ->     4'0010 16'0010000000001000
  transition:     4'1100 25'-------------110-00000-10 ->     4'0011 16'0011000000001000
  transition:     4'1100 25'00000000-------1-00000--0 -> INVALID_STATE(4'x) 16'xxxx000000001000  <ignored invalid transition!>
  transition:     4'1100 25'-----1---------1000000--0 ->     4'0000 16'0000000000001000
  transition:     4'1100 25'-----1---------1100000--0 ->     4'1000 16'1000000000001000
  transition:     4'1100 25'----1----------1-00000--0 ->     4'0001 16'0001000000001000
  transition:     4'1100 25'---1-----------1-00000--0 ->     4'0010 16'0010000000001000
  transition:     4'1100 25'1--------------1-00000--0 ->     4'0011 16'0011000000001000
  transition:     4'1100 25'------1--------1-00000--0 ->     4'0100 16'0100000000001000
  transition:     4'1100 25'--1------------1000000--0 ->     4'0101 16'0101000000001000
  transition:     4'1100 25'--1------------1100000--0 ->     4'1101 16'1101000000001000
  transition:     4'1100 25'-------1-------1-00000--0 ->     4'0110 16'0110000000001000
  transition:     4'1100 25'-1-------------1-00000--0 ->     4'0111 16'0111000000001000
  transition:     4'1100 25'00000000---------10000--0 -> INVALID_STATE(4'x) 16'xxxx000000001000  <ignored invalid transition!>
  transition:     4'1100 25'-----1-----------10000--0 ->     4'0000 16'0000000000001000
  transition:     4'1100 25'----1------------10000--0 ->     4'0001 16'0001000000001000
  transition:     4'1100 25'---1-------------10000--0 ->     4'0010 16'0010000000001000
  transition:     4'1100 25'1----------------10000--0 ->     4'0011 16'0011000000001000
  transition:     4'1100 25'------1----------10000--0 ->     4'0100 16'0100000000001000
  transition:     4'1100 25'--1-------------010000--0 ->     4'0101 16'0101000000001000
  transition:     4'1100 25'--1-------------110000--0 ->     4'1101 16'1101000000001000
  transition:     4'1100 25'-------1---------10000--0 ->     4'0110 16'0110000000001000
  transition:     4'1100 25'-1---------------10000--0 ->     4'0111 16'0111000000001000
  transition:     4'1100 25'------------------1000--0 ->     4'0000 16'0000000000001000
  transition:     4'1100 25'-------------------100--0 ->     4'1010 16'1010000000001000
  transition:     4'1100 25'--------------------10--0 ->     4'1100 16'1100000000001000
  transition:     4'1100 25'---------------------1--0 ->     4'1001 16'1001000000001000
  transition:     4'1100 25'------------------------1 ->     4'1100 16'1100000000001000
  transition:     4'0010 25'--------0000--00-00000--0 ->     4'0010 16'0010001000000000
  transition:     4'0010 25'--------1000-000-00000--0 ->     4'0010 16'0010001000000000
  transition:     4'0010 25'--------1000-100-00000--0 ->     4'0000 16'0000001000000000
  transition:     4'0010 25'---------100-000-00000--0 ->     4'0010 16'0010001000000000
  transition:     4'0010 25'---------100-100-00000--0 ->     4'0000 16'0000001000000000
  transition:     4'0010 25'----------10-000-00000--0 ->     4'0010 16'0010001000000000
  transition:     4'0010 25'----------10-100-00000--0 ->     4'0000 16'0000001000000000
  transition:     4'0010 25'-----------1-000-00000--0 ->     4'0010 16'0010001000000000
  transition:     4'0010 25'-----------1-100-00000--0 ->     4'0000 16'0000001000000000
  transition:     4'0010 25'------------0010-00000--0 ->     4'0010 16'0010001000000000
  transition:     4'0010 25'------------1010-00000--0 ->     4'0000 16'0000001000000000
  transition:     4'0010 25'-------------110-00000000 ->     4'1100 16'1100001000000000
  transition:     4'0010 25'-------------110-000001-0 ->     4'0010 16'0010001000000000
  transition:     4'0010 25'-------------110-00000-10 ->     4'0011 16'0011001000000000
  transition:     4'0010 25'00000000-------1-00000--0 -> INVALID_STATE(4'x) 16'xxxx001000000000  <ignored invalid transition!>
  transition:     4'0010 25'-----1---------1000000--0 ->     4'0000 16'0000001000000000
  transition:     4'0010 25'-----1---------1100000--0 ->     4'1000 16'1000001000000000
  transition:     4'0010 25'----1----------1-00000--0 ->     4'0001 16'0001001000000000
  transition:     4'0010 25'---1-----------1-00000--0 ->     4'0010 16'0010001000000000
  transition:     4'0010 25'1--------------1-00000--0 ->     4'0011 16'0011001000000000
  transition:     4'0010 25'------1--------1-00000--0 ->     4'0100 16'0100001000000000
  transition:     4'0010 25'--1------------1000000--0 ->     4'0101 16'0101001000000000
  transition:     4'0010 25'--1------------1100000--0 ->     4'1101 16'1101001000000000
  transition:     4'0010 25'-------1-------1-00000--0 ->     4'0110 16'0110001000000000
  transition:     4'0010 25'-1-------------1-00000--0 ->     4'0111 16'0111001000000000
  transition:     4'0010 25'00000000---------10000--0 -> INVALID_STATE(4'x) 16'xxxx001000000000  <ignored invalid transition!>
  transition:     4'0010 25'-----1-----------10000--0 ->     4'0000 16'0000001000000000
  transition:     4'0010 25'----1------------10000--0 ->     4'0001 16'0001001000000000
  transition:     4'0010 25'---1-------------10000--0 ->     4'0010 16'0010001000000000
  transition:     4'0010 25'1----------------10000--0 ->     4'0011 16'0011001000000000
  transition:     4'0010 25'------1----------10000--0 ->     4'0100 16'0100001000000000
  transition:     4'0010 25'--1-------------010000--0 ->     4'0101 16'0101001000000000
  transition:     4'0010 25'--1-------------110000--0 ->     4'1101 16'1101001000000000
  transition:     4'0010 25'-------1---------10000--0 ->     4'0110 16'0110001000000000
  transition:     4'0010 25'-1---------------10000--0 ->     4'0111 16'0111001000000000
  transition:     4'0010 25'------------------1000--0 ->     4'0000 16'0000001000000000
  transition:     4'0010 25'-------------------100--0 ->     4'1010 16'1010001000000000
  transition:     4'0010 25'--------------------10--0 ->     4'0010 16'0010001000000000
  transition:     4'0010 25'---------------------1--0 ->     4'1001 16'1001001000000000
  transition:     4'0010 25'------------------------1 ->     4'0010 16'0010001000000000
  transition:     4'1010 25'--------0000--00-00000--0 ->     4'1010 16'1010000000000100
  transition:     4'1010 25'--------1000-000-00000--0 ->     4'1010 16'1010000000000100
  transition:     4'1010 25'--------1000-100-00000--0 ->     4'0000 16'0000000000000100
  transition:     4'1010 25'---------100-000-00000--0 ->     4'1010 16'1010000000000100
  transition:     4'1010 25'---------100-100-00000--0 ->     4'0000 16'0000000000000100
  transition:     4'1010 25'----------10-000-00000--0 ->     4'1010 16'1010000000000100
  transition:     4'1010 25'----------10-100-00000--0 ->     4'0000 16'0000000000000100
  transition:     4'1010 25'-----------1-000-00000--0 ->     4'1010 16'1010000000000100
  transition:     4'1010 25'-----------1-100-00000--0 ->     4'0000 16'0000000000000100
  transition:     4'1010 25'------------0010-00000--0 ->     4'1010 16'1010000000000100
  transition:     4'1010 25'------------1010-00000--0 ->     4'0000 16'0000000000000100
  transition:     4'1010 25'-------------110-00000000 ->     4'1100 16'1100000000000100
  transition:     4'1010 25'-------------110-000001-0 ->     4'0010 16'0010000000000100
  transition:     4'1010 25'-------------110-00000-10 ->     4'0011 16'0011000000000100
  transition:     4'1010 25'00000000-------1-00000--0 -> INVALID_STATE(4'x) 16'xxxx000000000100  <ignored invalid transition!>
  transition:     4'1010 25'-----1---------1000000--0 ->     4'0000 16'0000000000000100
  transition:     4'1010 25'-----1---------1100000--0 ->     4'1000 16'1000000000000100
  transition:     4'1010 25'----1----------1-00000--0 ->     4'0001 16'0001000000000100
  transition:     4'1010 25'---1-----------1-00000--0 ->     4'0010 16'0010000000000100
  transition:     4'1010 25'1--------------1-00000--0 ->     4'0011 16'0011000000000100
  transition:     4'1010 25'------1--------1-00000--0 ->     4'0100 16'0100000000000100
  transition:     4'1010 25'--1------------1000000--0 ->     4'0101 16'0101000000000100
  transition:     4'1010 25'--1------------1100000--0 ->     4'1101 16'1101000000000100
  transition:     4'1010 25'-------1-------1-00000--0 ->     4'0110 16'0110000000000100
  transition:     4'1010 25'-1-------------1-00000--0 ->     4'0111 16'0111000000000100
  transition:     4'1010 25'00000000---------10000--0 -> INVALID_STATE(4'x) 16'xxxx000000000100  <ignored invalid transition!>
  transition:     4'1010 25'-----1-----------10000--0 ->     4'0000 16'0000000000000100
  transition:     4'1010 25'----1------------10000--0 ->     4'0001 16'0001000000000100
  transition:     4'1010 25'---1-------------10000--0 ->     4'0010 16'0010000000000100
  transition:     4'1010 25'1----------------10000--0 ->     4'0011 16'0011000000000100
  transition:     4'1010 25'------1----------10000--0 ->     4'0100 16'0100000000000100
  transition:     4'1010 25'--1-------------010000--0 ->     4'0101 16'0101000000000100
  transition:     4'1010 25'--1-------------110000--0 ->     4'1101 16'1101000000000100
  transition:     4'1010 25'-------1---------10000--0 ->     4'0110 16'0110000000000100
  transition:     4'1010 25'-1---------------10000--0 ->     4'0111 16'0111000000000100
  transition:     4'1010 25'------------------1000--0 ->     4'0000 16'0000000000000100
  transition:     4'1010 25'-------------------100--0 ->     4'1010 16'1010000000000100
  transition:     4'1010 25'--------------------10--0 ->     4'1010 16'1010000000000100
  transition:     4'1010 25'---------------------1--0 ->     4'1001 16'1001000000000100
  transition:     4'1010 25'------------------------1 ->     4'1010 16'1010000000000100
  transition:     4'0110 25'--------0000--00-00000--0 ->     4'0110 16'0110000000100000
  transition:     4'0110 25'--------1000-000-00000--0 ->     4'0110 16'0110000000100000
  transition:     4'0110 25'--------1000-100-00000--0 ->     4'0000 16'0000000000100000
  transition:     4'0110 25'---------100-000-00000--0 ->     4'0110 16'0110000000100000
  transition:     4'0110 25'---------100-100-00000--0 ->     4'0000 16'0000000000100000
  transition:     4'0110 25'----------10-000-00000--0 ->     4'0110 16'0110000000100000
  transition:     4'0110 25'----------10-100-00000--0 ->     4'0000 16'0000000000100000
  transition:     4'0110 25'-----------1-000-00000--0 ->     4'0110 16'0110000000100000
  transition:     4'0110 25'-----------1-100-00000--0 ->     4'0000 16'0000000000100000
  transition:     4'0110 25'------------0010-00000--0 ->     4'0110 16'0110000000100000
  transition:     4'0110 25'------------1010-00000--0 ->     4'0000 16'0000000000100000
  transition:     4'0110 25'-------------110-00000000 ->     4'1100 16'1100000000100000
  transition:     4'0110 25'-------------110-000001-0 ->     4'0010 16'0010000000100000
  transition:     4'0110 25'-------------110-00000-10 ->     4'0011 16'0011000000100000
  transition:     4'0110 25'00000000-------1-00000--0 -> INVALID_STATE(4'x) 16'xxxx000000100000  <ignored invalid transition!>
  transition:     4'0110 25'-----1---------1000000--0 ->     4'0000 16'0000000000100000
  transition:     4'0110 25'-----1---------1100000--0 ->     4'1000 16'1000000000100000
  transition:     4'0110 25'----1----------1-00000--0 ->     4'0001 16'0001000000100000
  transition:     4'0110 25'---1-----------1-00000--0 ->     4'0010 16'0010000000100000
  transition:     4'0110 25'1--------------1-00000--0 ->     4'0011 16'0011000000100000
  transition:     4'0110 25'------1--------1-00000--0 ->     4'0100 16'0100000000100000
  transition:     4'0110 25'--1------------1000000--0 ->     4'0101 16'0101000000100000
  transition:     4'0110 25'--1------------1100000--0 ->     4'1101 16'1101000000100000
  transition:     4'0110 25'-------1-------1-00000--0 ->     4'0110 16'0110000000100000
  transition:     4'0110 25'-1-------------1-00000--0 ->     4'0111 16'0111000000100000
  transition:     4'0110 25'00000000---------10000--0 -> INVALID_STATE(4'x) 16'xxxx000000100000  <ignored invalid transition!>
  transition:     4'0110 25'-----1-----------10000--0 ->     4'0000 16'0000000000100000
  transition:     4'0110 25'----1------------10000--0 ->     4'0001 16'0001000000100000
  transition:     4'0110 25'---1-------------10000--0 ->     4'0010 16'0010000000100000
  transition:     4'0110 25'1----------------10000--0 ->     4'0011 16'0011000000100000
  transition:     4'0110 25'------1----------10000--0 ->     4'0100 16'0100000000100000
  transition:     4'0110 25'--1-------------010000--0 ->     4'0101 16'0101000000100000
  transition:     4'0110 25'--1-------------110000--0 ->     4'1101 16'1101000000100000
  transition:     4'0110 25'-------1---------10000--0 ->     4'0110 16'0110000000100000
  transition:     4'0110 25'-1---------------10000--0 ->     4'0111 16'0111000000100000
  transition:     4'0110 25'------------------1000--0 ->     4'0000 16'0000000000100000
  transition:     4'0110 25'-------------------100--0 ->     4'1010 16'1010000000100000
  transition:     4'0110 25'--------------------10--0 ->     4'0110 16'0110000000100000
  transition:     4'0110 25'---------------------1--0 ->     4'1001 16'1001000000100000
  transition:     4'0110 25'------------------------1 ->     4'0110 16'0110000000100000
  transition:     4'0001 25'--------0000--00-00000--0 ->     4'0001 16'0001010000000000
  transition:     4'0001 25'--------1000-000-00000--0 ->     4'0001 16'0001010000000000
  transition:     4'0001 25'--------1000-100-00000--0 ->     4'0000 16'0000010000000000
  transition:     4'0001 25'---------100-000-00000--0 ->     4'0001 16'0001010000000000
  transition:     4'0001 25'---------100-100-00000--0 ->     4'0000 16'0000010000000000
  transition:     4'0001 25'----------10-000-00000--0 ->     4'0001 16'0001010000000000
  transition:     4'0001 25'----------10-100-00000--0 ->     4'0000 16'0000010000000000
  transition:     4'0001 25'-----------1-000-00000--0 ->     4'0001 16'0001010000000000
  transition:     4'0001 25'-----------1-100-00000--0 ->     4'0000 16'0000010000000000
  transition:     4'0001 25'------------0010-00000--0 ->     4'0001 16'0001010000000000
  transition:     4'0001 25'------------1010-00000--0 ->     4'0000 16'0000010000000000
  transition:     4'0001 25'-------------110-00000000 ->     4'1100 16'1100010000000000
  transition:     4'0001 25'-------------110-000001-0 ->     4'0010 16'0010010000000000
  transition:     4'0001 25'-------------110-00000-10 ->     4'0011 16'0011010000000000
  transition:     4'0001 25'00000000-------1-00000--0 -> INVALID_STATE(4'x) 16'xxxx010000000000  <ignored invalid transition!>
  transition:     4'0001 25'-----1---------1000000--0 ->     4'0000 16'0000010000000000
  transition:     4'0001 25'-----1---------1100000--0 ->     4'1000 16'1000010000000000
  transition:     4'0001 25'----1----------1-00000--0 ->     4'0001 16'0001010000000000
  transition:     4'0001 25'---1-----------1-00000--0 ->     4'0010 16'0010010000000000
  transition:     4'0001 25'1--------------1-00000--0 ->     4'0011 16'0011010000000000
  transition:     4'0001 25'------1--------1-00000--0 ->     4'0100 16'0100010000000000
  transition:     4'0001 25'--1------------1000000--0 ->     4'0101 16'0101010000000000
  transition:     4'0001 25'--1------------1100000--0 ->     4'1101 16'1101010000000000
  transition:     4'0001 25'-------1-------1-00000--0 ->     4'0110 16'0110010000000000
  transition:     4'0001 25'-1-------------1-00000--0 ->     4'0111 16'0111010000000000
  transition:     4'0001 25'00000000---------10000--0 -> INVALID_STATE(4'x) 16'xxxx010000000000  <ignored invalid transition!>
  transition:     4'0001 25'-----1-----------10000--0 ->     4'0000 16'0000010000000000
  transition:     4'0001 25'----1------------10000--0 ->     4'0001 16'0001010000000000
  transition:     4'0001 25'---1-------------10000--0 ->     4'0010 16'0010010000000000
  transition:     4'0001 25'1----------------10000--0 ->     4'0011 16'0011010000000000
  transition:     4'0001 25'------1----------10000--0 ->     4'0100 16'0100010000000000
  transition:     4'0001 25'--1-------------010000--0 ->     4'0101 16'0101010000000000
  transition:     4'0001 25'--1-------------110000--0 ->     4'1101 16'1101010000000000
  transition:     4'0001 25'-------1---------10000--0 ->     4'0110 16'0110010000000000
  transition:     4'0001 25'-1---------------10000--0 ->     4'0111 16'0111010000000000
  transition:     4'0001 25'------------------1000--0 ->     4'0000 16'0000010000000000
  transition:     4'0001 25'-------------------100--0 ->     4'1010 16'1010010000000000
  transition:     4'0001 25'--------------------10--0 ->     4'0001 16'0001010000000000
  transition:     4'0001 25'---------------------1--0 ->     4'1001 16'1001010000000000
  transition:     4'0001 25'------------------------1 ->     4'0001 16'0001010000000000
  transition:     4'1001 25'--------0000--00-00000--0 ->     4'1001 16'1001000000000000
  transition:     4'1001 25'--------1000-000-00000--0 ->     4'1001 16'1001000000000000
  transition:     4'1001 25'--------1000-100-00000--0 ->     4'0000 16'0000000000000000
  transition:     4'1001 25'---------100-000-00000--0 ->     4'1001 16'1001000000000000
  transition:     4'1001 25'---------100-100-00000--0 ->     4'0000 16'0000000000000000
  transition:     4'1001 25'----------10-000-00000--0 ->     4'1001 16'1001000000000000
  transition:     4'1001 25'----------10-100-00000--0 ->     4'0000 16'0000000000000000
  transition:     4'1001 25'-----------1-000-00000--0 ->     4'1001 16'1001000000000000
  transition:     4'1001 25'-----------1-100-00000--0 ->     4'0000 16'0000000000000000
  transition:     4'1001 25'------------0010-00000--0 ->     4'1001 16'1001000000000000
  transition:     4'1001 25'------------1010-00000--0 ->     4'0000 16'0000000000000000
  transition:     4'1001 25'-------------110-00000000 ->     4'1100 16'1100000000000000
  transition:     4'1001 25'-------------110-000001-0 ->     4'0010 16'0010000000000000
  transition:     4'1001 25'-------------110-00000-10 ->     4'0011 16'0011000000000000
  transition:     4'1001 25'00000000-------1-00000--0 -> INVALID_STATE(4'x) 16'xxxx000000000000  <ignored invalid transition!>
  transition:     4'1001 25'-----1---------1000000--0 ->     4'0000 16'0000000000000000
  transition:     4'1001 25'-----1---------1100000--0 ->     4'1000 16'1000000000000000
  transition:     4'1001 25'----1----------1-00000--0 ->     4'0001 16'0001000000000000
  transition:     4'1001 25'---1-----------1-00000--0 ->     4'0010 16'0010000000000000
  transition:     4'1001 25'1--------------1-00000--0 ->     4'0011 16'0011000000000000
  transition:     4'1001 25'------1--------1-00000--0 ->     4'0100 16'0100000000000000
  transition:     4'1001 25'--1------------1000000--0 ->     4'0101 16'0101000000000000
  transition:     4'1001 25'--1------------1100000--0 ->     4'1101 16'1101000000000000
  transition:     4'1001 25'-------1-------1-00000--0 ->     4'0110 16'0110000000000000
  transition:     4'1001 25'-1-------------1-00000--0 ->     4'0111 16'0111000000000000
  transition:     4'1001 25'00000000---------10000--0 -> INVALID_STATE(4'x) 16'xxxx000000000000  <ignored invalid transition!>
  transition:     4'1001 25'-----1-----------10000--0 ->     4'0000 16'0000000000000000
  transition:     4'1001 25'----1------------10000--0 ->     4'0001 16'0001000000000000
  transition:     4'1001 25'---1-------------10000--0 ->     4'0010 16'0010000000000000
  transition:     4'1001 25'1----------------10000--0 ->     4'0011 16'0011000000000000
  transition:     4'1001 25'------1----------10000--0 ->     4'0100 16'0100000000000000
  transition:     4'1001 25'--1-------------010000--0 ->     4'0101 16'0101000000000000
  transition:     4'1001 25'--1-------------110000--0 ->     4'1101 16'1101000000000000
  transition:     4'1001 25'-------1---------10000--0 ->     4'0110 16'0110000000000000
  transition:     4'1001 25'-1---------------10000--0 ->     4'0111 16'0111000000000000
  transition:     4'1001 25'------------------1000--0 ->     4'0000 16'0000000000000000
  transition:     4'1001 25'-------------------100--0 ->     4'1010 16'1010000000000000
  transition:     4'1001 25'--------------------10--0 ->     4'1001 16'1001000000000000
  transition:     4'1001 25'---------------------1--0 ->     4'1001 16'1001000000000000
  transition:     4'1001 25'------------------------1 ->     4'1001 16'1001000000000000
  transition:     4'0101 25'--------0000--00-00000--0 ->     4'0101 16'0101000001000000
  transition:     4'0101 25'--------1000-000-00000--0 ->     4'0101 16'0101000001000000
  transition:     4'0101 25'--------1000-100-00000--0 ->     4'0000 16'0000000001000000
  transition:     4'0101 25'---------100-000-00000--0 ->     4'0101 16'0101000001000000
  transition:     4'0101 25'---------100-100-00000--0 ->     4'0000 16'0000000001000000
  transition:     4'0101 25'----------10-000-00000--0 ->     4'0101 16'0101000001000000
  transition:     4'0101 25'----------10-100-00000--0 ->     4'0000 16'0000000001000000
  transition:     4'0101 25'-----------1-000-00000--0 ->     4'0101 16'0101000001000000
  transition:     4'0101 25'-----------1-100-00000--0 ->     4'0000 16'0000000001000000
  transition:     4'0101 25'------------0010-00000--0 ->     4'0101 16'0101000001000000
  transition:     4'0101 25'------------1010-00000--0 ->     4'0000 16'0000000001000000
  transition:     4'0101 25'-------------110-00000000 ->     4'1100 16'1100000001000000
  transition:     4'0101 25'-------------110-000001-0 ->     4'0010 16'0010000001000000
  transition:     4'0101 25'-------------110-00000-10 ->     4'0011 16'0011000001000000
  transition:     4'0101 25'00000000-------1-00000--0 -> INVALID_STATE(4'x) 16'xxxx000001000000  <ignored invalid transition!>
  transition:     4'0101 25'-----1---------1000000--0 ->     4'0000 16'0000000001000000
  transition:     4'0101 25'-----1---------1100000--0 ->     4'1000 16'1000000001000000
  transition:     4'0101 25'----1----------1-00000--0 ->     4'0001 16'0001000001000000
  transition:     4'0101 25'---1-----------1-00000--0 ->     4'0010 16'0010000001000000
  transition:     4'0101 25'1--------------1-00000--0 ->     4'0011 16'0011000001000000
  transition:     4'0101 25'------1--------1-00000--0 ->     4'0100 16'0100000001000000
  transition:     4'0101 25'--1------------1000000--0 ->     4'0101 16'0101000001000000
  transition:     4'0101 25'--1------------1100000--0 ->     4'1101 16'1101000001000000
  transition:     4'0101 25'-------1-------1-00000--0 ->     4'0110 16'0110000001000000
  transition:     4'0101 25'-1-------------1-00000--0 ->     4'0111 16'0111000001000000
  transition:     4'0101 25'00000000---------10000--0 -> INVALID_STATE(4'x) 16'xxxx000001000000  <ignored invalid transition!>
  transition:     4'0101 25'-----1-----------10000--0 ->     4'0000 16'0000000001000000
  transition:     4'0101 25'----1------------10000--0 ->     4'0001 16'0001000001000000
  transition:     4'0101 25'---1-------------10000--0 ->     4'0010 16'0010000001000000
  transition:     4'0101 25'1----------------10000--0 ->     4'0011 16'0011000001000000
  transition:     4'0101 25'------1----------10000--0 ->     4'0100 16'0100000001000000
  transition:     4'0101 25'--1-------------010000--0 ->     4'0101 16'0101000001000000
  transition:     4'0101 25'--1-------------110000--0 ->     4'1101 16'1101000001000000
  transition:     4'0101 25'-------1---------10000--0 ->     4'0110 16'0110000001000000
  transition:     4'0101 25'-1---------------10000--0 ->     4'0111 16'0111000001000000
  transition:     4'0101 25'------------------1000--0 ->     4'0000 16'0000000001000000
  transition:     4'0101 25'-------------------100--0 ->     4'1010 16'1010000001000000
  transition:     4'0101 25'--------------------10--0 ->     4'0101 16'0101000001000000
  transition:     4'0101 25'---------------------1--0 ->     4'1001 16'1001000001000000
  transition:     4'0101 25'------------------------1 ->     4'0101 16'0101000001000000
  transition:     4'1101 25'--------0000--00-00000--0 ->     4'1101 16'1101000000000010
  transition:     4'1101 25'--------1000-000-00000--0 ->     4'1101 16'1101000000000010
  transition:     4'1101 25'--------1000-100-00000--0 ->     4'0000 16'0000000000000010
  transition:     4'1101 25'---------100-000-00000--0 ->     4'1101 16'1101000000000010
  transition:     4'1101 25'---------100-100-00000--0 ->     4'0000 16'0000000000000010
  transition:     4'1101 25'----------10-000-00000--0 ->     4'1101 16'1101000000000010
  transition:     4'1101 25'----------10-100-00000--0 ->     4'0000 16'0000000000000010
  transition:     4'1101 25'-----------1-000-00000--0 ->     4'1101 16'1101000000000010
  transition:     4'1101 25'-----------1-100-00000--0 ->     4'0000 16'0000000000000010
  transition:     4'1101 25'------------0010-00000--0 ->     4'1101 16'1101000000000010
  transition:     4'1101 25'------------1010-00000--0 ->     4'0000 16'0000000000000010
  transition:     4'1101 25'-------------110-00000000 ->     4'1100 16'1100000000000010
  transition:     4'1101 25'-------------110-000001-0 ->     4'0010 16'0010000000000010
  transition:     4'1101 25'-------------110-00000-10 ->     4'0011 16'0011000000000010
  transition:     4'1101 25'00000000-------1-00000--0 -> INVALID_STATE(4'x) 16'xxxx000000000010  <ignored invalid transition!>
  transition:     4'1101 25'-----1---------1000000--0 ->     4'0000 16'0000000000000010
  transition:     4'1101 25'-----1---------1100000--0 ->     4'1000 16'1000000000000010
  transition:     4'1101 25'----1----------1-00000--0 ->     4'0001 16'0001000000000010
  transition:     4'1101 25'---1-----------1-00000--0 ->     4'0010 16'0010000000000010
  transition:     4'1101 25'1--------------1-00000--0 ->     4'0011 16'0011000000000010
  transition:     4'1101 25'------1--------1-00000--0 ->     4'0100 16'0100000000000010
  transition:     4'1101 25'--1------------1000000--0 ->     4'0101 16'0101000000000010
  transition:     4'1101 25'--1------------1100000--0 ->     4'1101 16'1101000000000010
  transition:     4'1101 25'-------1-------1-00000--0 ->     4'0110 16'0110000000000010
  transition:     4'1101 25'-1-------------1-00000--0 ->     4'0111 16'0111000000000010
  transition:     4'1101 25'00000000---------10000--0 -> INVALID_STATE(4'x) 16'xxxx000000000010  <ignored invalid transition!>
  transition:     4'1101 25'-----1-----------10000--0 ->     4'0000 16'0000000000000010
  transition:     4'1101 25'----1------------10000--0 ->     4'0001 16'0001000000000010
  transition:     4'1101 25'---1-------------10000--0 ->     4'0010 16'0010000000000010
  transition:     4'1101 25'1----------------10000--0 ->     4'0011 16'0011000000000010
  transition:     4'1101 25'------1----------10000--0 ->     4'0100 16'0100000000000010
  transition:     4'1101 25'--1-------------010000--0 ->     4'0101 16'0101000000000010
  transition:     4'1101 25'--1-------------110000--0 ->     4'1101 16'1101000000000010
  transition:     4'1101 25'-------1---------10000--0 ->     4'0110 16'0110000000000010
  transition:     4'1101 25'-1---------------10000--0 ->     4'0111 16'0111000000000010
  transition:     4'1101 25'------------------1000--0 ->     4'0000 16'0000000000000010
  transition:     4'1101 25'-------------------100--0 ->     4'1010 16'1010000000000010
  transition:     4'1101 25'--------------------10--0 ->     4'1101 16'1101000000000010
  transition:     4'1101 25'---------------------1--0 ->     4'1001 16'1001000000000010
  transition:     4'1101 25'------------------------1 ->     4'1101 16'1101000000000010
  transition:     4'0011 25'--------0000--00-00000--0 ->     4'0011 16'0011000100000000
  transition:     4'0011 25'--------1000-000-00000--0 ->     4'0011 16'0011000100000000
  transition:     4'0011 25'--------1000-100-00000--0 ->     4'0000 16'0000000100000000
  transition:     4'0011 25'---------100-000-00000--0 ->     4'0011 16'0011000100000000
  transition:     4'0011 25'---------100-100-00000--0 ->     4'0000 16'0000000100000000
  transition:     4'0011 25'----------10-000-00000--0 ->     4'0011 16'0011000100000000
  transition:     4'0011 25'----------10-100-00000--0 ->     4'0000 16'0000000100000000
  transition:     4'0011 25'-----------1-000-00000--0 ->     4'0011 16'0011000100000000
  transition:     4'0011 25'-----------1-100-00000--0 ->     4'0000 16'0000000100000000
  transition:     4'0011 25'------------0010-00000--0 ->     4'0011 16'0011000100000000
  transition:     4'0011 25'------------1010-00000--0 ->     4'0000 16'0000000100000000
  transition:     4'0011 25'-------------110-00000000 ->     4'1100 16'1100000100000000
  transition:     4'0011 25'-------------110-000001-0 ->     4'0010 16'0010000100000000
  transition:     4'0011 25'-------------110-00000-10 ->     4'0011 16'0011000100000000
  transition:     4'0011 25'00000000-------1-00000--0 -> INVALID_STATE(4'x) 16'xxxx000100000000  <ignored invalid transition!>
  transition:     4'0011 25'-----1---------1000000--0 ->     4'0000 16'0000000100000000
  transition:     4'0011 25'-----1---------1100000--0 ->     4'1000 16'1000000100000000
  transition:     4'0011 25'----1----------1-00000--0 ->     4'0001 16'0001000100000000
  transition:     4'0011 25'---1-----------1-00000--0 ->     4'0010 16'0010000100000000
  transition:     4'0011 25'1--------------1-00000--0 ->     4'0011 16'0011000100000000
  transition:     4'0011 25'------1--------1-00000--0 ->     4'0100 16'0100000100000000
  transition:     4'0011 25'--1------------1000000--0 ->     4'0101 16'0101000100000000
  transition:     4'0011 25'--1------------1100000--0 ->     4'1101 16'1101000100000000
  transition:     4'0011 25'-------1-------1-00000--0 ->     4'0110 16'0110000100000000
  transition:     4'0011 25'-1-------------1-00000--0 ->     4'0111 16'0111000100000000
  transition:     4'0011 25'00000000---------10000--0 -> INVALID_STATE(4'x) 16'xxxx000100000000  <ignored invalid transition!>
  transition:     4'0011 25'-----1-----------10000--0 ->     4'0000 16'0000000100000000
  transition:     4'0011 25'----1------------10000--0 ->     4'0001 16'0001000100000000
  transition:     4'0011 25'---1-------------10000--0 ->     4'0010 16'0010000100000000
  transition:     4'0011 25'1----------------10000--0 ->     4'0011 16'0011000100000000
  transition:     4'0011 25'------1----------10000--0 ->     4'0100 16'0100000100000000
  transition:     4'0011 25'--1-------------010000--0 ->     4'0101 16'0101000100000000
  transition:     4'0011 25'--1-------------110000--0 ->     4'1101 16'1101000100000000
  transition:     4'0011 25'-------1---------10000--0 ->     4'0110 16'0110000100000000
  transition:     4'0011 25'-1---------------10000--0 ->     4'0111 16'0111000100000000
  transition:     4'0011 25'------------------1000--0 ->     4'0000 16'0000000100000000
  transition:     4'0011 25'-------------------100--0 ->     4'1010 16'1010000100000000
  transition:     4'0011 25'--------------------10--0 ->     4'0011 16'0011000100000000
  transition:     4'0011 25'---------------------1--0 ->     4'1001 16'1001000100000000
  transition:     4'0011 25'------------------------1 ->     4'0011 16'0011000100000000
  transition:     4'0111 25'--------0000--00-00000--0 ->     4'0111 16'0111000000010000
  transition:     4'0111 25'--------1000-000-00000--0 ->     4'0111 16'0111000000010000
  transition:     4'0111 25'--------1000-100-00000--0 ->     4'0000 16'0000000000010000
  transition:     4'0111 25'---------100-000-00000--0 ->     4'0111 16'0111000000010000
  transition:     4'0111 25'---------100-100-00000--0 ->     4'0000 16'0000000000010000
  transition:     4'0111 25'----------10-000-00000--0 ->     4'0111 16'0111000000010000
  transition:     4'0111 25'----------10-100-00000--0 ->     4'0000 16'0000000000010000
  transition:     4'0111 25'-----------1-000-00000--0 ->     4'0111 16'0111000000010000
  transition:     4'0111 25'-----------1-100-00000--0 ->     4'0000 16'0000000000010000
  transition:     4'0111 25'------------0010-00000--0 ->     4'0111 16'0111000000010000
  transition:     4'0111 25'------------1010-00000--0 ->     4'0000 16'0000000000010000
  transition:     4'0111 25'-------------110-00000000 ->     4'1100 16'1100000000010000
  transition:     4'0111 25'-------------110-000001-0 ->     4'0010 16'0010000000010000
  transition:     4'0111 25'-------------110-00000-10 ->     4'0011 16'0011000000010000
  transition:     4'0111 25'00000000-------1-00000--0 -> INVALID_STATE(4'x) 16'xxxx000000010000  <ignored invalid transition!>
  transition:     4'0111 25'-----1---------1000000--0 ->     4'0000 16'0000000000010000
  transition:     4'0111 25'-----1---------1100000--0 ->     4'1000 16'1000000000010000
  transition:     4'0111 25'----1----------1-00000--0 ->     4'0001 16'0001000000010000
  transition:     4'0111 25'---1-----------1-00000--0 ->     4'0010 16'0010000000010000
  transition:     4'0111 25'1--------------1-00000--0 ->     4'0011 16'0011000000010000
  transition:     4'0111 25'------1--------1-00000--0 ->     4'0100 16'0100000000010000
  transition:     4'0111 25'--1------------1000000--0 ->     4'0101 16'0101000000010000
  transition:     4'0111 25'--1------------1100000--0 ->     4'1101 16'1101000000010000
  transition:     4'0111 25'-------1-------1-00000--0 ->     4'0110 16'0110000000010000
  transition:     4'0111 25'-1-------------1-00000--0 ->     4'0111 16'0111000000010000
  transition:     4'0111 25'00000000---------10000--0 -> INVALID_STATE(4'x) 16'xxxx000000010000  <ignored invalid transition!>
  transition:     4'0111 25'-----1-----------10000--0 ->     4'0000 16'0000000000010000
  transition:     4'0111 25'----1------------10000--0 ->     4'0001 16'0001000000010000
  transition:     4'0111 25'---1-------------10000--0 ->     4'0010 16'0010000000010000
  transition:     4'0111 25'1----------------10000--0 ->     4'0011 16'0011000000010000
  transition:     4'0111 25'------1----------10000--0 ->     4'0100 16'0100000000010000
  transition:     4'0111 25'--1-------------010000--0 ->     4'0101 16'0101000000010000
  transition:     4'0111 25'--1-------------110000--0 ->     4'1101 16'1101000000010000
  transition:     4'0111 25'-------1---------10000--0 ->     4'0110 16'0110000000010000
  transition:     4'0111 25'-1---------------10000--0 ->     4'0111 16'0111000000010000
  transition:     4'0111 25'------------------1000--0 ->     4'0000 16'0000000000010000
  transition:     4'0111 25'-------------------100--0 ->     4'1010 16'1010000000010000
  transition:     4'0111 25'--------------------10--0 ->     4'0111 16'0111000000010000
  transition:     4'0111 25'---------------------1--0 ->     4'1001 16'1001000000010000
  transition:     4'0111 25'------------------------1 ->     4'0111 16'0111000000010000
Extracting FSM `\Riscado_V.ctrlUnit.aluSrcA' from module `\processorci_top'.
  found $dff cell for state register: $flatten\Riscado_V.\ctrlUnit.$procdff$3576
  root of input selection tree: $flatten\Riscado_V.\ctrlUnit.$0\aluSrcA[1:0]
  found reset state: 2'00 (guessed from mux tree)
  found ctrl input: \Controller.Interpreter.core_reset
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y
  found state code: 2'00
  found state code: 2'10
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y
  found ctrl output: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:123$190_Y
  found ctrl output: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:122$189_Y
  found ctrl output: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:121$188_Y
  ctrl inputs: { $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y \Controller.Interpreter.core_reset }
  ctrl outputs: { $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:121$188_Y $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:122$189_Y $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:123$190_Y $flatten\Riscado_V.\ctrlUnit.$0\aluSrcA[1:0] }
  transition:       2'00 14'0000--00000000 ->       2'00 5'10000
  transition:       2'00 14'1000-000000000 ->       2'00 5'10000
  transition:       2'00 14'1000-100000000 ->       2'00 5'10000
  transition:       2'00 14'-100-000000000 ->       2'00 5'10000
  transition:       2'00 14'-100-100000000 ->       2'00 5'10000
  transition:       2'00 14'--10-000000000 ->       2'00 5'10000
  transition:       2'00 14'--10-100000000 ->       2'00 5'10000
  transition:       2'00 14'---1-000000000 ->       2'00 5'10000
  transition:       2'00 14'---1-100000000 ->       2'10 5'10010
  transition:       2'00 14'----0010000000 ->       2'00 5'10000
  transition:       2'00 14'----1010000000 ->       2'10 5'10010
  transition:       2'00 14'-----110000000 ->       2'00 5'10000
  transition:       2'00 14'-------1000000 ->       2'00 5'10000
  transition:       2'00 14'--------100000 ->       2'00 5'10000
  transition:       2'00 14'---------10000 ->       2'10 5'10010
  transition:       2'00 14'----------1000 ->       2'00 5'10000
  transition:       2'00 14'-----------100 ->       2'00 5'10000
  transition:       2'00 14'------------10 ->       2'00 5'10000
  transition:       2'00 14'-------------1 ->       2'00 5'10000
  transition:       2'10 14'0000--00000000 ->       2'10 5'00110
  transition:       2'10 14'1000-000000000 ->       2'10 5'00110
  transition:       2'10 14'1000-100000000 ->       2'00 5'00100
  transition:       2'10 14'-100-000000000 ->       2'10 5'00110
  transition:       2'10 14'-100-100000000 ->       2'00 5'00100
  transition:       2'10 14'--10-000000000 ->       2'10 5'00110
  transition:       2'10 14'--10-100000000 ->       2'00 5'00100
  transition:       2'10 14'---1-000000000 ->       2'10 5'00110
  transition:       2'10 14'---1-100000000 ->       2'10 5'00110
  transition:       2'10 14'----0010000000 ->       2'10 5'00110
  transition:       2'10 14'----1010000000 ->       2'10 5'00110
  transition:       2'10 14'-----110000000 ->       2'10 5'00110
  transition:       2'10 14'-------1000000 ->       2'10 5'00110
  transition:       2'10 14'--------100000 ->       2'10 5'00110
  transition:       2'10 14'---------10000 ->       2'10 5'00110
  transition:       2'10 14'----------1000 ->       2'10 5'00110
  transition:       2'10 14'-----------100 ->       2'10 5'00110
  transition:       2'10 14'------------10 ->       2'00 5'00100
  transition:       2'10 14'-------------1 ->       2'00 5'00100
Extracting FSM `\Riscado_V.ctrlUnit.aluSrcB' from module `\processorci_top'.
  found $dff cell for state register: $flatten\Riscado_V.\ctrlUnit.$procdff$3577
  root of input selection tree: $flatten\Riscado_V.\ctrlUnit.$0\aluSrcB[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \Controller.Interpreter.core_reset
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y
  found state code: 3'010
  found state code: 3'001
  found state code: 3'101
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y
  found state code: 3'011
  found state code: 3'000
  found state code: 3'100
  found ctrl output: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$199_Y
  found ctrl output: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$198_Y
  found ctrl output: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$197_Y
  found ctrl output: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$196_Y
  found ctrl output: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:129$195_Y
  found ctrl output: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:128$194_Y
  ctrl inputs: { $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y \Controller.Interpreter.core_reset }
  ctrl outputs: { $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:128$194_Y $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:129$195_Y $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$196_Y $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$197_Y $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$198_Y $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$199_Y $flatten\Riscado_V.\ctrlUnit.$0\aluSrcB[2:0] }
  transition:      3'000 14'0000--00000000 ->      3'000 9'100000000
  transition:      3'000 14'1000-000000000 ->      3'000 9'100000000
  transition:      3'000 14'1000-100000000 ->      3'010 9'100000010
  transition:      3'000 14'-100-000000000 ->      3'000 9'100000000
  transition:      3'000 14'-100-100000000 ->      3'001 9'100000001
  transition:      3'000 14'--10-000000000 ->      3'000 9'100000000
  transition:      3'000 14'--10-100000000 ->      3'001 9'100000001
  transition:      3'000 14'---1-000000000 ->      3'000 9'100000000
  transition:      3'000 14'---1-100000000 ->      3'101 9'100000101
  transition:      3'000 14'----0010000000 ->      3'000 9'100000000
  transition:      3'000 14'----1010000000 ->      3'011 9'100000011
  transition:      3'000 14'-----110000000 ->      3'000 9'100000000
  transition:      3'000 14'-------1000000 ->      3'000 9'100000000
  transition:      3'000 14'--------100000 ->      3'001 9'100000001
  transition:      3'000 14'---------10000 ->      3'100 9'100000100
  transition:      3'000 14'----------1000 ->      3'100 9'100000100
  transition:      3'000 14'-----------100 ->      3'000 9'100000000
  transition:      3'000 14'------------10 ->      3'000 9'100000000
  transition:      3'000 14'-------------1 ->      3'000 9'100000000
  transition:      3'100 14'0000--00000000 ->      3'100 9'010000100
  transition:      3'100 14'1000-000000000 ->      3'100 9'010000100
  transition:      3'100 14'1000-100000000 ->      3'010 9'010000010
  transition:      3'100 14'-100-000000000 ->      3'100 9'010000100
  transition:      3'100 14'-100-100000000 ->      3'001 9'010000001
  transition:      3'100 14'--10-000000000 ->      3'100 9'010000100
  transition:      3'100 14'--10-100000000 ->      3'001 9'010000001
  transition:      3'100 14'---1-000000000 ->      3'100 9'010000100
  transition:      3'100 14'---1-100000000 ->      3'101 9'010000101
  transition:      3'100 14'----0010000000 ->      3'100 9'010000100
  transition:      3'100 14'----1010000000 ->      3'011 9'010000011
  transition:      3'100 14'-----110000000 ->      3'100 9'010000100
  transition:      3'100 14'-------1000000 ->      3'000 9'010000000
  transition:      3'100 14'--------100000 ->      3'001 9'010000001
  transition:      3'100 14'---------10000 ->      3'100 9'010000100
  transition:      3'100 14'----------1000 ->      3'100 9'010000100
  transition:      3'100 14'-----------100 ->      3'100 9'010000100
  transition:      3'100 14'------------10 ->      3'000 9'010000000
  transition:      3'100 14'-------------1 ->      3'000 9'010000000
  transition:      3'010 14'0000--00000000 ->      3'010 9'000001010
  transition:      3'010 14'1000-000000000 ->      3'010 9'000001010
  transition:      3'010 14'1000-100000000 ->      3'010 9'000001010
  transition:      3'010 14'-100-000000000 ->      3'010 9'000001010
  transition:      3'010 14'-100-100000000 ->      3'001 9'000001001
  transition:      3'010 14'--10-000000000 ->      3'010 9'000001010
  transition:      3'010 14'--10-100000000 ->      3'001 9'000001001
  transition:      3'010 14'---1-000000000 ->      3'010 9'000001010
  transition:      3'010 14'---1-100000000 ->      3'101 9'000001101
  transition:      3'010 14'----0010000000 ->      3'010 9'000001010
  transition:      3'010 14'----1010000000 ->      3'011 9'000001011
  transition:      3'010 14'-----110000000 ->      3'010 9'000001010
  transition:      3'010 14'-------1000000 ->      3'000 9'000001000
  transition:      3'010 14'--------100000 ->      3'001 9'000001001
  transition:      3'010 14'---------10000 ->      3'100 9'000001100
  transition:      3'010 14'----------1000 ->      3'100 9'000001100
  transition:      3'010 14'-----------100 ->      3'010 9'000001010
  transition:      3'010 14'------------10 ->      3'000 9'000001000
  transition:      3'010 14'-------------1 ->      3'000 9'000001000
  transition:      3'001 14'0000--00000000 ->      3'001 9'001000001
  transition:      3'001 14'1000-000000000 ->      3'001 9'001000001
  transition:      3'001 14'1000-100000000 ->      3'010 9'001000010
  transition:      3'001 14'-100-000000000 ->      3'001 9'001000001
  transition:      3'001 14'-100-100000000 ->      3'001 9'001000001
  transition:      3'001 14'--10-000000000 ->      3'001 9'001000001
  transition:      3'001 14'--10-100000000 ->      3'001 9'001000001
  transition:      3'001 14'---1-000000000 ->      3'001 9'001000001
  transition:      3'001 14'---1-100000000 ->      3'101 9'001000101
  transition:      3'001 14'----0010000000 ->      3'001 9'001000001
  transition:      3'001 14'----1010000000 ->      3'011 9'001000011
  transition:      3'001 14'-----110000000 ->      3'001 9'001000001
  transition:      3'001 14'-------1000000 ->      3'000 9'001000000
  transition:      3'001 14'--------100000 ->      3'001 9'001000001
  transition:      3'001 14'---------10000 ->      3'100 9'001000100
  transition:      3'001 14'----------1000 ->      3'100 9'001000100
  transition:      3'001 14'-----------100 ->      3'001 9'001000001
  transition:      3'001 14'------------10 ->      3'000 9'001000000
  transition:      3'001 14'-------------1 ->      3'000 9'001000000
  transition:      3'101 14'0000--00000000 ->      3'101 9'000010101
  transition:      3'101 14'1000-000000000 ->      3'101 9'000010101
  transition:      3'101 14'1000-100000000 ->      3'010 9'000010010
  transition:      3'101 14'-100-000000000 ->      3'101 9'000010101
  transition:      3'101 14'-100-100000000 ->      3'001 9'000010001
  transition:      3'101 14'--10-000000000 ->      3'101 9'000010101
  transition:      3'101 14'--10-100000000 ->      3'001 9'000010001
  transition:      3'101 14'---1-000000000 ->      3'101 9'000010101
  transition:      3'101 14'---1-100000000 ->      3'101 9'000010101
  transition:      3'101 14'----0010000000 ->      3'101 9'000010101
  transition:      3'101 14'----1010000000 ->      3'011 9'000010011
  transition:      3'101 14'-----110000000 ->      3'101 9'000010101
  transition:      3'101 14'-------1000000 ->      3'000 9'000010000
  transition:      3'101 14'--------100000 ->      3'001 9'000010001
  transition:      3'101 14'---------10000 ->      3'100 9'000010100
  transition:      3'101 14'----------1000 ->      3'100 9'000010100
  transition:      3'101 14'-----------100 ->      3'101 9'000010101
  transition:      3'101 14'------------10 ->      3'000 9'000010000
  transition:      3'101 14'-------------1 ->      3'000 9'000010000
  transition:      3'011 14'0000--00000000 ->      3'011 9'000100011
  transition:      3'011 14'1000-000000000 ->      3'011 9'000100011
  transition:      3'011 14'1000-100000000 ->      3'010 9'000100010
  transition:      3'011 14'-100-000000000 ->      3'011 9'000100011
  transition:      3'011 14'-100-100000000 ->      3'001 9'000100001
  transition:      3'011 14'--10-000000000 ->      3'011 9'000100011
  transition:      3'011 14'--10-100000000 ->      3'001 9'000100001
  transition:      3'011 14'---1-000000000 ->      3'011 9'000100011
  transition:      3'011 14'---1-100000000 ->      3'101 9'000100101
  transition:      3'011 14'----0010000000 ->      3'011 9'000100011
  transition:      3'011 14'----1010000000 ->      3'011 9'000100011
  transition:      3'011 14'-----110000000 ->      3'011 9'000100011
  transition:      3'011 14'-------1000000 ->      3'000 9'000100000
  transition:      3'011 14'--------100000 ->      3'001 9'000100001
  transition:      3'011 14'---------10000 ->      3'100 9'000100100
  transition:      3'011 14'----------1000 ->      3'100 9'000100100
  transition:      3'011 14'-----------100 ->      3'011 9'000100011
  transition:      3'011 14'------------10 ->      3'000 9'000100000
  transition:      3'011 14'-------------1 ->      3'000 9'000100000
Extracting FSM `\Riscado_V.ctrlUnit.readLen' from module `\processorci_top'.
  found $dff cell for state register: $flatten\Riscado_V.\ctrlUnit.$procdff$3579
  root of input selection tree: $flatten\Riscado_V.\ctrlUnit.$0\readLen[1:0]
  found reset state: 2'10 (guessed from mux tree)
  found ctrl input: \Controller.Interpreter.core_reset
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y
  found state code: 2'10
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y
  found ctrl input: $auto$opt_reduce.cc:134:opt_pmux$3657
  found ctrl input: $auto$opt_reduce.cc:134:opt_pmux$3659
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$procmux$2918_CMP
  found state code: 2'01
  found state code: 2'00
  found ctrl output: $flatten\Riscado_V.\ls.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:110$233_Y
  found ctrl output: $flatten\Riscado_V.\ls.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:111$234_Y
  ctrl inputs: { $auto$opt_reduce.cc:134:opt_pmux$3659 $auto$opt_reduce.cc:134:opt_pmux$3657 $flatten\Riscado_V.\ctrlUnit.$procmux$2918_CMP $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y \Controller.Interpreter.core_reset }
  ctrl outputs: { $flatten\Riscado_V.\ctrlUnit.$0\readLen[1:0] $flatten\Riscado_V.\ls.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:111$234_Y $flatten\Riscado_V.\ls.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:110$233_Y }
  transition:       2'00 17'---0000--00000000 ->       2'00 4'0001
  transition:       2'00 17'---1000-000000000 ->       2'00 4'0001
  transition:       2'00 17'---1000-100000000 ->       2'10 4'1001
  transition:       2'00 17'----1000000000000 ->       2'00 4'0001
  transition:       2'00 17'000-1001000000000 ->       2'00 4'0001
  transition:       2'00 17'--1-1001000000000 ->       2'10 4'1001
  transition:       2'00 17'1---1001000000000 ->       2'00 4'0001
  transition:       2'00 17'-1--1001000000000 ->       2'01 4'0101
  transition:       2'00 17'----100-100000000 ->       2'00 4'0001
  transition:       2'00 17'-----10--00000000 ->       2'00 4'0001
  transition:       2'00 17'------1--00000000 ->       2'00 4'0001
  transition:       2'00 17'---------10000000 ->       2'00 4'0001
  transition:       2'00 17'----------1000000 ->       2'00 4'0001
  transition:       2'00 17'-----------100000 ->       2'00 4'0001
  transition:       2'00 17'------------10000 ->       2'00 4'0001
  transition:       2'00 17'-------------1000 ->       2'00 4'0001
  transition:       2'00 17'--------------100 ->       2'00 4'0001
  transition:       2'00 17'---------------10 ->       2'10 4'1001
  transition:       2'00 17'----------------1 ->       2'10 4'1001
  transition:       2'10 17'---0000--00000000 ->       2'10 4'1000
  transition:       2'10 17'---1000-000000000 ->       2'10 4'1000
  transition:       2'10 17'---1000-100000000 ->       2'10 4'1000
  transition:       2'10 17'----1000000000000 ->       2'10 4'1000
  transition:       2'10 17'000-1001000000000 ->       2'10 4'1000
  transition:       2'10 17'--1-1001000000000 ->       2'10 4'1000
  transition:       2'10 17'1---1001000000000 ->       2'00 4'0000
  transition:       2'10 17'-1--1001000000000 ->       2'01 4'0100
  transition:       2'10 17'----100-100000000 ->       2'10 4'1000
  transition:       2'10 17'-----10--00000000 ->       2'10 4'1000
  transition:       2'10 17'------1--00000000 ->       2'10 4'1000
  transition:       2'10 17'---------10000000 ->       2'10 4'1000
  transition:       2'10 17'----------1000000 ->       2'10 4'1000
  transition:       2'10 17'-----------100000 ->       2'10 4'1000
  transition:       2'10 17'------------10000 ->       2'10 4'1000
  transition:       2'10 17'-------------1000 ->       2'10 4'1000
  transition:       2'10 17'--------------100 ->       2'10 4'1000
  transition:       2'10 17'---------------10 ->       2'10 4'1000
  transition:       2'10 17'----------------1 ->       2'10 4'1000
  transition:       2'01 17'---0000--00000000 ->       2'01 4'0110
  transition:       2'01 17'---1000-000000000 ->       2'01 4'0110
  transition:       2'01 17'---1000-100000000 ->       2'10 4'1010
  transition:       2'01 17'----1000000000000 ->       2'01 4'0110
  transition:       2'01 17'000-1001000000000 ->       2'01 4'0110
  transition:       2'01 17'--1-1001000000000 ->       2'10 4'1010
  transition:       2'01 17'1---1001000000000 ->       2'00 4'0010
  transition:       2'01 17'-1--1001000000000 ->       2'01 4'0110
  transition:       2'01 17'----100-100000000 ->       2'01 4'0110
  transition:       2'01 17'-----10--00000000 ->       2'01 4'0110
  transition:       2'01 17'------1--00000000 ->       2'01 4'0110
  transition:       2'01 17'---------10000000 ->       2'01 4'0110
  transition:       2'01 17'----------1000000 ->       2'01 4'0110
  transition:       2'01 17'-----------100000 ->       2'01 4'0110
  transition:       2'01 17'------------10000 ->       2'01 4'0110
  transition:       2'01 17'-------------1000 ->       2'01 4'0110
  transition:       2'01 17'--------------100 ->       2'01 4'0110
  transition:       2'01 17'---------------10 ->       2'10 4'1010
  transition:       2'01 17'----------------1 ->       2'10 4'1010
Extracting FSM `\Riscado_V.ctrlUnit.regDataSrc' from module `\processorci_top'.
  found $dff cell for state register: $flatten\Riscado_V.\ctrlUnit.$procdff$3573
  root of input selection tree: $flatten\Riscado_V.\ctrlUnit.$0\regDataSrc[1:0]
  found ctrl input: \Controller.Interpreter.core_reset
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y
  found state code: 2'01
  found state code: 2'10
  found state code: 2'00
  found ctrl output: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:80$184_Y
  found ctrl output: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:79$183_Y
  found ctrl output: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:78$182_Y
  ctrl inputs: { $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y \Controller.Interpreter.core_reset }
  ctrl outputs: { $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:78$182_Y $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:79$183_Y $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:80$184_Y $flatten\Riscado_V.\ctrlUnit.$0\regDataSrc[1:0] }
  transition:       2'00 13'0000-00000000 ->       2'00 5'10000
  transition:       2'00 13'1000000000000 ->       2'00 5'10000
  transition:       2'00 13'1000100000000 ->       2'01 5'10001
  transition:       2'00 13'-100000000000 ->       2'00 5'10000
  transition:       2'00 13'-100100000000 ->       2'01 5'10001
  transition:       2'00 13'--10000000000 ->       2'00 5'10000
  transition:       2'00 13'--10100000000 ->       2'10 5'10010
  transition:       2'00 13'---1000000000 ->       2'00 5'10000
  transition:       2'00 13'---1100000000 ->       2'10 5'10010
  transition:       2'00 13'-----10000000 ->       2'00 5'10000
  transition:       2'00 13'------1000000 ->       2'00 5'10000
  transition:       2'00 13'-------100000 ->       2'00 5'10000
  transition:       2'00 13'--------10000 ->       2'00 5'10000
  transition:       2'00 13'---------1000 ->       2'00 5'10000
  transition:       2'00 13'----------100 ->       2'00 5'10000
  transition:       2'00 13'-----------10 ->       2'00 5'10000
  transition:       2'00 13'------------1 ->       2'00 5'10000
  transition:       2'10 13'0000-00000000 ->       2'10 5'00110
  transition:       2'10 13'1000000000000 ->       2'10 5'00110
  transition:       2'10 13'1000100000000 ->       2'01 5'00101
  transition:       2'10 13'-100000000000 ->       2'10 5'00110
  transition:       2'10 13'-100100000000 ->       2'01 5'00101
  transition:       2'10 13'--10000000000 ->       2'10 5'00110
  transition:       2'10 13'--10100000000 ->       2'10 5'00110
  transition:       2'10 13'---1000000000 ->       2'10 5'00110
  transition:       2'10 13'---1100000000 ->       2'10 5'00110
  transition:       2'10 13'-----10000000 ->       2'10 5'00110
  transition:       2'10 13'------1000000 ->       2'10 5'00110
  transition:       2'10 13'-------100000 ->       2'10 5'00110
  transition:       2'10 13'--------10000 ->       2'10 5'00110
  transition:       2'10 13'---------1000 ->       2'10 5'00110
  transition:       2'10 13'----------100 ->       2'10 5'00110
  transition:       2'10 13'-----------10 ->       2'00 5'00100
  transition:       2'10 13'------------1 ->       2'10 5'00110
  transition:       2'01 13'0000-00000000 ->       2'01 5'01001
  transition:       2'01 13'1000000000000 ->       2'01 5'01001
  transition:       2'01 13'1000100000000 ->       2'01 5'01001
  transition:       2'01 13'-100000000000 ->       2'01 5'01001
  transition:       2'01 13'-100100000000 ->       2'01 5'01001
  transition:       2'01 13'--10000000000 ->       2'01 5'01001
  transition:       2'01 13'--10100000000 ->       2'10 5'01010
  transition:       2'01 13'---1000000000 ->       2'01 5'01001
  transition:       2'01 13'---1100000000 ->       2'10 5'01010
  transition:       2'01 13'-----10000000 ->       2'01 5'01001
  transition:       2'01 13'------1000000 ->       2'01 5'01001
  transition:       2'01 13'-------100000 ->       2'01 5'01001
  transition:       2'01 13'--------10000 ->       2'01 5'01001
  transition:       2'01 13'---------1000 ->       2'01 5'01001
  transition:       2'01 13'----------100 ->       2'01 5'01001
  transition:       2'01 13'-----------10 ->       2'00 5'01000
  transition:       2'01 13'------------1 ->       2'01 5'01001
Extracting FSM `\Riscado_V.ctrlUnit.state' from module `\processorci_top'.
  found $dff cell for state register: $flatten\Riscado_V.\ctrlUnit.$procdff$3582
  root of input selection tree: $flatten\Riscado_V.\ctrlUnit.$0\state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \Controller.Interpreter.core_reset
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y
  found state code: 3'000
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:187$45_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:307$60_Y
  found state code: 3'101
  found state code: 3'100
  found state code: 3'011
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$or$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:175$44_Y
  found state code: 3'010
  found state code: 3'001
  found ctrl output: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y
  found ctrl output: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y
  found ctrl output: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y
  found ctrl output: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:187$45_Y
  found ctrl output: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:307$60_Y
  found ctrl output: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y
  ctrl inputs: { $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y $flatten\Riscado_V.\ctrlUnit.$or$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:175$44_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y \Controller.Interpreter.core_reset }
  ctrl outputs: { $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:307$60_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:187$45_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y $flatten\Riscado_V.\ctrlUnit.$0\state[2:0] }
  transition:      3'000 11'----------0 ->      3'001 9'000001001
  transition:      3'000 11'----------1 ->      3'000 9'000001000
  transition:      3'100 11'0000-000000 ->      3'000 9'010000000
  transition:      3'100 11'1000-000000 ->      3'101 9'010000101
  transition:      3'100 11'-100-000000 ->      3'000 9'010000000
  transition:      3'100 11'--10-000000 ->      3'000 9'010000000
  transition:      3'100 11'---1-000000 ->      3'000 9'010000000
  transition:      3'100 11'-----100000 ->      3'000 9'010000000
  transition:      3'100 11'------10000 ->      3'000 9'010000000
  transition:      3'100 11'-------1000 ->      3'000 9'010000000
  transition:      3'100 11'--------100 ->      3'000 9'010000000
  transition:      3'100 11'---------10 ->      3'000 9'010000000
  transition:      3'100 11'----------1 ->      3'000 9'010000000
  transition:      3'010 11'0000-000000 ->      3'000 9'000100000
  transition:      3'010 11'1000-000000 ->      3'011 9'000100011
  transition:      3'010 11'-100-000000 ->      3'011 9'000100011
  transition:      3'010 11'--10-000000 ->      3'011 9'000100011
  transition:      3'010 11'---1-000000 ->      3'011 9'000100011
  transition:      3'010 11'-----100000 ->      3'011 9'000100011
  transition:      3'010 11'------10000 ->      3'000 9'000100000
  transition:      3'010 11'-------1000 ->      3'000 9'000100000
  transition:      3'010 11'--------100 ->      3'000 9'000100000
  transition:      3'010 11'---------10 ->      3'000 9'000100000
  transition:      3'010 11'----------1 ->      3'000 9'000100000
  transition:      3'001 11'----------0 ->      3'010 9'000010010
  transition:      3'001 11'----------1 ->      3'000 9'000010000
  transition:      3'101 11'0000-000000 ->      3'000 9'100000000
  transition:      3'101 11'1000-000000 ->      3'000 9'100000000
  transition:      3'101 11'-100-000000 ->      3'101 9'100000101
  transition:      3'101 11'--10-000000 ->      3'000 9'100000000
  transition:      3'101 11'---1-000000 ->      3'000 9'100000000
  transition:      3'101 11'-----100000 ->      3'101 9'100000101
  transition:      3'101 11'------10000 ->      3'000 9'100000000
  transition:      3'101 11'-------1000 ->      3'000 9'100000000
  transition:      3'101 11'--------100 ->      3'000 9'100000000
  transition:      3'101 11'---------10 ->      3'000 9'100000000
  transition:      3'101 11'----------1 ->      3'000 9'100000000
  transition:      3'011 11'0000-000000 ->      3'000 9'001000000
  transition:      3'011 11'1000-000000 ->      3'100 9'001000100
  transition:      3'011 11'-100-000000 ->      3'100 9'001000100
  transition:      3'011 11'--10-000000 ->      3'000 9'001000000
  transition:      3'011 11'---1-000000 ->      3'000 9'001000000
  transition:      3'011 11'----0100000 ->      3'000 9'001000000
  transition:      3'011 11'----1100000 ->      3'100 9'001000100
  transition:      3'011 11'------10000 ->      3'000 9'001000000
  transition:      3'011 11'-------1000 ->      3'000 9'001000000
  transition:      3'011 11'--------100 ->      3'000 9'001000000
  transition:      3'011 11'---------10 ->      3'000 9'001000000
  transition:      3'011 11'----------1 ->      3'000 9'001000000
Extracting FSM `\Riscado_V.ctrlUnit.writeLen' from module `\processorci_top'.
  found $dff cell for state register: $flatten\Riscado_V.\ctrlUnit.$procdff$3580
  root of input selection tree: $flatten\Riscado_V.\ctrlUnit.$0\writeLen[1:0]
  found reset state: 2'10 (guessed from mux tree)
  found ctrl input: \Controller.Interpreter.core_reset
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:187$45_Y
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$procmux$2918_CMP
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$procmux$2876_CMP
  found ctrl input: $flatten\Riscado_V.\ctrlUnit.$procmux$2766_CMP
  found state code: 2'10
  found state code: 2'01
  found state code: 2'00
  found ctrl output: $flatten\Riscado_V.\ls.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:88$229_Y
  found ctrl output: $flatten\Riscado_V.\ls.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:89$230_Y
  ctrl inputs: { $flatten\Riscado_V.\ctrlUnit.$procmux$2918_CMP $flatten\Riscado_V.\ctrlUnit.$procmux$2876_CMP $flatten\Riscado_V.\ctrlUnit.$procmux$2766_CMP $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:187$45_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y \Controller.Interpreter.core_reset }
  ctrl outputs: { $flatten\Riscado_V.\ctrlUnit.$0\writeLen[1:0] $flatten\Riscado_V.\ls.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:89$230_Y $flatten\Riscado_V.\ls.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:88$229_Y }
  transition:       2'00 18'---0000---00000000 ->       2'00 4'0001
  transition:       2'00 18'---100000000000000 ->       2'00 4'0001
  transition:       2'00 18'000100010000000000 ->       2'00 4'0001
  transition:       2'00 18'--1100010000000000 ->       2'00 4'0001
  transition:       2'00 18'-1-100010000000000 ->       2'01 4'0101
  transition:       2'00 18'1--100010000000000 ->       2'10 4'1001
  transition:       2'00 18'---1000-1000000000 ->       2'00 4'0001
  transition:       2'00 18'---1000--100000000 ->       2'00 4'0001
  transition:       2'00 18'----100---00000000 ->       2'00 4'0001
  transition:       2'00 18'-----10---00000000 ->       2'00 4'0001
  transition:       2'00 18'------1---00000000 ->       2'00 4'0001
  transition:       2'00 18'----------10000000 ->       2'00 4'0001
  transition:       2'00 18'-----------1000000 ->       2'00 4'0001
  transition:       2'00 18'------------100000 ->       2'00 4'0001
  transition:       2'00 18'-------------10000 ->       2'00 4'0001
  transition:       2'00 18'--------------1000 ->       2'00 4'0001
  transition:       2'00 18'---------------100 ->       2'00 4'0001
  transition:       2'00 18'----------------10 ->       2'10 4'1001
  transition:       2'00 18'-----------------1 ->       2'10 4'1001
  transition:       2'10 18'---0000---00000000 ->       2'10 4'1000
  transition:       2'10 18'---100000000000000 ->       2'10 4'1000
  transition:       2'10 18'000100010000000000 ->       2'10 4'1000
  transition:       2'10 18'--1100010000000000 ->       2'00 4'0000
  transition:       2'10 18'-1-100010000000000 ->       2'01 4'0100
  transition:       2'10 18'1--100010000000000 ->       2'10 4'1000
  transition:       2'10 18'---1000-1000000000 ->       2'10 4'1000
  transition:       2'10 18'---1000--100000000 ->       2'10 4'1000
  transition:       2'10 18'----100---00000000 ->       2'10 4'1000
  transition:       2'10 18'-----10---00000000 ->       2'10 4'1000
  transition:       2'10 18'------1---00000000 ->       2'10 4'1000
  transition:       2'10 18'----------10000000 ->       2'10 4'1000
  transition:       2'10 18'-----------1000000 ->       2'10 4'1000
  transition:       2'10 18'------------100000 ->       2'10 4'1000
  transition:       2'10 18'-------------10000 ->       2'10 4'1000
  transition:       2'10 18'--------------1000 ->       2'10 4'1000
  transition:       2'10 18'---------------100 ->       2'10 4'1000
  transition:       2'10 18'----------------10 ->       2'10 4'1000
  transition:       2'10 18'-----------------1 ->       2'10 4'1000
  transition:       2'01 18'---0000---00000000 ->       2'01 4'0110
  transition:       2'01 18'---100000000000000 ->       2'01 4'0110
  transition:       2'01 18'000100010000000000 ->       2'01 4'0110
  transition:       2'01 18'--1100010000000000 ->       2'00 4'0010
  transition:       2'01 18'-1-100010000000000 ->       2'01 4'0110
  transition:       2'01 18'1--100010000000000 ->       2'10 4'1010
  transition:       2'01 18'---1000-1000000000 ->       2'01 4'0110
  transition:       2'01 18'---1000--100000000 ->       2'01 4'0110
  transition:       2'01 18'----100---00000000 ->       2'01 4'0110
  transition:       2'01 18'-----10---00000000 ->       2'01 4'0110
  transition:       2'01 18'------1---00000000 ->       2'01 4'0110
  transition:       2'01 18'----------10000000 ->       2'01 4'0110
  transition:       2'01 18'-----------1000000 ->       2'01 4'0110
  transition:       2'01 18'------------100000 ->       2'01 4'0110
  transition:       2'01 18'-------------10000 ->       2'01 4'0110
  transition:       2'01 18'--------------1000 ->       2'01 4'0110
  transition:       2'01 18'---------------100 ->       2'01 4'0110
  transition:       2'01 18'----------------10 ->       2'10 4'1010
  transition:       2'01 18'-----------------1 ->       2'10 4'1010

17.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.writeLen$3737' from module `\processorci_top'.
Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.state$3729' from module `\processorci_top'.
  Merging pattern 11'0000-000000 and 11'1000-000000 from group (4 0 9'100000000).
  Merging pattern 11'1000-000000 and 11'0000-000000 from group (4 0 9'100000000).
Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.regDataSrc$3724' from module `\processorci_top'.
  Merging pattern 13'--10000000000 and 13'--10100000000 from group (1 1 5'00110).
  Merging pattern 13'---1000000000 and 13'---1100000000 from group (1 1 5'00110).
  Merging pattern 13'--10100000000 and 13'--10000000000 from group (1 1 5'00110).
  Merging pattern 13'---1100000000 and 13'---1000000000 from group (1 1 5'00110).
  Merging pattern 13'1000000000000 and 13'1000100000000 from group (2 2 5'01001).
  Merging pattern 13'-100000000000 and 13'-100100000000 from group (2 2 5'01001).
  Merging pattern 13'1000100000000 and 13'1000000000000 from group (2 2 5'01001).
  Merging pattern 13'-100100000000 and 13'-100000000000 from group (2 2 5'01001).
  Merging pattern 13'0000-00000000 and 13'1000-00000000 from group (2 2 5'01001).
  Merging pattern 13'1000-00000000 and 13'0000-00000000 from group (2 2 5'01001).
  Merging pattern 13'-000-00000000 and 13'-100-00000000 from group (2 2 5'01001).
  Merging pattern 13'-100-00000000 and 13'-000-00000000 from group (2 2 5'01001).
Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.readLen$3720' from module `\processorci_top'.
  Merging pattern 17'---1000-000000000 and 17'---1000-100000000 from group (1 1 4'1000).
  Merging pattern 17'---1000-100000000 and 17'---1000-000000000 from group (1 1 4'1000).
  Merging pattern 17'---0000--00000000 and 17'---1000--00000000 from group (1 1 4'1000).
  Merging pattern 17'---1000--00000000 and 17'---0000--00000000 from group (1 1 4'1000).
Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.aluSrcB$3712' from module `\processorci_top'.
  Merging pattern 14'1000-000000000 and 14'1000-100000000 from group (2 2 9'000001010).
  Merging pattern 14'1000-100000000 and 14'1000-000000000 from group (2 2 9'000001010).
  Merging pattern 14'0000--00000000 and 14'1000--00000000 from group (2 2 9'000001010).
  Merging pattern 14'1000--00000000 and 14'0000--00000000 from group (2 2 9'000001010).
  Merging pattern 14'-100-000000000 and 14'-100-100000000 from group (3 3 9'001000001).
  Merging pattern 14'--10-000000000 and 14'--10-100000000 from group (3 3 9'001000001).
  Merging pattern 14'-100-100000000 and 14'-100-000000000 from group (3 3 9'001000001).
  Merging pattern 14'--10-100000000 and 14'--10-000000000 from group (3 3 9'001000001).
  Merging pattern 14'---1-000000000 and 14'---1-100000000 from group (4 4 9'000010101).
  Merging pattern 14'---1-100000000 and 14'---1-000000000 from group (4 4 9'000010101).
  Merging pattern 14'----0010000000 and 14'----1010000000 from group (5 5 9'000100011).
  Merging pattern 14'----1010000000 and 14'----0010000000 from group (5 5 9'000100011).
  Merging pattern 14'-----010000000 and 14'-----110000000 from group (5 5 9'000100011).
  Merging pattern 14'-----110000000 and 14'-----010000000 from group (5 5 9'000100011).
Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.aluSrcA$3707' from module `\processorci_top'.
  Merging pattern 14'1000-000000000 and 14'1000-100000000 from group (0 0 5'10000).
  Merging pattern 14'-100-000000000 and 14'-100-100000000 from group (0 0 5'10000).
  Merging pattern 14'--10-000000000 and 14'--10-100000000 from group (0 0 5'10000).
  Merging pattern 14'1000-100000000 and 14'1000-000000000 from group (0 0 5'10000).
  Merging pattern 14'-100-100000000 and 14'-100-000000000 from group (0 0 5'10000).
  Merging pattern 14'--10-100000000 and 14'--10-000000000 from group (0 0 5'10000).
  Merging pattern 14'0000--00000000 and 14'1000--00000000 from group (0 0 5'10000).
  Merging pattern 14'1000--00000000 and 14'0000--00000000 from group (0 0 5'10000).
  Merging pattern 14'-000--00000000 and 14'-100--00000000 from group (0 0 5'10000).
  Merging pattern 14'-100--00000000 and 14'-000--00000000 from group (0 0 5'10000).
  Merging pattern 14'--00--00000000 and 14'--10--00000000 from group (0 0 5'10000).
  Merging pattern 14'--10--00000000 and 14'--00--00000000 from group (0 0 5'10000).
  Merging pattern 14'---1-000000000 and 14'---1-100000000 from group (1 1 5'00110).
  Merging pattern 14'---1-100000000 and 14'---1-000000000 from group (1 1 5'00110).
  Merging pattern 14'----0010000000 and 14'----1010000000 from group (1 1 5'00110).
  Merging pattern 14'----1010000000 and 14'----0010000000 from group (1 1 5'00110).
  Merging pattern 14'-----010000000 and 14'-----110000000 from group (1 1 5'00110).
  Merging pattern 14'-----110000000 and 14'-----010000000 from group (1 1 5'00110).
Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.aluOperation$3693' from module `\processorci_top'.
  Merging pattern 25'--------1000-000-00000--0 and 25'--------1000-100-00000--0 from group (0 0 16'0000100000000000).
  Merging pattern 25'---------100-000-00000--0 and 25'---------100-100-00000--0 from group (0 0 16'0000100000000000).
  Merging pattern 25'----------10-000-00000--0 and 25'----------10-100-00000--0 from group (0 0 16'0000100000000000).
  Merging pattern 25'-----------1-000-00000--0 and 25'-----------1-100-00000--0 from group (0 0 16'0000100000000000).
  Merging pattern 25'--------1000-100-00000--0 and 25'--------1000-000-00000--0 from group (0 0 16'0000100000000000).
  Merging pattern 25'---------100-100-00000--0 and 25'---------100-000-00000--0 from group (0 0 16'0000100000000000).
  Merging pattern 25'----------10-100-00000--0 and 25'----------10-000-00000--0 from group (0 0 16'0000100000000000).
  Merging pattern 25'-----------1-100-00000--0 and 25'-----------1-000-00000--0 from group (0 0 16'0000100000000000).
  Merging pattern 25'------------0010-00000--0 and 25'------------1010-00000--0 from group (0 0 16'0000100000000000).
  Merging pattern 25'------------1010-00000--0 and 25'------------0010-00000--0 from group (0 0 16'0000100000000000).
  Merging pattern 25'--------0000--00-00000--0 and 25'--------1000--00-00000--0 from group (0 0 16'0000100000000000).
  Merging pattern 25'--------1000--00-00000--0 and 25'--------0000--00-00000--0 from group (0 0 16'0000100000000000).
  Merging pattern 25'---------000--00-00000--0 and 25'---------100--00-00000--0 from group (0 0 16'0000100000000000).
  Merging pattern 25'---------100--00-00000--0 and 25'---------000--00-00000--0 from group (0 0 16'0000100000000000).
  Merging pattern 25'----------00--00-00000--0 and 25'----------10--00-00000--0 from group (0 0 16'0000100000000000).
  Merging pattern 25'----------10--00-00000--0 and 25'----------00--00-00000--0 from group (0 0 16'0000100000000000).
  Merging pattern 25'-----------0--00-00000--0 and 25'-----------1--00-00000--0 from group (0 0 16'0000100000000000).
  Merging pattern 25'-----------1--00-00000--0 and 25'-----------0--00-00000--0 from group (0 0 16'0000100000000000).
Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$3687' from module `\processorci_top'.
  Merging pattern 2'0- and 2'1- from group (3 0 6'010000).
  Merging pattern 2'1- and 2'0- from group (3 0 6'010000).
Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$3680' from module `\processorci_top'.

17.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 178 unused cells and 187 unused wires.
<suppressed ~188 debug messages>

17.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$3680' from module `\processorci_top'.
  Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0].
  Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1].
  Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2].
Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$3687' from module `\processorci_top'.
  Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [0].
  Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [1].
  Removing unused output signal $flatten\Controller.\Uart.$procmux$2294_CMP.
  Removing unused output signal $flatten\Controller.\Uart.$procmux$2296_CMP.
Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.aluOperation$3693' from module `\processorci_top'.
  Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\aluOperation[3:0] [0].
  Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\aluOperation[3:0] [1].
  Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\aluOperation[3:0] [2].
  Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\aluOperation[3:0] [3].
Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.aluSrcA$3707' from module `\processorci_top'.
  Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\aluSrcA[1:0] [0].
  Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\aluSrcA[1:0] [1].
Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.aluSrcB$3712' from module `\processorci_top'.
  Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\aluSrcB[2:0] [0].
  Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\aluSrcB[2:0] [1].
  Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\aluSrcB[2:0] [2].
Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.readLen$3720' from module `\processorci_top'.
  Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\readLen[1:0] [0].
  Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\readLen[1:0] [1].
Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.regDataSrc$3724' from module `\processorci_top'.
  Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\regDataSrc[1:0] [0].
  Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\regDataSrc[1:0] [1].
Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.state$3729' from module `\processorci_top'.
  Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\state[2:0] [0].
  Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\state[2:0] [1].
  Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\state[2:0] [2].
Optimizing FSM `$fsm$\Riscado_V.ctrlUnit.writeLen$3737' from module `\processorci_top'.
  Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\writeLen[1:0] [0].
  Removing unused output signal $flatten\Riscado_V.\ctrlUnit.$0\writeLen[1:0] [1].

17.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$3680' from module `\processorci_top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ---1
  010 -> --1-
  001 -> -1--
  011 -> 1---
Recoding FSM `$fsm$\Controller.Uart.tx_fifo_read_state$3687' from module `\processorci_top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  00 -> ---1
  10 -> --1-
  01 -> -1--
  11 -> 1---
Recoding FSM `$fsm$\Riscado_V.ctrlUnit.aluOperation$3693' from module `\processorci_top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  0000 -> ------------1
  1000 -> -----------1-
  0100 -> ----------1--
  1100 -> ---------1---
  0010 -> --------1----
  1010 -> -------1-----
  0110 -> ------1------
  0001 -> -----1-------
  1001 -> ----1--------
  0101 -> ---1---------
  1101 -> --1----------
  0011 -> -1-----------
  0111 -> 1------------
Recoding FSM `$fsm$\Riscado_V.ctrlUnit.aluSrcA$3707' from module `\processorci_top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  00 -> -1
  10 -> 1-
Recoding FSM `$fsm$\Riscado_V.ctrlUnit.aluSrcB$3712' from module `\processorci_top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> -----1
  100 -> ----1-
  010 -> ---1--
  001 -> --1---
  101 -> -1----
  011 -> 1-----
Recoding FSM `$fsm$\Riscado_V.ctrlUnit.readLen$3720' from module `\processorci_top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  00 -> -1-
  10 -> --1
  01 -> 1--
Recoding FSM `$fsm$\Riscado_V.ctrlUnit.regDataSrc$3724' from module `\processorci_top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  00 -> --1
  10 -> -1-
  01 -> 1--
Recoding FSM `$fsm$\Riscado_V.ctrlUnit.state$3729' from module `\processorci_top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> -----1
  100 -> ----1-
  010 -> ---1--
  001 -> --1---
  101 -> -1----
  011 -> 1-----
Recoding FSM `$fsm$\Riscado_V.ctrlUnit.writeLen$3737' from module `\processorci_top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  00 -> -1-
  10 -> --1
  01 -> 1--

17.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$3680' from module `processorci_top':
-------------------------------------

  Information on FSM $fsm$\Controller.Uart.i_uart_rx.fsm_state$3680 (\Controller.Uart.i_uart_rx.fsm_state):

  Number of input signals:    4
  Number of output signals:   5
  Number of state bits:       4

  Input signals:
    0: \Controller.Uart.i_uart_rx.payload_done
    1: \Controller.Uart.i_uart_rx.next_bit
    2: \Controller.Uart.i_uart_rx.rxd_reg
    3: \ResetBootSystem.reset_o

  Output signals:
    0: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1181_Y
    1: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1172_Y
    2: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1168_Y
    3: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1167_Y
    4: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1155_Y

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 4'01--   ->     0 5'01010
      1:     0 4'1---   ->     0 5'01010
      2:     0 4'00--   ->     2 5'01010
      3:     1 4'1---   ->     0 5'00100
      4:     1 4'0--0   ->     1 5'00100
      5:     1 4'0--1   ->     3 5'00100
      6:     2 4'1---   ->     0 5'00011
      7:     2 4'0-1-   ->     1 5'00011
      8:     2 4'0-0-   ->     2 5'00011
      9:     3 4'0-1-   ->     0 5'10010
     10:     3 4'1---   ->     0 5'10010
     11:     3 4'0-0-   ->     3 5'10010

-------------------------------------

FSM `$fsm$\Controller.Uart.tx_fifo_read_state$3687' from module `processorci_top':
-------------------------------------

  Information on FSM $fsm$\Controller.Uart.tx_fifo_read_state$3687 (\Controller.Uart.tx_fifo_read_state):

  Number of input signals:    2
  Number of output signals:   2
  Number of state bits:       4

  Input signals:
    0: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1041_Y
    1: \ResetBootSystem.reset_o

  Output signals:
    0: $flatten\Controller.\Uart.$procmux$2283_CMP
    1: $flatten\Controller.\Uart.$procmux$2289_CMP

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 2'00   ->     0 2'01
      1:     0 2'1-   ->     0 2'01
      2:     0 2'01   ->     2 2'01
      3:     1 2'1-   ->     0 2'10
      4:     1 2'0-   ->     3 2'10
      5:     2 2'1-   ->     0 2'00
      6:     2 2'0-   ->     1 2'00
      7:     3 2'--   ->     0 2'00

-------------------------------------

FSM `$fsm$\Riscado_V.ctrlUnit.aluOperation$3693' from module `processorci_top':
-------------------------------------

  Information on FSM $fsm$\Riscado_V.ctrlUnit.aluOperation$3693 (\Riscado_V.ctrlUnit.aluOperation):

  Number of input signals:   25
  Number of output signals:  12
  Number of state bits:      13

  Input signals:
    0: \Controller.Interpreter.core_reset
    1: $auto$opt_reduce.cc:134:opt_pmux$3663
    2: $auto$opt_reduce.cc:134:opt_pmux$3665
    3: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y
    4: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y
    5: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y
    6: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y
    7: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y
    8: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:123$28_Y
    9: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y
   10: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y
   11: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y
   12: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y
   13: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y
   14: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y
   15: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y
   16: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y
   17: $flatten\Riscado_V.\ctrlUnit.$procmux$2764_CMP
   18: $flatten\Riscado_V.\ctrlUnit.$procmux$2765_CMP
   19: $flatten\Riscado_V.\ctrlUnit.$procmux$2766_CMP
   20: $flatten\Riscado_V.\ctrlUnit.$procmux$2876_CMP
   21: $flatten\Riscado_V.\ctrlUnit.$procmux$2918_CMP
   22: $flatten\Riscado_V.\ctrlUnit.$procmux$2973_CMP
   23: $flatten\Riscado_V.\ctrlUnit.$procmux$3046_CMP
   24: $flatten\Riscado_V.\ctrlUnit.$procmux$3060_CMP

  Output signals:
    0: $flatten\Riscado_V.\alu.$procmux$3468_CMP
    1: $flatten\Riscado_V.\alu.$procmux$3467_CMP
    2: $flatten\Riscado_V.\alu.$procmux$3466_CMP
    3: $flatten\Riscado_V.\alu.$procmux$3465_CMP
    4: $flatten\Riscado_V.\alu.$procmux$3469_CMP
    5: $flatten\Riscado_V.\alu.$procmux$3470_CMP
    6: $flatten\Riscado_V.\alu.$procmux$3471_CMP
    7: $flatten\Riscado_V.\alu.$procmux$3472_CMP
    8: $flatten\Riscado_V.\alu.$procmux$3473_CMP
    9: $flatten\Riscado_V.\alu.$procmux$3474_CMP
   10: $flatten\Riscado_V.\alu.$procmux$3475_CMP
   11: $flatten\Riscado_V.\alu.$procmux$3476_CMP

  State encoding:
    0: 13'------------1
    1: 13'-----------1-
    2: 13'----------1--
    3: 13'---------1---
    4: 13'--------1----
    5: 13'-------1-----
    6: 13'------1------
    7: 13'-----1-------
    8: 13'----1--------
    9: 13'---1---------
   10: 13'--1----------
   11: 13'-1-----------
   12: 13'1------------

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 25'-----1---------1000000--0   ->     0 12'100000000000
      1:     0 25'--------------00-00000--0   ->     0 12'100000000000
      2:     0 25'-------------010-00000--0   ->     0 12'100000000000
      3:     0 25'-----1-----------10000--0   ->     0 12'100000000000
      4:     0 25'------------------1000--0   ->     0 12'100000000000
      5:     0 25'--------------------10--0   ->     0 12'100000000000
      6:     0 25'------------------------1   ->     0 12'100000000000
      7:     0 25'-----1---------1100000--0   ->     1 12'100000000000
      8:     0 25'------1--------1-00000--0   ->     2 12'100000000000
      9:     0 25'------1----------10000--0   ->     2 12'100000000000
     10:     0 25'-------------110-00000000   ->     3 12'100000000000
     11:     0 25'-------------110-000001-0   ->     4 12'100000000000
     12:     0 25'---1-----------1-00000--0   ->     4 12'100000000000
     13:     0 25'---1-------------10000--0   ->     4 12'100000000000
     14:     0 25'-------------------100--0   ->     5 12'100000000000
     15:     0 25'-------1-------1-00000--0   ->     6 12'100000000000
     16:     0 25'-------1---------10000--0   ->     6 12'100000000000
     17:     0 25'----1----------1-00000--0   ->     7 12'100000000000
     18:     0 25'----1------------10000--0   ->     7 12'100000000000
     19:     0 25'---------------------1--0   ->     8 12'100000000000
     20:     0 25'--1------------1000000--0   ->     9 12'100000000000
     21:     0 25'--1-------------010000--0   ->     9 12'100000000000
     22:     0 25'--1------------1100000--0   ->    10 12'100000000000
     23:     0 25'--1-------------110000--0   ->    10 12'100000000000
     24:     0 25'-------------110-00000-10   ->    11 12'100000000000
     25:     0 25'1--------------1-00000--0   ->    11 12'100000000000
     26:     0 25'1----------------10000--0   ->    11 12'100000000000
     27:     0 25'-1-------------1-00000--0   ->    12 12'100000000000
     28:     0 25'-1---------------10000--0   ->    12 12'100000000000
     29:     1 25'-----1---------1000000--0   ->     0 12'000000000001
     30:     1 25'--------1000-100-00000--0   ->     0 12'000000000001
     31:     1 25'---------100-100-00000--0   ->     0 12'000000000001
     32:     1 25'----------10-100-00000--0   ->     0 12'000000000001
     33:     1 25'-----------1-100-00000--0   ->     0 12'000000000001
     34:     1 25'------------1010-00000--0   ->     0 12'000000000001
     35:     1 25'-----1-----------10000--0   ->     0 12'000000000001
     36:     1 25'------------------1000--0   ->     0 12'000000000001
     37:     1 25'-----1---------1100000--0   ->     1 12'000000000001
     38:     1 25'--------1000-000-00000--0   ->     1 12'000000000001
     39:     1 25'---------100-000-00000--0   ->     1 12'000000000001
     40:     1 25'----------10-000-00000--0   ->     1 12'000000000001
     41:     1 25'-----------1-000-00000--0   ->     1 12'000000000001
     42:     1 25'--------0000--00-00000--0   ->     1 12'000000000001
     43:     1 25'------------0010-00000--0   ->     1 12'000000000001
     44:     1 25'--------------------10--0   ->     1 12'000000000001
     45:     1 25'------------------------1   ->     1 12'000000000001
     46:     1 25'------1--------1-00000--0   ->     2 12'000000000001
     47:     1 25'------1----------10000--0   ->     2 12'000000000001
     48:     1 25'-------------110-00000000   ->     3 12'000000000001
     49:     1 25'-------------110-000001-0   ->     4 12'000000000001
     50:     1 25'---1-----------1-00000--0   ->     4 12'000000000001
     51:     1 25'---1-------------10000--0   ->     4 12'000000000001
     52:     1 25'-------------------100--0   ->     5 12'000000000001
     53:     1 25'-------1-------1-00000--0   ->     6 12'000000000001
     54:     1 25'-------1---------10000--0   ->     6 12'000000000001
     55:     1 25'----1----------1-00000--0   ->     7 12'000000000001
     56:     1 25'----1------------10000--0   ->     7 12'000000000001
     57:     1 25'---------------------1--0   ->     8 12'000000000001
     58:     1 25'--1------------1000000--0   ->     9 12'000000000001
     59:     1 25'--1-------------010000--0   ->     9 12'000000000001
     60:     1 25'--1------------1100000--0   ->    10 12'000000000001
     61:     1 25'--1-------------110000--0   ->    10 12'000000000001
     62:     1 25'-------------110-00000-10   ->    11 12'000000000001
     63:     1 25'1--------------1-00000--0   ->    11 12'000000000001
     64:     1 25'1----------------10000--0   ->    11 12'000000000001
     65:     1 25'-1-------------1-00000--0   ->    12 12'000000000001
     66:     1 25'-1---------------10000--0   ->    12 12'000000000001
     67:     2 25'-----1---------1000000--0   ->     0 12'000010000000
     68:     2 25'--------1000-100-00000--0   ->     0 12'000010000000
     69:     2 25'---------100-100-00000--0   ->     0 12'000010000000
     70:     2 25'----------10-100-00000--0   ->     0 12'000010000000
     71:     2 25'-----------1-100-00000--0   ->     0 12'000010000000
     72:     2 25'------------1010-00000--0   ->     0 12'000010000000
     73:     2 25'-----1-----------10000--0   ->     0 12'000010000000
     74:     2 25'------------------1000--0   ->     0 12'000010000000
     75:     2 25'-----1---------1100000--0   ->     1 12'000010000000
     76:     2 25'--------1000-000-00000--0   ->     2 12'000010000000
     77:     2 25'---------100-000-00000--0   ->     2 12'000010000000
     78:     2 25'----------10-000-00000--0   ->     2 12'000010000000
     79:     2 25'-----------1-000-00000--0   ->     2 12'000010000000
     80:     2 25'--------0000--00-00000--0   ->     2 12'000010000000
     81:     2 25'------------0010-00000--0   ->     2 12'000010000000
     82:     2 25'------1--------1-00000--0   ->     2 12'000010000000
     83:     2 25'------1----------10000--0   ->     2 12'000010000000
     84:     2 25'--------------------10--0   ->     2 12'000010000000
     85:     2 25'------------------------1   ->     2 12'000010000000
     86:     2 25'-------------110-00000000   ->     3 12'000010000000
     87:     2 25'-------------110-000001-0   ->     4 12'000010000000
     88:     2 25'---1-----------1-00000--0   ->     4 12'000010000000
     89:     2 25'---1-------------10000--0   ->     4 12'000010000000
     90:     2 25'-------------------100--0   ->     5 12'000010000000
     91:     2 25'-------1-------1-00000--0   ->     6 12'000010000000
     92:     2 25'-------1---------10000--0   ->     6 12'000010000000
     93:     2 25'----1----------1-00000--0   ->     7 12'000010000000
     94:     2 25'----1------------10000--0   ->     7 12'000010000000
     95:     2 25'---------------------1--0   ->     8 12'000010000000
     96:     2 25'--1------------1000000--0   ->     9 12'000010000000
     97:     2 25'--1-------------010000--0   ->     9 12'000010000000
     98:     2 25'--1------------1100000--0   ->    10 12'000010000000
     99:     2 25'--1-------------110000--0   ->    10 12'000010000000
    100:     2 25'-------------110-00000-10   ->    11 12'000010000000
    101:     2 25'1--------------1-00000--0   ->    11 12'000010000000
    102:     2 25'1----------------10000--0   ->    11 12'000010000000
    103:     2 25'-1-------------1-00000--0   ->    12 12'000010000000
    104:     2 25'-1---------------10000--0   ->    12 12'000010000000
    105:     3 25'-----1---------1000000--0   ->     0 12'000000001000
    106:     3 25'--------1000-100-00000--0   ->     0 12'000000001000
    107:     3 25'---------100-100-00000--0   ->     0 12'000000001000
    108:     3 25'----------10-100-00000--0   ->     0 12'000000001000
    109:     3 25'-----------1-100-00000--0   ->     0 12'000000001000
    110:     3 25'------------1010-00000--0   ->     0 12'000000001000
    111:     3 25'-----1-----------10000--0   ->     0 12'000000001000
    112:     3 25'------------------1000--0   ->     0 12'000000001000
    113:     3 25'-----1---------1100000--0   ->     1 12'000000001000
    114:     3 25'------1--------1-00000--0   ->     2 12'000000001000
    115:     3 25'------1----------10000--0   ->     2 12'000000001000
    116:     3 25'-------------110-00000000   ->     3 12'000000001000
    117:     3 25'--------1000-000-00000--0   ->     3 12'000000001000
    118:     3 25'---------100-000-00000--0   ->     3 12'000000001000
    119:     3 25'----------10-000-00000--0   ->     3 12'000000001000
    120:     3 25'-----------1-000-00000--0   ->     3 12'000000001000
    121:     3 25'--------0000--00-00000--0   ->     3 12'000000001000
    122:     3 25'------------0010-00000--0   ->     3 12'000000001000
    123:     3 25'--------------------10--0   ->     3 12'000000001000
    124:     3 25'------------------------1   ->     3 12'000000001000
    125:     3 25'-------------110-000001-0   ->     4 12'000000001000
    126:     3 25'---1-----------1-00000--0   ->     4 12'000000001000
    127:     3 25'---1-------------10000--0   ->     4 12'000000001000
    128:     3 25'-------------------100--0   ->     5 12'000000001000
    129:     3 25'-------1-------1-00000--0   ->     6 12'000000001000
    130:     3 25'-------1---------10000--0   ->     6 12'000000001000
    131:     3 25'----1----------1-00000--0   ->     7 12'000000001000
    132:     3 25'----1------------10000--0   ->     7 12'000000001000
    133:     3 25'---------------------1--0   ->     8 12'000000001000
    134:     3 25'--1------------1000000--0   ->     9 12'000000001000
    135:     3 25'--1-------------010000--0   ->     9 12'000000001000
    136:     3 25'--1------------1100000--0   ->    10 12'000000001000
    137:     3 25'--1-------------110000--0   ->    10 12'000000001000
    138:     3 25'-------------110-00000-10   ->    11 12'000000001000
    139:     3 25'1--------------1-00000--0   ->    11 12'000000001000
    140:     3 25'1----------------10000--0   ->    11 12'000000001000
    141:     3 25'-1-------------1-00000--0   ->    12 12'000000001000
    142:     3 25'-1---------------10000--0   ->    12 12'000000001000
    143:     4 25'-----1---------1000000--0   ->     0 12'001000000000
    144:     4 25'--------1000-100-00000--0   ->     0 12'001000000000
    145:     4 25'---------100-100-00000--0   ->     0 12'001000000000
    146:     4 25'----------10-100-00000--0   ->     0 12'001000000000
    147:     4 25'-----------1-100-00000--0   ->     0 12'001000000000
    148:     4 25'------------1010-00000--0   ->     0 12'001000000000
    149:     4 25'-----1-----------10000--0   ->     0 12'001000000000
    150:     4 25'------------------1000--0   ->     0 12'001000000000
    151:     4 25'-----1---------1100000--0   ->     1 12'001000000000
    152:     4 25'------1--------1-00000--0   ->     2 12'001000000000
    153:     4 25'------1----------10000--0   ->     2 12'001000000000
    154:     4 25'-------------110-00000000   ->     3 12'001000000000
    155:     4 25'-------------110-000001-0   ->     4 12'001000000000
    156:     4 25'--------1000-000-00000--0   ->     4 12'001000000000
    157:     4 25'---------100-000-00000--0   ->     4 12'001000000000
    158:     4 25'----------10-000-00000--0   ->     4 12'001000000000
    159:     4 25'-----------1-000-00000--0   ->     4 12'001000000000
    160:     4 25'--------0000--00-00000--0   ->     4 12'001000000000
    161:     4 25'------------0010-00000--0   ->     4 12'001000000000
    162:     4 25'---1-----------1-00000--0   ->     4 12'001000000000
    163:     4 25'---1-------------10000--0   ->     4 12'001000000000
    164:     4 25'--------------------10--0   ->     4 12'001000000000
    165:     4 25'------------------------1   ->     4 12'001000000000
    166:     4 25'-------------------100--0   ->     5 12'001000000000
    167:     4 25'-------1-------1-00000--0   ->     6 12'001000000000
    168:     4 25'-------1---------10000--0   ->     6 12'001000000000
    169:     4 25'----1----------1-00000--0   ->     7 12'001000000000
    170:     4 25'----1------------10000--0   ->     7 12'001000000000
    171:     4 25'---------------------1--0   ->     8 12'001000000000
    172:     4 25'--1------------1000000--0   ->     9 12'001000000000
    173:     4 25'--1-------------010000--0   ->     9 12'001000000000
    174:     4 25'--1------------1100000--0   ->    10 12'001000000000
    175:     4 25'--1-------------110000--0   ->    10 12'001000000000
    176:     4 25'-------------110-00000-10   ->    11 12'001000000000
    177:     4 25'1--------------1-00000--0   ->    11 12'001000000000
    178:     4 25'1----------------10000--0   ->    11 12'001000000000
    179:     4 25'-1-------------1-00000--0   ->    12 12'001000000000
    180:     4 25'-1---------------10000--0   ->    12 12'001000000000
    181:     5 25'-----1---------1000000--0   ->     0 12'000000000100
    182:     5 25'--------1000-100-00000--0   ->     0 12'000000000100
    183:     5 25'---------100-100-00000--0   ->     0 12'000000000100
    184:     5 25'----------10-100-00000--0   ->     0 12'000000000100
    185:     5 25'-----------1-100-00000--0   ->     0 12'000000000100
    186:     5 25'------------1010-00000--0   ->     0 12'000000000100
    187:     5 25'-----1-----------10000--0   ->     0 12'000000000100
    188:     5 25'------------------1000--0   ->     0 12'000000000100
    189:     5 25'-----1---------1100000--0   ->     1 12'000000000100
    190:     5 25'------1--------1-00000--0   ->     2 12'000000000100
    191:     5 25'------1----------10000--0   ->     2 12'000000000100
    192:     5 25'-------------110-00000000   ->     3 12'000000000100
    193:     5 25'-------------110-000001-0   ->     4 12'000000000100
    194:     5 25'---1-----------1-00000--0   ->     4 12'000000000100
    195:     5 25'---1-------------10000--0   ->     4 12'000000000100
    196:     5 25'--------1000-000-00000--0   ->     5 12'000000000100
    197:     5 25'---------100-000-00000--0   ->     5 12'000000000100
    198:     5 25'----------10-000-00000--0   ->     5 12'000000000100
    199:     5 25'-----------1-000-00000--0   ->     5 12'000000000100
    200:     5 25'--------0000--00-00000--0   ->     5 12'000000000100
    201:     5 25'------------0010-00000--0   ->     5 12'000000000100
    202:     5 25'-------------------100--0   ->     5 12'000000000100
    203:     5 25'--------------------10--0   ->     5 12'000000000100
    204:     5 25'------------------------1   ->     5 12'000000000100
    205:     5 25'-------1-------1-00000--0   ->     6 12'000000000100
    206:     5 25'-------1---------10000--0   ->     6 12'000000000100
    207:     5 25'----1----------1-00000--0   ->     7 12'000000000100
    208:     5 25'----1------------10000--0   ->     7 12'000000000100
    209:     5 25'---------------------1--0   ->     8 12'000000000100
    210:     5 25'--1------------1000000--0   ->     9 12'000000000100
    211:     5 25'--1-------------010000--0   ->     9 12'000000000100
    212:     5 25'--1------------1100000--0   ->    10 12'000000000100
    213:     5 25'--1-------------110000--0   ->    10 12'000000000100
    214:     5 25'-------------110-00000-10   ->    11 12'000000000100
    215:     5 25'1--------------1-00000--0   ->    11 12'000000000100
    216:     5 25'1----------------10000--0   ->    11 12'000000000100
    217:     5 25'-1-------------1-00000--0   ->    12 12'000000000100
    218:     5 25'-1---------------10000--0   ->    12 12'000000000100
    219:     6 25'-----1---------1000000--0   ->     0 12'000000100000
    220:     6 25'--------1000-100-00000--0   ->     0 12'000000100000
    221:     6 25'---------100-100-00000--0   ->     0 12'000000100000
    222:     6 25'----------10-100-00000--0   ->     0 12'000000100000
    223:     6 25'-----------1-100-00000--0   ->     0 12'000000100000
    224:     6 25'------------1010-00000--0   ->     0 12'000000100000
    225:     6 25'-----1-----------10000--0   ->     0 12'000000100000
    226:     6 25'------------------1000--0   ->     0 12'000000100000
    227:     6 25'-----1---------1100000--0   ->     1 12'000000100000
    228:     6 25'------1--------1-00000--0   ->     2 12'000000100000
    229:     6 25'------1----------10000--0   ->     2 12'000000100000
    230:     6 25'-------------110-00000000   ->     3 12'000000100000
    231:     6 25'-------------110-000001-0   ->     4 12'000000100000
    232:     6 25'---1-----------1-00000--0   ->     4 12'000000100000
    233:     6 25'---1-------------10000--0   ->     4 12'000000100000
    234:     6 25'-------------------100--0   ->     5 12'000000100000
    235:     6 25'--------1000-000-00000--0   ->     6 12'000000100000
    236:     6 25'---------100-000-00000--0   ->     6 12'000000100000
    237:     6 25'----------10-000-00000--0   ->     6 12'000000100000
    238:     6 25'-----------1-000-00000--0   ->     6 12'000000100000
    239:     6 25'--------0000--00-00000--0   ->     6 12'000000100000
    240:     6 25'------------0010-00000--0   ->     6 12'000000100000
    241:     6 25'-------1-------1-00000--0   ->     6 12'000000100000
    242:     6 25'-------1---------10000--0   ->     6 12'000000100000
    243:     6 25'--------------------10--0   ->     6 12'000000100000
    244:     6 25'------------------------1   ->     6 12'000000100000
    245:     6 25'----1----------1-00000--0   ->     7 12'000000100000
    246:     6 25'----1------------10000--0   ->     7 12'000000100000
    247:     6 25'---------------------1--0   ->     8 12'000000100000
    248:     6 25'--1------------1000000--0   ->     9 12'000000100000
    249:     6 25'--1-------------010000--0   ->     9 12'000000100000
    250:     6 25'--1------------1100000--0   ->    10 12'000000100000
    251:     6 25'--1-------------110000--0   ->    10 12'000000100000
    252:     6 25'-------------110-00000-10   ->    11 12'000000100000
    253:     6 25'1--------------1-00000--0   ->    11 12'000000100000
    254:     6 25'1----------------10000--0   ->    11 12'000000100000
    255:     6 25'-1-------------1-00000--0   ->    12 12'000000100000
    256:     6 25'-1---------------10000--0   ->    12 12'000000100000
    257:     7 25'-----1---------1000000--0   ->     0 12'010000000000
    258:     7 25'--------1000-100-00000--0   ->     0 12'010000000000
    259:     7 25'---------100-100-00000--0   ->     0 12'010000000000
    260:     7 25'----------10-100-00000--0   ->     0 12'010000000000
    261:     7 25'-----------1-100-00000--0   ->     0 12'010000000000
    262:     7 25'------------1010-00000--0   ->     0 12'010000000000
    263:     7 25'-----1-----------10000--0   ->     0 12'010000000000
    264:     7 25'------------------1000--0   ->     0 12'010000000000
    265:     7 25'-----1---------1100000--0   ->     1 12'010000000000
    266:     7 25'------1--------1-00000--0   ->     2 12'010000000000
    267:     7 25'------1----------10000--0   ->     2 12'010000000000
    268:     7 25'-------------110-00000000   ->     3 12'010000000000
    269:     7 25'-------------110-000001-0   ->     4 12'010000000000
    270:     7 25'---1-----------1-00000--0   ->     4 12'010000000000
    271:     7 25'---1-------------10000--0   ->     4 12'010000000000
    272:     7 25'-------------------100--0   ->     5 12'010000000000
    273:     7 25'-------1-------1-00000--0   ->     6 12'010000000000
    274:     7 25'-------1---------10000--0   ->     6 12'010000000000
    275:     7 25'--------1000-000-00000--0   ->     7 12'010000000000
    276:     7 25'---------100-000-00000--0   ->     7 12'010000000000
    277:     7 25'----------10-000-00000--0   ->     7 12'010000000000
    278:     7 25'-----------1-000-00000--0   ->     7 12'010000000000
    279:     7 25'--------0000--00-00000--0   ->     7 12'010000000000
    280:     7 25'------------0010-00000--0   ->     7 12'010000000000
    281:     7 25'----1----------1-00000--0   ->     7 12'010000000000
    282:     7 25'----1------------10000--0   ->     7 12'010000000000
    283:     7 25'--------------------10--0   ->     7 12'010000000000
    284:     7 25'------------------------1   ->     7 12'010000000000
    285:     7 25'---------------------1--0   ->     8 12'010000000000
    286:     7 25'--1------------1000000--0   ->     9 12'010000000000
    287:     7 25'--1-------------010000--0   ->     9 12'010000000000
    288:     7 25'--1------------1100000--0   ->    10 12'010000000000
    289:     7 25'--1-------------110000--0   ->    10 12'010000000000
    290:     7 25'-------------110-00000-10   ->    11 12'010000000000
    291:     7 25'1--------------1-00000--0   ->    11 12'010000000000
    292:     7 25'1----------------10000--0   ->    11 12'010000000000
    293:     7 25'-1-------------1-00000--0   ->    12 12'010000000000
    294:     7 25'-1---------------10000--0   ->    12 12'010000000000
    295:     8 25'-----1---------1000000--0   ->     0 12'000000000000
    296:     8 25'--------1000-100-00000--0   ->     0 12'000000000000
    297:     8 25'---------100-100-00000--0   ->     0 12'000000000000
    298:     8 25'----------10-100-00000--0   ->     0 12'000000000000
    299:     8 25'-----------1-100-00000--0   ->     0 12'000000000000
    300:     8 25'------------1010-00000--0   ->     0 12'000000000000
    301:     8 25'-----1-----------10000--0   ->     0 12'000000000000
    302:     8 25'------------------1000--0   ->     0 12'000000000000
    303:     8 25'-----1---------1100000--0   ->     1 12'000000000000
    304:     8 25'------1--------1-00000--0   ->     2 12'000000000000
    305:     8 25'------1----------10000--0   ->     2 12'000000000000
    306:     8 25'-------------110-00000000   ->     3 12'000000000000
    307:     8 25'-------------110-000001-0   ->     4 12'000000000000
    308:     8 25'---1-----------1-00000--0   ->     4 12'000000000000
    309:     8 25'---1-------------10000--0   ->     4 12'000000000000
    310:     8 25'-------------------100--0   ->     5 12'000000000000
    311:     8 25'-------1-------1-00000--0   ->     6 12'000000000000
    312:     8 25'-------1---------10000--0   ->     6 12'000000000000
    313:     8 25'----1----------1-00000--0   ->     7 12'000000000000
    314:     8 25'----1------------10000--0   ->     7 12'000000000000
    315:     8 25'--------1000-000-00000--0   ->     8 12'000000000000
    316:     8 25'---------100-000-00000--0   ->     8 12'000000000000
    317:     8 25'----------10-000-00000--0   ->     8 12'000000000000
    318:     8 25'-----------1-000-00000--0   ->     8 12'000000000000
    319:     8 25'--------0000--00-00000--0   ->     8 12'000000000000
    320:     8 25'------------0010-00000--0   ->     8 12'000000000000
    321:     8 25'--------------------10--0   ->     8 12'000000000000
    322:     8 25'---------------------1--0   ->     8 12'000000000000
    323:     8 25'------------------------1   ->     8 12'000000000000
    324:     8 25'--1------------1000000--0   ->     9 12'000000000000
    325:     8 25'--1-------------010000--0   ->     9 12'000000000000
    326:     8 25'--1------------1100000--0   ->    10 12'000000000000
    327:     8 25'--1-------------110000--0   ->    10 12'000000000000
    328:     8 25'-------------110-00000-10   ->    11 12'000000000000
    329:     8 25'1--------------1-00000--0   ->    11 12'000000000000
    330:     8 25'1----------------10000--0   ->    11 12'000000000000
    331:     8 25'-1-------------1-00000--0   ->    12 12'000000000000
    332:     8 25'-1---------------10000--0   ->    12 12'000000000000
    333:     9 25'-----1---------1000000--0   ->     0 12'000001000000
    334:     9 25'--------1000-100-00000--0   ->     0 12'000001000000
    335:     9 25'---------100-100-00000--0   ->     0 12'000001000000
    336:     9 25'----------10-100-00000--0   ->     0 12'000001000000
    337:     9 25'-----------1-100-00000--0   ->     0 12'000001000000
    338:     9 25'------------1010-00000--0   ->     0 12'000001000000
    339:     9 25'-----1-----------10000--0   ->     0 12'000001000000
    340:     9 25'------------------1000--0   ->     0 12'000001000000
    341:     9 25'-----1---------1100000--0   ->     1 12'000001000000
    342:     9 25'------1--------1-00000--0   ->     2 12'000001000000
    343:     9 25'------1----------10000--0   ->     2 12'000001000000
    344:     9 25'-------------110-00000000   ->     3 12'000001000000
    345:     9 25'-------------110-000001-0   ->     4 12'000001000000
    346:     9 25'---1-----------1-00000--0   ->     4 12'000001000000
    347:     9 25'---1-------------10000--0   ->     4 12'000001000000
    348:     9 25'-------------------100--0   ->     5 12'000001000000
    349:     9 25'-------1-------1-00000--0   ->     6 12'000001000000
    350:     9 25'-------1---------10000--0   ->     6 12'000001000000
    351:     9 25'----1----------1-00000--0   ->     7 12'000001000000
    352:     9 25'----1------------10000--0   ->     7 12'000001000000
    353:     9 25'---------------------1--0   ->     8 12'000001000000
    354:     9 25'--1------------1000000--0   ->     9 12'000001000000
    355:     9 25'--------1000-000-00000--0   ->     9 12'000001000000
    356:     9 25'---------100-000-00000--0   ->     9 12'000001000000
    357:     9 25'----------10-000-00000--0   ->     9 12'000001000000
    358:     9 25'-----------1-000-00000--0   ->     9 12'000001000000
    359:     9 25'--------0000--00-00000--0   ->     9 12'000001000000
    360:     9 25'------------0010-00000--0   ->     9 12'000001000000
    361:     9 25'--1-------------010000--0   ->     9 12'000001000000
    362:     9 25'--------------------10--0   ->     9 12'000001000000
    363:     9 25'------------------------1   ->     9 12'000001000000
    364:     9 25'--1------------1100000--0   ->    10 12'000001000000
    365:     9 25'--1-------------110000--0   ->    10 12'000001000000
    366:     9 25'-------------110-00000-10   ->    11 12'000001000000
    367:     9 25'1--------------1-00000--0   ->    11 12'000001000000
    368:     9 25'1----------------10000--0   ->    11 12'000001000000
    369:     9 25'-1-------------1-00000--0   ->    12 12'000001000000
    370:     9 25'-1---------------10000--0   ->    12 12'000001000000
    371:    10 25'-----1---------1000000--0   ->     0 12'000000000010
    372:    10 25'--------1000-100-00000--0   ->     0 12'000000000010
    373:    10 25'---------100-100-00000--0   ->     0 12'000000000010
    374:    10 25'----------10-100-00000--0   ->     0 12'000000000010
    375:    10 25'-----------1-100-00000--0   ->     0 12'000000000010
    376:    10 25'------------1010-00000--0   ->     0 12'000000000010
    377:    10 25'-----1-----------10000--0   ->     0 12'000000000010
    378:    10 25'------------------1000--0   ->     0 12'000000000010
    379:    10 25'-----1---------1100000--0   ->     1 12'000000000010
    380:    10 25'------1--------1-00000--0   ->     2 12'000000000010
    381:    10 25'------1----------10000--0   ->     2 12'000000000010
    382:    10 25'-------------110-00000000   ->     3 12'000000000010
    383:    10 25'-------------110-000001-0   ->     4 12'000000000010
    384:    10 25'---1-----------1-00000--0   ->     4 12'000000000010
    385:    10 25'---1-------------10000--0   ->     4 12'000000000010
    386:    10 25'-------------------100--0   ->     5 12'000000000010
    387:    10 25'-------1-------1-00000--0   ->     6 12'000000000010
    388:    10 25'-------1---------10000--0   ->     6 12'000000000010
    389:    10 25'----1----------1-00000--0   ->     7 12'000000000010
    390:    10 25'----1------------10000--0   ->     7 12'000000000010
    391:    10 25'---------------------1--0   ->     8 12'000000000010
    392:    10 25'--1------------1000000--0   ->     9 12'000000000010
    393:    10 25'--1-------------010000--0   ->     9 12'000000000010
    394:    10 25'--1------------1100000--0   ->    10 12'000000000010
    395:    10 25'--------1000-000-00000--0   ->    10 12'000000000010
    396:    10 25'---------100-000-00000--0   ->    10 12'000000000010
    397:    10 25'----------10-000-00000--0   ->    10 12'000000000010
    398:    10 25'-----------1-000-00000--0   ->    10 12'000000000010
    399:    10 25'--------0000--00-00000--0   ->    10 12'000000000010
    400:    10 25'------------0010-00000--0   ->    10 12'000000000010
    401:    10 25'--1-------------110000--0   ->    10 12'000000000010
    402:    10 25'--------------------10--0   ->    10 12'000000000010
    403:    10 25'------------------------1   ->    10 12'000000000010
    404:    10 25'-------------110-00000-10   ->    11 12'000000000010
    405:    10 25'1--------------1-00000--0   ->    11 12'000000000010
    406:    10 25'1----------------10000--0   ->    11 12'000000000010
    407:    10 25'-1-------------1-00000--0   ->    12 12'000000000010
    408:    10 25'-1---------------10000--0   ->    12 12'000000000010
    409:    11 25'-----1---------1000000--0   ->     0 12'000100000000
    410:    11 25'--------1000-100-00000--0   ->     0 12'000100000000
    411:    11 25'---------100-100-00000--0   ->     0 12'000100000000
    412:    11 25'----------10-100-00000--0   ->     0 12'000100000000
    413:    11 25'-----------1-100-00000--0   ->     0 12'000100000000
    414:    11 25'------------1010-00000--0   ->     0 12'000100000000
    415:    11 25'-----1-----------10000--0   ->     0 12'000100000000
    416:    11 25'------------------1000--0   ->     0 12'000100000000
    417:    11 25'-----1---------1100000--0   ->     1 12'000100000000
    418:    11 25'------1--------1-00000--0   ->     2 12'000100000000
    419:    11 25'------1----------10000--0   ->     2 12'000100000000
    420:    11 25'-------------110-00000000   ->     3 12'000100000000
    421:    11 25'-------------110-000001-0   ->     4 12'000100000000
    422:    11 25'---1-----------1-00000--0   ->     4 12'000100000000
    423:    11 25'---1-------------10000--0   ->     4 12'000100000000
    424:    11 25'-------------------100--0   ->     5 12'000100000000
    425:    11 25'-------1-------1-00000--0   ->     6 12'000100000000
    426:    11 25'-------1---------10000--0   ->     6 12'000100000000
    427:    11 25'----1----------1-00000--0   ->     7 12'000100000000
    428:    11 25'----1------------10000--0   ->     7 12'000100000000
    429:    11 25'---------------------1--0   ->     8 12'000100000000
    430:    11 25'--1------------1000000--0   ->     9 12'000100000000
    431:    11 25'--1-------------010000--0   ->     9 12'000100000000
    432:    11 25'--1------------1100000--0   ->    10 12'000100000000
    433:    11 25'--1-------------110000--0   ->    10 12'000100000000
    434:    11 25'-------------110-00000-10   ->    11 12'000100000000
    435:    11 25'--------1000-000-00000--0   ->    11 12'000100000000
    436:    11 25'---------100-000-00000--0   ->    11 12'000100000000
    437:    11 25'----------10-000-00000--0   ->    11 12'000100000000
    438:    11 25'-----------1-000-00000--0   ->    11 12'000100000000
    439:    11 25'--------0000--00-00000--0   ->    11 12'000100000000
    440:    11 25'------------0010-00000--0   ->    11 12'000100000000
    441:    11 25'1--------------1-00000--0   ->    11 12'000100000000
    442:    11 25'1----------------10000--0   ->    11 12'000100000000
    443:    11 25'--------------------10--0   ->    11 12'000100000000
    444:    11 25'------------------------1   ->    11 12'000100000000
    445:    11 25'-1-------------1-00000--0   ->    12 12'000100000000
    446:    11 25'-1---------------10000--0   ->    12 12'000100000000
    447:    12 25'-----1---------1000000--0   ->     0 12'000000010000
    448:    12 25'--------1000-100-00000--0   ->     0 12'000000010000
    449:    12 25'---------100-100-00000--0   ->     0 12'000000010000
    450:    12 25'----------10-100-00000--0   ->     0 12'000000010000
    451:    12 25'-----------1-100-00000--0   ->     0 12'000000010000
    452:    12 25'------------1010-00000--0   ->     0 12'000000010000
    453:    12 25'-----1-----------10000--0   ->     0 12'000000010000
    454:    12 25'------------------1000--0   ->     0 12'000000010000
    455:    12 25'-----1---------1100000--0   ->     1 12'000000010000
    456:    12 25'------1--------1-00000--0   ->     2 12'000000010000
    457:    12 25'------1----------10000--0   ->     2 12'000000010000
    458:    12 25'-------------110-00000000   ->     3 12'000000010000
    459:    12 25'-------------110-000001-0   ->     4 12'000000010000
    460:    12 25'---1-----------1-00000--0   ->     4 12'000000010000
    461:    12 25'---1-------------10000--0   ->     4 12'000000010000
    462:    12 25'-------------------100--0   ->     5 12'000000010000
    463:    12 25'-------1-------1-00000--0   ->     6 12'000000010000
    464:    12 25'-------1---------10000--0   ->     6 12'000000010000
    465:    12 25'----1----------1-00000--0   ->     7 12'000000010000
    466:    12 25'----1------------10000--0   ->     7 12'000000010000
    467:    12 25'---------------------1--0   ->     8 12'000000010000
    468:    12 25'--1------------1000000--0   ->     9 12'000000010000
    469:    12 25'--1-------------010000--0   ->     9 12'000000010000
    470:    12 25'--1------------1100000--0   ->    10 12'000000010000
    471:    12 25'--1-------------110000--0   ->    10 12'000000010000
    472:    12 25'-------------110-00000-10   ->    11 12'000000010000
    473:    12 25'1--------------1-00000--0   ->    11 12'000000010000
    474:    12 25'1----------------10000--0   ->    11 12'000000010000
    475:    12 25'--------1000-000-00000--0   ->    12 12'000000010000
    476:    12 25'---------100-000-00000--0   ->    12 12'000000010000
    477:    12 25'----------10-000-00000--0   ->    12 12'000000010000
    478:    12 25'-----------1-000-00000--0   ->    12 12'000000010000
    479:    12 25'--------0000--00-00000--0   ->    12 12'000000010000
    480:    12 25'------------0010-00000--0   ->    12 12'000000010000
    481:    12 25'-1-------------1-00000--0   ->    12 12'000000010000
    482:    12 25'-1---------------10000--0   ->    12 12'000000010000
    483:    12 25'--------------------10--0   ->    12 12'000000010000
    484:    12 25'------------------------1   ->    12 12'000000010000

-------------------------------------

FSM `$fsm$\Riscado_V.ctrlUnit.aluSrcA$3707' from module `processorci_top':
-------------------------------------

  Information on FSM $fsm$\Riscado_V.ctrlUnit.aluSrcA$3707 (\Riscado_V.ctrlUnit.aluSrcA):

  Number of input signals:   14
  Number of output signals:   3
  Number of state bits:       2

  Input signals:
    0: \Controller.Interpreter.core_reset
    1: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y
    2: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y
    3: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y
    4: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y
    5: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y
    6: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y
    7: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y
    8: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y
    9: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y
   10: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y
   11: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y
   12: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y
   13: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y

  Output signals:
    0: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:123$190_Y
    1: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:122$189_Y
    2: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:121$188_Y

  State encoding:
    0:       2'-1  <RESET STATE>
    1:       2'1-

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 14'---1-000000000   ->     0 3'100
      1:     0 14'---0--00000000   ->     0 3'100
      2:     0 14'----0010000000   ->     0 3'100
      3:     0 14'-----110000000   ->     0 3'100
      4:     0 14'-------1000000   ->     0 3'100
      5:     0 14'--------100000   ->     0 3'100
      6:     0 14'----------1000   ->     0 3'100
      7:     0 14'-----------100   ->     0 3'100
      8:     0 14'------------10   ->     0 3'100
      9:     0 14'-------------1   ->     0 3'100
     10:     0 14'---1-100000000   ->     1 3'100
     11:     0 14'----1010000000   ->     1 3'100
     12:     0 14'---------10000   ->     1 3'100
     13:     1 14'1000-100000000   ->     0 3'001
     14:     1 14'-100-100000000   ->     0 3'001
     15:     1 14'--10-100000000   ->     0 3'001
     16:     1 14'------------10   ->     0 3'001
     17:     1 14'-------------1   ->     0 3'001
     18:     1 14'1000-000000000   ->     1 3'001
     19:     1 14'-100-000000000   ->     1 3'001
     20:     1 14'--10-000000000   ->     1 3'001
     21:     1 14'0000--00000000   ->     1 3'001
     22:     1 14'---1--00000000   ->     1 3'001
     23:     1 14'------10000000   ->     1 3'001
     24:     1 14'-------1000000   ->     1 3'001
     25:     1 14'--------100000   ->     1 3'001
     26:     1 14'---------10000   ->     1 3'001
     27:     1 14'----------1000   ->     1 3'001
     28:     1 14'-----------100   ->     1 3'001

-------------------------------------

FSM `$fsm$\Riscado_V.ctrlUnit.aluSrcB$3712' from module `processorci_top':
-------------------------------------

  Information on FSM $fsm$\Riscado_V.ctrlUnit.aluSrcB$3712 (\Riscado_V.ctrlUnit.aluSrcB):

  Number of input signals:   14
  Number of output signals:   6
  Number of state bits:       6

  Input signals:
    0: \Controller.Interpreter.core_reset
    1: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y
    2: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y
    3: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y
    4: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y
    5: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y
    6: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y
    7: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y
    8: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y
    9: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y
   10: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y
   11: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y
   12: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y
   13: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y

  Output signals:
    0: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$199_Y
    1: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$198_Y
    2: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$197_Y
    3: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$196_Y
    4: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:129$195_Y
    5: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:128$194_Y

  State encoding:
    0:   6'-----1  <RESET STATE>
    1:   6'----1-
    2:   6'---1--
    3:   6'--1---
    4:   6'-1----
    5:   6'1-----

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 14'1000-000000000   ->     0 6'100000
      1:     0 14'-100-000000000   ->     0 6'100000
      2:     0 14'--10-000000000   ->     0 6'100000
      3:     0 14'---1-000000000   ->     0 6'100000
      4:     0 14'0000--00000000   ->     0 6'100000
      5:     0 14'----0010000000   ->     0 6'100000
      6:     0 14'-----110000000   ->     0 6'100000
      7:     0 14'-------1000000   ->     0 6'100000
      8:     0 14'-----------100   ->     0 6'100000
      9:     0 14'------------10   ->     0 6'100000
     10:     0 14'-------------1   ->     0 6'100000
     11:     0 14'---------10000   ->     1 6'100000
     12:     0 14'----------1000   ->     1 6'100000
     13:     0 14'1000-100000000   ->     2 6'100000
     14:     0 14'-100-100000000   ->     3 6'100000
     15:     0 14'--10-100000000   ->     3 6'100000
     16:     0 14'--------100000   ->     3 6'100000
     17:     0 14'---1-100000000   ->     4 6'100000
     18:     0 14'----1010000000   ->     5 6'100000
     19:     1 14'-------1000000   ->     0 6'010000
     20:     1 14'------------10   ->     0 6'010000
     21:     1 14'-------------1   ->     0 6'010000
     22:     1 14'1000-000000000   ->     1 6'010000
     23:     1 14'-100-000000000   ->     1 6'010000
     24:     1 14'--10-000000000   ->     1 6'010000
     25:     1 14'---1-000000000   ->     1 6'010000
     26:     1 14'0000--00000000   ->     1 6'010000
     27:     1 14'----0010000000   ->     1 6'010000
     28:     1 14'-----110000000   ->     1 6'010000
     29:     1 14'---------10000   ->     1 6'010000
     30:     1 14'----------1000   ->     1 6'010000
     31:     1 14'-----------100   ->     1 6'010000
     32:     1 14'1000-100000000   ->     2 6'010000
     33:     1 14'-100-100000000   ->     3 6'010000
     34:     1 14'--10-100000000   ->     3 6'010000
     35:     1 14'--------100000   ->     3 6'010000
     36:     1 14'---1-100000000   ->     4 6'010000
     37:     1 14'----1010000000   ->     5 6'010000
     38:     2 14'-------1000000   ->     0 6'000001
     39:     2 14'------------10   ->     0 6'000001
     40:     2 14'-------------1   ->     0 6'000001
     41:     2 14'---------10000   ->     1 6'000001
     42:     2 14'----------1000   ->     1 6'000001
     43:     2 14'-100-000000000   ->     2 6'000001
     44:     2 14'--10-000000000   ->     2 6'000001
     45:     2 14'---1-000000000   ->     2 6'000001
     46:     2 14'-000--00000000   ->     2 6'000001
     47:     2 14'----0010000000   ->     2 6'000001
     48:     2 14'-----110000000   ->     2 6'000001
     49:     2 14'-----------100   ->     2 6'000001
     50:     2 14'-100-100000000   ->     3 6'000001
     51:     2 14'--10-100000000   ->     3 6'000001
     52:     2 14'--------100000   ->     3 6'000001
     53:     2 14'---1-100000000   ->     4 6'000001
     54:     2 14'----1010000000   ->     5 6'000001
     55:     3 14'-------1000000   ->     0 6'001000
     56:     3 14'------------10   ->     0 6'001000
     57:     3 14'-------------1   ->     0 6'001000
     58:     3 14'---------10000   ->     1 6'001000
     59:     3 14'----------1000   ->     1 6'001000
     60:     3 14'1000-100000000   ->     2 6'001000
     61:     3 14'1000-000000000   ->     3 6'001000
     62:     3 14'---1-000000000   ->     3 6'001000
     63:     3 14'0000--00000000   ->     3 6'001000
     64:     3 14'-100--00000000   ->     3 6'001000
     65:     3 14'--10--00000000   ->     3 6'001000
     66:     3 14'----0010000000   ->     3 6'001000
     67:     3 14'-----110000000   ->     3 6'001000
     68:     3 14'--------100000   ->     3 6'001000
     69:     3 14'-----------100   ->     3 6'001000
     70:     3 14'---1-100000000   ->     4 6'001000
     71:     3 14'----1010000000   ->     5 6'001000
     72:     4 14'-------1000000   ->     0 6'000010
     73:     4 14'------------10   ->     0 6'000010
     74:     4 14'-------------1   ->     0 6'000010
     75:     4 14'---------10000   ->     1 6'000010
     76:     4 14'----------1000   ->     1 6'000010
     77:     4 14'1000-100000000   ->     2 6'000010
     78:     4 14'-100-100000000   ->     3 6'000010
     79:     4 14'--10-100000000   ->     3 6'000010
     80:     4 14'--------100000   ->     3 6'000010
     81:     4 14'1000-000000000   ->     4 6'000010
     82:     4 14'-100-000000000   ->     4 6'000010
     83:     4 14'--10-000000000   ->     4 6'000010
     84:     4 14'0000--00000000   ->     4 6'000010
     85:     4 14'---1--00000000   ->     4 6'000010
     86:     4 14'----0010000000   ->     4 6'000010
     87:     4 14'-----110000000   ->     4 6'000010
     88:     4 14'-----------100   ->     4 6'000010
     89:     4 14'----1010000000   ->     5 6'000010
     90:     5 14'-------1000000   ->     0 6'000100
     91:     5 14'------------10   ->     0 6'000100
     92:     5 14'-------------1   ->     0 6'000100
     93:     5 14'---------10000   ->     1 6'000100
     94:     5 14'----------1000   ->     1 6'000100
     95:     5 14'1000-100000000   ->     2 6'000100
     96:     5 14'-100-100000000   ->     3 6'000100
     97:     5 14'--10-100000000   ->     3 6'000100
     98:     5 14'--------100000   ->     3 6'000100
     99:     5 14'---1-100000000   ->     4 6'000100
    100:     5 14'1000-000000000   ->     5 6'000100
    101:     5 14'-100-000000000   ->     5 6'000100
    102:     5 14'--10-000000000   ->     5 6'000100
    103:     5 14'---1-000000000   ->     5 6'000100
    104:     5 14'0000--00000000   ->     5 6'000100
    105:     5 14'------10000000   ->     5 6'000100
    106:     5 14'-----------100   ->     5 6'000100

-------------------------------------

FSM `$fsm$\Riscado_V.ctrlUnit.readLen$3720' from module `processorci_top':
-------------------------------------

  Information on FSM $fsm$\Riscado_V.ctrlUnit.readLen$3720 (\Riscado_V.ctrlUnit.readLen):

  Number of input signals:   17
  Number of output signals:   2
  Number of state bits:       3

  Input signals:
    0: \Controller.Interpreter.core_reset
    1: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y
    2: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y
    3: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y
    4: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y
    5: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y
    6: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y
    7: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y
    8: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y
    9: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y
   10: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y
   11: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y
   12: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y
   13: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y
   14: $flatten\Riscado_V.\ctrlUnit.$procmux$2918_CMP
   15: $auto$opt_reduce.cc:134:opt_pmux$3657
   16: $auto$opt_reduce.cc:134:opt_pmux$3659

  Output signals:
    0: $flatten\Riscado_V.\ls.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:110$233_Y
    1: $flatten\Riscado_V.\ls.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:111$234_Y

  State encoding:
    0:      3'-1-
    1:      3'--1  <RESET STATE>
    2:      3'1--

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 17'----1000000000000   ->     0 2'01
      1:     0 17'000-1001000000000   ->     0 2'01
      2:     0 17'1---1001000000000   ->     0 2'01
      3:     0 17'---1000-000000000   ->     0 2'01
      4:     0 17'----100-100000000   ->     0 2'01
      5:     0 17'---0000--00000000   ->     0 2'01
      6:     0 17'-----10--00000000   ->     0 2'01
      7:     0 17'------1--00000000   ->     0 2'01
      8:     0 17'---------10000000   ->     0 2'01
      9:     0 17'----------1000000   ->     0 2'01
     10:     0 17'-----------100000   ->     0 2'01
     11:     0 17'------------10000   ->     0 2'01
     12:     0 17'-------------1000   ->     0 2'01
     13:     0 17'--------------100   ->     0 2'01
     14:     0 17'--1-1001000000000   ->     1 2'01
     15:     0 17'---1000-100000000   ->     1 2'01
     16:     0 17'---------------10   ->     1 2'01
     17:     0 17'----------------1   ->     1 2'01
     18:     0 17'-1--1001000000000   ->     2 2'01
     19:     1 17'1---1001000000000   ->     0 2'00
     20:     1 17'----1000000000000   ->     1 2'00
     21:     1 17'000-1001000000000   ->     1 2'00
     22:     1 17'--1-1001000000000   ->     1 2'00
     23:     1 17'----100-100000000   ->     1 2'00
     24:     1 17'----000--00000000   ->     1 2'00
     25:     1 17'-----10--00000000   ->     1 2'00
     26:     1 17'------1--00000000   ->     1 2'00
     27:     1 17'---------10000000   ->     1 2'00
     28:     1 17'----------1000000   ->     1 2'00
     29:     1 17'-----------100000   ->     1 2'00
     30:     1 17'------------10000   ->     1 2'00
     31:     1 17'-------------1000   ->     1 2'00
     32:     1 17'--------------100   ->     1 2'00
     33:     1 17'---------------10   ->     1 2'00
     34:     1 17'----------------1   ->     1 2'00
     35:     1 17'-1--1001000000000   ->     2 2'00
     36:     2 17'1---1001000000000   ->     0 2'10
     37:     2 17'--1-1001000000000   ->     1 2'10
     38:     2 17'---1000-100000000   ->     1 2'10
     39:     2 17'---------------10   ->     1 2'10
     40:     2 17'----------------1   ->     1 2'10
     41:     2 17'----1000000000000   ->     2 2'10
     42:     2 17'000-1001000000000   ->     2 2'10
     43:     2 17'-1--1001000000000   ->     2 2'10
     44:     2 17'---1000-000000000   ->     2 2'10
     45:     2 17'----100-100000000   ->     2 2'10
     46:     2 17'---0000--00000000   ->     2 2'10
     47:     2 17'-----10--00000000   ->     2 2'10
     48:     2 17'------1--00000000   ->     2 2'10
     49:     2 17'---------10000000   ->     2 2'10
     50:     2 17'----------1000000   ->     2 2'10
     51:     2 17'-----------100000   ->     2 2'10
     52:     2 17'------------10000   ->     2 2'10
     53:     2 17'-------------1000   ->     2 2'10
     54:     2 17'--------------100   ->     2 2'10

-------------------------------------

FSM `$fsm$\Riscado_V.ctrlUnit.regDataSrc$3724' from module `processorci_top':
-------------------------------------

  Information on FSM $fsm$\Riscado_V.ctrlUnit.regDataSrc$3724 (\Riscado_V.ctrlUnit.regDataSrc):

  Number of input signals:   13
  Number of output signals:   3
  Number of state bits:       3

  Input signals:
    0: \Controller.Interpreter.core_reset
    1: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y
    2: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y
    3: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y
    4: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y
    5: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y
    6: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y
    7: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y
    8: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y
    9: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y
   10: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y
   11: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y
   12: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y

  Output signals:
    0: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:80$184_Y
    1: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:79$183_Y
    2: $flatten\Riscado_V.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:78$182_Y

  State encoding:
    0:      3'--1
    1:      3'-1-
    2:      3'1--

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 13'1000000000000   ->     0 3'100
      1:     0 13'-100000000000   ->     0 3'100
      2:     0 13'--10000000000   ->     0 3'100
      3:     0 13'---1000000000   ->     0 3'100
      4:     0 13'0000-00000000   ->     0 3'100
      5:     0 13'-----10000000   ->     0 3'100
      6:     0 13'------1000000   ->     0 3'100
      7:     0 13'-------100000   ->     0 3'100
      8:     0 13'--------10000   ->     0 3'100
      9:     0 13'---------1000   ->     0 3'100
     10:     0 13'----------100   ->     0 3'100
     11:     0 13'-----------10   ->     0 3'100
     12:     0 13'------------1   ->     0 3'100
     13:     0 13'--10100000000   ->     1 3'100
     14:     0 13'---1100000000   ->     1 3'100
     15:     0 13'1000100000000   ->     2 3'100
     16:     0 13'-100100000000   ->     2 3'100
     17:     1 13'-----------10   ->     0 3'001
     18:     1 13'1000000000000   ->     1 3'001
     19:     1 13'-100000000000   ->     1 3'001
     20:     1 13'0000-00000000   ->     1 3'001
     21:     1 13'--10-00000000   ->     1 3'001
     22:     1 13'---1-00000000   ->     1 3'001
     23:     1 13'-----10000000   ->     1 3'001
     24:     1 13'------1000000   ->     1 3'001
     25:     1 13'-------100000   ->     1 3'001
     26:     1 13'--------10000   ->     1 3'001
     27:     1 13'---------1000   ->     1 3'001
     28:     1 13'----------100   ->     1 3'001
     29:     1 13'------------1   ->     1 3'001
     30:     1 13'1000100000000   ->     2 3'001
     31:     1 13'-100100000000   ->     2 3'001
     32:     2 13'-----------10   ->     0 3'010
     33:     2 13'--10100000000   ->     1 3'010
     34:     2 13'---1100000000   ->     1 3'010
     35:     2 13'--10000000000   ->     2 3'010
     36:     2 13'---1000000000   ->     2 3'010
     37:     2 13'--00-00000000   ->     2 3'010
     38:     2 13'-----10000000   ->     2 3'010
     39:     2 13'------1000000   ->     2 3'010
     40:     2 13'-------100000   ->     2 3'010
     41:     2 13'--------10000   ->     2 3'010
     42:     2 13'---------1000   ->     2 3'010
     43:     2 13'----------100   ->     2 3'010
     44:     2 13'------------1   ->     2 3'010

-------------------------------------

FSM `$fsm$\Riscado_V.ctrlUnit.state$3729' from module `processorci_top':
-------------------------------------

  Information on FSM $fsm$\Riscado_V.ctrlUnit.state$3729 (\Riscado_V.ctrlUnit.state):

  Number of input signals:   11
  Number of output signals:   6
  Number of state bits:       6

  Input signals:
    0: \Controller.Interpreter.core_reset
    1: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y
    2: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y
    3: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y
    4: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y
    5: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y
    6: $flatten\Riscado_V.\ctrlUnit.$or$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:175$44_Y
    7: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y
    8: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y
    9: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y
   10: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y

  Output signals:
    0: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y
    1: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y
    2: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y
    3: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y
    4: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:187$45_Y
    5: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:307$60_Y

  State encoding:
    0:   6'-----1  <RESET STATE>
    1:   6'----1-
    2:   6'---1--
    3:   6'--1---
    4:   6'-1----
    5:   6'1-----

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 11'----------1   ->     0 6'000001
      1:     0 11'----------0   ->     3 6'000001
      2:     1 11'0000-000000   ->     0 6'010000
      3:     1 11'-100-000000   ->     0 6'010000
      4:     1 11'--10-000000   ->     0 6'010000
      5:     1 11'---1-000000   ->     0 6'010000
      6:     1 11'-----100000   ->     0 6'010000
      7:     1 11'------10000   ->     0 6'010000
      8:     1 11'-------1000   ->     0 6'010000
      9:     1 11'--------100   ->     0 6'010000
     10:     1 11'---------10   ->     0 6'010000
     11:     1 11'----------1   ->     0 6'010000
     12:     1 11'1000-000000   ->     4 6'010000
     13:     2 11'0000-000000   ->     0 6'000100
     14:     2 11'------10000   ->     0 6'000100
     15:     2 11'-------1000   ->     0 6'000100
     16:     2 11'--------100   ->     0 6'000100
     17:     2 11'---------10   ->     0 6'000100
     18:     2 11'----------1   ->     0 6'000100
     19:     2 11'1000-000000   ->     5 6'000100
     20:     2 11'-100-000000   ->     5 6'000100
     21:     2 11'--10-000000   ->     5 6'000100
     22:     2 11'---1-000000   ->     5 6'000100
     23:     2 11'-----100000   ->     5 6'000100
     24:     3 11'----------1   ->     0 6'000010
     25:     3 11'----------0   ->     2 6'000010
     26:     4 11'-000-000000   ->     0 6'100000
     27:     4 11'--10-000000   ->     0 6'100000
     28:     4 11'---1-000000   ->     0 6'100000
     29:     4 11'------10000   ->     0 6'100000
     30:     4 11'-------1000   ->     0 6'100000
     31:     4 11'--------100   ->     0 6'100000
     32:     4 11'---------10   ->     0 6'100000
     33:     4 11'----------1   ->     0 6'100000
     34:     4 11'-100-000000   ->     4 6'100000
     35:     4 11'-----100000   ->     4 6'100000
     36:     5 11'0000-000000   ->     0 6'001000
     37:     5 11'--10-000000   ->     0 6'001000
     38:     5 11'---1-000000   ->     0 6'001000
     39:     5 11'----0100000   ->     0 6'001000
     40:     5 11'------10000   ->     0 6'001000
     41:     5 11'-------1000   ->     0 6'001000
     42:     5 11'--------100   ->     0 6'001000
     43:     5 11'---------10   ->     0 6'001000
     44:     5 11'----------1   ->     0 6'001000
     45:     5 11'1000-000000   ->     1 6'001000
     46:     5 11'-100-000000   ->     1 6'001000
     47:     5 11'----1100000   ->     1 6'001000

-------------------------------------

FSM `$fsm$\Riscado_V.ctrlUnit.writeLen$3737' from module `processorci_top':
-------------------------------------

  Information on FSM $fsm$\Riscado_V.ctrlUnit.writeLen$3737 (\Riscado_V.ctrlUnit.writeLen):

  Number of input signals:   18
  Number of output signals:   2
  Number of state bits:       3

  Input signals:
    0: \Controller.Interpreter.core_reset
    1: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:61$17_Y
    2: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:81$19_Y
    3: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22_Y
    4: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24_Y
    5: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26_Y
    6: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30_Y
    7: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:152$36_Y
    8: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:155$38_Y
    9: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:169$39_Y
   10: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:187$45_Y
   11: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:196$46_Y
   12: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:219$49_Y
   13: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52_Y
   14: $flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56_Y
   15: $flatten\Riscado_V.\ctrlUnit.$procmux$2766_CMP
   16: $flatten\Riscado_V.\ctrlUnit.$procmux$2876_CMP
   17: $flatten\Riscado_V.\ctrlUnit.$procmux$2918_CMP

  Output signals:
    0: $flatten\Riscado_V.\ls.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:88$229_Y
    1: $flatten\Riscado_V.\ls.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:89$230_Y

  State encoding:
    0:      3'-1-
    1:      3'--1  <RESET STATE>
    2:      3'1--

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 18'---100000000000000   ->     0 2'01
      1:     0 18'000100010000000000   ->     0 2'01
      2:     0 18'--1100010000000000   ->     0 2'01
      3:     0 18'---1000-1000000000   ->     0 2'01
      4:     0 18'---1000--100000000   ->     0 2'01
      5:     0 18'---0000---00000000   ->     0 2'01
      6:     0 18'----100---00000000   ->     0 2'01
      7:     0 18'-----10---00000000   ->     0 2'01
      8:     0 18'------1---00000000   ->     0 2'01
      9:     0 18'----------10000000   ->     0 2'01
     10:     0 18'-----------1000000   ->     0 2'01
     11:     0 18'------------100000   ->     0 2'01
     12:     0 18'-------------10000   ->     0 2'01
     13:     0 18'--------------1000   ->     0 2'01
     14:     0 18'---------------100   ->     0 2'01
     15:     0 18'1--100010000000000   ->     1 2'01
     16:     0 18'----------------10   ->     1 2'01
     17:     0 18'-----------------1   ->     1 2'01
     18:     0 18'-1-100010000000000   ->     2 2'01
     19:     1 18'--1100010000000000   ->     0 2'00
     20:     1 18'---100000000000000   ->     1 2'00
     21:     1 18'000100010000000000   ->     1 2'00
     22:     1 18'1--100010000000000   ->     1 2'00
     23:     1 18'---1000-1000000000   ->     1 2'00
     24:     1 18'---1000--100000000   ->     1 2'00
     25:     1 18'---0000---00000000   ->     1 2'00
     26:     1 18'----100---00000000   ->     1 2'00
     27:     1 18'-----10---00000000   ->     1 2'00
     28:     1 18'------1---00000000   ->     1 2'00
     29:     1 18'----------10000000   ->     1 2'00
     30:     1 18'-----------1000000   ->     1 2'00
     31:     1 18'------------100000   ->     1 2'00
     32:     1 18'-------------10000   ->     1 2'00
     33:     1 18'--------------1000   ->     1 2'00
     34:     1 18'---------------100   ->     1 2'00
     35:     1 18'----------------10   ->     1 2'00
     36:     1 18'-----------------1   ->     1 2'00
     37:     1 18'-1-100010000000000   ->     2 2'00
     38:     2 18'--1100010000000000   ->     0 2'10
     39:     2 18'1--100010000000000   ->     1 2'10
     40:     2 18'----------------10   ->     1 2'10
     41:     2 18'-----------------1   ->     1 2'10
     42:     2 18'---100000000000000   ->     2 2'10
     43:     2 18'000100010000000000   ->     2 2'10
     44:     2 18'-1-100010000000000   ->     2 2'10
     45:     2 18'---1000-1000000000   ->     2 2'10
     46:     2 18'---1000--100000000   ->     2 2'10
     47:     2 18'---0000---00000000   ->     2 2'10
     48:     2 18'----100---00000000   ->     2 2'10
     49:     2 18'-----10---00000000   ->     2 2'10
     50:     2 18'------1---00000000   ->     2 2'10
     51:     2 18'----------10000000   ->     2 2'10
     52:     2 18'-----------1000000   ->     2 2'10
     53:     2 18'------------100000   ->     2 2'10
     54:     2 18'-------------10000   ->     2 2'10
     55:     2 18'--------------1000   ->     2 2'10
     56:     2 18'---------------100   ->     2 2'10

-------------------------------------

17.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$3680' from module `\processorci_top'.
Mapping FSM `$fsm$\Controller.Uart.tx_fifo_read_state$3687' from module `\processorci_top'.
Mapping FSM `$fsm$\Riscado_V.ctrlUnit.aluOperation$3693' from module `\processorci_top'.
Mapping FSM `$fsm$\Riscado_V.ctrlUnit.aluSrcA$3707' from module `\processorci_top'.
Mapping FSM `$fsm$\Riscado_V.ctrlUnit.aluSrcB$3712' from module `\processorci_top'.
Mapping FSM `$fsm$\Riscado_V.ctrlUnit.readLen$3720' from module `\processorci_top'.
Mapping FSM `$fsm$\Riscado_V.ctrlUnit.regDataSrc$3724' from module `\processorci_top'.
Mapping FSM `$fsm$\Riscado_V.ctrlUnit.state$3729' from module `\processorci_top'.
Mapping FSM `$fsm$\Riscado_V.ctrlUnit.writeLen$3737' from module `\processorci_top'.

17.13. Executing OPT pass (performing simple optimizations).

17.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~65 debug messages>

17.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~840 debug messages>
Removed a total of 280 cells.

17.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~140 debug messages>

17.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

17.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

17.13.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $flatten\Riscado_V.\pc.$procdff$3568 ($dff) from module processorci_top (D = $flatten\Riscado_V.\pc.$procmux$2539_Y, Q = \Riscado_V.pc.pc, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$5223 ($sdff) from module processorci_top (D = $flatten\Riscado_V.\pc.$procmux$2539_Y, Q = \Riscado_V.pc.pc).
Adding EN signal on $flatten\Riscado_V.\pc.$procdff$3567 ($dff) from module processorci_top (D = $flatten\Riscado_V.\pc.$procmux$2547_Y, Q = \Riscado_V.pc.prevPc).
Adding EN signal on $flatten\Riscado_V.\ctrlUnit.$procdff$3583 ($dff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$2787_Y, Q = \Riscado_V.ctrlUnit.branchTestTrue).
Adding SRST signal on $auto$ff.cc:266:slice$5234 ($dffe) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$2784_Y, Q = \Riscado_V.ctrlUnit.branchTestTrue, rval = 1'0).
Adding SRST signal on $flatten\Riscado_V.\ctrlUnit.$procdff$3581 ($dff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$2907_Y, Q = \Riscado_V.ctrlUnit.readSignExtend, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$5256 ($sdff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$2883_Y, Q = \Riscado_V.ctrlUnit.readSignExtend).
Adding SRST signal on $flatten\Riscado_V.\ctrlUnit.$procdff$3575 ($dff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$3240_Y, Q = \Riscado_V.ctrlUnit.pcWriteEnable, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$5288 ($sdff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$3234_Y, Q = \Riscado_V.ctrlUnit.pcWriteEnable).
Adding SRST signal on $flatten\Riscado_V.\ctrlUnit.$procdff$3574 ($dff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$3287_Y, Q = \Riscado_V.ctrlUnit.regWriteEnable, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$5310 ($sdff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$3284_Y, Q = \Riscado_V.ctrlUnit.regWriteEnable).
Adding SRST signal on $flatten\Riscado_V.\ctrlUnit.$procdff$3572 ($dff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$3347_Y, Q = \Riscado_V.ctrlUnit.incrementPc, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$5326 ($sdff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$3347_Y, Q = \Riscado_V.ctrlUnit.incrementPc).
Adding SRST signal on $flatten\Riscado_V.\ctrlUnit.$procdff$3571 ($dff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$3399_Y, Q = \Riscado_V.ctrlUnit.addressIsPc, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$5330 ($sdff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$3375_Y, Q = \Riscado_V.ctrlUnit.addressIsPc).
Adding EN signal on $flatten\Riscado_V.\ctrlUnit.$procdff$3570 ($dff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$3411_Y, Q = \Riscado_V.ctrlUnit.irWriteEnable).
Adding SRST signal on $auto$ff.cc:266:slice$5364 ($dffe) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$3408_Y, Q = \Riscado_V.ctrlUnit.irWriteEnable, rval = 1'1).
Adding SRST signal on $flatten\Riscado_V.\ctrlUnit.$procdff$3569 ($dff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$3455_Y, Q = \Riscado_V.ctrlUnit.writeEnable, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$5372 ($sdff) from module processorci_top (D = $flatten\Riscado_V.\ctrlUnit.$procmux$3420_Y, Q = \Riscado_V.ctrlUnit.writeEnable).
Adding EN signal on $flatten\Riscado_V.$procdff$3563 ($dff) from module processorci_top (D = \Riscado_V.lsReadDataOut, Q = \Riscado_V.ir).
Adding EN signal on $flatten\ResetBootSystem.$procdff$3562 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter).
Adding EN signal on $flatten\ResetBootSystem.$procdff$3560 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$3504 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1505_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1499_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1490_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1481_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1472_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1463_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1445_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1454_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$5419 ($sdff) from module processorci_top (D = \Controller.Uart.uart_tx_data [7], Q = \Controller.Uart.i_uart_tx.data_to_send [7]).
Adding EN signal on $auto$ff.cc:266:slice$5419 ($sdff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1499_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1490_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1481_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1472_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1463_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1445_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1454_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send [6:0]).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$3502 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1421_Y, Q = \Controller.Uart.i_uart_tx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$5424 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1421_Y, Q = \Controller.Uart.i_uart_tx.bit_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$3501 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1410_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$5430 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1135_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$3500 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_tx.n_fsm_state, Q = \Controller.Uart.i_uart_tx.fsm_state, rval = 3'000).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$3499 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1399_Y, Q = \Controller.Uart.i_uart_tx.txd_reg, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$5435 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1399_Y, Q = \Controller.Uart.i_uart_tx.txd_reg).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$3498 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1388_Y, Q = \Controller.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$5441 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.recieved_data, Q = \Controller.Uart.i_uart_rx.uart_rx_data).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$3497 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_rx.$procmux$1365_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1356_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1347_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1338_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1329_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1320_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1302_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1311_Y }, Q = \Controller.Uart.i_uart_rx.recieved_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$5443 ($sdff) from module processorci_top (D = { \Controller.Uart.i_uart_rx.bit_sample \Controller.Uart.i_uart_rx.recieved_data [7:1] }, Q = \Controller.Uart.i_uart_rx.recieved_data).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$3495 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1284_Y, Q = \Controller.Uart.i_uart_rx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$5447 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1175_Y, Q = \Controller.Uart.i_uart_rx.bit_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$3494 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1279_Y, Q = \Controller.Uart.i_uart_rx.bit_sample, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$5451 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg, Q = \Controller.Uart.i_uart_rx.bit_sample).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$3493 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1271_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$5453 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1186_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$3491 ($dff) from module processorci_top (D = \rx, Q = \Controller.Uart.i_uart_rx.rxd_reg_0, rval = 1'1).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$3490 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg_0, Q = \Controller.Uart.i_uart_rx.rxd_reg, rval = 1'1).
Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$3489 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1248_Y, Q = \Controller.Uart.TX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$5459 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$995_Y [5:0], Q = \Controller.Uart.TX_FIFO.read_ptr).
Adding EN signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$3488 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$992_DATA, Q = \Controller.Uart.TX_FIFO.read_data).
Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$3484 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1243_Y, Q = \Controller.Uart.TX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$5466 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1011_Y [5:0], Q = \Controller.Uart.TX_FIFO.write_ptr).
Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$3489 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1248_Y, Q = \Controller.Uart.RX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$5468 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$995_Y [5:0], Q = \Controller.Uart.RX_FIFO.read_ptr).
Adding EN signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$3488 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$992_DATA, Q = \Controller.Uart.RX_FIFO.read_data).
Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$3484 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1243_Y, Q = \Controller.Uart.RX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$5475 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1011_Y [5:0], Q = \Controller.Uart.RX_FIFO.write_ptr).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$3552 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2419_Y, Q = \Controller.Uart.state_read, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$5477 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2419_Y, Q = \Controller.Uart.state_read).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$3551 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2444_Y, Q = \Controller.Uart.counter_read, rval = 3'000).
Adding EN signal on $auto$ff.cc:266:slice$5481 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2444_Y, Q = \Controller.Uart.counter_read).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$3550 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2408_Y, Q = \Controller.Uart.rx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$3549 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2459_Y, Q = \Controller.Uart.read_data, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$5498 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2457_Y, Q = \Controller.Uart.read_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$3548 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2397_Y, Q = \Controller.Uart.read_response, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$3547 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2341_Y, Q = \Controller.Uart.state_write, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$5505 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2341_Y, Q = \Controller.Uart.state_write).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$3546 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2363_Y, Q = \Controller.Uart.counter_write, rval = 3'000).
Adding EN signal on $auto$ff.cc:266:slice$5509 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2363_Y, Q = \Controller.Uart.counter_write).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$3545 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2377_Y, Q = \Controller.Uart.write_data_buffer, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$5519 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2377_Y, Q = \Controller.Uart.write_data_buffer).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$3544 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2391_Y, Q = \Controller.Uart.tx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$5529 ($sdff) from module processorci_top (D = \Controller.Uart.write_data_buffer [31:24], Q = \Controller.Uart.tx_fifo_write_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$3543 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2323_Y, Q = \Controller.Uart.tx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$3542 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2333_Y, Q = \Controller.Uart.write_response, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$3541 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2314_Y, Q = \Controller.Uart.rx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$5543 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.uart_rx_data, Q = \Controller.Uart.rx_fifo_write_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$3540 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2309_Y, Q = \Controller.Uart.rx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$3538 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2304_Y, Q = \Controller.Uart.uart_tx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$5546 ($sdff) from module processorci_top (D = \Controller.Uart.TX_FIFO.read_data, Q = \Controller.Uart.uart_tx_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$3537 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2280_Y, Q = \Controller.Uart.tx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$3536 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2288_Y, Q = \Controller.Uart.uart_tx_en, rval = 1'0).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$3535 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1827_Y, Q = \Controller.Interpreter.temp_buffer).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3534 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1870_Y, Q = \Controller.Interpreter.accumulator, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$5563 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1870_Y [63:8], Q = \Controller.Interpreter.accumulator [63:8]).
Adding EN signal on $auto$ff.cc:266:slice$5563 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1870_Y [7:0], Q = \Controller.Interpreter.accumulator [7:0]).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3533 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1880_Y, Q = \Controller.Interpreter.timeout_counter, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$5578 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1880_Y, Q = \Controller.Interpreter.timeout_counter).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$3532 ($dff) from module processorci_top (D = { 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, Q = \Controller.Interpreter.timeout).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$3531 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1921_Y, Q = \Controller.Interpreter.read_buffer).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3530 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1949_Y, Q = \Controller.Interpreter.communication_buffer, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$5594 ($sdff) from module processorci_top (D = \Controller.Uart.read_data, Q = \Controller.Interpreter.communication_buffer).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$3529 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1974_Y, Q = \Controller.Interpreter.num_of_positions).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3528 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1996_Y, Q = \Controller.Interpreter.num_of_pages, rval = 24'000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$5605 ($sdff) from module processorci_top (D = \Controller.Interpreter.communication_buffer [31:8], Q = \Controller.Interpreter.num_of_pages).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3527 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2002_Y, Q = \Controller.Interpreter.return_state, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$5607 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2002_Y, Q = \Controller.Interpreter.return_state).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$3526 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2026_Y, Q = \Controller.Interpreter.memory_page_number).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3525 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2034_Y, Q = \Controller.Interpreter.memory_mux_selector, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$5622 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2034_Y, Q = \Controller.Interpreter.memory_mux_selector).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3524 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2074_Y, Q = \Controller.Interpreter.end_position, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$5626 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2074_Y, Q = \Controller.Interpreter.end_position).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3522 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2116_Y, Q = \Controller.Interpreter.bus_mode, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$5630 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2116_Y, Q = \Controller.Interpreter.bus_mode).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3521 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1655_Y, Q = \Controller.Interpreter.reset_bus, rval = 1'1).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$3520 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2127_Y, Q = \Controller.Interpreter.num_of_cycles_to_pulse).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3519 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1760_Y, Q = \Controller.Interpreter.core_reset, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3518 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2137_Y, Q = \Controller.Interpreter.core_clk_enable, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$5643 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2137_Y, Q = \Controller.Interpreter.core_clk_enable).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$3517 ($dff) from module processorci_top (D = \Controller.Interpreter.read_buffer, Q = \Controller.Interpreter.communication_write_data).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3516 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1779_Y, Q = \Controller.Interpreter.communication_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3515 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1802_Y, Q = \Controller.Interpreter.communication_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3514 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1701_Y, Q = \Controller.Interpreter.memory_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3513 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1712_Y, Q = \Controller.Interpreter.write_pulse, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3512 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2213_Y, Q = \Controller.Interpreter.counter, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$5660 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2213_Y, Q = \Controller.Interpreter.counter).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$3511 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2237_Y, Q = \Controller.Interpreter.write_data).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3510 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1555_Y, Q = \Controller.Interpreter.state, rval = 8'00000000).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$3509 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2263_Y, Q = \Controller.Interpreter.address).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$3508 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1679_Y, Q = \Controller.Interpreter.memory_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\ClkDivider.$procdff$3505 ($dff) from module processorci_top (D = $flatten\Controller.\ClkDivider.$procmux$1529_Y, Q = \Controller.ClkDivider.pulse_counter, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$5682 ($sdff) from module processorci_top (D = $flatten\Controller.\ClkDivider.$procmux$1529_Y, Q = \Controller.ClkDivider.pulse_counter).
Adding SRST signal on $flatten\Controller.$procdff$3559 ($dff) from module processorci_top (D = $flatten\Controller.$procmux$2480_Y, Q = \Controller.finish_execution, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$5690 ($sdff) from module processorci_top (D = $flatten\Controller.$procmux$2480_Y, Q = \Controller.finish_execution).
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$5582 ($dffe) from module processorci_top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$5582 ($dffe) from module processorci_top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$5582 ($dffe) from module processorci_top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$5582 ($dffe) from module processorci_top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$5582 ($dffe) from module processorci_top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$5582 ($dffe) from module processorci_top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$5582 ($dffe) from module processorci_top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$5582 ($dffe) from module processorci_top.

17.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 175 unused cells and 534 unused wires.
<suppressed ~176 debug messages>

17.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~38 debug messages>

17.13.9. Rerunning OPT passes. (Maybe there is more to do..)

17.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~113 debug messages>

17.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$5449: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.fsm_state [3:2] \Controller.Uart.i_uart_rx.fsm_state [0] }
  Optimizing cells in module \processorci_top.
Performed a total of 1 changes.

17.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~153 debug messages>
Removed a total of 51 cells.

17.13.13. Executing OPT_DFF pass (perform DFF optimizations).

17.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 1 unused cells and 52 unused wires.
<suppressed ~2 debug messages>

17.13.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

17.13.16. Rerunning OPT passes. (Maybe there is more to do..)

17.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~114 debug messages>

17.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

17.13.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

17.13.20. Executing OPT_DFF pass (perform DFF optimizations).

17.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

17.13.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

17.13.23. Finished OPT passes. (There is nothing left to do.)

17.14. Executing WREDUCE pass (reducing word size of cells).
Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Data_Memory.$auto$proc_memwr.cc:45:proc_memwr$3585 (Controller.Data_Memory.memory).
Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$802 (Controller.Data_Memory.memory).
Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Memory.$auto$proc_memwr.cc:45:proc_memwr$3585 (Controller.Memory.memory).
Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$802 (Controller.Memory.memory).
Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$3584 (Controller.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$992 (Controller.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$3584 (Controller.Uart.TX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$992 (Controller.Uart.TX_FIFO.memory).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$115 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$116 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$117 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$118 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$119 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$120 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$121 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$122 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$123 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$124 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$125 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$126 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$127 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$128 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$129 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$130 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$131 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$132 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$133 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$134 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$135 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$136 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$137 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$138 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$139 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$140 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$141 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$142 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$143 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$144 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$145 (Riscado_V.registerFile.registers).
Removed top 27 address bits (of 32) from memory init port processorci_top.$flatten\Riscado_V.\registerFile.$meminit$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:20$146 (Riscado_V.registerFile.registers).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$3775 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$3761 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$3750 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$5695 ($ne).
Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$5685 ($ne).
Removed top 3 bits (of 18) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$5169 ($eq).
Removed top 1 bits (of 7) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$4949 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1093 ($gt).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:219$1050 ($eq).
Removed top 6 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1054 ($add).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1057 ($add).
Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1066 ($lt).
Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1071 ($eq).
Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1073 ($ge).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1556_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1557_CMP0 ($eq).
Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1559 ($mux).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1561_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1562_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1563_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1564_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1565_CMP0 ($eq).
Removed top 5 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1567 ($mux).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1569_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1570_CMP0 ($eq).
Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1572 ($mux).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1574_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1575_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1579_CMP0 ($eq).
Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1580_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1581_CMP0 ($eq).
Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1583 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1585_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1586_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1587_CMP0 ($eq).
Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1589 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1591_CMP0 ($eq).
Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1593 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1595_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1596_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1597_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1598_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1599_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1600_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1601_CMP0 ($eq).
Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1603 ($mux).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1605_CMP0 ($eq).
Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1607 ($mux).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1609_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1610_CMP0 ($eq).
Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1612 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1614_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1615_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1618_CMP0 ($eq).
Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1617 ($pmux).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1619_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1620_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1621_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1622_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1623_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1624_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1625_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1626_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1627_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1628_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1629_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1630_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1631_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1632_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1633_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1634_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1635_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1636_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1637_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1638_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1639_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1640_CMP0 ($eq).
Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1641_CMP0 ($eq).
Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1643 ($mux).
Removed top 7 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1645_CMP0 ($eq).
Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1647 ($mux).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1681_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1682_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1683_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1716_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1871_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1872_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1873_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1916_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2042_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2075_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2076_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2149_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2150_CMP0 ($eq).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:95$1024 ($lt).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:159$1029 ($lt).
Removed top 1 bits (of 7) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$5295 ($ne).
Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2328_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2334_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2335_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2347_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2349 ($mux).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2398_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2399_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2413_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2421_CMP0 ($eq).
Removed top 3 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2429 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1240 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1228 ($mux).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1012 ($sub).
Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1012 ($sub).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1011 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1010 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$1009 ($eq).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$995 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$994 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$993 ($eq).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1240 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1228 ($mux).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1012 ($sub).
Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1012 ($sub).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1011 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1010 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$1009 ($eq).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$995 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$994 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$993 ($eq).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1164 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:119$1163 ($mux).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1162 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1161 ($mux).
Removed top 2 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:110$1156 ($eq).
Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:108$1154 ($eq).
Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:152$1130 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:137$1122 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:135$1120 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1117 ($ne).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1116 ($ne).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:120$1112 ($eq).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1107 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1106 ($mux).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1105 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1104 ($mux).
Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:94$1100 ($eq).
Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:92$1098 ($eq).
Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Memory.$procmux$2471 ($mux).
Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Data_Memory.$procmux$2471 ($mux).
Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:96$779 ($mux).
Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$763 ($mux).
Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$762 ($mux).
Removed top 3 bits (of 16) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$4715 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$3800 ($eq).
Removed top 1 bits (of 9) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$3828 ($eq).
Removed top 1 bits (of 9) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$5238 ($ne).
Removed top 2 bits (of 10) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$4551 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$5409 ($ne).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Riscado_V.\alu.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:21$5 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Riscado_V.\alu.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:22$7 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Riscado_V.\alu.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:31$15 ($mux).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\Riscado_V.\ls.\br.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:15$208 ($eq).
Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:92$22 ($eq).
Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:102$24 ($eq).
Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:114$26 ($eq).
Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:123$28 ($eq).
Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:133$30 ($eq).
Removed top 5 bits (of 7) from port B of cell processorci_top.$flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:242$52 ($eq).
Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\Riscado_V.\ctrlUnit.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:276$56 ($eq).
Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Riscado_V.\ctrlUnit.$procmux$2876_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Riscado_V.\ctrlUnit.$procmux$2918_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Riscado_V.\ctrlUnit.$procmux$3060_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$5263 ($ne).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Riscado_V.\pc.$add$/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:30$64 ($add).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\ResetBootSystem.$procmux$2497_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$749 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$748 ($add).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$748 ($add).
Removed top 27 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$747 ($lt).
Removed top 20 bits (of 32) from wire processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$762_Y.
Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_ADDR[31:0]$806.
Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1559_Y.
Removed top 5 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1567_Y.
Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1572_Y.
Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1583_Y.
Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1589_Y.
Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1593_Y.
Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1603_Y.
Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1607_Y.
Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1612_Y.
Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1617_Y.
Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1643_Y.
Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1647_Y.
Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$800_ADDR[31:0]$806.
Removed top 1 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2349_Y.
Removed top 3 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2429_Y.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_ADDR[5:0]$997.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_ADDR[5:0]$1006.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$994_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1010_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1011_Y.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_ADDR[5:0]$997.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$987_ADDR[5:0]$1006.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$994_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1010_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$995_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1011_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$748_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Riscado_V.\alu.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:21$5_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Riscado_V.\alu.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:22$7_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Riscado_V.\alu.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:31$15_Y.

17.15. Executing PEEPOPT pass (run peephole optimizers).

17.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 32 unused wires.
<suppressed ~1 debug messages>

17.17. Executing SHARE pass (SAT-based resource sharing).
Found 7 cells in module processorci_top that may be considered for resource sharing.
  Analyzing resource sharing options for $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113 ($memrd):
    Found 13 activation_patterns using ctrl signal { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Controller.Memory.memory_write \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluOperation [12:9] \Riscado_V.ctrlUnit.aluOperation [7:0] \Controller.Interpreter.memory_mux_selector }.
    Found 1 candidates: $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110
    Analyzing resource sharing with $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110 ($memrd):
      Found 12 activation_patterns using ctrl signal { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [12:9] \Riscado_V.ctrlUnit.aluOperation [7:0] }.
      Forbidden control signals for this pair of cells: { $flatten\Riscado_V.\ctrlUnit.$or$/var/jenkins_home/workspace/riscado-v/riscado-v/control_unit.v:175$44_Y $flatten\Riscado_V.\ls.\br.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:14$207_Y $flatten\Riscado_V.\ls.\br.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:15$208_Y $flatten\Riscado_V.\ls.\br.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:16$209_Y $flatten\Riscado_V.\alu.$lt$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:21$4_Y $flatten\Riscado_V.\alu.$lt$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:22$6_Y $flatten\Riscado_V.\alu.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:31$14_Y $flatten\Controller.$eq$/eda/processor-ci-controller/src/controller.v:118$796_Y $flatten\Controller.$logic_or$/eda/processor-ci-controller/src/controller.v:121$799_Y }
      Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluOperation [5] } = 3'011
      Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluOperation [7] } = 3'011
      Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluOperation [9] } = 3'011
      Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluOperation [10] } = 3'011
      Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluOperation [0] } = 3'011
      Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluOperation [12] } = 3'011
      Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluOperation [3] } = 3'011
      Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluOperation [4] } = 3'011
      Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluOperation [11] } = 3'011
      Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluOperation [6] } = 3'011
      Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluOperation [1] } = 3'011
      Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluOperation [2] } = 3'011
      Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$113: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y \Controller.Memory.memory_write \Controller.Interpreter.memory_mux_selector } = 3'011
      Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [12:9] \Riscado_V.ctrlUnit.aluOperation [7:0] } = 14'01000000000000
      Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [0] } = 3'011
      Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [12] } = 3'011
      Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [3] } = 3'011
      Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [4] } = 3'011
      Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [11] } = 3'011
      Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [6] } = 3'011
      Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [7] } = 3'011
      Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [9] } = 3'011
      Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [10] } = 3'011
      Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [1] } = 3'011
      Activation pattern for cell $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [2] } = 3'011
      Size of SAT problem: 0 cells, 189 variables, 727 clauses
      According to the SAT solver this pair of cells can not be shared.
      Model from SAT solver: { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:30$112_Y $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Controller.Memory.memory_write \Riscado_V.ctrlUnit.aluSrcB [0] \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [12:9] \Riscado_V.ctrlUnit.aluOperation [7:0] \Controller.Interpreter.memory_mux_selector } = 18'000110000100000000
  Analyzing resource sharing options for $flatten\Riscado_V.\registerFile.$memrd$\registers$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$110 ($memrd):
    Found 12 activation_patterns using ctrl signal { $flatten\Riscado_V.\registerFile.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/register_file.v:29$109_Y \Riscado_V.ctrlUnit.aluSrcA [0] \Riscado_V.ctrlUnit.aluOperation [12:9] \Riscado_V.ctrlUnit.aluOperation [7:0] }.
    No candidates found.
  Analyzing resource sharing options for $flatten\Riscado_V.\alu.$sshr$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:28$13 ($sshr):
    Found 1 activation_patterns using ctrl signal \Riscado_V.ctrlUnit.aluOperation [10].
    No candidates found.
  Analyzing resource sharing options for $flatten\Riscado_V.\alu.$shr$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:24$9 ($shr):
    Found 1 activation_patterns using ctrl signal \Riscado_V.ctrlUnit.aluOperation [9].
    No candidates found.
  Analyzing resource sharing options for $flatten\Riscado_V.\alu.$shl$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:20$3 ($shl):
    Found 1 activation_patterns using ctrl signal \Riscado_V.ctrlUnit.aluOperation [7].
    No candidates found.
  Analyzing resource sharing options for $flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$802 ($memrd):
    Found 4 activation_patterns using ctrl signal { \Controller.Memory.memory_write \Controller.Memory.memory_read \Riscado_V.ctrlUnit.writeLen [2:1] $flatten\Controller.\Interpreter.$procmux$1599_CMP \Controller.Interpreter.address [31] \Controller.Interpreter.memory_mux_selector }.
    No candidates found.
  Analyzing resource sharing options for $flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$802 ($memrd):
    Found 1 activation_patterns using ctrl signal { \Controller.Data_Memory.memory_read $flatten\Controller.\Interpreter.$procmux$1599_CMP \Controller.Interpreter.address [31] \Controller.Interpreter.memory_mux_selector }.
    No candidates found.

17.18. Executing TECHMAP pass (map to technology primitives).

17.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

17.18.2. Continuing TECHMAP pass.
Using template $paramod$141b0f41d8ab4b936f42c52ead39f1f9a7c93200\_90_lut_cmp_ for cells of type $lt.
No more expansions possible.
<suppressed ~197 debug messages>

17.19. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

17.20. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 6 unused wires.
<suppressed ~1 debug messages>

17.21. Executing TECHMAP pass (map to technology primitives).

17.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.

17.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation.
Generating RTLIL representation for module `\$__MUL18X18'.
Successfully finished Verilog frontend.

17.21.3. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~5 debug messages>

17.22. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module processorci_top:
  creating $macc model for $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1094 ($sub).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1049 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1053 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1054 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1057 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1064 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1068 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1056 ($sub).
  creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1031 ($add).
  creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1026 ($add).
  creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$994 ($add).
  creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1010 ($add).
  creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1012 ($sub).
  creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$994 ($add).
  creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1010 ($add).
  creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1012 ($sub).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1175 ($add).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1186 ($add).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1124 ($add).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1135 ($add).
  creating $macc model for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$748 ($add).
  creating $macc model for $flatten\Riscado_V.\alu.$add$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:19$2 ($add).
  creating $macc model for $flatten\Riscado_V.\alu.$sub$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:27$12 ($sub).
  creating $macc model for $flatten\Riscado_V.\pc.$add$/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:30$64 ($add).
  creating $alu model for $macc $flatten\Riscado_V.\pc.$add$/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:30$64.
  creating $alu model for $macc $flatten\Riscado_V.\alu.$sub$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:27$12.
  creating $alu model for $macc $flatten\Riscado_V.\alu.$add$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:19$2.
  creating $alu model for $macc $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$748.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1135.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1124.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1186.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1175.
  creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1012.
  creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1010.
  creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$994.
  creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1012.
  creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1010.
  creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$994.
  creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1026.
  creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1031.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1056.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1068.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1064.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1057.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1054.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1053.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1049.
  creating $alu model for $macc $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1094.
  creating $alu model for $flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1093 ($gt): new $alu
  creating $alu model for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1073 ($ge): new $alu
  creating $alu model for $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1066 ($lt): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1073.
  creating $alu model for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$747 ($lt): new $alu
  creating $alu model for $flatten\Riscado_V.\alu.$lt$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:21$4 ($lt): new $alu
  creating $alu model for $flatten\Riscado_V.\alu.$lt$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:22$6 ($lt): merged with $flatten\Riscado_V.\alu.$sub$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:27$12.
  creating $alu model for $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1071 ($eq): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1073.
  creating $alu model for $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$749 ($eq): merged with $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$747.
  creating $alu model for $flatten\Riscado_V.\alu.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:31$14 ($eq): merged with $flatten\Riscado_V.\alu.$sub$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:27$12.
  creating $alu cell for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$747, $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$749: $auto$alumacc.cc:485:replace_alu$5739
  creating $alu cell for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1073, $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1066, $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1071: $auto$alumacc.cc:485:replace_alu$5750
  creating $alu cell for $flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1093: $auto$alumacc.cc:485:replace_alu$5763
  creating $alu cell for $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1094: $auto$alumacc.cc:485:replace_alu$5768
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1049: $auto$alumacc.cc:485:replace_alu$5771
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1053: $auto$alumacc.cc:485:replace_alu$5774
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1054: $auto$alumacc.cc:485:replace_alu$5777
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1057: $auto$alumacc.cc:485:replace_alu$5780
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1064: $auto$alumacc.cc:485:replace_alu$5783
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1068: $auto$alumacc.cc:485:replace_alu$5786
  creating $alu cell for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1056: $auto$alumacc.cc:485:replace_alu$5789
  creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1031: $auto$alumacc.cc:485:replace_alu$5792
  creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1026: $auto$alumacc.cc:485:replace_alu$5795
  creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$994: $auto$alumacc.cc:485:replace_alu$5798
  creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1010: $auto$alumacc.cc:485:replace_alu$5801
  creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1012: $auto$alumacc.cc:485:replace_alu$5804
  creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$994: $auto$alumacc.cc:485:replace_alu$5807
  creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1010: $auto$alumacc.cc:485:replace_alu$5810
  creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1012: $auto$alumacc.cc:485:replace_alu$5813
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1175: $auto$alumacc.cc:485:replace_alu$5816
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1186: $auto$alumacc.cc:485:replace_alu$5819
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1124: $auto$alumacc.cc:485:replace_alu$5822
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1135: $auto$alumacc.cc:485:replace_alu$5825
  creating $alu cell for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$748: $auto$alumacc.cc:485:replace_alu$5828
  creating $alu cell for $flatten\Riscado_V.\alu.$lt$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:21$4: $auto$alumacc.cc:485:replace_alu$5831
  creating $alu cell for $flatten\Riscado_V.\alu.$add$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:19$2: $auto$alumacc.cc:485:replace_alu$5838
  creating $alu cell for $flatten\Riscado_V.\alu.$sub$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:27$12, $flatten\Riscado_V.\alu.$lt$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:22$6, $flatten\Riscado_V.\alu.$eq$/var/jenkins_home/workspace/riscado-v/riscado-v/alu.v:31$14: $auto$alumacc.cc:485:replace_alu$5841
  creating $alu cell for $flatten\Riscado_V.\pc.$add$/var/jenkins_home/workspace/riscado-v/riscado-v/program_counter.v:30$64: $auto$alumacc.cc:485:replace_alu$5848
  created 28 $alu and 0 $macc cells.

17.23. Executing OPT pass (performing simple optimizations).

17.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~4 debug messages>

17.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

17.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~114 debug messages>

17.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

17.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

17.23.6. Executing OPT_DFF pass (perform DFF optimizations).

17.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 1 unused cells and 12 unused wires.
<suppressed ~2 debug messages>

17.23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

17.23.9. Rerunning OPT passes. (Maybe there is more to do..)

17.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~114 debug messages>

17.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

17.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

17.23.13. Executing OPT_DFF pass (perform DFF optimizations).

17.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

17.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

17.23.16. Finished OPT passes. (There is nothing left to do.)

17.24. Executing MEMORY pass.

17.24.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

17.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

17.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing processorci_top.Controller.Data_Memory.memory write port 0.
  Analyzing processorci_top.Controller.Memory.memory write port 0.
  Analyzing processorci_top.Controller.Uart.RX_FIFO.memory write port 0.
  Analyzing processorci_top.Controller.Uart.TX_FIFO.memory write port 0.
  Analyzing processorci_top.Riscado_V.registerFile.registers write port 0.

17.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

17.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no output FF found.
Checking read port `\Controller.Memory.memory'[0] in module `\processorci_top': no output FF found.
Checking read port `\Controller.Uart.RX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\Controller.Uart.TX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\Riscado_V.registerFile.registers'[0] in module `\processorci_top': no output FF found.
Checking read port `\Riscado_V.registerFile.registers'[1] in module `\processorci_top': no output FF found.
Checking read port address `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no address FF found.
Checking read port address `\Controller.Memory.memory'[0] in module `\processorci_top': no address FF found.
Checking read port address `\Riscado_V.registerFile.registers'[0] in module `\processorci_top': address FF has fully-defined init value, not supported.
Checking read port address `\Riscado_V.registerFile.registers'[1] in module `\processorci_top': address FF has fully-defined init value, not supported.

17.24.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 2 unused cells and 18 unused wires.
<suppressed ~3 debug messages>

17.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
Consolidating read ports of memory processorci_top.Riscado_V.registerFile.registers by address:

17.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

17.24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

17.24.10. Executing MEMORY_COLLECT pass (generating $mem cells).

17.25. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

17.26. Executing MEMORY_LIBMAP pass (mapping memories to cells).
mapping memory processorci_top.Controller.Data_Memory.memory via $__TRELLIS_DPR16X4_
mapping memory processorci_top.Controller.Memory.memory via $__TRELLIS_DPR16X4_
mapping memory processorci_top.Controller.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of processorci_top.Controller.Uart.RX_FIFO.memory: $\Controller.Uart.RX_FIFO.memory$rdreg[0]
mapping memory processorci_top.Controller.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of processorci_top.Controller.Uart.TX_FIFO.memory: $\Controller.Uart.TX_FIFO.memory$rdreg[0]
mapping memory processorci_top.Riscado_V.registerFile.registers via $__TRELLIS_DPR16X4_
<suppressed ~1170 debug messages>

17.27. Executing TECHMAP pass (map to technology primitives).

17.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.

17.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD_'.
Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'.
Successfully finished Verilog frontend.

17.27.3. Continuing TECHMAP pass.
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
Using template $paramod$23110e440dd343be7ccff453e7838cea1dda03ba\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
No more expansions possible.
<suppressed ~1091 debug messages>

17.28. Executing OPT pass (performing simple optimizations).

17.28.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~180 debug messages>

17.28.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~9 debug messages>
Removed a total of 3 cells.

17.28.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $flatten\ResetBootSystem.$procdff$3561 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state).
Adding SRST signal on $auto$ff.cc:266:slice$5615 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1068_Y, Q = \Controller.Interpreter.memory_page_number, rval = 24'000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$5554 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1827_Y [1:0], Q = \Controller.Interpreter.temp_buffer [1:0]).
Adding SRST signal on $auto$ff.cc:266:slice$5403 ($dffe) from module processorci_top (D = $flatten\ResetBootSystem.$procmux$2494_Y, Q = \ResetBootSystem.counter, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$5224 ($sdffe) from module processorci_top (D = $flatten\Riscado_V.\pc.$procmux$2539_Y [1:0], Q = \Riscado_V.pc.pc [1:0]).

17.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 2 unused cells and 7546 unused wires.
<suppressed ~3 debug messages>

17.28.5. Rerunning OPT passes. (Removed registers in this run.)

17.28.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~10 debug messages>

17.28.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

17.28.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$8285 ($sdffce) from module processorci_top (D = $auto$wreduce.cc:461:run$5727 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000).

17.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 1 unused cells and 9 unused wires.
<suppressed ~2 debug messages>

17.28.10. Rerunning OPT passes. (Removed registers in this run.)

17.28.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

17.28.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

17.28.13. Executing OPT_DFF pass (perform DFF optimizations).

17.28.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

17.28.15. Finished fast OPT passes.

17.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

17.30. Executing OPT pass (performing simple optimizations).

17.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

17.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

17.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~73 debug messages>

17.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$8283: { $auto$opt_dff.cc:194:make_patterns_logic$8280 $auto$fsm_map.cc:74:implement_pattern_cache$3795 $auto$opt_dff.cc:194:make_patterns_logic$5555 $auto$opt_dff.cc:194:make_patterns_logic$5557 }
    Consolidated identical input bits for $mux cell $flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$762:
      Old ports: A=\Controller.core_address_memory [11:0], B={ \Controller.Interpreter.memory_page_number [5:0] \Controller.core_address_memory [5:0] }, Y=$auto$wreduce.cc:461:run$5699 [11:0]
      New ports: A=\Controller.core_address_memory [11:6], B=\Controller.Interpreter.memory_page_number [5:0], Y=$auto$wreduce.cc:461:run$5699 [11:6]
      New connections: $auto$wreduce.cc:461:run$5699 [5:0] = \Controller.core_address_memory [5:0]
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1567:
      Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:461:run$5702 [2:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$5702 [2] $auto$wreduce.cc:461:run$5702 [0] }
      New connections: $auto$wreduce.cc:461:run$5702 [1] = $auto$wreduce.cc:461:run$5702 [0]
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1572:
      Old ports: A=7'1010010, B=7'0010101, Y=$auto$wreduce.cc:461:run$5703 [6:0]
      New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$5703 [1:0]
      New connections: $auto$wreduce.cc:461:run$5703 [6:2] = { $auto$wreduce.cc:461:run$5703 [1] 3'010 $auto$wreduce.cc:461:run$5703 [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1583:
      Old ports: A=4'1100, B=4'0000, Y=$auto$wreduce.cc:461:run$5704 [3:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$5704 [2]
      New connections: { $auto$wreduce.cc:461:run$5704 [3] $auto$wreduce.cc:461:run$5704 [1:0] } = { $auto$wreduce.cc:461:run$5704 [2] 2'00 }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1593:
      Old ports: A=4'1001, B=4'0000, Y=$auto$wreduce.cc:461:run$5706 [3:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$5706 [0]
      New connections: $auto$wreduce.cc:461:run$5706 [3:1] = { $auto$wreduce.cc:461:run$5706 [0] 2'00 }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1607:
      Old ports: A=7'0000110, B=7'1010111, Y=$auto$wreduce.cc:461:run$5708 [6:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$5708 [0]
      New connections: $auto$wreduce.cc:461:run$5708 [6:1] = { $auto$wreduce.cc:461:run$5708 [0] 1'0 $auto$wreduce.cc:461:run$5708 [0] 3'011 }
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$2002:
      Old ports: A=8'00001011, B=302978816, Y=$flatten\Controller.\Interpreter.$procmux$2002_Y
      New ports: A=5'01011, B=20'10010011111011100000, Y=$flatten\Controller.\Interpreter.$procmux$2002_Y [4:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$2002_Y [7:5] = 3'000
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$2127:
      Old ports: A={ 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, B={ 40'0000000000000000000000000001010000000000 \Controller.Interpreter.timeout [23:0] }, Y=$flatten\Controller.\Interpreter.$procmux$2127_Y
      New ports: A=\Controller.Interpreter.communication_buffer [31:8], B={ 24'000000000000000000010100 \Controller.Interpreter.timeout [23:0] }, Y=$flatten\Controller.\Interpreter.$procmux$2127_Y [23:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$2127_Y [31:24] = 8'00000000
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2137: $auto$opt_reduce.cc:134:opt_pmux$3629
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2341:
      Old ports: A=4'0000, B={ 1'0 $auto$wreduce.cc:461:run$5714 [2:0] 12'000100100011 }, Y=$flatten\Controller.\Uart.$procmux$2341_Y
      New ports: A=3'000, B={ $auto$wreduce.cc:461:run$5714 [2:0] 9'001010011 }, Y=$flatten\Controller.\Uart.$procmux$2341_Y [2:0]
      New connections: $flatten\Controller.\Uart.$procmux$2341_Y [3] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2349:
      Old ports: A=3'000, B=3'100, Y=$auto$wreduce.cc:461:run$5714 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$5714 [2]
      New connections: $auto$wreduce.cc:461:run$5714 [1:0] = 2'00
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2425:
      Old ports: A=4'0010, B=4'0100, Y=$flatten\Controller.\Uart.$procmux$2425_Y
      New ports: A=2'01, B=2'10, Y=$flatten\Controller.\Uart.$procmux$2425_Y [2:1]
      New connections: { $flatten\Controller.\Uart.$procmux$2425_Y [3] $flatten\Controller.\Uart.$procmux$2425_Y [0] } = 2'00
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_rx.$procmux$1383:
      Old ports: A=3'000, B={ 2'00 $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1161_Y [0] 1'0 $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1162_Y [1:0] 2'01 \Controller.Uart.i_uart_rx.payload_done 1'0 $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1164_Y [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state
      New ports: A=2'00, B={ 1'0 $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1161_Y [0] $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1162_Y [1:0] 1'1 \Controller.Uart.i_uart_rx.payload_done $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1164_Y [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state [1:0]
      New connections: \Controller.Uart.i_uart_rx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1164:
      Old ports: A=2'11, B=2'00, Y=$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1164_Y [1:0]
      New ports: A=1'1, B=1'0, Y=$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1164_Y [0]
      New connections: $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1164_Y [1] = $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1164_Y [0]
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_tx.$procmux$1520:
      Old ports: A=3'000, B={ 2'00 \Controller.Uart.uart_tx_en 1'0 $flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1105_Y [1:0] 2'01 \Controller.Uart.i_uart_tx.payload_done 1'0 $flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1107_Y [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state
      New ports: A=2'00, B={ 1'0 \Controller.Uart.uart_tx_en $flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1105_Y [1:0] 1'1 \Controller.Uart.i_uart_tx.payload_done $flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1107_Y [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state [1:0]
      New connections: \Controller.Uart.i_uart_tx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1107:
      Old ports: A=2'11, B=2'00, Y=$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1107_Y [1:0]
      New ports: A=1'1, B=1'0, Y=$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1107_Y [0]
      New connections: $flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1107_Y [1] = $flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1107_Y [0]
    New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$2505: { $flatten\ResetBootSystem.$procmux$2498_CMP $flatten\ResetBootSystem.$procmux$2497_CMP }
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2508:
      Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$2508_Y
      New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$2508_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2508_Y [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200:
      Old ports: A=0, B={ \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31:25] \Riscado_V.ir [11:7] }, Y=$flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y
      New ports: A=12'000000000000, B={ \Riscado_V.ir [31:25] \Riscado_V.ir [11:7] }, Y=$flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11:0]
      New connections: $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [31:12] = { $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] }
    Consolidated identical input bits for $mux cell $flatten\Riscado_V.\ls.\br.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:18$213:
      Old ports: A={ 24'000000000000000000000000 \Riscado_V.ls.br.byte }, B={ \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte [7] \Riscado_V.ls.br.byte }, Y=\Riscado_V.ls.byteReadOut
      New ports: A=1'0, B=\Riscado_V.ls.br.byte [7], Y=\Riscado_V.ls.byteReadOut [8]
      New connections: { \Riscado_V.ls.byteReadOut [31:9] \Riscado_V.ls.byteReadOut [7:0] } = { \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.byteReadOut [8] \Riscado_V.ls.br.byte }
    Consolidated identical input bits for $mux cell $flatten\Riscado_V.\ls.\bw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:43$222:
      Old ports: A={ \Riscado_V.ls.writeDataIn [7:0] \Riscado_V.ls.br.dataIn [23:0] }, B={ \Riscado_V.ls.br.dataIn [31:24] \Riscado_V.ls.writeDataIn [7:0] \Riscado_V.ls.br.dataIn [15:0] }, Y=$flatten\Riscado_V.\ls.\bw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:43$222_Y
      New ports: A={ \Riscado_V.ls.writeDataIn [7:0] \Riscado_V.ls.br.dataIn [23:16] }, B={ \Riscado_V.ls.br.dataIn [31:24] \Riscado_V.ls.writeDataIn [7:0] }, Y=$flatten\Riscado_V.\ls.\bw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:43$222_Y [31:16]
      New connections: $flatten\Riscado_V.\ls.\bw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:43$222_Y [15:0] = \Riscado_V.ls.br.dataIn [15:0]
    Consolidated identical input bits for $mux cell $flatten\Riscado_V.\ls.\hr.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:31$218:
      Old ports: A={ 16'0000000000000000 \Riscado_V.ls.hr.half }, B={ \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half [15] \Riscado_V.ls.hr.half }, Y=\Riscado_V.ls.halfReadOut
      New ports: A=1'0, B=\Riscado_V.ls.hr.half [15], Y=\Riscado_V.ls.halfReadOut [16]
      New connections: { \Riscado_V.ls.halfReadOut [31:17] \Riscado_V.ls.halfReadOut [15:0] } = { \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.halfReadOut [16] \Riscado_V.ls.hr.half }
    Consolidated identical input bits for $mux cell $flatten\Riscado_V.\ls.\hw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:54$227:
      Old ports: A={ \Riscado_V.ls.writeDataIn [15:0] \Riscado_V.ls.br.dataIn [15:0] }, B={ \Riscado_V.ls.br.dataIn [31:24] \Riscado_V.ls.writeDataIn [15:0] \Riscado_V.ls.br.dataIn [7:0] }, Y=$flatten\Riscado_V.\ls.\hw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:54$227_Y
      New ports: A={ \Riscado_V.ls.writeDataIn [15:0] \Riscado_V.ls.br.dataIn [15:8] }, B={ \Riscado_V.ls.br.dataIn [31:24] \Riscado_V.ls.writeDataIn [15:0] }, Y=$flatten\Riscado_V.\ls.\hw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:54$227_Y [31:8]
      New connections: $flatten\Riscado_V.\ls.\hw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:54$227_Y [7:0] = \Riscado_V.ls.br.dataIn [7:0]
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2419:
      Old ports: A=4'0000, B={ 3'000 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2425_Y 8'00010011 }, Y=$flatten\Controller.\Uart.$procmux$2419_Y
      New ports: A=3'000, B={ 2'00 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2425_Y [2:1] 7'0001011 }, Y=$flatten\Controller.\Uart.$procmux$2419_Y [2:0]
      New connections: $flatten\Controller.\Uart.$procmux$2419_Y [3] = 1'0
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2514:
      Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$2508_Y, Y=$flatten\ResetBootSystem.$procmux$2514_Y
      New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$2508_Y [1], Y=$flatten\ResetBootSystem.$procmux$2514_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2514_Y [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201:
      Old ports: A=$flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y, B={ \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [19:12] \Riscado_V.ir [20] \Riscado_V.ir [30:21] 1'0 }, Y=$flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y
      New ports: A={ $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:133$200_Y [11:0] }, B={ \Riscado_V.ir [31] \Riscado_V.ir [19:12] \Riscado_V.ir [20] \Riscado_V.ir [30:21] 1'0 }, Y=$flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [20:0]
      New connections: $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [31:21] = { $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [20] }
    Consolidated identical input bits for $mux cell $flatten\Riscado_V.\ls.\bw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:42$223:
      Old ports: A=$flatten\Riscado_V.\ls.\bw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:43$222_Y, B={ \Riscado_V.ls.br.dataIn [31:16] \Riscado_V.ls.writeDataIn [7:0] \Riscado_V.ls.br.dataIn [7:0] }, Y=$flatten\Riscado_V.\ls.\bw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:42$223_Y
      New ports: A={ $flatten\Riscado_V.\ls.\bw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:43$222_Y [31:16] \Riscado_V.ls.br.dataIn [15:8] }, B={ \Riscado_V.ls.br.dataIn [31:16] \Riscado_V.ls.writeDataIn [7:0] }, Y=$flatten\Riscado_V.\ls.\bw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:42$223_Y [31:8]
      New connections: $flatten\Riscado_V.\ls.\bw.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/load_store.v:42$223_Y [7:0] = \Riscado_V.ls.br.dataIn [7:0]
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $mux cell $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202:
      Old ports: A=$flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y, B={ \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [7] \Riscado_V.ir [30:25] \Riscado_V.ir [11:8] 1'0 }, Y=$flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y
      New ports: A=$flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:132$201_Y [20:0], B={ \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [7] \Riscado_V.ir [30:25] \Riscado_V.ir [11:8] 1'0 }, Y=$flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [20:0]
      New connections: $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [31:21] = { $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [20] }
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $mux cell $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203:
      Old ports: A=$flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y, B={ \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31:20] }, Y=$flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y
      New ports: A=$flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:131$202_Y [20:0], B={ \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31] \Riscado_V.ir [31:20] }, Y=$flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y [20:0]
      New connections: $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y [31:21] = { $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y [20] $flatten\Riscado_V.$ternary$/var/jenkins_home/workspace/riscado-v/riscado-v/riscv.v:130$203_Y [20] }
  Optimizing cells in module \processorci_top.
Performed a total of 32 changes.

17.30.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

17.30.6. Executing OPT_DFF pass (perform DFF optimizations).

17.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

17.30.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~1 debug messages>

17.30.9. Rerunning OPT passes. (Maybe there is more to do..)

17.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~75 debug messages>

17.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

17.30.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

17.30.13. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$5434 ($sdff) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$5478 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$5506 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$5608 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$5608 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$5608 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$5635 ($dffe) from module processorci_top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$5635 ($dffe) from module processorci_top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$5635 ($dffe) from module processorci_top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$5635 ($dffe) from module processorci_top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$5635 ($dffe) from module processorci_top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$5635 ($dffe) from module processorci_top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$5635 ($dffe) from module processorci_top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$5635 ($dffe) from module processorci_top.

17.30.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

17.30.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~4 debug messages>

17.30.16. Rerunning OPT passes. (Maybe there is more to do..)

17.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~75 debug messages>

17.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1577:
      Old ports: A=8'00000100, B={ 3'000 \Controller.Interpreter.return_state [4:0] }, Y=$flatten\Controller.\Interpreter.$procmux$1577_Y
      New ports: A=5'00100, B=\Controller.Interpreter.return_state [4:0], Y=$flatten\Controller.\Interpreter.$procmux$1577_Y [4:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$1577_Y [7:5] = 3'000
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$1555:
      Old ports: A=8'00000000, B={ 7'0000000 $auto$wreduce.cc:461:run$5712 [0] 6'000000 $auto$wreduce.cc:461:run$5705 [1:0] 1'0 $auto$wreduce.cc:461:run$5710 [6:0] 14'00001101000011 $auto$wreduce.cc:461:run$5709 [1:0] 3'000 \Controller.Interpreter.return_state [4:0] 1'0 $auto$wreduce.cc:461:run$5708 [6] 1'0 $auto$wreduce.cc:461:run$5708 [6] 3'011 $auto$wreduce.cc:461:run$5708 [6] 7'0000011 \Controller.Uart.read_response 4'0000 $auto$wreduce.cc:461:run$5704 [3] 2'00 $auto$wreduce.cc:461:run$5704 [3] 6'000010 $auto$wreduce.cc:461:run$5705 [1:0] 20'00001000000010110000 $auto$wreduce.cc:461:run$5704 [3] $auto$wreduce.cc:461:run$5704 [3] 18'000000010100000100 $flatten\Controller.\Interpreter.$procmux$1577_Y 1'0 $auto$wreduce.cc:461:run$5703 [6] 3'010 $auto$wreduce.cc:461:run$5703 [2] $auto$wreduce.cc:461:run$5703 [6] $auto$wreduce.cc:461:run$5703 [2] 13'0001001100010 $auto$wreduce.cc:461:run$5702 [2:1] $auto$wreduce.cc:461:run$5702 [1] 31'0001011001010010000100000001000 $auto$wreduce.cc:461:run$5701 [0] 8'00000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1555_Y
      New ports: A=7'0000000, B={ 6'000000 $auto$wreduce.cc:461:run$5712 [0] 5'00000 $auto$wreduce.cc:461:run$5705 [1:0] $auto$wreduce.cc:461:run$5710 [6:0] 12'000110100011 $auto$wreduce.cc:461:run$5709 [1:0] 2'00 \Controller.Interpreter.return_state [4:0] $auto$wreduce.cc:461:run$5708 [6] 1'0 $auto$wreduce.cc:461:run$5708 [6] 3'011 $auto$wreduce.cc:461:run$5708 [6] 6'000011 \Controller.Uart.read_response 3'000 $auto$wreduce.cc:461:run$5704 [3] 2'00 $auto$wreduce.cc:461:run$5704 [3] 5'00010 $auto$wreduce.cc:461:run$5705 [1:0] 17'00010000001011000 $auto$wreduce.cc:461:run$5704 [3] $auto$wreduce.cc:461:run$5704 [3] 18'000000101000010000 $flatten\Controller.\Interpreter.$procmux$1577_Y [4:0] $auto$wreduce.cc:461:run$5703 [6] 3'010 $auto$wreduce.cc:461:run$5703 [2] $auto$wreduce.cc:461:run$5703 [6] $auto$wreduce.cc:461:run$5703 [2] 11'00100110010 $auto$wreduce.cc:461:run$5702 [2:1] $auto$wreduce.cc:461:run$5702 [1] 27'001011010100100010000001000 $auto$wreduce.cc:461:run$5701 [0] 7'0000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1555_Y [6:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$1555_Y [7] = 1'0
  Optimizing cells in module \processorci_top.
Performed a total of 2 changes.

17.30.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

17.30.20. Executing OPT_DFF pass (perform DFF optimizations).

17.30.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

17.30.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

17.30.23. Rerunning OPT passes. (Maybe there is more to do..)

17.30.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~75 debug messages>

17.30.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

17.30.26. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

17.30.27. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$5671 ($sdff) from module processorci_top.

17.30.28. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

17.30.29. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~1 debug messages>

17.30.30. Rerunning OPT passes. (Maybe there is more to do..)

17.30.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~75 debug messages>

17.30.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

17.30.33. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

17.30.34. Executing OPT_DFF pass (perform DFF optimizations).

17.30.35. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

17.30.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

17.30.37. Finished OPT passes. (There is nothing left to do.)

17.31. Executing TECHMAP pass (map to technology primitives).

17.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

17.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ecp5_alu'.
Successfully finished Verilog frontend.

17.31.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $dffe.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $bmux.
Using template $paramod$eaeb96106163dbf82031649d189817109fe07c69\_90_demux for cells of type $demux.
Using template $paramod$824a2ca00d29d886599434cf8ea60471635f2955\_90_demux for cells of type $demux.
Using extmapper simplemap for cells of type $ne.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $lut.
Using extmapper simplemap for cells of type $sdffe.
Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu.
Using template $paramod$c04af8dbf0e5d1d69bbccb2c7bd8a93fc9ef54dc\_80_ecp5_alu for cells of type $alu.
Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ecp5_alu for cells of type $alu.
Using template $paramod$039520c137afc9cd69dd56c3fb11a4e1fbe5f664\_80_ecp5_alu for cells of type $alu.
Using template $paramod$bdc78fe5225b43c64ccdf13e5eb67d9dcf228e8a\_80_ecp5_alu for cells of type $alu.
Using template $paramod$ff467a932a72bec5a93c27dba04bf3daba067451\_80_ecp5_alu for cells of type $alu.
Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu.
Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu.
Using template $paramod$79aa992f2eb7f354d4aaf651790713cf239111fa\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod$c9511eeb847f2aa95252b1013477609463f67ee0\_80_ecp5_alu for cells of type $alu.
Using template $paramod$a7b312e4ba8fdc79d4c5e0789e4e6c41ea3896fb\_90_pmux for cells of type $pmux.
Using template $paramod$7a385d5b7a2e603dbc5beef838648775b433f248\_90_pmux for cells of type $pmux.
Using template $paramod$54a4503cc57b9df40b70c1899504d6aac2650719\_90_pmux for cells of type $pmux.
Using template $paramod$59b03ae2620a41577de8da5f5c97b2919e82362b\_90_pmux for cells of type $pmux.
Using template $paramod$24fb226dd75c9d3f6955ec2ad61d794776778cf6\_90_pmux for cells of type $pmux.
Using template $paramod$cc1e387d9d5ac1d3f6e6bed180038d9c0ac48d0c\_90_pmux for cells of type $pmux.
Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux.
Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $sdff.
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux.
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
Using template $paramod$ac45afa5bcd8e16ca475cce13f9d19bb109f1516\_80_ecp5_alu for cells of type $alu.
Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux.
Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$335cfd09f1afa8139c4aafcbbe5f361887b79c5e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl.
Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu.
Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$feecc7a0dbd012970970f2858f15e786e251f677\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr.
Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$e765c459d3029c22a22a27989e94858fd9ebfa9c\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr.
Using template $paramod$44a13d10af618e7fbe7b9aad2f6151ffcee1e2fa\_80_ecp5_alu for cells of type $alu.
Using template $paramod$ed6389a5938b09f91843a91d67becca5abedb1bd\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $sdffce.
Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux.
Using template $paramod$610911f8769324f781128d641f7fe2120143c328\_80_ecp5_alu for cells of type $alu.
Using template $paramod$2653f68ddb8eab7b1907b4a20767b72a824a7a36\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux.
No more expansions possible.
<suppressed ~5435 debug messages>

17.32. Executing OPT pass (performing simple optimizations).

17.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~11021 debug messages>

17.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~5124 debug messages>
Removed a total of 1708 cells.

17.32.3. Executing OPT_DFF pass (perform DFF optimizations).

17.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 1275 unused cells and 4748 unused wires.
<suppressed ~1281 debug messages>

17.32.5. Finished fast OPT passes.

17.33. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

17.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

17.35. Executing TECHMAP pass (map to technology primitives).

17.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

17.35.2. Continuing TECHMAP pass.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
No more expansions possible.
<suppressed ~920 debug messages>

17.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~102 debug messages>

17.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).

17.38. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in processorci_top.

17.39. Executing ATTRMVCP pass (move or copy attributes).

17.40. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 4432 unused wires.
<suppressed ~1 debug messages>

17.41. Executing TECHMAP pass (map to technology primitives).

17.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

17.41.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>

17.42. Executing ABC9 pass.

17.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

17.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

17.42.3. Executing PROC pass (convert processes to netlists).

17.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$39041'.
Cleaned up 1 empty switch.

17.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$39042 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

17.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

17.42.3.4. Executing PROC_INIT pass (extract init attributes).

17.42.3.5. Executing PROC_ARST pass (detect async resets in processes).

17.42.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

17.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39066'.
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$39042'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$39040_EN[3:0]$39048
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$39040_DATA[3:0]$39047
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$39040_ADDR[3:0]$39046
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$39041'.

17.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

17.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39066'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39026_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39066'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39027_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39066'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39028_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39066'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39032_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39066'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39033_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39066'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39034_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39066'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39038_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39066'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39024_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39066'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39029_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39066'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39036_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39066'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39035_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39066'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39039_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39066'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39030_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39066'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39037_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39066'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39031_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39066'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39025_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39066'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$39040_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$39042'.
  created $dff cell `$procdff$39092' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$39040_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$39042'.
  created $dff cell `$procdff$39093' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$39040_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$39042'.
  created $dff cell `$procdff$39094' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$39041'.
  created direct connection (no actual register cell created).

17.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

17.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39066'.
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$39042'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$39041'.
Cleaned up 1 empty switch.

17.42.3.12. Executing OPT_EXPR pass (perform const folding).

17.42.4. Executing PROC pass (convert processes to netlists).

17.42.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$39112'.
Cleaned up 1 empty switch.

17.42.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$39113 in module $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

17.42.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

17.42.4.4. Executing PROC_INIT pass (extract init attributes).

17.42.4.5. Executing PROC_ARST pass (detect async resets in processes).

17.42.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

17.42.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39137'.
Creating decoders for process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$39113'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$39111_EN[3:0]$39119
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$39111_DATA[3:0]$39117
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$39111_ADDR[3:0]$39118
Creating decoders for process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$39112'.

17.42.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).

17.42.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39108_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39137'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39106_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39137'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39107_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39137'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.\i' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39137'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39099_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39137'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39095_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39137'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39102_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39137'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39096_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39137'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39097_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39137'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39101_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39137'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39098_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39137'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39103_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39137'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39104_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39137'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39109_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39137'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39110_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39137'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39105_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39137'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$39100_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39137'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$39111_DATA' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$39113'.
  created $dff cell `$procdff$39163' with positive edge clock.
Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$39111_ADDR' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$39113'.
  created $dff cell `$procdff$39164' with positive edge clock.
Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$39111_EN' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$39113'.
  created $dff cell `$procdff$39165' with positive edge clock.
Creating register for signal `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.\muxwre' using process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$39112'.
  created direct connection (no actual register cell created).

17.42.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

17.42.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$39137'.
Found and cleaned up 1 empty switch in `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$39113'.
Removing empty process `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$39112'.
Cleaned up 1 empty switch.

17.42.4.12. Executing OPT_EXPR pass (perform const folding).

17.42.5. Executing SCC pass (detecting logic loops).
Found an SCC: $auto$opt_expr.cc:617:replace_const_cells$37793 $auto$ff.cc:266:slice$24066 $auto$ff.cc:479:convert_ce_over_srst$38121 $auto$alumacc.cc:485:replace_alu$5739.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$10707 $auto$simplemap.cc:38:simplemap_not$32739 $auto$ff.cc:266:slice$24067 $auto$ff.cc:479:convert_ce_over_srst$38123 $auto$ff.cc:266:slice$24068 $auto$ff.cc:479:convert_ce_over_srst$38125 $auto$alumacc.cc:485:replace_alu$5739.slice[2].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$10711 $auto$simplemap.cc:126:simplemap_reduce$10708 $auto$simplemap.cc:38:simplemap_not$24731 $auto$ff.cc:266:slice$24069 $auto$ff.cc:479:convert_ce_over_srst$38127 $auto$simplemap.cc:38:simplemap_not$10888 $auto$alumacc.cc:485:replace_alu$5739.slice[4].ccu2c_i $auto$ff.cc:266:slice$24070 $auto$ff.cc:479:convert_ce_over_srst$38129 $auto$simplemap.cc:126:simplemap_reduce$23415 $auto$simplemap.cc:75:simplemap_bitop$15778 $auto$simplemap.cc:126:simplemap_reduce$18306 $auto$simplemap.cc:126:simplemap_reduce$10713 $auto$simplemap.cc:126:simplemap_reduce$10709 $auto$simplemap.cc:38:simplemap_not$32743 $auto$ff.cc:266:slice$24071 $auto$ff.cc:479:convert_ce_over_srst$38131 $auto$simplemap.cc:126:simplemap_reduce$18273 $auto$simplemap.cc:126:simplemap_reduce$18271 $auto$simplemap.cc:126:simplemap_reduce$18309 $auto$simplemap.cc:126:simplemap_reduce$18307 $auto$simplemap.cc:38:simplemap_not$11381
Found an SCC: $auto$opt_expr.cc:617:replace_const_cells$37509 $auto$simplemap.cc:267:simplemap_mux$32708 $auto$simplemap.cc:126:simplemap_reduce$32693 $auto$simplemap.cc:126:simplemap_reduce$32690 $auto$opt_expr.cc:617:replace_const_cells$37493 $auto$ff.cc:266:slice$16565 $auto$simplemap.cc:126:simplemap_reduce$16689 $auto$simplemap.cc:126:simplemap_reduce$16704 $auto$ff.cc:266:slice$16564 $auto$ff.cc:266:slice$16563 $auto$simplemap.cc:267:simplemap_mux$16675 $auto$simplemap.cc:225:simplemap_logbin$16678 $auto$simplemap.cc:196:simplemap_lognot$16693 $auto$simplemap.cc:126:simplemap_reduce$16691 $auto$simplemap.cc:126:simplemap_reduce$16688 $auto$opt_expr.cc:617:replace_const_cells$37495 $auto$simplemap.cc:75:simplemap_bitop$32703 $auto$simplemap.cc:196:simplemap_lognot$16708 $auto$simplemap.cc:126:simplemap_reduce$16706 $auto$simplemap.cc:126:simplemap_reduce$16703 $auto$ff.cc:266:slice$16562 $auto$simplemap.cc:126:simplemap_reduce$18095 $auto$simplemap.cc:126:simplemap_reduce$18093 $auto$simplemap.cc:225:simplemap_logbin$16633 $auto$simplemap.cc:196:simplemap_lognot$16643 $auto$simplemap.cc:126:simplemap_reduce$16641 $auto$opt_expr.cc:617:replace_const_cells$37507 $auto$simplemap.cc:267:simplemap_mux$32707 $auto$simplemap.cc:126:simplemap_reduce$32698 $auto$simplemap.cc:126:simplemap_reduce$32695 $auto$simplemap.cc:75:simplemap_bitop$32706
Found an SCC: $auto$opt_expr.cc:617:replace_const_cells$37361 $auto$ff.cc:266:slice$16400 $auto$opt_expr.cc:617:replace_const_cells$37377 $auto$ff.cc:266:slice$16405 $auto$ff.cc:266:slice$16406 $auto$simplemap.cc:126:simplemap_reduce$16520 $auto$simplemap.cc:126:simplemap_reduce$16547 $auto$opt_expr.cc:617:replace_const_cells$37375 $auto$ff.cc:266:slice$16404 $auto$opt_expr.cc:617:replace_const_cells$37365 $auto$ff.cc:266:slice$16403 $auto$simplemap.cc:126:simplemap_reduce$16523 $auto$simplemap.cc:126:simplemap_reduce$16519 $auto$simplemap.cc:126:simplemap_reduce$16550 $auto$simplemap.cc:126:simplemap_reduce$16546 $auto$opt_expr.cc:617:replace_const_cells$37373 $auto$ff.cc:266:slice$16402 $auto$simplemap.cc:126:simplemap_reduce$16518 $auto$simplemap.cc:126:simplemap_reduce$16545 $auto$opt_expr.cc:617:replace_const_cells$37371 $auto$ff.cc:266:slice$16401 $auto$ff.cc:266:slice$16399 $auto$simplemap.cc:225:simplemap_logbin$16502 $auto$simplemap.cc:196:simplemap_lognot$16529 $auto$simplemap.cc:126:simplemap_reduce$16527 $auto$simplemap.cc:126:simplemap_reduce$16525 $auto$simplemap.cc:126:simplemap_reduce$16522 $auto$simplemap.cc:126:simplemap_reduce$16517 $auto$simplemap.cc:225:simplemap_logbin$16501 $auto$simplemap.cc:196:simplemap_lognot$16556 $auto$simplemap.cc:126:simplemap_reduce$16554 $auto$simplemap.cc:126:simplemap_reduce$16552 $auto$simplemap.cc:126:simplemap_reduce$16549 $auto$simplemap.cc:126:simplemap_reduce$16544 $auto$opt_expr.cc:617:replace_const_cells$37369 $auto$ff.cc:266:slice$16398 $auto$simplemap.cc:167:logic_reduce$10755
Found an SCC: $auto$ff.cc:266:slice$16574 $auto$opt_expr.cc:617:replace_const_cells$37505 $auto$ff.cc:266:slice$16573 $auto$simplemap.cc:126:simplemap_reduce$16726 $auto$opt_expr.cc:617:replace_const_cells$37503 $auto$ff.cc:266:slice$16572 $auto$ff.cc:266:slice$16571 $auto$simplemap.cc:126:simplemap_reduce$16729 $auto$simplemap.cc:126:simplemap_reduce$16725 $auto$opt_expr.cc:617:replace_const_cells$37501 $auto$ff.cc:266:slice$16570 $auto$opt_expr.cc:617:replace_const_cells$37499 $auto$ff.cc:266:slice$16569 $auto$ff.cc:266:slice$16568 $auto$ff.cc:266:slice$16567 $auto$simplemap.cc:126:simplemap_reduce$16723 $auto$opt_expr.cc:617:replace_const_cells$37497 $auto$ff.cc:266:slice$16566 $auto$simplemap.cc:126:simplemap_reduce$17930 $auto$simplemap.cc:196:simplemap_lognot$16735 $auto$simplemap.cc:126:simplemap_reduce$16733 $auto$simplemap.cc:126:simplemap_reduce$16731 $auto$simplemap.cc:126:simplemap_reduce$16728 $auto$simplemap.cc:126:simplemap_reduce$16724
Found 4 SCCs in module processorci_top.
Found 4 SCCs.

17.42.6. Executing ABC9_OPS pass (helper functions for ABC9).

17.42.7. Executing PROC pass (convert processes to netlists).

17.42.7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

17.42.7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

17.42.7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

17.42.7.4. Executing PROC_INIT pass (extract init attributes).

17.42.7.5. Executing PROC_ARST pass (detect async resets in processes).

17.42.7.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

17.42.7.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

17.42.7.8. Executing PROC_DLATCH pass (convert process syncs to latches).

17.42.7.9. Executing PROC_DFF pass (convert process syncs to FFs).

17.42.7.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

17.42.7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

17.42.7.12. Executing OPT_EXPR pass (perform const folding).

17.42.8. Executing TECHMAP pass (map to technology primitives).

17.42.8.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

17.42.8.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~164 debug messages>

17.42.9. Executing OPT pass (performing simple optimizations).

17.42.9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.

17.42.9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

17.42.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

17.42.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
  Optimizing cells in module $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.
Performed a total of 0 changes.

17.42.9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Finding identical cells in module `$paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

17.42.9.6. Executing OPT_DFF pass (perform DFF optimizations).

17.42.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
Finding unused cells or wires in module $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4..

17.42.9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Optimizing module $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.

17.42.9.9. Finished OPT passes. (There is nothing left to do.)

17.42.10. Executing TECHMAP pass (map to technology primitives).

17.42.10.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.

17.42.10.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4 for cells of type $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.
No more expansions possible.
<suppressed ~1064 debug messages>

17.42.11. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.

17.42.12. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

17.42.13. Executing ABC9_OPS pass (helper functions for ABC9).

17.42.14. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

17.42.15. Executing TECHMAP pass (map to technology primitives).

17.42.15.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

17.42.15.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $and.
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~203 debug messages>

17.42.16. Executing OPT pass (performing simple optimizations).

17.42.16.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~18 debug messages>

17.42.16.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

17.42.16.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

17.42.16.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

17.42.16.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

17.42.16.6. Executing OPT_DFF pass (perform DFF optimizations).

17.42.16.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 55 unused wires.
<suppressed ~1 debug messages>

17.42.16.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

17.42.16.9. Rerunning OPT passes. (Maybe there is more to do..)

17.42.16.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

17.42.16.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

17.42.16.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

17.42.16.13. Executing OPT_DFF pass (perform DFF optimizations).

17.42.16.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

17.42.16.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

17.42.16.16. Finished OPT passes. (There is nothing left to do.)

17.42.17. Executing AIGMAP pass (map logic to AIG).
Module processorci_top: replaced 18 cells with 120 new cells, skipped 39 cells.
  replaced 3 cell types:
       2 $_OR_
       2 $_XOR_
      14 $_MUX_
  not replaced 3 cell types:
      31 $specify2
       4 $_NOT_
       4 $_AND_

17.42.18. Executing AIGMAP pass (map logic to AIG).
Module processorci_top: replaced 7956 cells with 50475 new cells, skipped 4840 cells.
  replaced 3 cell types:
    1739 $_OR_
     180 $_XOR_
    6037 $_MUX_
  not replaced 11 cell types:
      11 $print
      21 $scopeinfo
     390 $_NOT_
    1255 $_AND_
     805 TRELLIS_FF
    1028 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4
      32 $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4
    1028 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
      32 $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4_$abc9_byp
     237 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
       1 $__ABC9_SCC_BREAKER

17.42.18.1. Executing ABC9_OPS pass (helper functions for ABC9).

17.42.18.2. Executing ABC9_OPS pass (helper functions for ABC9).

17.42.18.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 21645 AND gates and 63034 wires from module `processorci_top' to a netlist network with 5056 inputs and 1165 outputs.

17.42.18.4. Executing ABC9_EXE pass (technology mapping using ABC9).

17.42.18.5. Executing ABC9.
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_lut <abc-temp-dir>/input.lut 
ABC: + read_box <abc-temp-dir>/input.box 
ABC: + &read <abc-temp-dir>/input.xaig 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   5056/   1165  and =   19868  lev =   58 (6.51)  mem = 0.56 MB  box = 1297  bb = 1060
ABC: Warning: AIG with boxes has internal fanout in 0 complex flops and 1 carries.
ABC: + &scorr 
ABC: Warning: The network is combinational.
ABC: + &sweep 
ABC: + &dc2 
ABC: + &dch -f 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   5056/   1165  and =   25463  lev =   66 (5.20)  mem = 0.62 MB  ch = 2433  box = 1281  bb = 1060
ABC: Warning: AIG with boxes has internal fanout in 0 complex flops and 1 carries.
ABC: + &if -W 300 -v 
ABC: K = 7. Memory (bytes): Truth =    0. Cut =   64. Obj =  148. Set =  672. CutMin = no
ABC: Node =   25463.  Ch =  1812.  Total mem =    7.36 MB. Peak cut mem =    0.33 MB.
ABC: P:  Del = 8689.00.  Ar =   26629.0.  Edge =    30051.  Cut =   330787.  T =     0.16 sec
ABC: P:  Del = 8623.00.  Ar =   26274.0.  Edge =    29441.  Cut =   327186.  T =     0.16 sec
ABC: P:  Del = 8623.00.  Ar =   13765.0.  Edge =    27881.  Cut =   589352.  T =     0.27 sec
ABC: F:  Del = 8616.00.  Ar =    7895.0.  Edge =    22397.  Cut =   516473.  T =     0.24 sec
ABC: A:  Del = 8616.00.  Ar =    6956.0.  Edge =    20018.  Cut =   500089.  T =     0.35 sec
ABC: A:  Del = 8616.00.  Ar =    6862.0.  Edge =    19908.  Cut =   501268.  T =     0.35 sec
ABC: Total time =     1.52 sec
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + &mfs 
ABC: + &ps -l 
ABC: <abc-temp-dir>/input : i/o =   5056/   1165  and =   16085  lev =   51 (5.45)  mem = 0.51 MB  box = 1281  bb = 1060
ABC: Mapping (K=7)  :  lut =   5090  edge =   19764  lev =   17 (2.27)  Boxes are not in a topological order. Switching to level computation without boxes.
ABC: levB =   51  mem = 0.26 MB
ABC: LUT = 5090 : 2=527 10.4 %  3=801 15.7 %  4=2762 54.3 %  5=832 16.3 %  6=77 1.5 %  7=91 1.8 %  Ave = 3.88
ABC: Warning: AIG with boxes has internal fanout in 0 complex flops and 1 carries.
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + time 
ABC: elapse: 15.27 seconds, total: 15.27 seconds

17.42.18.6. Executing AIGER frontend.
<suppressed ~12470 debug messages>
Removed 21461 unused cells and 47766 unused wires.

17.42.18.7. Executing ABC9_OPS pass (helper functions for ABC9).
ABC RESULTS:              $lut cells:     5101
ABC RESULTS:   $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells:     1028
ABC RESULTS:   $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4_$abc9_byp cells:       32
ABC RESULTS:   $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells:      221
ABC RESULTS:           input signals:     1140
ABC RESULTS:          output signals:      235
Removing temp directory.

17.42.19. Executing TECHMAP pass (map to technology primitives).

17.42.19.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.

17.42.19.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4 for cells of type $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4.
Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000000110 for cells of type $__ABC9_SCC_BREAKER.
Using template $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$e65cfc0fa558124bdcdce13f023dbd05639efacd\TRELLIS_DPR16X4_$abc9_byp.
No more expansions possible.
<suppressed ~2363 debug messages>
Removed 400 unused cells and 79127 unused wires.

17.43. Executing TECHMAP pass (map to technology primitives).

17.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

17.43.2. Continuing TECHMAP pass.
Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut.
Using template $paramod$ce56ef3cd635ab10f24c48b829a9c23913bdb858\$lut for cells of type $lut.
Using template $paramod$f3e1547c4b47e64c590e75cf09078b2507c8cc75\$lut for cells of type $lut.
Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5\$lut for cells of type $lut.
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod$6e46ec5a196ba1a24b8e69ab094cadc07c13ac1f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001100 for cells of type $lut.
Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut.
Using template $paramod$e0286d7bdebdb6346cb367bb1962e01892ba2e32\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut.
Using template $paramod$16773ebb5e5d8dbce266b8a86bb4af4574d61ffd\$lut for cells of type $lut.
Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
Using template $paramod$d226e235966975de1e60eb4de35cd0ecd592eea1\$lut for cells of type $lut.
Using template $paramod$b45e5cb971154e30a797eecb0461619c3eeae12d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod$9256a92edc7b95b13cb92b8d69124efbc2dbd89d\$lut for cells of type $lut.
Using template $paramod$cfca0d60a5530b0ba2f6892ecc3e0931abb488df\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
Using template $paramod$6b7c9c56fc2a32a479d463d5f3b0d3f4673b67f1\$lut for cells of type $lut.
Using template $paramod$fc735a6b7ee41acd03b3c70d70e6e1d6f5252226\$lut for cells of type $lut.
Using template $paramod$c6932d0419018208e5384761d78f0ead9bcc772f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut.
Using template $paramod$96fb3234aee435e167d512822a0548b5860ec3b1\$lut for cells of type $lut.
Using template $paramod$70ebb6cf5bc7d63c5c1a98ccefefa2af79e8f2a9\$lut for cells of type $lut.
Using template $paramod$18bae5195eb8a56a96d2430b2583b478653a0cde\$lut for cells of type $lut.
Using template $paramod$b5caae141dfb3c259f904e31e72e1e60d0f53123\$lut for cells of type $lut.
Using template $paramod$dc9c215adf430fe146293bd1a8c0ece29df469f5\$lut for cells of type $lut.
Using template $paramod$b4f15f202f50520dbc381cd0880ac94f830f05a8\$lut for cells of type $lut.
Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut.
Using template $paramod$7ea2352f8f054781a715aeddf3e67f1db65f005a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut.
Using template $paramod$e1e55ea0dbac07f2531370944f065c7d9ae44785\$lut for cells of type $lut.
Using template $paramod$121f66828c71d3c18a58c99e9f44b94525cfca81\$lut for cells of type $lut.
Using template $paramod$2b29ccbd5fb8b9c557f92ddec1023c75686f32ae\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut.
Using template $paramod$90b1db66a6d0166c4e3b5bf5715741db4499a36f\$lut for cells of type $lut.
Using template $paramod$46a9d0e9d20fa7ad6bc1e8e22dc804e878bf1130\$lut for cells of type $lut.
Using template $paramod$a774b09e3178d80116816480d4c5d1b8e087fd6c\$lut for cells of type $lut.
Using template $paramod$e3e4230bb990723642112b292aa705ee0cbad0d4\$lut for cells of type $lut.
Using template $paramod$682dcf7a44e09cdf417bc55247ac658426f4c8e6\$lut for cells of type $lut.
Using template $paramod$b925d358746ccd299742458390d3fa220c31581a\$lut for cells of type $lut.
Using template $paramod$cb3f11b3dc41fb411db0ebc8b103ddb7d046633c\$lut for cells of type $lut.
Using template $paramod$13c0646927d52c588e1b7096a11dadeb3105c279\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001101 for cells of type $lut.
Using template $paramod$00be959c8f2f6b8eefaa3d33cbd6e1a67b2fd5d5\$lut for cells of type $lut.
Using template $paramod$9e354de8d358bf081aa0c089488ea3bc5b7c2fd9\$lut for cells of type $lut.
Using template $paramod$4fb50b041225be6d356d4cb4e00bcdc85b7c4a56\$lut for cells of type $lut.
Using template $paramod$8047a6f809c8770d17fded70c2951e9612e81e83\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110010 for cells of type $lut.
Using template $paramod$0de052767abdccc3aefc818722bdc3c7850d25d6\$lut for cells of type $lut.
Using template $paramod$d1088e62ce917367af6d3bdefd80398c954f4dd8\$lut for cells of type $lut.
Using template $paramod$e01a027fedb28671a20c130493a89c7afd4e87d3\$lut for cells of type $lut.
Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut.
Using template $paramod$4510eba2a677839819a732cbe77f93d08c929cbf\$lut for cells of type $lut.
Using template $paramod$72602303d8c1d2afad52a2a1c8978dbafa8fcbe5\$lut for cells of type $lut.
Using template $paramod$b68f9800cc1bf69afcfbc0567a25e43ebb01456c\$lut for cells of type $lut.
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut.
Using template $paramod$fdf742b1b8ec731910cd575c9aab947a6c0075bf\$lut for cells of type $lut.
Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod$018d71a0fe325d6362687fe53ac13dd6340e400d\$lut for cells of type $lut.
Using template $paramod$19f568890ed784cb1efc3ce1b67eed20a6c54d9a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut.
Using template $paramod$eb90d1e1d5bbf5cfe3ce6d3ea84119ff804f43fc\$lut for cells of type $lut.
Using template $paramod$fadb3223ae6c39e7e595df4dc88cb71a60c971aa\$lut for cells of type $lut.
Using template $paramod$4853050665c020c8d21fb1a749196950a09d9df8\$lut for cells of type $lut.
Using template $paramod$db08fd84fb3c4d6a41eaec6adfffe445fb7eb17f\$lut for cells of type $lut.
Using template $paramod$a6b2d4693fada6bebbe4480262641915d709d280\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
Using template $paramod$5502a85110dbca29ac631107f0b0635e7fade476\$lut for cells of type $lut.
Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut.
Using template $paramod$855b2c1d6931bc7ac39a5e8ecd8eb6e90ffc6baf\$lut for cells of type $lut.
Using template $paramod$1bb26330f94b9f62b6acb8cc6af86c50c7c3906f\$lut for cells of type $lut.
Using template $paramod$a670b08a47dd8a34f954c50cd06e9996d77e8467\$lut for cells of type $lut.
Using template $paramod$cdc5bba2585477f1744fd1f869bebc8beb23d707\$lut for cells of type $lut.
Using template $paramod$e54349d9a634ecff5f53629ed023a0262d334efb\$lut for cells of type $lut.
Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut.
Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut.
Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut.
Using template $paramod$b86b68a00733dbecb31d58a14a13683475a2002a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut.
Using template $paramod$87bca40d761a2c70b8bcdbcfd8f9ddfdab71cae8\$lut for cells of type $lut.
Using template $paramod$992bdc10cff2c6edd722994f0e1044bc863f79f7\$lut for cells of type $lut.
Using template $paramod$2382b0dd4cb27fd4312681c40a6dd179c2a7a26a\$lut for cells of type $lut.
Using template $paramod$78b4324556f6321a85bd440441a5392f271ea218\$lut for cells of type $lut.
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut.
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut.
Using template $paramod$dbdbcb07b9994e498bb1324e5c006c6aa08a7a37\$lut for cells of type $lut.
Using template $paramod$e6a1c13a5bc311f61c57140a3b57bdc80236984a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut.
Using template $paramod$424278221e230ed0676a75e2f35abfaacebd1718\$lut for cells of type $lut.
Using template $paramod$ab5f6cbda813df0763ad05c5e0cfe5a674acf259\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110010 for cells of type $lut.
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut.
Using template $paramod$440c55e9b86a4d19d2d9af4513ac1f3c626292af\$lut for cells of type $lut.
Using template $paramod$de81bb4f24bddd9c01fb4a8d2c0db4e04ac2517e\$lut for cells of type $lut.
Using template $paramod$72b7140785249879ab4c7e8664af3d89d354bf8b\$lut for cells of type $lut.
Using template $paramod$f6237aabc588eff7ee9b4f827dabc5f8e6a972a0\$lut for cells of type $lut.
Using template $paramod$d91785164a7476cce22509b5a5712aa80d820c6b\$lut for cells of type $lut.
Using template $paramod$dc327062330ee79aecc5e2013660e3b5909921a1\$lut for cells of type $lut.
Using template $paramod$02750f8d568bd99efbda01449a05e084a3143ca8\$lut for cells of type $lut.
Using template $paramod$001f44ab3b98ea7dcda3797f287948696b598e6e\$lut for cells of type $lut.
Using template $paramod$ebcc848e253f195d03dbce54cd7714c5e4ce9ad3\$lut for cells of type $lut.
Using template $paramod$a784147b30887ec8848a57709661fdb9cb0d528e\$lut for cells of type $lut.
Using template $paramod$151cc61869e7cf4cf4bd07f6ebd8187604529cbc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut.
Using template $paramod$2caeb761483fdb6a547632a4cc3a2b2e1c966f51\$lut for cells of type $lut.
Using template $paramod$bf06ca3c6121213f9a6ff40836893aeef52fde5a\$lut for cells of type $lut.
Using template $paramod$fd4d03bd5561169aa4c5b1da0079e42da4bc6ba9\$lut for cells of type $lut.
Using template $paramod$1cc8da27f4ac3121850bf00f0b2e489d37556f07\$lut for cells of type $lut.
Using template $paramod$b4286900da1bbbce775d940132d12ee69163aa6e\$lut for cells of type $lut.
Using template $paramod$6bbecc238d553ded483f2323ce76a99b796f10c9\$lut for cells of type $lut.
Using template $paramod$2cb90edbefd7638f92a4216b3809ac8b60fb0f91\$lut for cells of type $lut.
Using template $paramod$f8435c138e960922ed8b709fd7767dbe500c97dc\$lut for cells of type $lut.
Using template $paramod$26425dec57140ed61af01796b72a186668d03c11\$lut for cells of type $lut.
Using template $paramod$9d97d87b86d3f588730de47fd9f36e9d70f98a88\$lut for cells of type $lut.
Using template $paramod$73d3ad4079724b80535c506a091cf6296d7d3490\$lut for cells of type $lut.
Using template $paramod$4d6bebab0ab7c9b76c6ad30bbdaf715044d47fe2\$lut for cells of type $lut.
Using template $paramod$5e52b663d86121ae6bb088f6d7efdfe1f07c8a0e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut.
Using template $paramod$497c7c24933ae65d0e00be74f44fa54a58eb3685\$lut for cells of type $lut.
Using template $paramod$3a7a87113ea3481b3e3776e3b40fed8bddfae17e\$lut for cells of type $lut.
Using template $paramod$9cf976b4f3a576aa2cd6b51304cf5de7fc836fbd\$lut for cells of type $lut.
Using template $paramod$1f6d79798d5d95877d7c39722aefd3ddc609f3cf\$lut for cells of type $lut.
Using template $paramod$b8c12e9f20286ec99dd92b2fd58c920f7e7cec0f\$lut for cells of type $lut.
Using template $paramod$8af87c443b78497491432cb6a477122fa6e8e8b9\$lut for cells of type $lut.
Using template $paramod$8c6722bab578fe45e367ac62205739333ec34098\$lut for cells of type $lut.
Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut.
Using template $paramod$60ce1b6da000f354fdc197a86b56d64ba43488f4\$lut for cells of type $lut.
Using template $paramod$f055bc982b4a866d683b18f8858ce2620b247329\$lut for cells of type $lut.
Using template $paramod$d5769c2d4fabfde4b830b4b57220b17fb0df8d66\$lut for cells of type $lut.
Using template $paramod$e0268bb521b73bd9cfa3422e99d7098a0aa3306f\$lut for cells of type $lut.
Using template $paramod$dc7ab99c1a011e5a4d743f98492bbd8266d6d171\$lut for cells of type $lut.
Using template $paramod$5cf5eb13943a64200bb7dcf3c6f1ffadb3afbe56\$lut for cells of type $lut.
Using template $paramod$9eed22699c2653b52e395b92910215456ca209e1\$lut for cells of type $lut.
Using template $paramod$34d87daed6749540c757e1e7b0f228931508f3d3\$lut for cells of type $lut.
Using template $paramod$1e7784927bf120495b3c5c4fcc2765a9d979d7d5\$lut for cells of type $lut.
Using template $paramod$3575d2ee4e75578324d17c3f3178c31b6cd4f79e\$lut for cells of type $lut.
Using template $paramod$ecc6fffa4441eeec887a2ca7b23afaf2d420a4c7\$lut for cells of type $lut.
Using template $paramod$8972d009849f49cd383b5ffc16bec1a2e573a4ed\$lut for cells of type $lut.
Using template $paramod$085cb83d0db09780ae5aa544a0f286ba9445143f\$lut for cells of type $lut.
Using template $paramod$4981294a7caafabf6d7b76c8e6721c70638ee4c2\$lut for cells of type $lut.
Using template $paramod$2380dcfa48846b0c44a07da45467d8b1ae5c75d7\$lut for cells of type $lut.
Using template $paramod$a8a911473276b59ddac002e64b8cc2467599eec5\$lut for cells of type $lut.
Using template $paramod$17fad009f9a1c08c0da97724737ecb1db74208ff\$lut for cells of type $lut.
Using template $paramod$bb7bed88424f7ff2dfdbd1843ad88d92218bef51\$lut for cells of type $lut.
Using template $paramod$e6b2b3c27bfc83777a6bab018b3e7765669cb66e\$lut for cells of type $lut.
Using template $paramod$9170559509d63481f909ab867c5ab09e64a52a24\$lut for cells of type $lut.
Using template $paramod$a08fe2462bdcdc30db8a81758ff51b6fe69add33\$lut for cells of type $lut.
Using template $paramod$d64fc2a3a3e6d902d5542aa2b7c812b036df829a\$lut for cells of type $lut.
Using template $paramod$1e06da73d21c5736c1f943dd00fdcd4f80e36a2b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
Using template $paramod$2731f51c9112d7289345f502e051a90b73e27fad\$lut for cells of type $lut.
Using template $paramod$36b7d8209200ca95c844934f9e4add2d5121b073\$lut for cells of type $lut.
Using template $paramod$e05e2c71597e2e35c678e58052bd876f12c0b025\$lut for cells of type $lut.
Using template $paramod$3666188b96545248717c2ff7edce939f185fe6fd\$lut for cells of type $lut.
Using template $paramod$d462c1036b159cddae3de55d4cd2ced9cedf9818\$lut for cells of type $lut.
Using template $paramod$1c754ba6cd627f95a67755b75121c1464d98e70e\$lut for cells of type $lut.
Using template $paramod$cee83f16785ece8243b59cc4548900d6dba48f22\$lut for cells of type $lut.
Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut.
Using template $paramod$9344c4025b02204dea933d63914633498911eac3\$lut for cells of type $lut.
Using template $paramod$5a1757302dca122ae37643a838c81088b578ab0d\$lut for cells of type $lut.
Using template $paramod$fbd55d1b12935a22902cde46a0a7b6e309d6aa42\$lut for cells of type $lut.
Using template $paramod$06172e21c36d8a499af1cea1109a56c553bc9d72\$lut for cells of type $lut.
Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod$d7ec878ecfa8f5f7604d3e91692b5d4c2ee758ad\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut.
Using template $paramod$037be5c00d8a02858cdb1ab049b58a0133287ff1\$lut for cells of type $lut.
Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut.
Using template $paramod$adce9c89515a4e83641fc3471eb3c01ec7b082ff\$lut for cells of type $lut.
Using template $paramod$ba7f31f246a278c41fa0648a6e0512f63185dec0\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
Using template $paramod$8963f17916abf131e1c8feafe1b3e52eccc90831\$lut for cells of type $lut.
Using template $paramod$afd7b4c177a33f5eb62789d24240afa93e05edd1\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod$51307cdec77060d17363ea3d60427c9afef1ddc2\$lut for cells of type $lut.
Using template $paramod$332a399730bfc61adea04021a76b1c4e4030f37d\$lut for cells of type $lut.
Using template $paramod$250fbcc6263177ad1751ac3b022a0a4cec921836\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001110 for cells of type $lut.
Using template $paramod$653ed1fca2cbea6092fc92115114dddd9158d22d\$lut for cells of type $lut.
Using template $paramod$74b88973ec1b4011436044ad7d9940531eda196f\$lut for cells of type $lut.
Using template $paramod$00ffcc628ccb870304683cac36ad3a16cc41b6a4\$lut for cells of type $lut.
Using template $paramod$6f9324703e8fcc3b6df2bc2bec54ec19a446ae96\$lut for cells of type $lut.
Using template $paramod$5c6d01824df27a97c3776b3694e8814e23c197cd\$lut for cells of type $lut.
Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut.
Using template $paramod$f23946112f6c4f34470881607086fc6153ffc4c2\$lut for cells of type $lut.
Using template $paramod$11c86b7a6cb6e98dcfb16c5f4d4cc1052b93d8a4\$lut for cells of type $lut.
Using template $paramod$2e9afba29670cc6475874639e7c1b3979c8ebde3\$lut for cells of type $lut.
Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut.
Using template $paramod$8543e1291fe490fb963397fed07c47b1aa2d40cb\$lut for cells of type $lut.
Using template $paramod$ce15874c299a587dd16825ec2d2d2759b547554e\$lut for cells of type $lut.
Using template $paramod$6e4a86e6f1a5dc8f826898a131e83cdba4a4fc9e\$lut for cells of type $lut.
Using template $paramod$89f931611b66d827751f4a175a88569d5ab95376\$lut for cells of type $lut.
Using template $paramod$ab8bb87959c5d7cfa27886cee1355b38e054a61a\$lut for cells of type $lut.
Using template $paramod$8628856e6adeeb85015bfec6f5bd4d2d43863a7b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
Using template $paramod$8ada4d3ba14b06e065cba0eb1f5f6c4325964d32\$lut for cells of type $lut.
Using template $paramod$b9305c669fd883d24574655b402c7ff9f28efb1a\$lut for cells of type $lut.
Using template $paramod$734cd1512f671d92bc4f41153da0d9781801dd98\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111010 for cells of type $lut.
Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d\$lut for cells of type $lut.
Using template $paramod$a47d3f6fd9a7aebdb1b556bc977da3380a17c8cf\$lut for cells of type $lut.
Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut.
Using template $paramod$2de23df76a24087ecc0fa38a78ecc970cd3f2492\$lut for cells of type $lut.
Using template $paramod$4834046533425f54583d6bd31e49deb63455e1a5\$lut for cells of type $lut.
Using template $paramod$515ef3a9b5e42bd5d7533bdf444ebd44fa8b3ff0\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut.
Using template $paramod$d909494d67d7075f17a422f7cb5526f6d6564ea6\$lut for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut.
Using template $paramod$19ad8133454c7f62a97a967a2dc3610da25829e1\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
Using template $paramod$5afdc7428159757eedf89ce514f7efa32b31c8e7\$lut for cells of type $lut.
Using template $paramod$e73a09ed6e8141daa8ce17cef33fa6e84b146f58\$lut for cells of type $lut.
Using template $paramod$37c9af120c85145419565a9ccf4ceb7397fbbe92\$lut for cells of type $lut.
Using template $paramod$9c6e6a10ea00e5b0682f6243b802d7839a398197\$lut for cells of type $lut.
Using template $paramod$5eade7c43026a770e3e647590c1378f4476f00e5\$lut for cells of type $lut.
Using template $paramod$97bfd0f207e3cd11e81dc81c48f8e4fa7fc28966\$lut for cells of type $lut.
Using template $paramod$e8b1383c6901b56df73ac402d78a5e0a42461be0\$lut for cells of type $lut.
Using template $paramod$187b265af118a45b7880d2dcc0524ee2abd6b591\$lut for cells of type $lut.
Using template $paramod$20ba583962918fa0136fc97b1558cc45cc91cc29\$lut for cells of type $lut.
Using template $paramod$01b636f2759ab594c2741266b3c22685988e291c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110010 for cells of type $lut.
Using template $paramod$dc801840eeaf83fdf99128871ec5a9f7070474ca\$lut for cells of type $lut.
Using template $paramod$3a25a8f1460b199f9dbf12b0e9e9b3c7361977cb\$lut for cells of type $lut.
Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut.
Using template $paramod$3360ef9c0b80eff193f2cccb3c940a3180862f3e\$lut for cells of type $lut.
Using template $paramod$e6a488add0b5a2d742e2ae29f62ce7616e04271d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100111 for cells of type $lut.
Using template $paramod$e4b832d686d12318ec0715f027fe549b42e45c20\$lut for cells of type $lut.
Using template $paramod$bcbfb3b09702fd4745ace03c93b2e7969a3187a8\$lut for cells of type $lut.
Using template $paramod$0194c0078616f389ecfa855718b2074839b66531\$lut for cells of type $lut.
Using template $paramod$e277a522d8a930c8c8c8cdb56d33d42914aefec4\$lut for cells of type $lut.
Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5\$lut for cells of type $lut.
Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d\$lut for cells of type $lut.
Using template $paramod$b61e0fdba4a735ed16d21e65fc617fc083973f6d\$lut for cells of type $lut.
Using template $paramod$857512ea84a5fe5464efcd374b77666399ea78e1\$lut for cells of type $lut.
Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut.
Using template $paramod$cdfb4ce36e9b97ab980954e4bd7262833a7086a8\$lut for cells of type $lut.
Using template $paramod$cf93df6a751c015d454aef52e32716809f254f3e\$lut for cells of type $lut.
Using template $paramod$96b88e987a5a94f6555d50cd65fde7a290b148c8\$lut for cells of type $lut.
Using template $paramod$dbd6bfc0079f30bdbd8251243755394b48ae1fbb\$lut for cells of type $lut.
Using template $paramod$902ed43dcaa6101b2d051ad26600288d910a8996\$lut for cells of type $lut.
Using template $paramod$e6062a78edaf68ec0dbea59d4c8352dcb2ce0366\$lut for cells of type $lut.
Using template $paramod$f20ce4917fd5b3c1bb5c623666c4e99ee36747d1\$lut for cells of type $lut.
Using template $paramod$f3d649e8076d16e16e181b135cf4011cee04a458\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110001 for cells of type $lut.
Using template $paramod$4f4b8fc203f5e5f28456abb41eaf0848d148a9cd\$lut for cells of type $lut.
Using template $paramod$f65cf6380214e831938c4f25f730307ae86218f7\$lut for cells of type $lut.
Using template $paramod$238fde728bc553951a83532ddf050daa9aabbfe2\$lut for cells of type $lut.
Using template $paramod$4133fe00eb18442862a284ccc67a95f8194d041c\$lut for cells of type $lut.
Using template $paramod$a8ff24295e45aabda71972c6a839bf0640df5e86\$lut for cells of type $lut.
Using template $paramod$11f892f7697195a9ff54aea2fd70d79ff09abf39\$lut for cells of type $lut.
Using template $paramod$9691bd68f4d2ef2b75c70aa4b21c952828b6b4ec\$lut for cells of type $lut.
Using template $paramod$2646f79d883fe55c6115f3a5c1d9911a69497523\$lut for cells of type $lut.
Using template $paramod$20015ebccbd8f1951705eee2414da34b875c2f3e\$lut for cells of type $lut.
Using template $paramod$20f3f4b8e32f8a8b038b0056872dc94926194798\$lut for cells of type $lut.
Using template $paramod$4a8554d0a765102353ca9705f6a3cc329f4379e7\$lut for cells of type $lut.
Using template $paramod$b40ed8783cd24943f4c31bddb9063d9895eb569a\$lut for cells of type $lut.
Using template $paramod$2955ab75367a3dc9d6f50d3655eebcd4f615031f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut.
Using template $paramod$25003f26a78bb2f583f23824f1e0b8cc16b88761\$lut for cells of type $lut.
Using template $paramod$feac1814a13647ff95d85e23385825c648d6c2ee\$lut for cells of type $lut.
Using template $paramod$c8f16510db975553c8b0be1064e8f5234175f8a8\$lut for cells of type $lut.
Using template $paramod$9506ecf18c91672f3dae4008b6ad1f2863e8019f\$lut for cells of type $lut.
Using template $paramod$488cb1c1ab330d1b6e394717ecf8a4333e6fc4b1\$lut for cells of type $lut.
Using template $paramod$b1680225cc6a5792caa95f54b8b3218fae21705d\$lut for cells of type $lut.
Using template $paramod$41326ad8644342a66dfb051d050f2b6fbf15015b\$lut for cells of type $lut.
Using template $paramod$dcba541ad53a9873d71bfba6c13dc2a8e2a60a79\$lut for cells of type $lut.
Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut.
Using template $paramod$1dbc25919a322e869a77d671bad704787ff253be\$lut for cells of type $lut.
Using template $paramod$db8d333bf66c0cdffe51960a4478272318cfbbaa\$lut for cells of type $lut.
Using template $paramod$694c95659b447cef99dd4cdbd49b87dfd5f6c806\$lut for cells of type $lut.
Using template $paramod$58bd588a49a6a3b9d057d75f907cb4932e1635f6\$lut for cells of type $lut.
Using template $paramod$b2e8d279775d333b39e310bd45fd5952acdde290\$lut for cells of type $lut.
Using template $paramod$2f35f125a78690286f0cd2faecbaee9c64828b65\$lut for cells of type $lut.
Using template $paramod$526e4703e3f9e5bf75da836fd3d4410dd76747a6\$lut for cells of type $lut.
Using template $paramod$ea79e410ad0f4fc3326666c891e1f3992816d636\$lut for cells of type $lut.
Using template $paramod$79a5f4f6c85f6353a05008626bbb50a513afc30e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut.
Using template $paramod$c4fe0d52e4fa3d649d75cb9587992cb08e44f263\$lut for cells of type $lut.
Using template $paramod$06e62c2045624c211a1abe4f2f36c8f22c688165\$lut for cells of type $lut.
Using template $paramod$05f158fdaf927defe0ac9f29c0e78a37e6aee070\$lut for cells of type $lut.
Using template $paramod$baa9d2fb2d21010939721b85aa9f11effe0b53c4\$lut for cells of type $lut.
Using template $paramod$6be53ab59e0a69757fc32adb071ddcb64e8c87b6\$lut for cells of type $lut.
Using template $paramod$91d6743ceb0f093b57d242b538f7f23d2346d4c9\$lut for cells of type $lut.
Using template $paramod$325e90edf97670f9dea57833ae1f51a5e8bcddea\$lut for cells of type $lut.
Using template $paramod$e67f7401ddeed7957ea40cf37767a32ba5d5b941\$lut for cells of type $lut.
Using template $paramod$a4640096cbef09c4ef8613155a589c40164ac034\$lut for cells of type $lut.
Using template $paramod$d508977a36cd39b25dcea83139b05dff7c37e204\$lut for cells of type $lut.
Using template $paramod$e7b36b0d91b09eb7f9bada1b511a39f8367c34ad\$lut for cells of type $lut.
Using template $paramod$8b5edd505331ea1322066a97b8d3ee73c26bc941\$lut for cells of type $lut.
Using template $paramod$95e147e99d454ddd1ee5b79983201f0a8f91ffef\$lut for cells of type $lut.
Using template $paramod$4f0dfe11521b507f619561f0dacc7636582ac20d\$lut for cells of type $lut.
Using template $paramod$3135514bcd40c6151e06ec7025dd49ca534b3bc4\$lut for cells of type $lut.
Using template $paramod$1d4b814988bc68a0b6b4daeea72aefc56af2a292\$lut for cells of type $lut.
Using template $paramod$44a6586fa21c1d277ba2728177750c6c473bb6e3\$lut for cells of type $lut.
Using template $paramod$66658cbed86a8310f9b7ba1190d35eff90ee749b\$lut for cells of type $lut.
Using template $paramod$6d345a2b13b18cce8571c208f108ba6011b422aa\$lut for cells of type $lut.
Using template $paramod$8614da24b3846fe751594d00fba789cfcb7b874c\$lut for cells of type $lut.
Using template $paramod$800ad51c173ef1531dc8c2197ac409be85e8cb0a\$lut for cells of type $lut.
Using template $paramod$712505941a295086314c22735153725461a87f4a\$lut for cells of type $lut.
Using template $paramod$2ec6422db00d358fc7469efce6208bffbc8521cd\$lut for cells of type $lut.
Using template $paramod$03032dc5e55252b7d85660ddcfab95c7ce1807d9\$lut for cells of type $lut.
Using template $paramod$4fc6efaec5bd8994232500ce8f8be9cb357522d5\$lut for cells of type $lut.
Using template $paramod$8e076ba68a9eb05bf3e9651a526c69f58c0fa542\$lut for cells of type $lut.
Using template $paramod$485f88f1ce5bc0269fe39659f0704d8295854137\$lut for cells of type $lut.
Using template $paramod$b4e9ea3921e02bce0d630933f106608ba1bed76e\$lut for cells of type $lut.
Using template $paramod$873ea1d40ce9a0dc205e85e3af45871f73c851d7\$lut for cells of type $lut.
Using template $paramod$32abbd1d449a67fb913b4733374e345d4c17175b\$lut for cells of type $lut.
Using template $paramod$f546bd96bcec6e3bf1b78bdea64b0f5bbbaff6df\$lut for cells of type $lut.
Using template $paramod$d578a6cbd267f4547d216fd6590de950269b4e70\$lut for cells of type $lut.
Using template $paramod$42ba6cdeb0da25e705e5f725e83196149243f1e3\$lut for cells of type $lut.
Using template $paramod$83651bb404549d04911ccbf5b5544d55051b31c3\$lut for cells of type $lut.
Using template $paramod$068092ddede495d8462ffe530e6d91711913edbc\$lut for cells of type $lut.
Using template $paramod$7bcb80c1884d745e7d262a6ef25071cdabb1869a\$lut for cells of type $lut.
Using template $paramod$08731891a7ba47af170a108a660b6a0a9bb30fb9\$lut for cells of type $lut.
Using template $paramod$e00ff85da7896355acb0b5a7f085b5b3c7149d92\$lut for cells of type $lut.
Using template $paramod$df29fe9e6d6d694a9cc5697e4251bf7d8cd4d8e4\$lut for cells of type $lut.
Using template $paramod$89383f3d9c6981db274fd4b17de891c73a3414cc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101101 for cells of type $lut.
Using template $paramod$c66e7b215e6f80c1915bda1df6f2ae95d0bda68c\$lut for cells of type $lut.
Using template $paramod$a5d5c745abad930299600272e8260a256cf53240\$lut for cells of type $lut.
Using template $paramod$8c14e6d85060218e346675600ae1194fdf5a803e\$lut for cells of type $lut.
Using template $paramod$bbf8d2391d746c2af3dbc28034fca9f58de66064\$lut for cells of type $lut.
Using template $paramod$02f222530db39a8a31d75f48a5f0ca4b0932388c\$lut for cells of type $lut.
Using template $paramod$5ea104ff2da46cfad97c205d53e744ebf03f5b3d\$lut for cells of type $lut.
Using template $paramod$f69f26d871b1713139ee8403a3eecd547f86cddc\$lut for cells of type $lut.
Using template $paramod$b34f0e72bf5675ebb8f7a9ba088658d5c50a0625\$lut for cells of type $lut.
Using template $paramod$291c7d966491d437de39032efb1d7155830a4d6a\$lut for cells of type $lut.
Using template $paramod$29bc9d4af96d11f5388d5af18ed3c3e2e3c82fb6\$lut for cells of type $lut.
Using template $paramod$688854e562fccd949c644aa392a22c5c1aae8484\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut.
Using template $paramod$3ec53e812e56e3a6694e2062d36c6d66c39c4f54\$lut for cells of type $lut.
Using template $paramod$e53fc24d412e590742f6d50628e8f1111ab8f2e3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut.
Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut.
Using template $paramod$7f4670b933e9d0d313fe2dbe752fa82b1cf04d5c\$lut for cells of type $lut.
Using template $paramod$f6bad0c59ab167149c1805436d46cf42ed9a1b1b\$lut for cells of type $lut.
Using template $paramod$f503ae6dd13af4ce255f26a38c5b2bb42d3444fc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111011 for cells of type $lut.
Using template $paramod$ac7616b2cacec1d9afcf01db7702b3bf58101dac\$lut for cells of type $lut.
Using template $paramod$a4bbe892a28ec0471eac4c548ab7ee6abbaf1e36\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut.
Using template $paramod$adb84e058b0f32ce56f004e6ffa19883ace75fc0\$lut for cells of type $lut.
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut.
Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut.
Using template $paramod$71039eaa750b63c13b47d102108a4d1b67d00b7c\$lut for cells of type $lut.
Using template $paramod$3d7168c8134c4765b84a7b86d5ef7e1e65bbf4a0\$lut for cells of type $lut.
Using template $paramod$86cd99a42d2aa92b63304646658399230f8f28bb\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011101 for cells of type $lut.
Using template $paramod$9a383ca297ef012b6f33ce559547f89432250d88\$lut for cells of type $lut.
Using template $paramod$beae4210b922fc9ba2fcc4008a7474b475e38c50\$lut for cells of type $lut.
Using template $paramod$f9a0078410fd30726e07234e1fe5dcfa55aae7d5\$lut for cells of type $lut.
Using template $paramod$14411b3f8a4e7a1eda5bedee4af5cb3472abde0d\$lut for cells of type $lut.
Using template $paramod$eaea85d27cc0950ed001348e061727a194f5cf9c\$lut for cells of type $lut.
Using template $paramod$2d70e360329f2b83357618532825d0cf30a325f3\$lut for cells of type $lut.
Using template $paramod$3a0a392069bc969f34c65c546a8c56fbbb67e282\$lut for cells of type $lut.
Using template $paramod$faba0cf60f1c89602d59ba2d491152c8f0d36384\$lut for cells of type $lut.
Using template $paramod$099af7f70fcc70b41da4ec1f8df6dd0abf473cb5\$lut for cells of type $lut.
Using template $paramod$9cc51547ab44a72dd506ee5bb84a864365a103da\$lut for cells of type $lut.
Using template $paramod$707701b498a5cd123a043548b93e61e0b6bdc440\$lut for cells of type $lut.
Using template $paramod$7e8d331d1e06632d29fbdf6c3afc2de1856d3c67\$lut for cells of type $lut.
Using template $paramod$ab187b3361de42517771e043d17e1a21d175a6f9\$lut for cells of type $lut.
Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut.
Using template $paramod$ee5364a8a73752d26afd1567c264a554d6d45936\$lut for cells of type $lut.
Using template $paramod$f48d7786c1cf296347ee1d181136f09f8dd6d358\$lut for cells of type $lut.
Using template $paramod$a52434fdf58f77272788520e71716cca8dda77c0\$lut for cells of type $lut.
Using template $paramod$af574ac083faf8d8036edb1d34eb40d28d20ac3a\$lut for cells of type $lut.
Using template $paramod$3f8bddb26a8905ea147acf4247acf6d000ca20f7\$lut for cells of type $lut.
Using template $paramod$18150bd82850d68594c76ffc4c752360fabfb01c\$lut for cells of type $lut.
Using template $paramod$24c187f5d3485046bae75ae1936fe59cc94ba68b\$lut for cells of type $lut.
Using template $paramod$9de64a00ba0a4210856b2bfe0a12c1975f49ed7b\$lut for cells of type $lut.
Using template $paramod$4dbc0593c01c210dafad30629f5bdd8171b52184\$lut for cells of type $lut.
Using template $paramod$aeb27cd9efe624def2282ecf09671da132bf31e8\$lut for cells of type $lut.
Using template $paramod$07584341de7cccc8753a4905af6265c6a1387e92\$lut for cells of type $lut.
Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut.
Using template $paramod$2eafbbb6c23646832088b9e1d844a44c4d20bfc2\$lut for cells of type $lut.
Using template $paramod$b53357ee6fde5ef3078cb0414ab34f9bac50e1b4\$lut for cells of type $lut.
Using template $paramod$2a71eb927b26dd23378b94eb5ee3cdded6a71652\$lut for cells of type $lut.
Using template $paramod$07029e33c04696d66701875080b7ce0ecdb15d52\$lut for cells of type $lut.
Using template $paramod$1a585ab1b06d77b10a630aa9fac0cbab46b59dff\$lut for cells of type $lut.
Using template $paramod$f610396a8c1614f373f4d73e3d1e988bc93e396c\$lut for cells of type $lut.
Using template $paramod$d21d214a5aa271f2d9da3f90f22432c0ecee130f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
Using template $paramod$e0e0b9515c7031ae11155409478b65d3742b804e\$lut for cells of type $lut.
Using template $paramod$c07d61aaf1d93e15249de987e8fd0ca391dbd52a\$lut for cells of type $lut.
Using template $paramod$ac1b1b649e5fc8d9373ff3c8e90156a2d5f30a46\$lut for cells of type $lut.
Using template $paramod$51a556a57b01d5a1f80d9dd10539eeb2bbc1b2bb\$lut for cells of type $lut.
Using template $paramod$5e904ac3515b06e537d9f8f841b5ec9a9e0179d2\$lut for cells of type $lut.
Using template $paramod$e80686e6a456634e4612e7ab0ee0f4485f5433ad\$lut for cells of type $lut.
Using template $paramod$004d209e4d2763c7851b945acd5d2f9415eb6f4b\$lut for cells of type $lut.
Using template $paramod$c3e9404bbee96227485bbf320e921a029449f50a\$lut for cells of type $lut.
Using template $paramod$7c085cdbf0919cd3ad402d9495d97f0d71e4db93\$lut for cells of type $lut.
Using template $paramod$d58395840ef3a83a79a663d9644929fc235dc99e\$lut for cells of type $lut.
Using template $paramod$59f2a3e232df3029c8bc36978b9bbe72a71dfb5a\$lut for cells of type $lut.
Using template $paramod$94590782de849ac3f1512d9a660ffcf1af2ef7f6\$lut for cells of type $lut.
Using template $paramod$e8795183b442cf032e09fd3892efce7a55f2177d\$lut for cells of type $lut.
Using template $paramod$e332cff882edd417f410bab5fe07a0f88572cce3\$lut for cells of type $lut.
Using template $paramod$c08a774c89ef1ea6ee2ef4d8c3b071eb141d4259\$lut for cells of type $lut.
Using template $paramod$27190b166827ead7a5b229ee873e4b91ee0faf61\$lut for cells of type $lut.
Using template $paramod$1114d560ed98e9182fe073c9893577168d869f6b\$lut for cells of type $lut.
Using template $paramod$003792e368661cf56a14aaaad6379250866ab2f3\$lut for cells of type $lut.
Using template $paramod$4b2297966ddb718657b80566604f97685ffc0120\$lut for cells of type $lut.
Using template $paramod$32ccf65669c41e1e3bce1f16051f6d60ad96a2a0\$lut for cells of type $lut.
Using template $paramod$9891217114ca63a6e9d48073351d843bb1d46faf\$lut for cells of type $lut.
Using template $paramod$812f633adb63ee5c3031a25df88a84362040bd10\$lut for cells of type $lut.
Using template $paramod$380eef9e0179c88842a606dfa701fb47f45dca1c\$lut for cells of type $lut.
Using template $paramod$928de89363c1709229b8424c852686f29a7adbd4\$lut for cells of type $lut.
Using template $paramod$ca357517489332a2cf261ee222c33ad12293e4d5\$lut for cells of type $lut.
Using template $paramod$60fa917a28d34b80d6677c1205fcae2e719774c5\$lut for cells of type $lut.
Using template $paramod$fd2a8b445663f67e309e876f0eec0ba2cd3ee1e5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut.
Using template $paramod$20f9a90a9b58ed3dd945872642992a9d4f2cfd6f\$lut for cells of type $lut.
Using template $paramod$57845085f548dde890ceb6797fd0e4b4e66d8f55\$lut for cells of type $lut.
Using template $paramod$7bb6a37e65823eeb4b38c370fec30ab082759a14\$lut for cells of type $lut.
Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut.
Using template $paramod$cc8b0c2ca5fc8e4cf840690a8995bcc9737a40bc\$lut for cells of type $lut.
Using template $paramod$b784d0e6a75bfa72beb170a27c1d1e14f831e736\$lut for cells of type $lut.
Using template $paramod$cfb0bc79ce85be37688b0ada625c3cd2f718fb26\$lut for cells of type $lut.
Using template $paramod$9b8ad6ec287ad078c7ff8f3a8ca4083f5a7cb8c9\$lut for cells of type $lut.
Using template $paramod$1fd85f0af077d92c5a6da4f294734384105bae93\$lut for cells of type $lut.
Using template $paramod$c10a219db5a9afc085c10b61d5232a5f96cf39d8\$lut for cells of type $lut.
Using template $paramod$36f80a1d9ed0e6092222b4891aa116e2cd56bab7\$lut for cells of type $lut.
Using template $paramod$3c6187868b01513c14780e5ac5fbd9d836bce0f1\$lut for cells of type $lut.
Using template $paramod$98e1d11683c0a22e595b32649124489a2d73a644\$lut for cells of type $lut.
Using template $paramod$9111d68cf2c15cd98e35433450e2eb92b679070f\$lut for cells of type $lut.
Using template $paramod$8384e66d408d22ab39dfb451efb7879731befeb8\$lut for cells of type $lut.
Using template $paramod$564fe09316370b500736f281e6bb40fddffec569\$lut for cells of type $lut.
Using template $paramod$833db83dfba94101900f38726761c5faa252a28a\$lut for cells of type $lut.
Using template $paramod$476a67091744122aadf8ca517035a95c45c1a308\$lut for cells of type $lut.
Using template $paramod$f79dc556b838338aa6df603260eb12847ca40eed\$lut for cells of type $lut.
Using template $paramod$cbb2dfe31d344d3326d567c2ed5a4b2a29f63219\$lut for cells of type $lut.
Using template $paramod$6780637edf0c0d622960ccbac224e01afe00dc99\$lut for cells of type $lut.
Using template $paramod$b0f298d90de50cc2c159c8b0e3e6cbfa024c6f0e\$lut for cells of type $lut.
Using template $paramod$63d8e9d4b0e4a942bb4af70415c232bdb07ee87b\$lut for cells of type $lut.
Using template $paramod$779c448584c9deb5a715f2816f74c425f81276a3\$lut for cells of type $lut.
Using template $paramod$bfb199caef76fb241d166d9d961a064b97aed5e5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110100 for cells of type $lut.
Using template $paramod$b60bf12111393250ce644d3bcf234c32f15777f5\$lut for cells of type $lut.
Using template $paramod$6d937d8a77a6356f2f9cc89d5646fb948bb8225e\$lut for cells of type $lut.
Using template $paramod$18d8b5918662de78ca38067ca361ca26699e338c\$lut for cells of type $lut.
Using template $paramod$fe5b6043e65e98368b275f38e2ca7ec95af2534a\$lut for cells of type $lut.
Using template $paramod$20db8e8195c71b8649e624b9f7bbe840d2be7c66\$lut for cells of type $lut.
Using template $paramod$4b8324809148df6161610ef5b5bd73df0086e19e\$lut for cells of type $lut.
Using template $paramod$b833110cb242b277d581ac706029ae0cf8b7ee30\$lut for cells of type $lut.
Using template $paramod$7cb8a916371a2059b10378bb011b15e5360916cd\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000111 for cells of type $lut.
Using template $paramod$ee454ad2383885733a4273245816698f8443c10b\$lut for cells of type $lut.
Using template $paramod$d158f2a539c9d3cb6e76a9e6e7de3ce0b0b34ab9\$lut for cells of type $lut.
Using template $paramod$4cab3b31c601551ff65536bf4f533afa0b2094ee\$lut for cells of type $lut.
Using template $paramod$a4550ffad09d079c5cfc8911b53f312523a5783a\$lut for cells of type $lut.
Using template $paramod$26f673982b1855b3e21a4992dbd3fb5fe7c3cec2\$lut for cells of type $lut.
Using template $paramod$7b733f5b3466ec911060896fccc5c2626cbe3d64\$lut for cells of type $lut.
Using template $paramod$ee2bd12100341040ee6b331ecc07736628574e6b\$lut for cells of type $lut.
Using template $paramod$599d173132bceb40d47ee7a14b75088a87d11293\$lut for cells of type $lut.
Using template $paramod$b7685cb0c8a6753256bc84bc31d36a443c15fab7\$lut for cells of type $lut.
Using template $paramod$f52df4b90f46c2ab9e801e1f39516c9cb1bb6ae7\$lut for cells of type $lut.
Using template $paramod$6591216ccda226c4b7a70dfa31df99a870585a0c\$lut for cells of type $lut.
Using template $paramod$973818279bc95792902f3c09371fd2407d04a2a5\$lut for cells of type $lut.
Using template $paramod$f87bcf1791971b4eaa30f3f28437044fef878a04\$lut for cells of type $lut.
Using template $paramod$a36debbcfde9e32a01ea5076ccf3d75225452c4d\$lut for cells of type $lut.
Using template $paramod$7ad442e26470179523f0451f48962d394e31888a\$lut for cells of type $lut.
Using template $paramod$73f837ea3e53430f33d1a454b63163239392c8c1\$lut for cells of type $lut.
Using template $paramod$51fcdf1b47519e53d208a157cb0c9f1fc512c00f\$lut for cells of type $lut.
Using template $paramod$9998c61c50285bf1d3dc1a1ed624f8f310df58c4\$lut for cells of type $lut.
Using template $paramod$e9435e7c32613b70c835ebcf96a814225729d972\$lut for cells of type $lut.
Using template $paramod$fe1497207981e9e4f2f9556fad9970ec052e0a6d\$lut for cells of type $lut.
Using template $paramod$40882341c54dcd36f630f00dd7e46a35652abd36\$lut for cells of type $lut.
Using template $paramod$4fa54c26ed1828223450420ca53d4097fddd10ed\$lut for cells of type $lut.
Using template $paramod$c44f6ab620dfc2b8e2b9cea98a6b5afb75914ddb\$lut for cells of type $lut.
Using template $paramod$2a0c44e71872f0780c388665bf94ffd596d2d316\$lut for cells of type $lut.
Using template $paramod$e528eb855484dedcf5c355cd7bb313439524a631\$lut for cells of type $lut.
Using template $paramod$56be3be0d09f7de8119eab1ef7402866e7a4be2c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut.
Using template $paramod$f405ee362848dd1a47c58160f854302f6ecf95ff\$lut for cells of type $lut.
Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba\$lut for cells of type $lut.
Using template $paramod$35d6d6bee07fbed4c99d77928117736fae8df929\$lut for cells of type $lut.
Using template $paramod$a1e5618dd93058f029f56e4c9a94c122d300c343\$lut for cells of type $lut.
Using template $paramod$f4c73d849f7d47805ca1aefb950c4e26e4eae9d0\$lut for cells of type $lut.
Using template $paramod$8c11a155773d2e4aba9b1022fc059160b55313e8\$lut for cells of type $lut.
Using template $paramod$c0e395c2d0dfbafa147a6aae7cfc1897ce26affb\$lut for cells of type $lut.
Using template $paramod$23da582b86241546eace0c8bedadb42614eea4c1\$lut for cells of type $lut.
Using template $paramod$153c6cdaaddbc43e6ef3facd06aa851de33910ae\$lut for cells of type $lut.
Using template $paramod$f72217d55e8c28cbf17aa2ad60621cb2e1a5c998\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110101 for cells of type $lut.
Using template $paramod$a02c42646fe7ec38a119dfa7d53fba93d3ada1f1\$lut for cells of type $lut.
Using template $paramod$51b138c6601401861f3f66aa30cc9212c6a6619a\$lut for cells of type $lut.
Using template $paramod$681f59595c87f489ea14853c86c4f2b4fcaf27d8\$lut for cells of type $lut.
Using template $paramod$1d4b1231c0c0b0db059aad3b753069e641d90dcb\$lut for cells of type $lut.
Using template $paramod$bea08a495d16293f8cc454a45845d26cde0762b6\$lut for cells of type $lut.
Using template $paramod$1b48bc962a0c1e178183f21032378372adc5e26c\$lut for cells of type $lut.
Using template $paramod$94ac66a11090dca84889e55fcf03297912a5b7ec\$lut for cells of type $lut.
Using template $paramod$33469441402c436c9913b4f1192e73cfd6ebcad1\$lut for cells of type $lut.
Using template $paramod$d7856980c8e3df62f97c26ab34037f33a9e831b5\$lut for cells of type $lut.
Using template $paramod$ba4b1c9b57f942a38af35848615a2f06189d3bfe\$lut for cells of type $lut.
Using template $paramod$253532b742d151c01e8e51f153c24d934b8f6185\$lut for cells of type $lut.
Using template $paramod$b7d5a1d13a95755f80d49e78f7fe57dd63a6cfbe\$lut for cells of type $lut.
Using template $paramod$d7cb295742f7b0b199be627c2445ca9db23a646f\$lut for cells of type $lut.
Using template $paramod$edfdd002d369b276282ba114ad80081aeb01c009\$lut for cells of type $lut.
Using template $paramod$58df2c605746858c7e53492c8f57d6f1fafa12d2\$lut for cells of type $lut.
Using template $paramod$3702268f692b8bf258e428f65d3bca4e1f76d98b\$lut for cells of type $lut.
Using template $paramod$16894c241be5ea1f024e9339dea788b4dbe184ae\$lut for cells of type $lut.
Using template $paramod$18368a3da11a7221c7fb674ec80ee0d0bd64b883\$lut for cells of type $lut.
Using template $paramod$436f5b2a701f46b4f2c40432561ff700e1d0a2c0\$lut for cells of type $lut.
Using template $paramod$3ec5e45cb3e54de9dbe908707155b5f9917c9370\$lut for cells of type $lut.
Using template $paramod$bf9d12be9e757c28b1374b63e168615e76b4b315\$lut for cells of type $lut.
Using template $paramod$75d5c453cca75cc7a7ca320c4fb7be0932b6aaa7\$lut for cells of type $lut.
Using template $paramod$0ee0167fb5dd83bdfe7197fff23e2c7146c57037\$lut for cells of type $lut.
Using template $paramod$a63014c5e66a56dc5e61848489c809a59ebe7c34\$lut for cells of type $lut.
Using template $paramod$fcff9a7b1687e357a40264efcefe8443c8b2971a\$lut for cells of type $lut.
Using template $paramod$4b9b235bc4444ff899bef0c648e4109b26737f1a\$lut for cells of type $lut.
Using template $paramod$1a95e0da14fff355d7b4438b7358c951bbb08ccd\$lut for cells of type $lut.
Using template $paramod$cc680ff53b1f353d6fb4a452cf455777cc96519b\$lut for cells of type $lut.
Using template $paramod$a50bbaf70b48eb6d78317eddf4f7e11e8988acec\$lut for cells of type $lut.
Using template $paramod$a7c07944e10969b2e1fd563a5b72f89493cb3705\$lut for cells of type $lut.
Using template $paramod$e2d96f36ef28053ecd27167cd95b944485ac3146\$lut for cells of type $lut.
Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730\$lut for cells of type $lut.
Using template $paramod$adbb1dde6c987d24ce9039960a9f4e56a141c78d\$lut for cells of type $lut.
Using template $paramod$acb15e6231c510f745510acf4b8ac1efc35e5fb7\$lut for cells of type $lut.
Using template $paramod$000fa2164e1f538c16460571efee2b6209a086cc\$lut for cells of type $lut.
Using template $paramod$c506f2c444efce9b750bd027c026315e148d2023\$lut for cells of type $lut.
Using template $paramod$d8c15619e14e23259772acc1552b8b29afbd81c5\$lut for cells of type $lut.
Using template $paramod$5a621b016c894274d07edef48c49b401a15fd796\$lut for cells of type $lut.
Using template $paramod$6a9b42dd2737c91073e6a695b8ac858c4a8587d7\$lut for cells of type $lut.
Using template $paramod$a03ef989f8f4e1878ce2f5c4e0e3d2dfb54307ef\$lut for cells of type $lut.
Using template $paramod$8921e608da57eb3483e6390a11938d2bd4d7314d\$lut for cells of type $lut.
Using template $paramod$10937e50ec10e9b0ee9a0254632063f0278f51d5\$lut for cells of type $lut.
Using template $paramod$12ab4ac9a458997cfab0c618d6b4e5b6b68b140c\$lut for cells of type $lut.
Using template $paramod$3548f6e93628807ae6cc989ec88fe8ae640cb47a\$lut for cells of type $lut.
Using template $paramod$39b0d201a18bed5573a88835da3f39d40814d360\$lut for cells of type $lut.
Using template $paramod$81a95dc4becda1145224d7418e43bb13f6272d71\$lut for cells of type $lut.
Using template $paramod$f24ba3ced4b870f8e829f5ac5a8af88573350e6f\$lut for cells of type $lut.
Using template $paramod$c8c2f45d9083177b70913b41d4370d01f048f309\$lut for cells of type $lut.
Using template $paramod$09244871c4b5bfde1862f3870962d986eba7a18e\$lut for cells of type $lut.
Using template $paramod$d8948be14d641b06fbaa2f14f13eb0320e2b1ac1\$lut for cells of type $lut.
Using template $paramod$bd3e77c5ae0c34ff2c9f3dae31b7c406cf14c40c\$lut for cells of type $lut.
Using template $paramod$ab4188c7524eec831e9177bc675d62b21a3ccd8b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod$b0d03287dee77810fac31097b2733c0ff570bc76\$lut for cells of type $lut.
Using template $paramod$17c27ffdda03355f95b2ba5edc73ca082237c935\$lut for cells of type $lut.
Using template $paramod$686c3a61e478baf572ab8cdb36800066d07b2c60\$lut for cells of type $lut.
Using template $paramod$176a6ceafa512d807921d7dfc76320dfbbfb5fe4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001110 for cells of type $lut.
Using template $paramod$8cbea7472fe8ec8b0d9b301f17edad7f1c398048\$lut for cells of type $lut.
Using template $paramod$fa19cc41652af82990288e2743fe6239cdab2658\$lut for cells of type $lut.
Using template $paramod$34536926332939882b8ff52380fffc08ed1f405f\$lut for cells of type $lut.
Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut.
Using template $paramod$5dc745bb48e2cf535179547ba13f0fe5364d6d54\$lut for cells of type $lut.
Using template $paramod$fb5ee0bdef1c4e74aaf1fd8efae98b46a2f5e564\$lut for cells of type $lut.
Using template $paramod$bf99bfee99457541520a558ec277501d23240ca8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110010 for cells of type $lut.
Using template $paramod$a14a8c12a7d9be4302fd5be96e31aac1077e087b\$lut for cells of type $lut.
Using template $paramod$b637cf4714c2e93484bb499728e176a6ab69c910\$lut for cells of type $lut.
Using template $paramod$c78b28b0674e1f0605658e28384d11f25f372de7\$lut for cells of type $lut.
Using template $paramod$4d5fa0c21aaa9745a301eda7465c650b5896bed0\$lut for cells of type $lut.
Using template $paramod$b89c522b7f70adaee1a35d80e932f38159b6a445\$lut for cells of type $lut.
Using template $paramod$20869ac69888a147c4525f14de7a7ec7d62c1112\$lut for cells of type $lut.
Using template $paramod$c24d0e2a94559837d969df5b5aaf84188feaf3d8\$lut for cells of type $lut.
Using template $paramod$e4723c78131b859cdb296cc7099a965ce6bf28d9\$lut for cells of type $lut.
Using template $paramod$ff7b4776e95c73ef189816542c3a84d65b50b8d8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011101 for cells of type $lut.
Using template $paramod$b419810ab1d51da1962917a1949cecc5f27935eb\$lut for cells of type $lut.
Using template $paramod$c2717e4c2499581f5d3d1df34c696743c230a696\$lut for cells of type $lut.
Using template $paramod$c6a234b1fd9b047d8452094c01e2bc4b0dcb4298\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110111 for cells of type $lut.
Using template $paramod$d577c156a63771bbfc98298a46242703048eed02\$lut for cells of type $lut.
Using template $paramod$70f68cc10fbeada9b6fa90c3bb75475e348ca467\$lut for cells of type $lut.
Using template $paramod$44236511622e197854fa4814b088d63bb24df320\$lut for cells of type $lut.
Using template $paramod$8be603794459732f9a374f76041b510fc63b115b\$lut for cells of type $lut.
Using template $paramod$08376f7fae321567207e85bf6db3a9f247ca9620\$lut for cells of type $lut.
Using template $paramod$ff05e31f900671d722aa86741f7bffad25d3518b\$lut for cells of type $lut.
Using template $paramod$ef0f7ee2667266b7715ee356b6b8a1113ea89912\$lut for cells of type $lut.
Using template $paramod$cce6b847e730f5f1cfb4a8ef6c78f9f44e4f1145\$lut for cells of type $lut.
Using template $paramod$fe9a0158d0352193457c4f5b6282ac86d35fb3ee\$lut for cells of type $lut.
Using template $paramod$722bfd9af0ae56ca9d1d12a221cb5ede16461f26\$lut for cells of type $lut.
Using template $paramod$84a9bb4ea112cac05b4a6b108a4c6ec2091f4ef3\$lut for cells of type $lut.
Using template $paramod$18e50808df562b188523e13714b96fedec6427c1\$lut for cells of type $lut.
Using template $paramod$d50aaf7bc91b84437dde85e30486261cdbeeccac\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001111 for cells of type $lut.
Using template $paramod$7295da7c5b19f528a428229f2570e0a23ad372af\$lut for cells of type $lut.
Using template $paramod$47b2f5a9f58cb4be072657772748a1ab82d6819a\$lut for cells of type $lut.
Using template $paramod$850f48dac4014f6ce06187aa7664648cd494a38b\$lut for cells of type $lut.
Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221\$lut for cells of type $lut.
Using template $paramod$e77dca5e1fc847f9005cbcedebcb6de355499010\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110100 for cells of type $lut.
Using template $paramod$bab0ea0d717fb03593996e2a9f716c39db2520fb\$lut for cells of type $lut.
Using template $paramod$27d6ec7ecb7b8378e858bc3925078e4f971c691c\$lut for cells of type $lut.
Using template $paramod$b80e608920ce9cfa1f5c7d21df7a72954e9b0a70\$lut for cells of type $lut.
Using template $paramod$bb4fff1cc3b827238aa40993cafede1c5beecbe3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut.
Using template $paramod$6eaa285474ca0c16a33be004e48a6a32f35674a1\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
Using template $paramod$01d6171b877f7655dc0d32e32900a6a207a75b44\$lut for cells of type $lut.
Using template $paramod$432e4e01d71b10f1550b48be5a824f4f5138a82c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101111 for cells of type $lut.
Using template $paramod$0a37cf5c1bbf5678a7d95c5d11fcf616a3fc4fb6\$lut for cells of type $lut.
Using template $paramod$f9862fc384130049aba0daf01b573a025832014a\$lut for cells of type $lut.
Using template $paramod$965f8f2fa1a796a6c51222eabb50fbd26e97d98b\$lut for cells of type $lut.
Using template $paramod$bcd0ec8486cd042d1327ec39d9c0f6f57473bc07\$lut for cells of type $lut.
Using template $paramod$f2411b7acc510e728faf1cefff1a2f4dd424a294\$lut for cells of type $lut.
Using template $paramod$18924ca594703ba3a178bd09acccc452011221c2\$lut for cells of type $lut.
No more expansions possible.
<suppressed ~13533 debug messages>

17.44. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in processorci_top.
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141718.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141731.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141898.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141907.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141751.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141784.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141785.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$25907.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[31].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[31].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[31].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[31].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[30].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[30].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[30].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[29].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[29].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[29].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[28].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[28].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[28].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[27].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[27].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[27].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[27].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[26].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$24651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$24651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$24395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$24395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[23].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[23].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[23].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[23].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[23].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[22].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[22].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[22].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[22].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$23760.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[21].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[21].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[21].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$23395.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[18].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[18].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[18].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[18].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[18].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$22691.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22691.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22691.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22691.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22691.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22691.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22249.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22249.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22249.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$22244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$22244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$22244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$22244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$22244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$21749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$20703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$20636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$20636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$20636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$20636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$20636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$20636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$20630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$20630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$20625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20602.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20602.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20602.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20582.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$20577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$20469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$20469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$20469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$20469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$20469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$20368.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$20015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19957.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$19957.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$19957.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$19957.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$19957.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$19951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$19592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$19470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$19398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$19393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$19366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$19361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[5].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[5].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[5].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$18992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$18985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$18842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$18842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$18842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$18842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$18842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$18706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$18706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$18706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$18706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$18706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$18633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$18633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$18633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$18633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$18633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$18633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$18627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[4].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[4].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[4].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[4].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[4].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[4].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$17840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$17840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[3].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[3].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$17207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$17184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$17179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17144.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17144.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17144.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$16438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$16438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$16438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$16438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$16431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16431.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$auto$fsm_map.cc:170:map_fsm$3741[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[1].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[1].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[1].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[1].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[1].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[1].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$15348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$15348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$14933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$14933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$14933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$14933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$14933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$14864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[0].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[0].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$14563.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$14548.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$14548.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$14489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$14489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$14489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$14489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$14489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$14482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$14482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$14482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$14482.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$14475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$14475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$14450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$14434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$14383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$13942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$13942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$12769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$12136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$12127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12108.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$12108.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$12095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$12095.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$12078.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$12060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$12054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$12021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$12021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$12021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12005.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$11964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$11964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$11964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$11950.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$11924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$11901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$11901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$11888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$11845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$11845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$11836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$11836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$11821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$11815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$11815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11815.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$11805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11805.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11799.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$11792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$11792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$11792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$11777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$11771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$11759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11730.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$11730.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$11724.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$11718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11662.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$11522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11514.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$11514.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$11514.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$11455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$11455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$11455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$11041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$10843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$10480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$10152.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$auto$opt_dff.cc:219:make_patterns_logic$5649.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$10229.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10441.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10480.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10495.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10527.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10534.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10555.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10579.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10637.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10653.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10832.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10851.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$10966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$10981.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10992.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11007.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11041.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141972.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11128.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11143.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11292.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11362.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11455.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11462.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11487.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11504.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11514.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$11522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$11522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11629.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$11636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11662.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11662.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11685.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11695.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11712.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11718.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11724.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11752.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11759.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11771.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11777.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11785.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$11792.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$11809.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11821.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11857.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$11863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11863.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11888.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11894.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$11901.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11924.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$11928.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$11937.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$11954.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$11964.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$11983.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12010.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$12021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$12021.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12026.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$12054.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12060.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$12078.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12083.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$12089.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12108.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12113.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$12121.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12136.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$12148.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12184.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12205.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12213.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12220.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12275.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$12291.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12344.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$12355.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12371.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12396.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$12415.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12437.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12444.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12448.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$12455.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12480.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$12491.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12507.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12523.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12539.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12607.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12641.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$12657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$12665.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12681.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12691.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12698.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12754.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12761.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$12769.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$12777.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12920.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12945.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$12981.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$13039.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$13057.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$13074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$13132.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$13180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$13228.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$13237.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$13252.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$13279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$13287.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$13347.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$13357.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$13415.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$13440.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$13489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$13497.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$13551.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$13577.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$13598.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$13606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$13693.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$13742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$13751.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$13799.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$13838.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$13842.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$13857.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$13864.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$13877.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$13899.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$13942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$13942.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$13982.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14015.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$14108.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14232.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14239.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$14287.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$14294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14315.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$14320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$14327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$14383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$14418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14434.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14444.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$14459.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$14475.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$14489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$14525.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14555.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14563.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14563.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14594.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$auto$opt_dff.cc:219:make_patterns_logic$5410.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$auto$fsm_map.cc:170:map_fsm$4918[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$14769.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14774.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14804.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14820.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14845.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$14852.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14859.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14871.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14887.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14903.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$14933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$14943.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14959.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14975.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$14991.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15010.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15026.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15033.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15043.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15063.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$15081.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15097.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15113.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15148.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15174.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15181.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15197.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$15219.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15235.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15252.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15278.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15285.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15318.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$15352.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15438.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15454.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15482.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15522.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15538.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15551.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$15645.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15678.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15710.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15738.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15745.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15761.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15774.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$15854.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15976.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$15992.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16021.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16037.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16071.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16087.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16094.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16104.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16120.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16149.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16184.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16191.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16257.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16273.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16280.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16287.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$16294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16361.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16387.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16394.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16414.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16521.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16537.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16553.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16569.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16588.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16637.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16656.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16674.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$16693.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16700.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$16707.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16725.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16741.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$16819.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16844.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$16849.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16853.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16864.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16868.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$16881.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16886.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16895.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16899.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16906.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16922.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16972.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$16979.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$16995.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17002.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17012.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17028.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17044.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17079.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17108.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$17144.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17148.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17174.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17184.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$17189.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17193.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17207.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$17221.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$17253.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17283.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[3].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$17408.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17425.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17441.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17457.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17485.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17492.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17517.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$17533.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$17552.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17571.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$17587.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$17603.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$17611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17616.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17638.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17671.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17700.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$17707.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17723.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17739.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17764.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$17774.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17799.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$17815.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$17831.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$17840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$17840.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$17847.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17863.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17879.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17895.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17914.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17937.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17947.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$17980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$18018.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18036.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$18055.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18062.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$18069.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18081.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$18122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$18215.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18231.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18247.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18383.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18409.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18416.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18426.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$18435.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$18454.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18482.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$18489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18499.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$18508.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$18524.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18563.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18579.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18617.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18627.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$18637.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18644.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18676.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$18706.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$18713.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18739.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18772.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18779.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18795.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18820.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$18836.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$18842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$18842.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$18852.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18868.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18919.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18927.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18952.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18968.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$18992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19037.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19103.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19152.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19165.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19190.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19251.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19291.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19328.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19361.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19366.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$19371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$19388.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19393.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$19398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$19424.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19440.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19465.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$19470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$19470.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$19476.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$19483.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19524.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$19540.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$19550.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19576.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$19592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$19599.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19609.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19704.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19741.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19748.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$19757.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$19773.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19789.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19807.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19823.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$19885.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$19915.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19919.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$19946.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19951.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19957.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$19957.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$19976.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$19983.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$19993.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20015.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$20020.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$20027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20037.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20047.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$20084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$20098.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20110.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20117.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20135.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$20151.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20158.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$20177.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$20195.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20227.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20255.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20262.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$20319.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$20330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20355.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$20363.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20368.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20368.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20399.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20438.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20454.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20469.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$20473.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$20513.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20529.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20554.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$20570.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$20577.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20582.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20582.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20602.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20607.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20625.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20630.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$20636.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[7].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$20690.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$20703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[8].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$20718.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20734.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20755.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$20769.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20787.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20803.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20821.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20837.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$20933.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20946.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$20970.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$20977.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$20984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$21002.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$21018.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$21036.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$21052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$21072.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$21097.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$21211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$21248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$21255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$21264.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$21280.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$21296.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$21314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$21327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$21415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$21422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$21435.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$21456.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$21466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$21473.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$21491.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$21504.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$21525.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$21543.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$21601.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$21617.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$21638.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$21645.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$21654.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$21670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$21683.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$21704.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$21722.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$21749.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut\Controller.Memory.write_data[13].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$21873.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$21889.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$21907.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$21917.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$21924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$21942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$21955.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$21976.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$21992.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$22052.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22086.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$22103.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22121.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$22155.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$22201.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut\Controller.Memory.write_data[14].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$22244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$22253.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22305.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$22337.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22355.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22368.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$22389.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22405.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$22529.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22545.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$22563.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22573.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$22582.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$22598.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22632.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$22691.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[17].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$22713.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22722.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22741.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22756.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22766.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$22773.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22791.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22804.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$22825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22841.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$22927.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22964.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$22971.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$22983.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$22996.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23009.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$23027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$23054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$23066.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23073.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[19].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$23188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$23188.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$23194.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23207.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23223.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23241.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23251.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$23258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23276.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23292.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$23310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23328.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$23400.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$23425.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23441.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23462.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23469.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$23476.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23494.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23510.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$23528.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$23567.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[21].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$23616.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23623.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23639.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$23657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23683.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23693.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23706.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$23728.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23738.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$23745.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23764.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$23832.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23850.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$23869.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$23883.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23901.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23917.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23935.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$23951.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[23].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$24055.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$24090.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$24107.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$24126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$24157.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$24176.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24186.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24241.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$24248.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24264.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$24282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24317.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24333.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24351.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24395.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$24425.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$24452.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24465.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24483.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24499.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24518.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24534.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$24563.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$24580.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$24601.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[25].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$24651.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$24681.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$24688.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24704.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24714.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24721.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24731.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$24738.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$24759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$24794.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24804.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$24811.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24843.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$24907.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24937.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$24947.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$24970.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$24974.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$25040.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$25062.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$25104.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$25111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$25221.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$25254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$25260.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$25350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$25376.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$25460.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$25487.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$25506.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$25519.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$25533.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$25569.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$25619.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$25669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[30].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$25721.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$25744.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$25822.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$141642$lut$aiger141641$25875.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$25954.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$25961.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$auto$fsm_map.cc:170:map_fsm$4378[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[11].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[13].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut\Controller.Memory.write_data[16].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut\Controller.Memory.write_data[23].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[9].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut$auto$opt_dff.cc:219:make_patterns_logic$5253.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut$auto$opt_dff.cc:219:make_patterns_logic$5286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[0].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut$auto$opt_dff.cc:219:make_patterns_logic$5489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$flatten\Controller.\Interpreter.$procmux$1555.Y[5].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$16438.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[15].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[28].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[4].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut\Controller.Memory.write_data[11].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[18].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[29].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$141642$lut\Controller.Memory.write_data[9].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut$aiger141641$15810.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$141642$lut\Controller.Memory.write_data[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.lsReadDataOut[4].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[1].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[3].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[5].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut\Riscado_V.registerFile.dataIn[6].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141656.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141652.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141663.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141670.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141672.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141678.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141683.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141688.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141691.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141691.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141695.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141698.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141700.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141700.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141709.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141711.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141711.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141718.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141720.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141724.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141724.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141730.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141731.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141739.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141739.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141750.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141751.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141756.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141756.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141766.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141766.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141771.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141771.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141777.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141777.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141783.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141792.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141792.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141793.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141797.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141797.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141799.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141810.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141823.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141813.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141822.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141823.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141826.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141826.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141829.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141830.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141832.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141845.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141841.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141843.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141843.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141853.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141853.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141855.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141680.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141859.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141863.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141863.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141757.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141869.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141871.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141975.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141877.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141877.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141890.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141882.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141889.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141902.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141906.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141916.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141916.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141918.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141975.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141875.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141985.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141986.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141992.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141994.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$141998.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142000.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142018.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142023.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142027.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$141642$lut$aiger141641$10843.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142031.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142033.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142035.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142037.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142039.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142041.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$142043.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$141642$lut$aiger141641$10265.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
Removed 0 unused cells and 15110 unused wires.

17.45. Executing AUTONAME pass.
Renamed 297463 objects in module processorci_top (199 iterations).
<suppressed ~17339 debug messages>

17.46. Executing HIERARCHY pass (managing design hierarchy).

17.46.1. Analyzing design hierarchy..
Top module:  \processorci_top

17.46.2. Analyzing design hierarchy..
Top module:  \processorci_top
Removed 0 unused modules.
Module processorci_top directly or indirectly displays text -> setting "keep" attribute.

17.47. Printing statistics.

=== processorci_top ===

   Number of wires:               8044
   Number of wire bits:          23251
   Number of public wires:        8044
   Number of public wire bits:   23251
   Number of ports:                 10
   Number of port bits:             10
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:              10620
     $print                         11
     $scopeinfo                     21
     CCU2C                         221
     L6MUX21                       350
     LUT4                         6802
     PFUMX                        1350
     TRELLIS_DPR16X4              1060
     TRELLIS_FF                    805

17.48. Executing CHECK pass (checking for obvious problems).
Checking module processorci_top...
Found and reported 0 problems.

17.49. Executing JSON backend.

Warnings: 35 unique messages, 35 total
End of script. Logfile hash: 458e3c5402, CPU: user 26.73s system 0.21s, MEM: 311.25 MB peak
Yosys 0.45+139 (git sha1 4d581a97d, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3)
Time spent: 36% 1x abc9_exe (15 sec), 14% 11x techmap (6 sec), ...
/eda/oss-cad-suite/bin/nextpnr-ecp5 --json colorlight_i9.json --write colorlight_i9_pnr.json --45k \
	--lpf /eda/processor_ci/constraints/colorlight_i9.lpf --textcfg colorlight_i9.config --package CABGA381 \
	--speed 6 --lpf-allow-unconstrained  --ignore-loops
/eda/oss-cad-suite/bin/ecppack --compress --input colorlight_i9.config  --bit colorlight_i9.bit

[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
[Pipeline] dir
Running in /var/jenkins_home/workspace/riscado-v/riscado-v
[Pipeline] {
[Pipeline] echo
Flashing FPGA colorlight_i9.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p riscado-v -b colorlight_i9 -l
Final configuration file generated at /var/jenkins_home/workspace/riscado-v/riscado-v/build_colorlight_i9.tcl
Makefile executed successfully.
Makefile output:
/eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 colorlight_i9.bit
empty
Found 1 compatible device:
	0x0d28 0x0204 0x3 (null)
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE

Loading: [====                                              ] 7.78%
Loading: [========                                          ] 15.57%
Loading: [============                                      ] 23.35%
Loading: [================                                  ] 31.14%
Loading: [====================                              ] 38.92%
Loading: [========================                          ] 46.71%
Loading: [============================                      ] 54.49%
Loading: [================================                  ] 62.28%
Loading: [====================================              ] 70.06%
Loading: [=======================================           ] 77.85%
Loading: [===========================================       ] 85.63%
Loading: [===============================================   ] 93.41%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE

[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test colorlight_i9)
[Pipeline] echo
Testing FPGA colorlight_i9.
[Pipeline] dir
Running in /var/jenkins_home/workspace/riscado-v/riscado-v
[Pipeline] {
[Pipeline] sh
+ echo Test for FPGA in /dev/ttyACM0
Test for FPGA in /dev/ttyACM0
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: colorlight_i9]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
No test report files were found. Configuration error?
Error when executing always post condition:
Also:   org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: 0b23f58a-c0c8-47a6-a542-768c47f85b62
hudson.AbortException: No test report files were found. Configuration error?
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253)
	at hudson.FilePath.act(FilePath.java:1234)
	at hudson.FilePath.act(FilePath.java:1217)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27)
	at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:47)
	at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source)
	at java.base/java.util.concurrent.FutureTask.run(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source)
	at java.base/java.lang.Thread.run(Unknown Source)

[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE