Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date         : Sun Jul 12 23:51:04 2026
| Host         : 685a421e500f running 64-bit unknown
| Command      : report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
| Design       : fpga_top
| Device       : xc7a100t
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Control Set Information

Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Total control sets                                       |    91 |
|    Minimum number of control sets                        |    91 |
|    Addition due to synthesis replication                 |     0 |
|    Addition due to physical synthesis replication        |     0 |
| Unused register locations in slices containing registers |    86 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions


2. Histogram
------------

+--------------------+-------+
|       Fanout       | Count |
+--------------------+-------+
| Total control sets |    91 |
| >= 0 to < 4        |     3 |
| >= 4 to < 6        |     5 |
| >= 6 to < 8        |     2 |
| >= 8 to < 10       |     7 |
| >= 10 to < 12      |     4 |
| >= 12 to < 14      |     3 |
| >= 14 to < 16      |     0 |
| >= 16              |    67 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design


3. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |               9 |            7 |
| No           | No                    | Yes                    |               0 |            0 |
| No           | Yes                   | No                     |             165 |           61 |
| Yes          | No                    | No                     |             193 |           62 |
| Yes          | No                    | Yes                    |              32 |            8 |
| Yes          | Yes                   | No                     |            1715 |          698 |
+--------------+-----------------------+------------------------+-----------------+--------------+


4. Detailed Control Set Information
-----------------------------------

+--------------------------------------+---------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+
|             Clock Signal             |                            Enable Signal                            |                       Set/Reset Signal                       | Slice Load Count | Bel Load Count | Bels / Slice |
+--------------------------------------+---------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                    | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_1_n_0             |                1 |              1 |         1.00 |
|  clk_IBUF_BUFG                       |                                                                     |                                                              |                1 |              1 |         1.00 |
|  u_Controller/ClkDivider/clk_o_pulse |                                                                     |                                                              |                2 |              2 |         1.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/next_bit                           | ptop/u_Controller/Uart/i_uart_rx/bit_counter[3]_i_1__0_n_0   |                1 |              4 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_2__0_n_0          | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_1_n_0      |                1 |              4 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/E[0]                               |                                                              |                1 |              4 |         4.00 |
|  clk_o_BUFG                          | ResetBootSystem/counter                                             |                                                              |                2 |              4 |         2.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/return_state                          | ResetBootSystem/rst_o_reg_0                                  |                1 |              5 |         5.00 |
|  clk_o_BUFG                          |                                                                     |                                                              |                4 |              6 |         1.50 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/data_to_send[6]_i_1_n_0            | ResetBootSystem/rst_o_reg_0                                  |                2 |              7 |         3.50 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/recieved_data0                     | ptop/u_Controller/Uart/i_uart_rx/recieved_data[7]_i_1_n_0    |                2 |              8 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/E[0]                               | ResetBootSystem/rst_o_reg_0                                  |                2 |              8 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/accumulator[7]_i_1_n_0                | ResetBootSystem/rst_o_reg_0                                  |                2 |              8 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/uart_rx_data[7]_i_1_n_0            | ResetBootSystem/rst_o_reg_0                                  |                2 |              8 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/uart_tx_en                                   | ResetBootSystem/rst_o_reg_0                                  |                2 |              8 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/FSM_sequential_state_write_reg[2][0] | ResetBootSystem/rst_o_reg_0                                  |                3 |              8 |         2.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/counter                               | ResetBootSystem/rst_o_reg_0                                  |                4 |              8 |         2.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/cycle_counter0                     | ptop/u_Controller/Uart/i_uart_rx/cycle_counter[9]_i_1__0_n_0 |                3 |             10 |         3.33 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                    | ResetBootSystem/SR[0]                                        |                3 |             10 |         3.33 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/rx_fifo/read_ptr0                            | ResetBootSystem/rst_o_reg_0                                  |                3 |             11 |         3.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/read_ptr[2]_i_1_n_0                  | ResetBootSystem/rst_o_reg_0                                  |                3 |             11 |         3.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/address[31]_i_1_n_0                   |                                                              |                5 |             12 |         2.40 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/rx_fifo/memory_reg_0_7_0_5_i_1__0_n_0        |                                                              |                2 |             12 |         6.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/memory_reg_0_7_0_5_i_1_n_0           |                                                              |                2 |             12 |         6.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/num_of_pages                          | ResetBootSystem/rst_o_reg_0                                  |                4 |             24 |         6.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/memory_page_number[23]_i_2_n_0        | ptop/u_Controller/Interpreter/memory_page_number[23]_i_1_n_0 |                7 |             24 |         3.43 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/num_of_cycles_to_pulse[23]_i_1_n_0    |                                                              |                7 |             24 |         3.43 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/timeout                               | ResetBootSystem/rst_o_reg_0                                  |                7 |             24 |         3.43 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/accumulator0                          | ResetBootSystem/rst_o_reg_0                                  |                5 |             24 |         4.80 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/E[0]                                     |                                                              |               13 |             30 |         2.31 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/halted_reg_0[0]                             | ptop/u_Controller/Interpreter/rst_core                       |                9 |             31 |         3.44 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/csr_unit/csr_mepc[31]_i_1_n_0               | ptop/u_Controller/Interpreter/rst_core                       |                8 |             31 |         3.88 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[23][31]_i_1_n_0                     | ptop/u_Controller/Interpreter/rst_core                       |               20 |             32 |         1.60 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[10][31]_i_1_n_0                     | ptop/u_Controller/Interpreter/rst_core                       |               17 |             32 |         1.88 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[6][31]_i_1_n_0                      | ptop/u_Controller/Interpreter/rst_core                       |               19 |             32 |         1.68 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[24][31]_i_1_n_0                     | ptop/u_Controller/Interpreter/rst_core                       |                8 |             32 |         4.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[7][31]_i_1_n_0                      | ptop/u_Controller/Interpreter/rst_core                       |               17 |             32 |         1.88 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[27][31]_i_1_n_0                     | ptop/u_Controller/Interpreter/rst_core                       |               14 |             32 |         2.29 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[26][31]_i_1_n_0                     | ptop/u_Controller/Interpreter/rst_core                       |               12 |             32 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[16][31]_i_1_n_0                     | ptop/u_Controller/Interpreter/rst_core                       |               15 |             32 |         2.13 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[4][31]_i_1_n_0                      | ptop/u_Controller/Interpreter/rst_core                       |               15 |             32 |         2.13 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[1][31]_i_1_n_0                      | ptop/u_Controller/Interpreter/rst_core                       |               11 |             32 |         2.91 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[31][31]_i_1_n_0                     | ptop/u_Controller/Interpreter/rst_core                       |               24 |             32 |         1.33 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[11][31]_i_1_n_0                     | ptop/u_Controller/Interpreter/rst_core                       |               12 |             32 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[29][31]_i_1_n_0                     | ptop/u_Controller/Interpreter/rst_core                       |               18 |             32 |         1.78 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[3][31]_i_1_n_0                      | ptop/u_Controller/Interpreter/rst_core                       |               12 |             32 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[21][31]_i_1_n_0                     | ptop/u_Controller/Interpreter/rst_core                       |               14 |             32 |         2.29 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[12][31]_i_1_n_0                     | ptop/u_Controller/Interpreter/rst_core                       |               17 |             32 |         1.88 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[17][31]_i_1_n_0                     | ptop/u_Controller/Interpreter/rst_core                       |               15 |             32 |         2.13 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[22][31]_i_1_n_0                     | ptop/u_Controller/Interpreter/rst_core                       |               11 |             32 |         2.91 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/csr_unit/csr_mtvec_mode[1]_i_1_n_0          | ptop/u_Controller/Interpreter/rst_core                       |               25 |             32 |         1.28 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[5][31]_i_1_n_0                      | ptop/u_Controller/Interpreter/rst_core                       |               19 |             32 |         1.68 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[14][31]_i_1_n_0                     | ptop/u_Controller/Interpreter/rst_core                       |               14 |             32 |         2.29 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[13][31]_i_1_n_0                     | ptop/u_Controller/Interpreter/rst_core                       |               15 |             32 |         2.13 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[25][31]_i_1_n_0                     | ptop/u_Controller/Interpreter/rst_core                       |               11 |             32 |         2.91 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[19][31]_i_1_n_0                     | ptop/u_Controller/Interpreter/rst_core                       |               12 |             32 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[8][31]_i_1_n_0                      | ptop/u_Controller/Interpreter/rst_core                       |               19 |             32 |         1.68 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[9][31]_i_1_n_0                      | ptop/u_Controller/Interpreter/rst_core                       |               27 |             32 |         1.19 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[20][31]_i_1_n_0                     | ptop/u_Controller/Interpreter/rst_core                       |               11 |             32 |         2.91 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[18][31]_i_1_n_0                     | ptop/u_Controller/Interpreter/rst_core                       |               12 |             32 |         2.67 |
|  clk_o_BUFG                          | ptop/u_Controller/ClkDivider/pulse_counter[0]_i_1_n_0               | ResetBootSystem/rst_o_reg_0                                  |                8 |             32 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/timeout_counter                       | ResetBootSystem/rst_o_reg_0                                  |                6 |             32 |         5.33 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/write_data[31]_i_1_n_0                |                                                              |               13 |             32 |         2.46 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[30][31]_i_1_n_0                     | ptop/u_Controller/Interpreter/rst_core                       |               15 |             32 |         2.13 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/communication_write_data[31]_i_1_n_0  |                                                              |                9 |             32 |         3.56 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/end_position[31]_i_1_n_0              | ResetBootSystem/rst_o_reg_0                                  |                7 |             32 |         4.57 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/read_buffer                           | ResetBootSystem/rst_o_reg_0                                  |               13 |             32 |         2.46 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/E[0]                                 | ResetBootSystem/rst_o_reg_0                                  |                4 |             32 |         8.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/rx_fifo/E[0]                                 | ResetBootSystem/rst_o_reg_0                                  |                5 |             32 |         6.40 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[15][31]_i_1_n_0                     | ptop/u_Controller/Interpreter/rst_core                       |               15 |             32 |         2.13 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[28][31]_i_1_n_0                     | ptop/u_Controller/Interpreter/rst_core                       |               17 |             32 |         1.88 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/communication_buffer[31]_i_1_n_0      | ResetBootSystem/rst_o_reg_0                                  |                8 |             32 |         4.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/rf/regs[2][31]_i_1_n_0                      | ptop/u_Controller/Interpreter/rst_core                       |               14 |             32 |         2.29 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/csr_unit/core_reset_reg                     | ptop/u_atomrv/atom_core/rf/SR[0]                             |               14 |             34 |         2.43 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/num_of_positions[23]_i_1_n_0          |                                                              |               12 |             55 |         4.58 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/E[0]                                        | ptop/u_Controller/Interpreter/rst_core                       |               34 |             62 |         1.82 |
|  u_Controller/ClkDivider/clk_o_pulse |                                                                     | ptop/u_Controller/Interpreter/rst_core                       |               25 |             79 |         3.16 |
|  clk_o_BUFG                          |                                                                     | ResetBootSystem/rst_o_reg_0                                  |               36 |             86 |         2.39 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_atomrv/atom_core/csr_unit/core_reset_reg                     | ptop/u_Controller/Interpreter/rst_core                       |               35 |            126 |         3.60 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/iport_wb_adr_o_reg[12]_5              |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/iport_wb_adr_o_reg[12]_4              |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/iport_wb_adr_o_reg[12]_3              |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/iport_wb_adr_o_reg[12]_2              |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/iport_wb_adr_o_reg[12]_1              |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/iport_wb_adr_o_reg[12]                |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/iport_wb_adr_o_reg[12]_0              |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/dport_wb_adr_o_reg[10]_0              |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/address_reg[10]_0                     |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/dport_wb_adr_o_reg[10]                |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/address_reg[11]_0                     |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/iport_wb_adr_o_reg[12]_6              |                                                              |               32 |            128 |         4.00 |
+--------------------------------------+---------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+


