Started by timer [Pipeline] Start of Pipeline [Pipeline] node Still waiting to schedule task Waiting for next available executor Running on Jenkins in /var/jenkins_home/workspace/rocket-chip [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -rf *.xml [Pipeline] sh + rm -rf rocket-chip [Pipeline] sh + git clone --recursive --depth=1 https://github.com/chipsalliance/rocket-chip rocket-chip Cloning into 'rocket-chip'... Submodule 'dependencies/cde' (https://github.com/chipsalliance/cde.git) registered for path 'dependencies/cde' Submodule 'dependencies/chisel' (https://github.com/chipsalliance/chisel.git) registered for path 'dependencies/chisel' Submodule 'dependencies/diplomacy' (https://github.com/chipsalliance/diplomacy.git) registered for path 'dependencies/diplomacy' Submodule 'dependencies/hardfloat' (https://github.com/ucb-bar/berkeley-hardfloat.git) registered for path 'dependencies/hardfloat' Cloning into '/var/jenkins_home/workspace/rocket-chip/rocket-chip/dependencies/cde'... Cloning into '/var/jenkins_home/workspace/rocket-chip/rocket-chip/dependencies/chisel'... Cloning into '/var/jenkins_home/workspace/rocket-chip/rocket-chip/dependencies/diplomacy'... Cloning into '/var/jenkins_home/workspace/rocket-chip/rocket-chip/dependencies/hardfloat'... Submodule path 'dependencies/cde': checked out '52768c97a27b254c0cc0ac9401feb55b29e18c28' Submodule path 'dependencies/chisel': checked out 'e3bcc90db37f1aec9f8048813f4f0666098d9bee' Submodule path 'dependencies/diplomacy': checked out 'fe5e131d4fc8adec14a3ce4a4935bb5c0a269871' Submodule path 'dependencies/hardfloat': checked out 'd93aa570806013dea479a92ba9bb33d1f2d4f69f' Submodule 'berkeley-softfloat-3' (https://github.com/ucb-bar/berkeley-softfloat-3.git) registered for path 'dependencies/hardfloat/berkeley-softfloat-3' Submodule 'berkeley-testfloat-3' (https://github.com/ucb-bar/berkeley-testfloat-3.git) registered for path 'dependencies/hardfloat/berkeley-testfloat-3' Cloning into '/var/jenkins_home/workspace/rocket-chip/rocket-chip/dependencies/hardfloat/berkeley-softfloat-3'... Cloning into '/var/jenkins_home/workspace/rocket-chip/rocket-chip/dependencies/hardfloat/berkeley-testfloat-3'... Submodule path 'dependencies/hardfloat/berkeley-softfloat-3': checked out '5c06db33fc1e2130f67c045327b0ec949032df1d' Submodule path 'dependencies/hardfloat/berkeley-testfloat-3': checked out '06b20075dd3c1a5d0dd007a93643282832221612' [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Simulation) [Pipeline] dir Running in /var/jenkins_home/workspace/rocket-chip/rocket-chip [Pipeline] { [Pipeline] echo FPGA > Simulation [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Utilities) [Pipeline] dir Running in /var/jenkins_home/workspace/rocket-chip/rocket-chip [Pipeline] { [Pipeline] sh + pwd + python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/rocket-chip/rocket-chip -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels Trying to read file: /var/jenkins_home/workspace/rocket-chip/rocket-chip/src/main/resources/vsrc/AsyncResetReg.v Cache-related signals in debug_rob.v Results saved to /jenkins/processor_ci_utils/labels/rocket-chip.json [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Build Pipeline) [Pipeline] parallel [Pipeline] { (Branch: digilent_arty_a7_100t) [Pipeline] stage [Pipeline] { (digilent_arty_a7_100t) [Pipeline] lock Trying to acquire lock on [Resource: digilent_arty_a7_100t] The resource [digilent_arty_a7_100t] is locked by build leaf #421 #421 since Apr 11, 2026, 4:39 AM. [Resource: digilent_arty_a7_100t] is not free, waiting for execution ... [Required resources: [digilent_arty_a7_100t]] added into queue at position 0 Lock acquired on [Resource: digilent_arty_a7_100t] [Pipeline] { [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] dir Running in /var/jenkins_home/workspace/rocket-chip/rocket-chip [Pipeline] { [Pipeline] echo Starting synthesis for FPGA digilent_arty_a7_100t. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p rocket-chip -b digilent_arty_a7_100t [LOCK] Criado: run.lock File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'. Final configuration file generated at /var/jenkins_home/workspace/rocket-chip/rocket-chip/build_digilent_arty_a7_100t.tcl [LOCK] Removido: run.lock Error executing Makefile. ERROR: [Synth 8-2716] syntax error near '"DPI-C' [/var/jenkins_home/workspace/rocket-chip/rocket-chip/src/main/resources/vsrc/SimDTM.v:4] ERROR: [Synth 8-8896] 'bit' is an unknown type [/var/jenkins_home/workspace/rocket-chip/rocket-chip/src/main/resources/vsrc/SimDTM.v:36] ERROR: [Synth 8-8896] 'bit' is an unknown type [/var/jenkins_home/workspace/rocket-chip/rocket-chip/src/main/resources/vsrc/SimDTM.v:43] ERROR: [Synth 8-8896] 'int' is an unknown type [/var/jenkins_home/workspace/rocket-chip/rocket-chip/src/main/resources/vsrc/SimDTM.v:44] ERROR: [Synth 8-8896] 'int' is an unknown type [/var/jenkins_home/workspace/rocket-chip/rocket-chip/src/main/resources/vsrc/SimDTM.v:45] ERROR: [Synth 8-8896] 'int' is an unknown type [/var/jenkins_home/workspace/rocket-chip/rocket-chip/src/main/resources/vsrc/SimDTM.v:46] ERROR: [Synth 8-8896] 'bit' is an unknown type [/var/jenkins_home/workspace/rocket-chip/rocket-chip/src/main/resources/vsrc/SimDTM.v:47] ERROR: [Synth 8-8896] 'int' is an unknown type [/var/jenkins_home/workspace/rocket-chip/rocket-chip/src/main/resources/vsrc/SimDTM.v:48] ERROR: [Synth 8-439] module 'uart_rx' not found [/eda/processor-ci-controller/modules/uart.sv:260] ERROR: [Synth 8-6156] failed synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.sv:1] ERROR: [Synth 8-6156] failed synthesizing module 'Controller' [/eda/processor-ci-controller/rtl/controller.sv:1] ERROR: [Synth 8-6156] failed synthesizing module 'processorci_top' [/eda/processor_ci/rtl/rocket-chip.sv:7] ERROR: [Synth 8-6156] failed synthesizing module 'fpga_top' [/eda/processor_ci/internal/fpga_top.sv:8] ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details make: *** [/eda/processor_ci/makefiles/digilent_arty_a7_100t.mk:12: digilent_arty_a7_100t.bit] Error 1 Traceback (most recent call last): File "/eda/processor_ci/main.py", line 142, in main( File "/eda/processor_ci/main.py", line 89, in main build(build_file_path, board_name, toolchain_path) File "/eda/processor_ci/core/fpga.py", line 299, in build raise subprocess.CalledProcessError(process.returncode, 'make') subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2. [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash digilent_arty_a7_100t) Stage "Flash digilent_arty_a7_100t" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test digilent_arty_a7_100t) Stage "Test digilent_arty_a7_100t" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: digilent_arty_a7_100t] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } Failed in branch digilent_arty_a7_100t [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Declarative: Post Actions) [Pipeline] junit Recording test results [Checks API] No suitable checks publisher found. [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline ERROR: script returned exit code 1 Finished: FAILURE