#*****************************************************************************************
# Vivado (TM) v2019.2 (64-bit)
#
# create_post_synthesis_project.tcl: Tcl script for re-creating project 'rsd_post_synthesis'
#
# Generated by Vivado on Mon Jan 20 22:37:54 JST 2020
# IP Build 2700528 on Thu Nov  7 00:09:20 MST 2019
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
# when this script was generated. In order to re-create the project, please source this
# file in the Vivado Tcl Shell.
#
# * Note that the runs in the created project will be configured the same way as the
#   original project, however they will not be launched automatically. To regenerate the
#   run results please launch the synthesis/implementation runs as needed.
#
#*****************************************************************************************
# NOTE: In order to use this script for source control purposes, please make sure that the
#       following files are added to the source control system:-
#
# 1. This project restoration tcl script (create_post_synthesis_project.tcl) that was generated.
#
# 2. The following source(s) files that were local or imported into the original project.
#    (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
#
#    <none>
#
# 3. The following remote source files that were added to the original project:-
#
#    "/home/matsuo/workspace/rsd/Processor/Src/BasicTypes.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Memory/MemoryMapTypes.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Decoder/OpFormat.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Decoder/MicroOp.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Cache/CacheSystemTypes.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/LoadStoreUnit/LoadStoreUnitTypes.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/RenameLogic/RenameLogicTypes.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/RegisterFile/BypassTypes.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/FetchUnit/FetchUnitTypes.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Scheduler/SchedulerTypes.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/PipelineTypes.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Debug/DebugTypes.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/BasicMacros.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/RenameLogic/ActiveList.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/RenameLogic/ActiveListIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Memory/MemoryTypes.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/IO/IO_UnitTypes.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/FetchUnit/BTB.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/FetchUnit/BranchPredictor.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/RegisterFile/BypassController.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/RegisterFile/BypassNetwork.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/RegisterFile/BypassNetworkIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Privileged/CSR_UnitTypes.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Privileged/CSR_Unit.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Privileged/CSR_UnitIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Cache/CacheSystemIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/CommitStage.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/CommitStageIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/ComplexIntegerBackEnd/ComplexIntegerExecutionStage.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/ComplexIntegerBackEnd/ComplexIntegerExecutionStageIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/ComplexIntegerBackEnd/ComplexIntegerIssueStage.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/ComplexIntegerBackEnd/ComplexIntegerIssueStageIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/ComplexIntegerBackEnd/ComplexIntegerRegisterReadStage.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/ComplexIntegerBackEnd/ComplexIntegerRegisterReadStageIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/ComplexIntegerBackEnd/ComplexIntegerRegisterWriteStage.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Controller.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/ControllerIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Core.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Cache/DCache.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Cache/DCacheIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Debug/Debug.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Debug/DebugIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/DecodeStage.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/DecodeStageIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Decoder/DecodedBranchResolver.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Decoder/Decoder.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Scheduler/DestinationRAM.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/DispatchStage.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Primitives/Divider.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/ExecUnit/DividerUnit.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/FetchStage/FetchStage.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/FetchStage/FetchStageIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Primitives/FlipFlop.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Primitives/FreeList.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/FetchUnit/Gshare.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Debug/HardwareCounter.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Debug/HardwareCounterIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Cache/ICache.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/IO/IO_Unit.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/IO/IO_UnitIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/ExecUnit/IntALU.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/IntegerBackEnd/IntegerExecutionStage.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/IntegerBackEnd/IntegerExecutionStageIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/IntegerBackEnd/IntegerIssueStage.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/IntegerBackEnd/IntegerIssueStageIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/IntegerBackEnd/IntegerRegisterReadStage.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/IntegerBackEnd/IntegerRegisterReadStageIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/IntegerBackEnd/IntegerRegisterWriteStage.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Privileged/InterruptController.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Scheduler/IssueQueue.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/LoadStoreUnit/LoadQueue.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/LoadStoreUnit/LoadStoreUnit.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/LoadStoreUnit/LoadStoreUnitIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Main_Zynq.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Memory/Memory.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Cache/MemoryAccessController.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/MemoryBackEnd/MemoryAccessStage.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/MemoryBackEnd/MemoryAccessStageIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Scheduler/MemoryDependencyPredictor.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/MemoryBackEnd/MemoryExecutionStage.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/MemoryBackEnd/MemoryExecutionStageIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/MemoryBackEnd/MemoryIssueStage.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/MemoryBackEnd/MemoryIssueStageIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/MemoryBackEnd/MemoryRegisterReadStage.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/MemoryBackEnd/MemoryRegisterReadStageIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/MemoryBackEnd/MemoryRegisterWriteStage.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Memory/MemoryRequestQueue.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/MemoryBackEnd/MemoryTagAccessStage.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/MemoryBackEnd/MemoryTagAccessStageIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/MulDivUnit/MulDivUnit.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/MulDivUnit/MulDivUnitIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Primitives/Multiplier.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/ExecUnit/MultiplierUnit.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/FetchStage/NextPCStage.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/FetchStage/NextPCStageIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/FetchStage/PC.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Primitives/Picker.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/PreDecodeStage.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/PreDecodeStageIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Scheduler/ProducerMatrix.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Primitives/Queue.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Primitives/RAM_Vivado.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/RenameLogic/RMT.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Scheduler/ReadyBitTable.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Recovery/RecoveryManager.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Recovery/RecoveryManagerIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/RegisterFile/RegisterFile.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/RegisterFile/RegisterFileIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/RenameLogic/RenameLogic.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/RenameLogic/RenameLogicCommitter.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/RenameLogic/RenameLogicIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/RenameStage.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/RenameStageIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Scheduler/ReplayQueue.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/ResetController.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/RenameLogic/RetirementRMT.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/ScheduleStage.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/ScheduleStageIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Scheduler/Scheduler.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Scheduler/SchedulerIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Scheduler/SelectLogic.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/ExecUnit/Shifter.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/LoadStoreUnit/StoreCommitter.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/LoadStoreUnit/StoreQueue.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Scheduler/WakeupLogic.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Scheduler/WakeupPipelineRegister.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Scheduler/WakeupSelectIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Main_Zynq_Wrapper.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/SynthesisMacros.svh"
#    "/home/matsuo/workspace/rsd/Processor/Src/Memory/Axi4LiteControlRegister.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Memory/Axi4LiteControlRegisterIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Memory/ControlQueue.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Memory/Axi4MemoryIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Memory/MemoryReadReqQueue.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Memory/MemoryWriteDataQueue.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Memory/Axi4Memory.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Memory/Axi4LiteControlMemoryIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Memory/Axi4LiteMemory.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/FetchUnit/Bimodal.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/ExecUnit/BitCounter.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Cache/CachePrimitives.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Primitives/LRU_Counter.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/ExecUnit/PipelinedRefDivider.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Scheduler/SourceCAM.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/RegisterFile/VectorBypassNetwork.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/ExecUnit/VectorUnit.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/MemoryBackEnd/MemoryRegisterWriteStageIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/DispatchStageIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Pipeline/IntegerBackEnd/IntegerRegisterWriteStageIF.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Verification/Dumper.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/Verification/TestBenchClockGenerator.sv"
#    "/home/matsuo/workspace/rsd/Processor/Project/Vivado/TargetBoards/Zedboard/code.hex"
#    "/home/matsuo/workspace/rsd/Processor/Src/Verification/TestMain.sv"
#    "/home/matsuo/workspace/rsd/Processor/Src/BasicMacros.sv"
#
#*****************************************************************************************

# Set the reference directory for source file relative paths (by default the value is script directory path)
set origin_dir "$env(RSD_ROOT)/Processor/Project/Vivado/TargetBoards/Zedboard"

# Use origin directory path location variable, if specified in the tcl shell
if { [info exists ::origin_dir_loc] } {
  set origin_dir $::origin_dir_loc
}

# Set the project name
set _xil_proj_name_ "rsd_post_synthesis"

# Use project name variable, if specified in the tcl shell
if { [info exists ::user_project_name] } {
  set _xil_proj_name_ $::user_project_name
}

variable script_file
set script_file "create_post_synthesis_project.tcl"

# Help information for this script
proc print_help {} {
  variable script_file
  puts "\nDescription:"
  puts "Recreate a Vivado project from this script. The created project will be"
  puts "functionally equivalent to the original project for which this script was"
  puts "generated. The script contains commands for creating a project, filesets,"
  puts "runs, adding/importing sources and setting properties on various objects.\n"
  puts "Syntax:"
  puts "$script_file"
  puts "$script_file -tclargs \[--origin_dir <path>\]"
  puts "$script_file -tclargs \[--project_name <name>\]"
  puts "$script_file -tclargs \[--help\]\n"
  puts "Usage:"
  puts "Name                   Description"
  puts "-------------------------------------------------------------------------"
  puts "\[--origin_dir <path>\]  Determine source file paths wrt this path. Default"
  puts "                       origin_dir path value is \".\", otherwise, the value"
  puts "                       that was set with the \"-paths_relative_to\" switch"
  puts "                       when this script was generated.\n"
  puts "\[--project_name <name>\] Create project with the specified name. Default"
  puts "                       name is the name of the project from where this"
  puts "                       script was generated.\n"
  puts "\[--help\]               Print help information for this script"
  puts "-------------------------------------------------------------------------\n"
  exit 0
}

if { $::argc > 0 } {
  for {set i 0} {$i < $::argc} {incr i} {
    set option [string trim [lindex $::argv $i]]
    switch -regexp -- $option {
      "--origin_dir"   { incr i; set origin_dir [lindex $::argv $i] }
      "--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
      "--help"         { print_help }
      default {
        if { [regexp {^-} $option] } {
          puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
          return 1
        }
      }
    }
  }
}

# Set the directory path for the original project from where this script was exported
set orig_proj_dir "[file normalize "$origin_dir/rsd_post_synthesis"]"

# Create project
create_project ${_xil_proj_name_} $origin_dir/${_xil_proj_name_} -part xc7z020clg484-1

# Set the directory path for the new project
set proj_dir [get_property directory [current_project]]

# Set project properties
set obj [current_project]
set_property -name "board_part" -value "em.avnet.com:zed:part0:1.4" -objects $obj
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
set_property -name "enable_vhdl_2008" -value "1" -objects $obj
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
set_property -name "platform.board_id" -value "zed" -objects $obj
set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
set_property -name "simulator_language" -value "Mixed" -objects $obj
set_property -name "webtalk.xsim_launch_sim" -value "28" -objects $obj

# Create 'sources_1' fileset (if not found)
if {[string equal [get_filesets -quiet sources_1] ""]} {
  create_fileset -srcset sources_1
}

# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
set files [list \
