Skip to content
[Jenkins]Jenkins
log in

Workspace

/ rv3n /
.git
.Xil
build
FPGA
rtl
sim
testbench
.gitattributesSep 7, 2026, 1:18:05 AM66 B
build_digilent_arty_a7_100t.tclSep 7, 2026, 1:18:46 AM3.39 KiB
clockInfo.txtSep 7, 2026, 1:20:49 AM375 B
diagram.pngSep 7, 2026, 1:18:05 AM57.29 KiB
digilent_arty_a7_100t.bitSep 7, 2026, 1:22:05 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptSep 7, 2026, 1:21:01 AM23.58 KiB
digilent_arty_a7_control_sets.rptSep 7, 2026, 1:21:00 AM26.53 KiB
digilent_arty_a7_drc.rptSep 7, 2026, 1:21:42 AM2.34 KiB
digilent_arty_a7_io.rptSep 7, 2026, 1:21:00 AM96.81 KiB
digilent_arty_a7_power.rptSep 7, 2026, 1:21:45 AM9.05 KiB
digilent_arty_a7_route_status.rptSep 7, 2026, 1:21:41 AM651 B
digilent_arty_a7_timing.rptSep 7, 2026, 1:21:43 AM22.74 KiB
digilent_arty_a7_utilization_hierarchical_place.rptSep 7, 2026, 1:21:00 AM6.36 KiB
digilent_arty_a7_utilization_place.rptSep 7, 2026, 1:21:00 AM10.65 KiB
LICENSESep 7, 2026, 1:18:05 AM11.06 KiB
processor_ci_defines.vhSep 7, 2026, 1:18:46 AM300 B
README.mdSep 7, 2026, 1:18:05 AM3.88 KiB