Skip to content
[Jenkins]Jenkins
log in

Workspace

/ rv3n /
.git
.Xil
build
FPGA
rtl
sim
testbench
.gitattributesJul 31, 2026, 1:18:04 AM66 B
build_digilent_arty_a7_100t.tclJul 31, 2026, 1:18:45 AM3.39 KiB
clockInfo.txtJul 31, 2026, 1:20:50 AM375 B
diagram.pngJul 31, 2026, 1:18:04 AM57.29 KiB
digilent_arty_a7_100t.bitJul 31, 2026, 1:22:06 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptJul 31, 2026, 1:21:02 AM23.58 KiB
digilent_arty_a7_control_sets.rptJul 31, 2026, 1:21:01 AM26.53 KiB
digilent_arty_a7_drc.rptJul 31, 2026, 1:21:43 AM2.34 KiB
digilent_arty_a7_io.rptJul 31, 2026, 1:21:01 AM96.81 KiB
digilent_arty_a7_power.rptJul 31, 2026, 1:21:46 AM9.05 KiB
digilent_arty_a7_route_status.rptJul 31, 2026, 1:21:42 AM651 B
digilent_arty_a7_timing.rptJul 31, 2026, 1:21:44 AM22.74 KiB
digilent_arty_a7_utilization_hierarchical_place.rptJul 31, 2026, 1:21:01 AM6.36 KiB
digilent_arty_a7_utilization_place.rptJul 31, 2026, 1:21:01 AM10.65 KiB
LICENSEJul 31, 2026, 1:18:04 AM11.06 KiB
processor_ci_defines.vhJul 31, 2026, 1:18:45 AM300 B
README.mdJul 31, 2026, 1:18:04 AM3.88 KiB