Skip to content
[Jenkins]Jenkins
log in

Workspace

/ rv3n /
.git
.Xil
build
FPGA
rtl
sim
testbench
.gitattributesSep 4, 2026, 1:18:06 AM66 B
build_digilent_arty_a7_100t.tclSep 4, 2026, 1:18:51 AM3.39 KiB
clockInfo.txtSep 4, 2026, 1:20:54 AM375 B
diagram.pngSep 4, 2026, 1:18:06 AM57.29 KiB
digilent_arty_a7_100t.bitSep 4, 2026, 1:22:12 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptSep 4, 2026, 1:21:08 AM23.58 KiB
digilent_arty_a7_control_sets.rptSep 4, 2026, 1:21:07 AM26.53 KiB
digilent_arty_a7_drc.rptSep 4, 2026, 1:21:49 AM2.34 KiB
digilent_arty_a7_io.rptSep 4, 2026, 1:21:07 AM96.81 KiB
digilent_arty_a7_power.rptSep 4, 2026, 1:21:52 AM9.05 KiB
digilent_arty_a7_route_status.rptSep 4, 2026, 1:21:48 AM651 B
digilent_arty_a7_timing.rptSep 4, 2026, 1:21:50 AM22.74 KiB
digilent_arty_a7_utilization_hierarchical_place.rptSep 4, 2026, 1:21:06 AM6.36 KiB
digilent_arty_a7_utilization_place.rptSep 4, 2026, 1:21:06 AM10.65 KiB
LICENSESep 4, 2026, 1:18:06 AM11.06 KiB
processor_ci_defines.vhSep 4, 2026, 1:18:51 AM300 B
README.mdSep 4, 2026, 1:18:06 AM3.88 KiB