Skip to content

Workspace

/ rv3n /
.git
.Xil
build
FPGA
rtl
sim
testbench
.gitattributesJul 15, 2026, 1:18:03 AM66 B
build_digilent_arty_a7_100t.tclJul 15, 2026, 1:18:44 AM3.39 KiB
clockInfo.txtJul 15, 2026, 1:20:45 AM375 B
diagram.pngJul 15, 2026, 1:18:03 AM57.29 KiB
digilent_arty_a7_100t.bitJul 15, 2026, 1:22:00 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptJul 15, 2026, 1:20:57 AM23.58 KiB
digilent_arty_a7_control_sets.rptJul 15, 2026, 1:20:56 AM26.53 KiB
digilent_arty_a7_drc.rptJul 15, 2026, 1:21:38 AM2.34 KiB
digilent_arty_a7_io.rptJul 15, 2026, 1:20:56 AM96.81 KiB
digilent_arty_a7_power.rptJul 15, 2026, 1:21:40 AM9.05 KiB
digilent_arty_a7_route_status.rptJul 15, 2026, 1:21:36 AM651 B
digilent_arty_a7_timing.rptJul 15, 2026, 1:21:39 AM22.74 KiB
digilent_arty_a7_utilization_hierarchical_place.rptJul 15, 2026, 1:20:56 AM6.36 KiB
digilent_arty_a7_utilization_place.rptJul 15, 2026, 1:20:56 AM10.65 KiB
LICENSEJul 15, 2026, 1:18:03 AM11.06 KiB
processor_ci_defines.vhJul 15, 2026, 1:18:44 AM300 B
README.mdJul 15, 2026, 1:18:03 AM3.88 KiB