| .git |
| .Xil |
| build |
| FPGA |
| rtl |
| sim |
| testbench |
| .gitattributes | Jul 15, 2026, 1:18:03 AM | 66 B | |
| build_digilent_arty_a7_100t.tcl | Jul 15, 2026, 1:18:44 AM | 3.39 KiB | |
| clockInfo.txt | Jul 15, 2026, 1:20:45 AM | 375 B | |
| diagram.png | Jul 15, 2026, 1:18:03 AM | 57.29 KiB | |
| digilent_arty_a7_100t.bit | Jul 15, 2026, 1:22:00 AM | 3.65 MiB | |
| digilent_arty_a7_clock_utilization.rpt | Jul 15, 2026, 1:20:57 AM | 23.58 KiB | |
| digilent_arty_a7_control_sets.rpt | Jul 15, 2026, 1:20:56 AM | 26.53 KiB | |
| digilent_arty_a7_drc.rpt | Jul 15, 2026, 1:21:38 AM | 2.34 KiB | |
| digilent_arty_a7_io.rpt | Jul 15, 2026, 1:20:56 AM | 96.81 KiB | |
| digilent_arty_a7_power.rpt | Jul 15, 2026, 1:21:40 AM | 9.05 KiB | |
| digilent_arty_a7_route_status.rpt | Jul 15, 2026, 1:21:36 AM | 651 B | |
| digilent_arty_a7_timing.rpt | Jul 15, 2026, 1:21:39 AM | 22.74 KiB | |
| digilent_arty_a7_utilization_hierarchical_place.rpt | Jul 15, 2026, 1:20:56 AM | 6.36 KiB | |
| digilent_arty_a7_utilization_place.rpt | Jul 15, 2026, 1:20:56 AM | 10.65 KiB | |
| LICENSE | Jul 15, 2026, 1:18:03 AM | 11.06 KiB | |
| processor_ci_defines.vh | Jul 15, 2026, 1:18:44 AM | 300 B | |
| README.md | Jul 15, 2026, 1:18:03 AM | 3.88 KiB | |
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