Started by timer [Pipeline] Start of Pipeline [Pipeline] node Running on Jenkins in /var/jenkins_home/workspace/rv3n [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -rf test_results_1776043346.2084181.xml [Pipeline] sh + rm -rf rv3n [Pipeline] sh + git clone --recursive --depth=1 https://github.com/risclite/rv3n rv3n Cloning into 'rv3n'... [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Simulation) [Pipeline] dir Running in /var/jenkins_home/workspace/rv3n/rv3n [Pipeline] { [Pipeline] echo FPGA > Simulation [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Utilities) [Pipeline] dir Running in /var/jenkins_home/workspace/rv3n/rv3n [Pipeline] { [Pipeline] sh + pwd + python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/rv3n/rv3n -c /eda/processor_ci/config -o /jenkins/processor_ci_utils/labels Trying to read file: /var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_top.v Trying to read file: /var/jenkins_home/workspace/rv3n/rv3n/rtl/define.v Trying to read file: /var/jenkins_home/workspace/rv3n/rv3n/rtl/define_para.v Trying to read file: /var/jenkins_home/workspace/rv3n/rv3n/rtl/include_func.v Trying to read file: /var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_chain_manager.v Trying to read file: /var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_csr.v Cache-related signals in rv3n_chain_manager.v Cache-related signals in include_func.v Cache-related signals in rv3n_stage_id.v Cache-related signals in rv3n_stage_dc.v Results saved to /jenkins/processor_ci_utils/labels/rv3n.json [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Build Pipeline) [Pipeline] parallel [Pipeline] { (Branch: digilent_arty_a7_100t) [Pipeline] stage [Pipeline] { (digilent_arty_a7_100t) [Pipeline] lock Trying to acquire lock on [Resource: digilent_arty_a7_100t] The resource [digilent_arty_a7_100t] is locked by build Grande-Risco-5 #551 #551 since Apr 14, 2026, 1:15 AM. [Resource: digilent_arty_a7_100t] is not free, waiting for execution ... [Required resources: [digilent_arty_a7_100t]] added into queue at position 0 Lock acquired on [Resource: digilent_arty_a7_100t] [Pipeline] { [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] dir Running in /var/jenkins_home/workspace/rv3n/rv3n [Pipeline] { [Pipeline] echo Starting synthesis for FPGA digilent_arty_a7_100t. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p rv3n -b digilent_arty_a7_100t [LOCK] Criado: run.lock File 'processor_ci_defines.vh' generated for board: 'digilent_arty_a7_100t'. Final configuration file generated at /var/jenkins_home/workspace/rv3n/rv3n/build_digilent_arty_a7_100t.tcl [LOCK] Removido: run.lock Makefile executed successfully. Makefile output: Building the Design... /eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source /var/jenkins_home/workspace/rv3n/rv3n/build_digilent_arty_a7_100t.tcl ****** Vivado v2023.2 (64-bit) **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023 **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023 **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023 ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved. source /var/jenkins_home/workspace/rv3n/rv3n/build_digilent_arty_a7_100t.tcl # read_verilog -sv /eda/processor_ci/rtl/rv3n.sv read_verilog: Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 1320.000 ; gain = 0.023 ; free physical = 1807 ; free virtual = 25826 # read_verilog /var/jenkins_home/workspace/rv3n/rv3n/rtl/define.v # read_verilog /var/jenkins_home/workspace/rv3n/rv3n/rtl/define_para.v # read_verilog /var/jenkins_home/workspace/rv3n/rv3n/rtl/include_func.v # read_verilog /var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_chain_manager.v # read_verilog /var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_csr.v # read_verilog /var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_func_jcond.v # read_verilog /var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_func_lsu.v # read_verilog /var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_func_muldiv.v # read_verilog /var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_func_op.v # read_verilog /var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_gsr.v # read_verilog /var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_predictor.v # read_verilog /var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_stage_ch.v # read_verilog /var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_stage_dc.v # read_verilog /var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_stage_id.v # read_verilog /var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_stage_if.v # read_verilog /var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_top.v # set_property include_dirs [list "/var/jenkins_home/workspace/rv3n/rv3n/rtl" ] [get_filesets sources_1] # read_verilog -sv /eda/processor-ci-controller/modules/uart.sv # read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v # read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v # read_verilog -sv /eda/processor_ci/internal/ahblite_to_wishbone.sv # read_verilog -sv /eda/processor_ci/internal/axi4_to_wishbone.sv # read_verilog -sv /eda/processor_ci/internal/axi4lite_to_wishbone.sv # read_verilog -sv /eda/processor-ci-controller/rtl/fifo.sv # read_verilog -sv /eda/processor-ci-controller/rtl/reset.sv # read_verilog -sv /eda/processor-ci-controller/rtl/clk_divider.sv # read_verilog -sv /eda/processor-ci-controller/rtl/memory.sv # read_verilog -sv /eda/processor-ci-controller/rtl/interpreter.sv # read_verilog -sv /eda/processor-ci-controller/rtl/controller.sv # read_verilog -sv /eda/processor-ci-controller/rtl/timer.sv # read_verilog -sv /eda/processor_ci/internal/fpga_top.sv # set_param general.maxThreads 16 # read_xdc "/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc" # set_property PROCESSING_ORDER EARLY [get_files /eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] # synth_design -top "fpga_top" -part "xc7a100tcsg324-1" Command: synth_design -top fpga_top -part xc7a100tcsg324-1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t' INFO: [Device 21-403] Loading part xc7a100tcsg324-1 INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes. INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes INFO: [Synth 8-7075] Helper process launched with PID 2155674 --------------------------------------------------------------------------------- Starting RTL Elaboration : Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2031.785 ; gain = 402.746 ; free physical = 864 ; free virtual = 24883 --------------------------------------------------------------------------------- WARNING: [Synth 8-6901] identifier 'wstrb' is used before its declaration [/eda/processor_ci/internal/ahblite_to_wishbone.sv:79] WARNING: [Synth 8-6901] identifier 'timer_data_out' is used before its declaration [/eda/processor-ci-controller/rtl/controller.sv:149] WARNING: [Synth 8-9535] ignoring re-definition of command line macro 'SYNTHESIS' [/eda/processor_ci/internal/fpga_top.sv:7] WARNING: [Synth 8-11145] root scope declaration is not allowed in Verilog 95/2K mode [/var/jenkins_home/workspace/rv3n/rv3n/rtl/include_func.v:36] WARNING: [Synth 8-11145] root scope declaration is not allowed in Verilog 95/2K mode [/var/jenkins_home/workspace/rv3n/rv3n/rtl/include_func.v:465] WARNING: [Synth 8-11145] root scope declaration is not allowed in Verilog 95/2K mode [/var/jenkins_home/workspace/rv3n/rv3n/rtl/include_func.v:513] WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:16] WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:16] INFO: [Synth 8-6157] synthesizing module 'fpga_top' [/eda/processor_ci/internal/fpga_top.sv:8] INFO: [Synth 8-6157] synthesizing module 'processorci_top' [/eda/processor_ci/rtl/rv3n.sv:9] INFO: [Synth 8-6157] synthesizing module 'Controller' [/eda/processor-ci-controller/rtl/controller.sv:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer Parameter BUFFER_SIZE bound to: 8 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer Parameter BUS_WIDTH bound to: 32 - type: integer Parameter WORD_SIZE_BY bound to: 4 - type: integer Parameter ID bound to: 1095914585 - type: integer Parameter RESET_CLK_CYCLES bound to: 20 - type: integer Parameter MEMORY_FILE bound to: (null) - type: string Parameter MEMORY_SIZE bound to: 8192 - type: integer INFO: [Synth 8-6157] synthesizing module 'ClkDivider' [/eda/processor-ci-controller/rtl/clk_divider.sv:1] Parameter COUNTER_BITS bound to: 32 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer INFO: [Synth 8-6155] done synthesizing module 'ClkDivider' (0#1) [/eda/processor-ci-controller/rtl/clk_divider.sv:1] INFO: [Synth 8-6157] synthesizing module 'Interpreter' [/eda/processor-ci-controller/rtl/interpreter.sv:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer Parameter BUS_WIDTH bound to: 32 - type: integer Parameter ID bound to: 1095914585 - type: integer Parameter RESET_CLK_CYCLES bound to: 20 - type: integer INFO: [Synth 8-6155] done synthesizing module 'Interpreter' (0#1) [/eda/processor-ci-controller/rtl/interpreter.sv:1] INFO: [Synth 8-6157] synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.sv:1] Parameter CLK_FREQ bound to: 50000000 - type: integer Parameter BIT_RATE bound to: 115200 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer Parameter BUFFER_SIZE bound to: 8 - type: integer Parameter WORD_SIZE_BY bound to: 4 - type: integer INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/modules/uart.sv:66] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/modules/uart.sv:125] INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/modules/uart.sv:199] INFO: [Synth 8-226] default block is never used [/eda/processor-ci-controller/modules/uart.sv:199] INFO: [Synth 8-6157] synthesizing module 'FIFO' [/eda/processor-ci-controller/rtl/fifo.sv:1] Parameter DEPTH bound to: 8 - type: integer Parameter WIDTH bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/eda/processor-ci-controller/rtl/fifo.sv:1] INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 50000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9] INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10] Parameter BIT_RATE bound to: 115200 - type: integer Parameter CLK_HZ bound to: 50000000 - type: integer Parameter PAYLOAD_BITS bound to: 8 - type: integer INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10] INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/eda/processor-ci-controller/modules/uart.sv:1] INFO: [Synth 8-6157] synthesizing module 'Memory' [/eda/processor-ci-controller/rtl/memory.sv:1] Parameter MEMORY_FILE bound to: (null) - type: string Parameter MEMORY_SIZE bound to: 8192 - type: integer INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/eda/processor-ci-controller/rtl/memory.sv:1] INFO: [Synth 8-6157] synthesizing module 'Timer' [/eda/processor-ci-controller/rtl/timer.sv:1] INFO: [Synth 8-6155] done synthesizing module 'Timer' (0#1) [/eda/processor-ci-controller/rtl/timer.sv:1] INFO: [Synth 8-6157] synthesizing module 'Memory__parameterized0' [/eda/processor-ci-controller/rtl/memory.sv:1] Parameter MEMORY_SIZE bound to: 4096 - type: integer INFO: [Synth 8-6155] done synthesizing module 'Memory__parameterized0' (0#1) [/eda/processor-ci-controller/rtl/memory.sv:1] INFO: [Synth 8-6155] done synthesizing module 'Controller' (0#1) [/eda/processor-ci-controller/rtl/controller.sv:1] INFO: [Synth 8-6157] synthesizing module 'rv3n_top' [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_top.v:21] INFO: [Synth 8-6157] synthesizing module 'rv3n_stage_ch' [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_stage_ch.v:21] INFO: [Synth 8-6155] done synthesizing module 'rv3n_stage_ch' (0#1) [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_stage_ch.v:21] INFO: [Synth 8-6157] synthesizing module 'rv3n_func_op' [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_func_op.v:21] INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_func_op.v:76] INFO: [Synth 8-6155] done synthesizing module 'rv3n_func_op' (0#1) [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_func_op.v:21] INFO: [Synth 8-6157] synthesizing module 'rv3n_stage_if' [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_stage_if.v:21] INFO: [Synth 8-6155] done synthesizing module 'rv3n_stage_if' (0#1) [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_stage_if.v:21] INFO: [Synth 8-6157] synthesizing module 'rv3n_stage_dc' [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_stage_dc.v:21] INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/rv3n/rv3n/rtl/include_func.v:131] INFO: [Synth 8-226] default block is never used [/var/jenkins_home/workspace/rv3n/rv3n/rtl/include_func.v:194] INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/rv3n/rv3n/rtl/include_func.v:314] INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/rv3n/rv3n/rtl/include_func.v:474] INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/rv3n/rv3n/rtl/include_func.v:488] INFO: [Synth 8-6155] done synthesizing module 'rv3n_stage_dc' (0#1) [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_stage_dc.v:21] INFO: [Synth 8-6157] synthesizing module 'rv3n_stage_id' [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_stage_id.v:21] INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_stage_id.v:298] INFO: [Synth 8-6155] done synthesizing module 'rv3n_stage_id' (0#1) [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_stage_id.v:21] INFO: [Synth 8-6157] synthesizing module 'rv3n_chain_manager' [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_chain_manager.v:21] INFO: [Synth 8-6157] synthesizing module 'get_rs_available' [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_chain_manager.v:586] INFO: [Synth 8-6155] done synthesizing module 'get_rs_available' (0#1) [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_chain_manager.v:586] INFO: [Synth 8-6157] synthesizing module 'shift_rs_map' [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_chain_manager.v:567] INFO: [Synth 8-6155] done synthesizing module 'shift_rs_map' (0#1) [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_chain_manager.v:567] INFO: [Synth 8-6155] done synthesizing module 'rv3n_chain_manager' (0#1) [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_chain_manager.v:21] INFO: [Synth 8-6157] synthesizing module 'rv3n_func_lsu' [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_func_lsu.v:21] INFO: [Synth 8-6155] done synthesizing module 'rv3n_func_lsu' (0#1) [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_func_lsu.v:21] INFO: [Synth 8-6157] synthesizing module 'rv3n_func_muldiv' [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_func_muldiv.v:22] INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_func_muldiv.v:108] INFO: [Synth 8-6155] done synthesizing module 'rv3n_func_muldiv' (0#1) [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_func_muldiv.v:22] INFO: [Synth 8-6157] synthesizing module 'rv3n_func_jcond' [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_func_jcond.v:21] INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_func_jcond.v:68] INFO: [Synth 8-6155] done synthesizing module 'rv3n_func_jcond' (0#1) [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_func_jcond.v:21] INFO: [Synth 8-6157] synthesizing module 'rv3n_predictor' [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_predictor.v:29] INFO: [Synth 8-6155] done synthesizing module 'rv3n_predictor' (0#1) [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_predictor.v:29] INFO: [Synth 8-6157] synthesizing module 'rv3n_gsr' [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_gsr.v:22] INFO: [Synth 8-6155] done synthesizing module 'rv3n_gsr' (0#1) [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_gsr.v:22] INFO: [Synth 8-6157] synthesizing module 'rv3n_csr' [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_csr.v:22] INFO: [Synth 8-155] case statement is not full and has no default [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_csr.v:106] INFO: [Synth 8-6155] done synthesizing module 'rv3n_csr' (0#1) [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_csr.v:22] INFO: [Synth 8-6155] done synthesizing module 'rv3n_top' (0#1) [/var/jenkins_home/workspace/rv3n/rv3n/rtl/rv3n_top.v:21] INFO: [Synth 8-6155] done synthesizing module 'processorci_top' (0#1) [/eda/processor_ci/rtl/rv3n.sv:9] INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/eda/processor-ci-controller/rtl/reset.sv:1] Parameter CYCLES bound to: 32'sb00000000000000000000000000010100 INFO: [Synth 8-294] found qualifier unique on case statement: implementing as parallel_case [/eda/processor-ci-controller/rtl/reset.sv:32] INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/eda/processor-ci-controller/rtl/reset.sv:1] WARNING: [Synth 8-7071] port 'start' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/internal/fpga_top.sv:98] WARNING: [Synth 8-7071] port 'rst_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor_ci/internal/fpga_top.sv:98] WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 4 connections declared, but only 2 given [/eda/processor_ci/internal/fpga_top.sv:98] INFO: [Synth 8-6155] done synthesizing module 'fpga_top' (0#1) [/eda/processor_ci/internal/fpga_top.sv:8] WARNING: [Synth 8-3848] Net intr_o in module/entity Controller does not have driver. [/eda/processor-ci-controller/rtl/controller.sv:25] WARNING: [Synth 8-3848] Net miso in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/rv3n.sv:22] WARNING: [Synth 8-3848] Net core_data_out in module/entity processorci_top does not have driver. [/eda/processor_ci/rtl/rv3n.sv:66] WARNING: [Synth 8-7129] Port func_csr_req_para[7] in module rv3n_csr is either unconnected or has no load WARNING: [Synth 8-7129] Port func_csr_req_para[6] in module rv3n_csr is either unconnected or has no load WARNING: [Synth 8-7129] Port func_csr_req_para[3] in module rv3n_csr is either unconnected or has no load WARNING: [Synth 8-7129] Port func_csr_req_imm[12] in module rv3n_csr is either unconnected or has no load WARNING: [Synth 8-7129] Port func_csr_req_imm[11] in module rv3n_csr is either unconnected or has no load WARNING: [Synth 8-7129] Port func_csr_req_imm[10] in module rv3n_csr is either unconnected or has no load WARNING: [Synth 8-7129] Port func_csr_req_imm[9] in module rv3n_csr is either unconnected or has no load WARNING: [Synth 8-7129] Port func_csr_req_imm[8] in module rv3n_csr is either unconnected or has no load WARNING: [Synth 8-7129] Port func_csr_req_imm[7] in module rv3n_csr is either unconnected or has no load WARNING: [Synth 8-7129] Port func_csr_req_imm[6] in module rv3n_csr is either unconnected or has no load WARNING: [Synth 8-7129] Port func_csr_req_imm[5] in module rv3n_csr is either unconnected or has no load WARNING: [Synth 8-7129] Port func_csr_req_imm[4] in module rv3n_csr is either unconnected or has no load WARNING: [Synth 8-7129] Port func_csr_req_imm[3] in module rv3n_csr is either unconnected or has no load WARNING: [Synth 8-7129] Port func_csr_req_imm[2] in module rv3n_csr is either unconnected or has no load WARNING: [Synth 8-7129] Port func_csr_req_imm[1] in module rv3n_csr is either unconnected or has no load WARNING: [Synth 8-7129] Port func_csr_req_imm[0] in module rv3n_csr is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_para[7] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_para[6] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_para[5] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_para[4] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_para[3] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_imm[12] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_imm[11] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_imm[10] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_imm[9] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_imm[8] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_imm[7] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_imm[6] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_imm[5] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_imm[4] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_imm[3] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_imm[2] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_imm[1] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_imm[0] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[31] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[30] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[29] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[28] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[27] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[26] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[25] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[24] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[23] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[22] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[21] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[20] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[19] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[18] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[17] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[16] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[15] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[14] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[13] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[12] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[11] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[10] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[9] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[8] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[7] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[6] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[5] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[4] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[3] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[2] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[1] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_muldiv_req_pc[0] in module rv3n_func_muldiv is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_para[7] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_para[6] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[31] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[30] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[29] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[28] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[27] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[26] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[25] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[24] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[23] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[22] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[21] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[20] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[19] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[18] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[17] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[16] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[15] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[14] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[13] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[12] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[11] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[10] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[9] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[8] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[7] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[6] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[5] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[4] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[3] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[2] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[1] in module rv3n_func_lsu is either unconnected or has no load WARNING: [Synth 8-7129] Port func_lsu_req_pc[0] in module rv3n_func_lsu is either unconnected or has no load INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2145.723 ; gain = 516.684 ; free physical = 727 ; free virtual = 24748 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2163.535 ; gain = 534.496 ; free physical = 724 ; free virtual = 24745 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 2163.535 ; gain = 534.496 ; free physical = 724 ; free virtual = 24745 --------------------------------------------------------------------------------- Netlist sorting complete. Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.08 . Memory (MB): peak = 2163.535 ; gain = 0.000 ; free physical = 723 ; free virtual = 24744 INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/fpga_top_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/fpga_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Completed Processing XDC Constraints Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2311.285 ; gain = 0.000 ; free physical = 702 ; free virtual = 24723 INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. Constraint Validation Runtime : Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2311.320 ; gain = 0.000 ; free physical = 699 ; free virtual = 24720 --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2311.320 ; gain = 682.281 ; free physical = 692 ; free virtual = 24714 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7a100tcsg324-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2311.320 ; gain = 682.281 ; free physical = 691 ; free virtual = 24713 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:16 ; elapsed = 00:00:16 . Memory (MB): peak = 2311.320 ; gain = 682.281 ; free physical = 690 ; free virtual = 24712 --------------------------------------------------------------------------------- INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_rx' INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tx' INFO: [Synth 8-802] inferred FSM for state register 'state_read_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'state_write_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'tx_read_fifo_state_reg' in module 'UART' INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_RECV | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_rx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- FSM_IDLE | 00 | 000 FSM_START | 11 | 001 FSM_SEND | 10 | 010 FSM_STOP | 01 | 011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tx' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 000 | 0000 READ | 001 | 0001 COPY_READ_BUFFER | 010 | 0100 WB | 011 | 0010 FINISH | 100 | 0011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_read_reg' using encoding 'sequential' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- IDLE | 000 | 0000 COPY_WRITE_BUFFER | 001 | 0100 WRITE | 010 | 0101 WB | 011 | 0010 FINISH | 100 | 0011 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_write_reg' using encoding 'sequential' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- TX_FIFO_IDLE | 0001 | 00 TX_FIFO_READ_FIFO | 0010 | 01 TX_FIFO_WRITE_TX | 0100 | 10 TX_FIFO_WAIT | 1000 | 11 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'tx_read_fifo_state_reg' using encoding 'one-hot' in module 'UART' --------------------------------------------------------------------------------------------------- State | New Encoding | Previous Encoding --------------------------------------------------------------------------------------------------- INIT | 001 | 00 RESET_COUNTER | 010 | 01 IDLE | 100 | 10 --------------------------------------------------------------------------------------------------- INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'one-hot' in module 'ResetBootSystem' --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:19 ; elapsed = 00:00:18 . Memory (MB): peak = 2311.320 ; gain = 682.281 ; free physical = 684 ; free virtual = 24707 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Adders : 2 Input 64 Bit Adders := 2 2 Input 35 Bit Adders := 2 3 Input 33 Bit Adders := 1 2 Input 33 Bit Adders := 1 2 Input 32 Bit Adders := 13 3 Input 32 Bit Adders := 2 2 Input 25 Bit Adders := 2 2 Input 24 Bit Adders := 2 2 Input 10 Bit Adders := 2 2 Input 8 Bit Adders := 1 2 Input 7 Bit Adders := 1 2 Input 6 Bit Adders := 1 3 Input 5 Bit Adders := 1 2 Input 5 Bit Adders := 5 2 Input 4 Bit Adders := 4 2 Input 3 Bit Adders := 7 4 Input 3 Bit Adders := 1 3 Input 3 Bit Adders := 1 2 Input 2 Bit Adders := 1 +---XORs : 2 Input 32 Bit XORs := 1 2 Input 3 Bit XORs := 4 2 Input 1 Bit XORs := 4 +---Registers : 153 Bit Registers := 3 96 Bit Registers := 1 78 Bit Registers := 1 64 Bit Registers := 4 35 Bit Registers := 1 32 Bit Registers := 68 25 Bit Registers := 1 24 Bit Registers := 4 15 Bit Registers := 2 12 Bit Registers := 1 10 Bit Registers := 2 8 Bit Registers := 12 7 Bit Registers := 1 6 Bit Registers := 3 5 Bit Registers := 6 4 Bit Registers := 3 3 Bit Registers := 32 2 Bit Registers := 2 1 Bit Registers := 63 +---RAMs : 64K Bit (2048 X 32 bit) RAMs := 1 32K Bit (1024 X 32 bit) RAMs := 1 64 Bit (8 X 8 bit) RAMs := 2 +---Muxes : 2 Input 153 Bit Muxes := 3 2 Input 96 Bit Muxes := 1 4 Input 64 Bit Muxes := 1 2 Input 64 Bit Muxes := 8 48 Input 64 Bit Muxes := 2 2 Input 35 Bit Muxes := 1 5 Input 32 Bit Muxes := 2 2 Input 32 Bit Muxes := 42 15 Input 32 Bit Muxes := 1 12 Input 32 Bit Muxes := 1 4 Input 32 Bit Muxes := 2 8 Input 32 Bit Muxes := 1 2 Input 25 Bit Muxes := 1 48 Input 24 Bit Muxes := 1 3 Input 21 Bit Muxes := 2 2 Input 21 Bit Muxes := 2 2 Input 16 Bit Muxes := 1 2 Input 15 Bit Muxes := 6 5 Input 13 Bit Muxes := 1 12 Input 13 Bit Muxes := 1 2 Input 13 Bit Muxes := 2 48 Input 8 Bit Muxes := 2 2 Input 8 Bit Muxes := 6 24 Input 7 Bit Muxes := 1 2 Input 7 Bit Muxes := 2 2 Input 6 Bit Muxes := 6 5 Input 6 Bit Muxes := 1 15 Input 6 Bit Muxes := 1 7 Input 6 Bit Muxes := 1 8 Input 6 Bit Muxes := 2 12 Input 6 Bit Muxes := 1 3 Input 6 Bit Muxes := 1 2 Input 5 Bit Muxes := 29 6 Input 5 Bit Muxes := 2 12 Input 5 Bit Muxes := 3 15 Input 5 Bit Muxes := 1 2 Input 4 Bit Muxes := 11 15 Input 4 Bit Muxes := 1 4 Input 4 Bit Muxes := 1 5 Input 3 Bit Muxes := 5 2 Input 3 Bit Muxes := 35 15 Input 3 Bit Muxes := 3 4 Input 3 Bit Muxes := 1 9 Input 3 Bit Muxes := 1 3 Input 3 Bit Muxes := 1 2 Input 2 Bit Muxes := 18 48 Input 2 Bit Muxes := 1 4 Input 2 Bit Muxes := 5 5 Input 2 Bit Muxes := 1 2 Input 1 Bit Muxes := 88 48 Input 1 Bit Muxes := 22 3 Input 1 Bit Muxes := 7 4 Input 1 Bit Muxes := 6 5 Input 1 Bit Muxes := 11 12 Input 1 Bit Muxes := 10 15 Input 1 Bit Muxes := 3 14 Input 1 Bit Muxes := 1 13 Input 1 Bit Muxes := 1 16 Input 1 Bit Muxes := 4 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 240 (col length:80) BRAMs: 270 (col length: RAMB18 80 RAMB36 40) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-7080] Parallel synthesis criteria is not met --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:01:11 ; elapsed = 00:01:11 . Memory (MB): peak = 2311.320 ; gain = 682.281 ; free physical = 603 ; free virtual = 24639 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- ROM: Preliminary Mapping Report +---------------+---------------------+---------------+----------------+ |Module Name | RTL Object | Depth x Width | Implemented As | +---------------+---------------------+---------------+----------------+ |Interpreter | memory_mux_selector | 256x1 | LUT | |rv3n_predictor | predict_bit0 | 32x1 | LUT | |rv3n_predictor | predict_bit1 | 32x1 | LUT | |rv3n_predictor | predict_bit2 | 32x1 | LUT | |rv3n_predictor | predict_bit3 | 32x1 | LUT | |rv3n_predictor | predict_bit | 32x1 | LUT | |Interpreter | memory_mux_selector | 256x1 | LUT | |rv3n_predictor | predict_bit0 | 32x1 | LUT | |rv3n_predictor | predict_bit1 | 32x1 | LUT | |rv3n_predictor | predict_bit2 | 32x1 | LUT | |rv3n_predictor | predict_bit3 | 32x1 | LUT | |rv3n_predictor | predict_bit | 32x1 | LUT | +---------------+---------------------+---------------+----------------+ Distributed RAM: Preliminary Mapping Report (see note below) +------------+-----------------------------------------------+-----------+----------------------+------------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------+-----------------------------------------------+-----------+----------------------+------------------+ |fpga_top | ptop/u_Controller/Uart/tx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |fpga_top | ptop/u_Controller/Uart/rx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |fpga_top | ptop/u_Controller/Core_Memory/memory_reg | Implied | 2 K x 32 | RAM256X1S x 256 | |fpga_top | ptop/u_Controller/Core_Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | +------------+-----------------------------------------------+-----------+----------------------+------------------+ Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once. --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:15 ; elapsed = 00:01:16 . Memory (MB): peak = 2311.320 ; gain = 682.281 ; free physical = 601 ; free virtual = 24637 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:01:21 ; elapsed = 00:01:22 . Memory (MB): peak = 2311.320 ; gain = 682.281 ; free physical = 587 ; free virtual = 24622 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- Distributed RAM: Final Mapping Report +------------+-----------------------------------------------+-----------+----------------------+------------------+ |Module Name | RTL Object | Inference | Size (Depth x Width) | Primitives | +------------+-----------------------------------------------+-----------+----------------------+------------------+ |fpga_top | ptop/u_Controller/Uart/tx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |fpga_top | ptop/u_Controller/Uart/rx_fifo/memory_reg | Implied | 8 x 8 | RAM32M x 2 | |fpga_top | ptop/u_Controller/Core_Memory/memory_reg | Implied | 2 K x 32 | RAM256X1S x 256 | |fpga_top | ptop/u_Controller/Core_Data_Memory/memory_reg | Implied | 1 K x 32 | RAM256X1S x 128 | +------------+-----------------------------------------------+-----------+----------------------+------------------+ --------------------------------------------------------------------------------- Finished ROM, RAM, DSP, Shift Register and Retiming Reporting --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:01:25 ; elapsed = 00:01:26 . Memory (MB): peak = 2311.320 ; gain = 682.281 ; free physical = 578 ; free virtual = 24614 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:01:30 ; elapsed = 00:01:30 . Memory (MB): peak = 2314.254 ; gain = 685.215 ; free physical = 585 ; free virtual = 24621 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:01:30 ; elapsed = 00:01:30 . Memory (MB): peak = 2314.254 ; gain = 685.215 ; free physical = 585 ; free virtual = 24621 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:30 ; elapsed = 00:01:31 . Memory (MB): peak = 2314.254 ; gain = 685.215 ; free physical = 583 ; free virtual = 24619 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:01:30 ; elapsed = 00:01:31 . Memory (MB): peak = 2314.254 ; gain = 685.215 ; free physical = 579 ; free virtual = 24615 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:01:31 ; elapsed = 00:01:32 . Memory (MB): peak = 2314.254 ; gain = 685.215 ; free physical = 583 ; free virtual = 24619 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:01:31 ; elapsed = 00:01:32 . Memory (MB): peak = 2314.254 ; gain = 685.215 ; free physical = 579 ; free virtual = 24615 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+----------+------+ | |Cell |Count | +------+----------+------+ |1 |BUFG | 3| |2 |CARRY4 | 256| |3 |LUT1 | 47| |4 |LUT2 | 544| |5 |LUT3 | 833| |6 |LUT4 | 579| |7 |LUT5 | 1105| |8 |LUT6 | 2759| |9 |MUXF7 | 353| |10 |RAM256X1S | 384| |11 |RAM32M | 2| |12 |RAM32X1D | 4| |13 |FDCE | 2850| |14 |FDPE | 4| |15 |FDRE | 757| |16 |FDSE | 4| |17 |IBUF | 2| |18 |OBUF | 1| |19 |OBUFT | 2| +------+----------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:01:31 ; elapsed = 00:01:32 . Memory (MB): peak = 2314.254 ; gain = 685.215 ; free physical = 577 ; free virtual = 24613 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 225 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:01:27 ; elapsed = 00:01:29 . Memory (MB): peak = 2314.254 ; gain = 537.430 ; free physical = 585 ; free virtual = 24621 Synthesis Optimization Complete : Time (s): cpu = 00:01:31 ; elapsed = 00:01:32 . Memory (MB): peak = 2314.262 ; gain = 685.215 ; free physical = 585 ; free virtual = 24621 INFO: [Project 1-571] Translating synthesized netlist Netlist sorting complete. Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2314.262 ; gain = 0.000 ; free physical = 865 ; free virtual = 24901 INFO: [Netlist 29-17] Analyzing 999 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] WARNING: [Vivado 12-507] No nets matched 'sck_IBUF'. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc:112] Resolution: If [get_] was used to populate the object, check to make sure this command returns at least one valid object. Finished Parsing XDC File [/eda/processor_ci/constraints/digilent_arty_a7_100t.xdc] INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2416.238 ; gain = 0.000 ; free physical = 852 ; free virtual = 24888 INFO: [Project 1-111] Unisim Transformation Summary: A total of 390 instances were transformed. RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 384 instances RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances Synth Design complete | Checksum: 7762600 INFO: [Common 17-83] Releasing license: Synthesis 99 Infos, 117 Warnings, 2 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:01:41 ; elapsed = 00:01:39 . Memory (MB): peak = 2416.273 ; gain = 1096.273 ; free physical = 852 ; free virtual = 24888 INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2141.421; main = 1852.590; forked = 430.017 INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3293.641; main = 2416.242; forked = 982.352 # opt_design Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command opt_design Starting DRC Task INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.7 . Memory (MB): peak = 2480.270 ; gain = 63.996 ; free physical = 853 ; free virtual = 24888 Starting Cache Timing Information Task INFO: [Timing 38-35] Done setting XDC timing constraints. Ending Cache Timing Information Task | Checksum: e2edf5de Time (s): cpu = 00:00:03 ; elapsed = 00:00:02 . Memory (MB): peak = 2557.098 ; gain = 76.828 ; free physical = 807 ; free virtual = 24843 Starting Logic Optimization Task Phase 1 Initialization Phase 1.1 Core Generation And Design Setup Phase 1.1 Core Generation And Design Setup | Checksum: e2edf5de Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2793.098 ; gain = 0.000 ; free physical = 560 ; free virtual = 24596 Phase 1.2 Setup Constraints And Sort Netlist Phase 1.2 Setup Constraints And Sort Netlist | Checksum: e2edf5de Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2793.098 ; gain = 0.000 ; free physical = 560 ; free virtual = 24596 Phase 1 Initialization | Checksum: e2edf5de Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2793.098 ; gain = 0.000 ; free physical = 560 ; free virtual = 24596 Phase 2 Timer Update And Timing Data Collection Phase 2.1 Timer Update Phase 2.1 Timer Update | Checksum: e2edf5de Time (s): cpu = 00:00:00.5 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2793.098 ; gain = 0.000 ; free physical = 560 ; free virtual = 24595 Phase 2.2 Timing Data Collection Phase 2.2 Timing Data Collection | Checksum: e2edf5de Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2793.098 ; gain = 0.000 ; free physical = 560 ; free virtual = 24595 Phase 2 Timer Update And Timing Data Collection | Checksum: e2edf5de Time (s): cpu = 00:00:00.52 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2793.098 ; gain = 0.000 ; free physical = 560 ; free virtual = 24595 Phase 3 Retarget INFO: [Opt 31-1566] Pulled 7 inverters resulting in an inversion of 24 pins INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). Phase 3 Retarget | Checksum: 21ebc1470 Time (s): cpu = 00:00:00.68 ; elapsed = 00:00:00.31 . Memory (MB): peak = 2793.098 ; gain = 0.000 ; free physical = 560 ; free virtual = 24595 Retarget | Checksum: 21ebc1470 INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 11 cells Phase 4 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). Phase 4 Constant propagation | Checksum: 1c5a2575c Time (s): cpu = 00:00:00.76 ; elapsed = 00:00:00.4 . Memory (MB): peak = 2793.098 ; gain = 0.000 ; free physical = 560 ; free virtual = 24595 Constant propagation | Checksum: 1c5a2575c INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 5 Sweep Phase 5 Sweep | Checksum: 2222b5036 Time (s): cpu = 00:00:00.88 ; elapsed = 00:00:00.51 . Memory (MB): peak = 2793.098 ; gain = 0.000 ; free physical = 560 ; free virtual = 24595 Sweep | Checksum: 2222b5036 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1 cells Phase 6 BUFG optimization Phase 6 BUFG optimization | Checksum: 2222b5036 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.6 . Memory (MB): peak = 2825.113 ; gain = 32.016 ; free physical = 559 ; free virtual = 24595 BUFG optimization | Checksum: 2222b5036 INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells. Phase 7 Shift Register Optimization INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs Phase 7 Shift Register Optimization | Checksum: 2222b5036 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.61 . Memory (MB): peak = 2825.113 ; gain = 32.016 ; free physical = 559 ; free virtual = 24595 Shift Register Optimization | Checksum: 2222b5036 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Phase 8 Post Processing Netlist Phase 8 Post Processing Netlist | Checksum: 2222b5036 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.64 . Memory (MB): peak = 2825.113 ; gain = 32.016 ; free physical = 559 ; free virtual = 24595 Post Processing Netlist | Checksum: 2222b5036 INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells Phase 9 Finalization Phase 9.1 Finalizing Design Cores and Updating Shapes Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 163ea0523 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.78 . Memory (MB): peak = 2825.113 ; gain = 32.016 ; free physical = 559 ; free virtual = 24595 Phase 9.2 Verifying Netlist Connectivity Starting Connectivity Check Task Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2825.113 ; gain = 0.000 ; free physical = 559 ; free virtual = 24595 Phase 9.2 Verifying Netlist Connectivity | Checksum: 163ea0523 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.79 . Memory (MB): peak = 2825.113 ; gain = 32.016 ; free physical = 559 ; free virtual = 24595 Phase 9 Finalization | Checksum: 163ea0523 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.8 . Memory (MB): peak = 2825.113 ; gain = 32.016 ; free physical = 559 ; free virtual = 24595 Opt_design Change Summary ========================= ------------------------------------------------------------------------------------------------------------------------- | Phase | #Cells created | #Cells Removed | #Constrained objects preventing optimizations | ------------------------------------------------------------------------------------------------------------------------- | Retarget | 0 | 11 | 0 | | Constant propagation | 0 | 0 | 0 | | Sweep | 0 | 1 | 0 | | BUFG optimization | 0 | 0 | 0 | | Shift Register Optimization | 0 | 0 | 0 | | Post Processing Netlist | 0 | 0 | 0 | ------------------------------------------------------------------------------------------------------------------------- Ending Logic Optimization Task | Checksum: 163ea0523 Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.8 . Memory (MB): peak = 2825.113 ; gain = 32.016 ; free physical = 559 ; free virtual = 24595 INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8 Done building netlist checker database: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2825.113 ; gain = 0.000 ; free physical = 559 ; free virtual = 24595 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. Ending Power Optimization Task | Checksum: 163ea0523 Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2825.113 ; gain = 0.000 ; free physical = 559 ; free virtual = 24595 Starting Final Cleanup Task Ending Final Cleanup Task | Checksum: 163ea0523 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2825.113 ; gain = 0.000 ; free physical = 559 ; free virtual = 24595 Starting Netlist Obfuscation Task Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2825.113 ; gain = 0.000 ; free physical = 559 ; free virtual = 24595 Ending Netlist Obfuscation Task | Checksum: 163ea0523 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2825.113 ; gain = 0.000 ; free physical = 559 ; free virtual = 24595 INFO: [Common 17-83] Releasing license: Implementation 19 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully opt_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:06 . Memory (MB): peak = 2825.113 ; gain = 408.840 ; free physical = 559 ; free virtual = 24595 # place_design Command: place_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-83] Releasing license: Implementation INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Running DRC as a precondition to command place_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs Starting Placer Task Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2857.129 ; gain = 0.000 ; free physical = 557 ; free virtual = 24593 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 108b0a5b5 Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2857.129 ; gain = 0.000 ; free physical = 557 ; free virtual = 24593 Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2857.129 ; gain = 0.000 ; free physical = 557 ; free virtual = 24593 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 17cbc22b5 Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2857.129 ; gain = 0.000 ; free physical = 560 ; free virtual = 24596 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 21ad93e9a Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 560 ; free virtual = 24596 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 21ad93e9a Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 557 ; free virtual = 24593 Phase 1 Placer Initialization | Checksum: 21ad93e9a Time (s): cpu = 00:00:09 ; elapsed = 00:00:04 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 554 ; free virtual = 24589 Phase 2 Global Placement Phase 2.1 Floorplanning Phase 2.1 Floorplanning | Checksum: 1ee90705b Time (s): cpu = 00:00:10 ; elapsed = 00:00:04 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 552 ; free virtual = 24588 Phase 2.2 Update Timing before SLR Path Opt Phase 2.2 Update Timing before SLR Path Opt | Checksum: 234a49fe2 Time (s): cpu = 00:00:10 ; elapsed = 00:00:04 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 546 ; free virtual = 24582 Phase 2.3 Post-Processing in Floorplanning Phase 2.3 Post-Processing in Floorplanning | Checksum: 234a49fe2 Time (s): cpu = 00:00:10 ; elapsed = 00:00:04 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 556 ; free virtual = 24591 Phase 2.4 Global Placement Core Phase 2.4.1 UpdateTiming Before Physical Synthesis Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 190ae8421 Time (s): cpu = 00:00:18 ; elapsed = 00:00:06 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 543 ; free virtual = 24579 Phase 2.4.2 Physical Synthesis In Placer INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 245 LUT instances to create LUTNM shape INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0 INFO: [Physopt 32-1138] End 1 Pass. Optimized 93 nets or LUTs. Breaked 0 LUT, combined 93 existing LUTs and moved 0 existing LUT INFO: [Physopt 32-65] No nets found for high-fanout optimization. INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance. INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell INFO: [Physopt 32-670] No setup violation found. DSP Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register to Pipeline Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. Shift Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. BRAM Register Optimization was not performed. INFO: [Physopt 32-670] No setup violation found. URAM Register Optimization was not performed. INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2864.156 ; gain = 0.000 ; free physical = 555 ; free virtual = 24591 Summary of Physical Synthesis Optimizations ============================================ ----------------------------------------------------------------------------------------------------------------------------------------------------------- | Optimization | Added Cells | Removed Cells | Optimized Cells/Nets | Dont Touch | Iterations | Elapsed | ----------------------------------------------------------------------------------------------------------------------------------------------------------- | LUT Combining | 0 | 93 | 93 | 0 | 1 | 00:00:01 | | Retime | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Very High Fanout | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | DSP Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register to Pipeline | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Shift Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | BRAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | URAM Register | 0 | 0 | 0 | 0 | 0 | 00:00:00 | | Dynamic/Static Region Interface Net Replication | 0 | 0 | 0 | 0 | 1 | 00:00:00 | | Total | 0 | 93 | 93 | 0 | 4 | 00:00:01 | ----------------------------------------------------------------------------------------------------------------------------------------------------------- Phase 2.4.2 Physical Synthesis In Placer | Checksum: 123d6f35d Time (s): cpu = 00:00:19 ; elapsed = 00:00:08 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 555 ; free virtual = 24591 Phase 2.4 Global Placement Core | Checksum: fc73d40b Time (s): cpu = 00:00:20 ; elapsed = 00:00:08 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 554 ; free virtual = 24590 Phase 2 Global Placement | Checksum: fc73d40b Time (s): cpu = 00:00:20 ; elapsed = 00:00:08 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 554 ; free virtual = 24590 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros Phase 3.1 Commit Multi Column Macros | Checksum: eeb1c8a2 Time (s): cpu = 00:00:20 ; elapsed = 00:00:08 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 554 ; free virtual = 24590 Phase 3.2 Commit Most Macros & LUTRAMs Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 19f0f0309 Time (s): cpu = 00:00:21 ; elapsed = 00:00:08 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 554 ; free virtual = 24590 Phase 3.3 Area Swap Optimization Phase 3.3 Area Swap Optimization | Checksum: 1523b758d Time (s): cpu = 00:00:21 ; elapsed = 00:00:08 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 554 ; free virtual = 24590 Phase 3.4 Pipeline Register Optimization Phase 3.4 Pipeline Register Optimization | Checksum: f18c6172 Time (s): cpu = 00:00:21 ; elapsed = 00:00:08 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 554 ; free virtual = 24590 Phase 3.5 Small Shape Detail Placement Phase 3.5 Small Shape Detail Placement | Checksum: 9cb6d285 Time (s): cpu = 00:00:23 ; elapsed = 00:00:11 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 554 ; free virtual = 24591 Phase 3.6 Re-assign LUT pins Phase 3.6 Re-assign LUT pins | Checksum: 8f07eca3 Time (s): cpu = 00:00:24 ; elapsed = 00:00:11 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 554 ; free virtual = 24591 Phase 3.7 Pipeline Register Optimization Phase 3.7 Pipeline Register Optimization | Checksum: 16e58808e Time (s): cpu = 00:00:24 ; elapsed = 00:00:11 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 554 ; free virtual = 24591 Phase 3 Detail Placement | Checksum: 16e58808e Time (s): cpu = 00:00:24 ; elapsed = 00:00:11 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 554 ; free virtual = 24591 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization Post Placement Optimization Initialization | Checksum: c3f6ea5f Phase 4.1.1.1 BUFG Insertion Starting Physical Synthesis Task Phase 1 Physical Synthesis Initialization INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs INFO: [Physopt 32-619] Estimated Timing Summary | WNS=8.875 | TNS=0.000 | Phase 1 Physical Synthesis Initialization | Checksum: e54bf3be Time (s): cpu = 00:00:00.54 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2864.156 ; gain = 0.000 ; free physical = 555 ; free virtual = 24591 INFO: [Place 46-33] Processed net ptop/u_Controller/Interpreter/rst_core, BUFG insertion was skipped due to placement/routing conflicts. INFO: [Place 46-56] BUFG insertion identified 1 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 1, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0. Ending Physical Synthesis Task | Checksum: e54bf3be Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.55 . Memory (MB): peak = 2864.156 ; gain = 0.000 ; free physical = 555 ; free virtual = 24591 Phase 4.1.1.1 BUFG Insertion | Checksum: c3f6ea5f Time (s): cpu = 00:00:32 ; elapsed = 00:00:14 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 555 ; free virtual = 24591 Phase 4.1.1.2 Post Placement Timing Optimization INFO: [Place 30-746] Post Placement Timing Summary WNS=8.875. For the most accurate timing information please run report_timing. Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: fa4d90da Time (s): cpu = 00:00:32 ; elapsed = 00:00:14 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 555 ; free virtual = 24591 Time (s): cpu = 00:00:32 ; elapsed = 00:00:14 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 555 ; free virtual = 24591 Phase 4.1 Post Commit Optimization | Checksum: fa4d90da Time (s): cpu = 00:00:32 ; elapsed = 00:00:14 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 555 ; free virtual = 24591 Phase 4.2 Post Placement Cleanup Phase 4.2 Post Placement Cleanup | Checksum: fa4d90da Time (s): cpu = 00:00:32 ; elapsed = 00:00:14 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 555 ; free virtual = 24591 Phase 4.3 Placer Reporting Phase 4.3.1 Print Estimated Congestion INFO: [Place 30-612] Post-Placement Estimated Congestion ____________________________________________________ | | Global Congestion | Short Congestion | | Direction | Region Size | Region Size | |___________|___________________|___________________| | North| 1x1| 2x2| |___________|___________________|___________________| | South| 1x1| 2x2| |___________|___________________|___________________| | East| 1x1| 1x1| |___________|___________________|___________________| | West| 1x1| 1x1| |___________|___________________|___________________| Phase 4.3.1 Print Estimated Congestion | Checksum: fa4d90da Time (s): cpu = 00:00:32 ; elapsed = 00:00:14 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 555 ; free virtual = 24591 Phase 4.3 Placer Reporting | Checksum: fa4d90da Time (s): cpu = 00:00:32 ; elapsed = 00:00:14 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 554 ; free virtual = 24590 Phase 4.4 Final Placement Cleanup Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2864.156 ; gain = 0.000 ; free physical = 553 ; free virtual = 24589 Time (s): cpu = 00:00:32 ; elapsed = 00:00:14 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 553 ; free virtual = 24589 Phase 4 Post Placement Optimization and Clean-Up | Checksum: 18f212c81 Time (s): cpu = 00:00:32 ; elapsed = 00:00:15 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 546 ; free virtual = 24582 Ending Placer Task | Checksum: 11ee62ff7 Time (s): cpu = 00:00:33 ; elapsed = 00:00:15 . Memory (MB): peak = 2864.156 ; gain = 7.027 ; free physical = 539 ; free virtual = 24575 30 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully place_design: Time (s): cpu = 00:00:34 ; elapsed = 00:00:15 . Memory (MB): peak = 2864.156 ; gain = 39.043 ; free physical = 537 ; free virtual = 24573 # report_utilization -hierarchical -file digilent_arty_a7_utilization_hierarchical_place.rpt # report_utilization -file digilent_arty_a7_utilization_place.rpt # report_io -file digilent_arty_a7_io.rpt report_io: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.07 . Memory (MB): peak = 2864.156 ; gain = 0.000 ; free physical = 557 ; free virtual = 24593 # report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt report_control_sets: Time (s): cpu = 00:00:00.04 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2864.156 ; gain = 0.000 ; free physical = 552 ; free virtual = 24588 # report_clock_utilization -file digilent_arty_a7_clock_utilization.rpt # route_design Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command route_design INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information. Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs Phase 1 Build RT Design Checksum: PlaceDB: 4a324fdf ConstDB: 0 ShapeSum: d4b3e018 RouteDB: 0 Post Restoration Checksum: NetGraph: b3d98246 | NumContArr: 68a31149 | Constraints: c2a8fa9d | Timing: c2a8fa9d Phase 1 Build RT Design | Checksum: 2a1ce88c9 Time (s): cpu = 00:00:38 ; elapsed = 00:00:26 . Memory (MB): peak = 2920.184 ; gain = 0.000 ; free physical = 543 ; free virtual = 24579 Phase 2 Router Initialization Phase 2.1 Fix Topology Constraints Phase 2.1 Fix Topology Constraints | Checksum: 2a1ce88c9 Time (s): cpu = 00:00:38 ; elapsed = 00:00:26 . Memory (MB): peak = 2920.184 ; gain = 0.000 ; free physical = 543 ; free virtual = 24579 Phase 2.2 Pre Route Cleanup Phase 2.2 Pre Route Cleanup | Checksum: 2a1ce88c9 Time (s): cpu = 00:00:38 ; elapsed = 00:00:26 . Memory (MB): peak = 2920.184 ; gain = 0.000 ; free physical = 543 ; free virtual = 24579 Number of Nodes with overlaps = 0 Phase 2.3 Update Timing Phase 2.3 Update Timing | Checksum: 228313a10 Time (s): cpu = 00:00:48 ; elapsed = 00:00:29 . Memory (MB): peak = 2920.184 ; gain = 0.000 ; free physical = 526 ; free virtual = 24563 INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.797 | TNS=0.000 | WHS=0.008 | THS=0.000 | Router Utilization Summary Global Vertical Routing Utilization = 0.0157114 % Global Horizontal Routing Utilization = 0.00134982 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 7872 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 7835 Number of Partially Routed Nets = 37 Number of Node Overlaps = 17 Phase 2 Router Initialization | Checksum: 1f06f15ec Time (s): cpu = 00:00:52 ; elapsed = 00:00:30 . Memory (MB): peak = 2920.184 ; gain = 0.000 ; free physical = 517 ; free virtual = 24554 Phase 3 Initial Routing Phase 3.1 Global Routing Phase 3.1 Global Routing | Checksum: 1f06f15ec Time (s): cpu = 00:00:52 ; elapsed = 00:00:30 . Memory (MB): peak = 2920.184 ; gain = 0.000 ; free physical = 517 ; free virtual = 24554 Phase 3.2 Initial Net Routing Phase 3.2 Initial Net Routing | Checksum: 207767398 Time (s): cpu = 00:00:55 ; elapsed = 00:00:31 . Memory (MB): peak = 2920.184 ; gain = 0.000 ; free physical = 514 ; free virtual = 24550 Phase 3 Initial Routing | Checksum: 207767398 Time (s): cpu = 00:00:55 ; elapsed = 00:00:31 . Memory (MB): peak = 2920.184 ; gain = 0.000 ; free physical = 513 ; free virtual = 24549 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 964 Number of Nodes with overlaps = 2 Number of Nodes with overlaps = 0 INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.401 | TNS=0.000 | WHS=N/A | THS=N/A | Phase 4.1 Global Iteration 0 | Checksum: 1a01d7475 Time (s): cpu = 00:01:03 ; elapsed = 00:00:34 . Memory (MB): peak = 2920.184 ; gain = 0.000 ; free physical = 504 ; free virtual = 24541 Phase 4 Rip-up And Reroute | Checksum: 1a01d7475 Time (s): cpu = 00:01:03 ; elapsed = 00:00:34 . Memory (MB): peak = 2920.184 ; gain = 0.000 ; free physical = 504 ; free virtual = 24540 Phase 5 Delay and Skew Optimization Phase 5.1 Delay CleanUp Phase 5.1 Delay CleanUp | Checksum: 1a01d7475 Time (s): cpu = 00:01:03 ; elapsed = 00:00:34 . Memory (MB): peak = 2920.184 ; gain = 0.000 ; free physical = 504 ; free virtual = 24540 Phase 5.2 Clock Skew Optimization Phase 5.2 Clock Skew Optimization | Checksum: 1a01d7475 Time (s): cpu = 00:01:03 ; elapsed = 00:00:34 . Memory (MB): peak = 2920.184 ; gain = 0.000 ; free physical = 503 ; free virtual = 24540 Phase 5 Delay and Skew Optimization | Checksum: 1a01d7475 Time (s): cpu = 00:01:03 ; elapsed = 00:00:34 . Memory (MB): peak = 2920.184 ; gain = 0.000 ; free physical = 503 ; free virtual = 24539 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing Phase 6.1.1 Update Timing | Checksum: 20109f2e7 Time (s): cpu = 00:01:04 ; elapsed = 00:00:34 . Memory (MB): peak = 2920.184 ; gain = 0.000 ; free physical = 508 ; free virtual = 24544 INFO: [Route 35-416] Intermediate Timing Summary | WNS=8.497 | TNS=0.000 | WHS=0.414 | THS=0.000 | Phase 6.1 Hold Fix Iter | Checksum: 20109f2e7 Time (s): cpu = 00:01:04 ; elapsed = 00:00:34 . Memory (MB): peak = 2920.184 ; gain = 0.000 ; free physical = 507 ; free virtual = 24543 Phase 6 Post Hold Fix | Checksum: 20109f2e7 Time (s): cpu = 00:01:04 ; elapsed = 00:00:34 . Memory (MB): peak = 2920.184 ; gain = 0.000 ; free physical = 507 ; free virtual = 24543 Phase 7 Route finalize Router Utilization Summary Global Vertical Routing Utilization = 1.78139 % Global Horizontal Routing Utilization = 2.27678 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. Number of Failed Nets = 0 (Failed Nets is the sum of unrouted and partially routed nets) Number of Unrouted Nets = 0 Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 Phase 7 Route finalize | Checksum: 20109f2e7 Time (s): cpu = 00:01:04 ; elapsed = 00:00:34 . Memory (MB): peak = 2920.184 ; gain = 0.000 ; free physical = 510 ; free virtual = 24547 Phase 8 Verifying routed nets Verification completed successfully Phase 8 Verifying routed nets | Checksum: 20109f2e7 Time (s): cpu = 00:01:04 ; elapsed = 00:00:34 . Memory (MB): peak = 2920.184 ; gain = 0.000 ; free physical = 507 ; free virtual = 24544 Phase 9 Depositing Routes Phase 9 Depositing Routes | Checksum: 2cf463cda Time (s): cpu = 00:01:05 ; elapsed = 00:00:35 . Memory (MB): peak = 2920.184 ; gain = 0.000 ; free physical = 516 ; free virtual = 24553 Phase 10 Post Router Timing INFO: [Route 35-57] Estimated Timing Summary | WNS=8.497 | TNS=0.000 | WHS=0.414 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. Phase 10 Post Router Timing | Checksum: 2cf463cda Time (s): cpu = 00:01:06 ; elapsed = 00:00:35 . Memory (MB): peak = 2920.184 ; gain = 0.000 ; free physical = 516 ; free virtual = 24553 INFO: [Route 35-16] Router Completed Successfully Phase 11 Post-Route Event Processing Phase 11 Post-Route Event Processing | Checksum: 10d296126 Time (s): cpu = 00:01:06 ; elapsed = 00:00:35 . Memory (MB): peak = 2920.184 ; gain = 0.000 ; free physical = 516 ; free virtual = 24553 Ending Routing Task | Checksum: 10d296126 Time (s): cpu = 00:01:06 ; elapsed = 00:00:35 . Memory (MB): peak = 2920.184 ; gain = 0.000 ; free physical = 516 ; free virtual = 24553 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 12 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully route_design: Time (s): cpu = 00:01:08 ; elapsed = 00:00:37 . Memory (MB): peak = 2920.184 ; gain = 0.000 ; free physical = 511 ; free virtual = 24547 # report_timing_summary -no_header -no_detailed_paths INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs ------------------------------------------------------------------------------------------------ | Timer Settings | -------------- ------------------------------------------------------------------------------------------------ Enable Multi Corner Analysis : Yes Enable Pessimism Removal : Yes Pessimism Removal Resolution : Nearest Common Node Enable Input Delay Default Clock : No Enable Preset / Clear Arcs : No Disable Flight Delays : No Ignore I/O Paths : No Timing Early Launch at Borrowing Latches : No Borrow Time for Max Delay Exceptions : Yes Merge Timing Exceptions : Yes Inter-SLR Compensation : Conservative Corner Analyze Analyze Name Max Paths Min Paths ------ --------- --------- Slow Yes Yes Fast Yes Yes ------------------------------------------------------------------------------------------------ | Report Methodology | ------------------ ------------------------------------------------------------------------------------------------ No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations. check_timing report Table of Contents ----------------- 1. checking no_clock (97590) 2. checking constant_clock (0) 3. checking pulse_width_clock (0) 4. checking unconstrained_internal_endpoints (24877) 5. checking no_input_delay (1) 6. checking no_output_delay (1) 7. checking multiple_clock (0) 8. checking generated_clocks (0) 9. checking loops (0) 10. checking partial_input_delay (0) 11. checking partial_output_delay (0) 12. checking latch_loops (0) 1. checking no_clock (97590) ---------------------------- There are 5174 register/latch pins with no clock driven by root clock pin: clk_o_reg/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[0]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[10]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[11]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[12]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[13]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[14]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[15]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[16]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[17]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[18]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[19]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[1]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[20]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[21]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[22]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[23]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[24]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[25]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[26]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[27]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[28]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[29]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[2]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[30]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[31]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[3]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[4]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[5]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[6]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[7]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[8]/Q (HIGH) There are 2888 register/latch pins with no clock driven by root clock pin: ptop/u_Controller/ClkDivider/pulse_counter_reg[9]/Q (HIGH) 2. checking constant_clock (0) ------------------------------ There are 0 register/latch pins with constant_clock. 3. checking pulse_width_clock (0) --------------------------------- There are 0 register/latch pins which need pulse_width check 4. checking unconstrained_internal_endpoints (24877) ---------------------------------------------------- There are 24877 pins that are not constrained for maximum delay. (HIGH) There are 0 pins that are not constrained for maximum delay due to constant clock. 5. checking no_input_delay (1) ------------------------------ There is 1 input port with no input delay specified. (HIGH) There are 0 input ports with no input delay but user has a false path constraint. 6. checking no_output_delay (1) ------------------------------- There is 1 port with no output delay specified. (HIGH) There are 0 ports with no output delay but user has a false path constraint There are 0 ports with no output delay but with a timing clock defined on it or propagating through it 7. checking multiple_clock (0) ------------------------------ There are 0 register/latch pins with multiple clocks. 8. checking generated_clocks (0) -------------------------------- There are 0 generated clocks that are not connected to a clock source. 9. checking loops (0) --------------------- There are 0 combinational loops in the design. 10. checking partial_input_delay (0) ------------------------------------ There are 0 input ports with partial input delay specified. 11. checking partial_output_delay (0) ------------------------------------- There are 0 ports with partial output delay specified. 12. checking latch_loops (0) ---------------------------- There are 0 combinational latch loops in the design through latch input ------------------------------------------------------------------------------------------------ | Design Timing Summary | --------------------- ------------------------------------------------------------------------------------------------ WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- 8.522 0.000 0 1 0.430 0.000 0 1 4.500 0.000 0 2 All user specified timing constraints are met. ------------------------------------------------------------------------------------------------ | Clock Summary | ------------- ------------------------------------------------------------------------------------------------ Clock Waveform(ns) Period(ns) Frequency(MHz) ----- ------------ ---------- -------------- sck {0.000 50.000} 100.000 10.000 sys_clk_pin {0.000 5.000} 10.000 100.000 ------------------------------------------------------------------------------------------------ | Intra Clock Table | ----------------- ------------------------------------------------------------------------------------------------ Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- sys_clk_pin 8.522 0.000 0 1 0.430 0.000 0 1 4.500 0.000 0 2 ------------------------------------------------------------------------------------------------ | Inter Clock Table | ----------------- ------------------------------------------------------------------------------------------------ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- ------------------------------------------------------------------------------------------------ | Other Path Groups Table | ----------------------- ------------------------------------------------------------------------------------------------ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- # report_route_status -file digilent_arty_a7_route_status.rpt # report_drc -file digilent_arty_a7_drc.rpt Command: report_drc -file digilent_arty_a7_drc.rpt INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'. INFO: [DRC 23-27] Running DRC with 8 threads INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/jenkins_home/workspace/rv3n/rv3n/digilent_arty_a7_drc.rpt. report_drc completed successfully # report_timing_summary -datasheet -max_paths 10 -file digilent_arty_a7_timing.rpt INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max. INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs # report_power -file digilent_arty_a7_power.rpt Command: report_power -file digilent_arty_a7_power.rpt Running Vector-less Activity Propagation... Finished Running Vector-less Activity Propagation WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis. Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report. 0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. report_power completed successfully # write_bitstream -force "digilent_arty_a7_100t.bit" Command: write_bitstream -force digilent_arty_a7_100t.bit Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t' Running DRC as a precondition to command write_bitstream INFO: [IP_Flow 19-1839] IP Catalog is up to date. INFO: [DRC 23-27] Running DRC with 8 threads WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information. INFO: [Designutils 20-2272] Running write_bitstream with 8 threads. Loading data files... Loading site data... Loading route data... Processing options... Creating bitmap... Creating bitstream... Writing bitstream ./digilent_arty_a7_100t.bit... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory. INFO: [Common 17-83] Releasing license: Implementation 9 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully write_bitstream: Time (s): cpu = 00:00:18 ; elapsed = 00:00:14 . Memory (MB): peak = 3213.383 ; gain = 239.066 ; free physical = 172 ; free virtual = 24187 # exit INFO: [Common 17-206] Exiting Vivado at Mon Apr 13 21:21:50 2026... [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash digilent_arty_a7_100t) [Pipeline] dir Running in /var/jenkins_home/workspace/rv3n/rv3n [Pipeline] { [Pipeline] echo Flashing FPGA digilent_arty_a7_100t. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config -p rv3n -b digilent_arty_a7_100t -l Makefile executed successfully. Makefile output: Flashing the FPGA... /eda/oss-cad-suite/bin/openFPGALoader -b arty_a7_100t digilent_arty_a7_100t.bit empty Jtag frequency : requested 10.00MHz -> real 10.00MHz Open file DONE Parse file DONE load program Load SRAM: [================ ] 31.00% Load SRAM: [================================ ] 63.00% Load SRAM: [================================================ ] 95.00% Load SRAM: [===================================================] 100.00% Done Shift IR 35 ir: 1 isc_done 1 isc_ena 0 init 1 done 1 [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test digilent_arty_a7_100t) [Pipeline] echo Testing FPGA digilent_arty_a7_100t. [Pipeline] sh + echo Test for FPGA in /dev/ttyUSB1 Test for FPGA in /dev/ttyUSB1 [Pipeline] sh + python3 /eda/processor_ci_tests/main.py -b 115200 -s 2 -c /eda/processor_ci_tests/config.json --p /dev/ttyUSB1 -m rv32i -k 0x41525459 -ctm 32 Connected to FPGA with ID: b'ARTY' Checking for sync keyword... Sync keyword matched. Testsuite configurated. Running tests: RV32I in /eda/processor_ci_tests/tests/RV32I Running basic tests in /eda/processor_ci_tests/tests/RV32I/basic, with breakpoint 60 Running test: 000-addi.hex Running test: 001-sw.hex Running test: 002-slti.hex Running test: 003-sltiu.hex Running test: 004-xori.hex Running test: 005-ori.hex Running test: 006-andi.hex Running test: 007-slli.hex Running test: 008-srli.hex Running test: 009-srai.hex Running test: 010-lui.hex Running test: 011-auipc.hex Running test: 012-jal.hex Running test: 013-jalr.hex Running test: 014-beq.hex Running test: 015-bne.hex Running test: 016-blt.hex Running test: 017-bge.hex Running test: 018-bltu.hex Running test: 019-bgeu.hex Running test: 020-lb.hex Running test: 021-lh.hex Running test: 022-lw.hex Running test: 023-lbu.hex Running test: 024-lhu.hex Running test: 025-sb.hex Running test: 026-sh.hex Running test: 027-add.hex Running test: 028-sub.hex Running test: 029-sll.hex Running test: 030-slt.hex Running test: 031-sltu.hex Running test: 032-xor.hex Running test: 033-srl.hex Running test: 034-sra.hex Running test: 035-or.hex Running test: 036-and.hex Running test: 037-fence.hex Running test: 038-ecall.hex Running test: 039-ebreak.hex Running test: 040-timeout.hex Running test: 041-forwarding.hex Running test: 042-forwarding-lw.hex JUnit XML report generated: test_results_1776129731.9413881.xml All tests finished. [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: digilent_arty_a7_100t] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Declarative: Post Actions) [Pipeline] junit Recording test results [Checks API] No suitable checks publisher found. [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline Finished: UNSTABLE