#

Report generated on 2020-12-17 16:50 GMT by riscof v1.17.2

## Environment

Riscof Version | 1.17.2
Reference | sail c simulator
ISA | RV64IMCZicsr_Zifencei
User Spec Version | 2.3
Privilege Spec Version | 1.10

## Yaml

Name
/scratch/git-repo/incoresemi/riscof/riscof_work/sail_isa_checked.yaml
hart_ids: [0] hart0: ISA: RV64IMCZicsr_Zifencei User_Spec_Version: '2.3' supported_xlen: - 64 Privilege_Spec_Version: '1.10' hw_data_misaligned_support: false misa: rv32: accessible: false rv64: accessible: true fields: - extensions - mxl - - - 26 - 61 mxl: implemented: false description: Encodes the native base integer ISA width. shadow: msb: 63 lsb: 62 extensions: implemented: false description: Encodes the presence of the standard extensions, with a single bit per letter of the alphabet. shadow: msb: 25 lsb: 0 description: misa is a read-write register reporting the ISA supported by the hart. address: 769 priv_mode: M reset-val: 0 mstatus: rv32: accessible: false rv64: accessible: true fields: - uie - sie - mie - upie - spie - mpie - spp - mpp - fs - xs - mprv - sum - mxr - tvm - tw - tsr - uxl - sxl - sd - - - 2 - - 6 - - 9 - 10 - - 23 - 31 - - 36 - 62 uie: implemented: false description: Stores the state of the user mode interrupts. shadow: msb: 0 lsb: 0 sie: implemented: false description: Stores the state of the supervisor mode interrupts. shadow: msb: 1 lsb: 1 mie: implemented: true description: Stores the state of the machine mode interrupts. shadow: msb: 3 lsb: 3 type: wlrl: - 0:1 upie: implemented: false description: Stores the state of the user mode interrupts prior to the trap. shadow: msb: 4 lsb: 4 spie: implemented: false description: Stores the state of the supervisor mode interrupts prior to the trap. shadow: msb: 5 lsb: 5 mpie: implemented: true description: Stores the state of the machine mode interrupts prior to the trap. shadow: msb: 7 lsb: 7 type: wlrl: - 0:1 spp: implemented: false description: Stores the previous priority mode for supervisor. shadow: msb: 8 lsb: 8 mpp: implemented: true description: Stores the previous priority mode for machine. shadow: msb: 12 lsb: 11 type: {ro_constant: 0} fs: implemented: false description: Encodes the status of the floating-point unit, including the CSR fcsr and floating-point data registers. shadow: msb: 14 lsb: 13 xs: implemented: false description: Encodes the status of additional user-mode extensions and associated state. shadow: msb: 16 lsb: 15 mprv: implemented: false description: Modifies the privilege level at which loads and stores execute in all privilege modes. shadow: msb: 17 lsb: 17 sum: implemented: false description: Modifies the privilege with which S-mode loads and stores access virtual memory. shadow: msb: 18 lsb: 18 mxr: implemented: false description: Modifies the privilege with which loads access virtual memory. shadow: msb: 19 lsb: 19 tvm: implemented: false description: Supports intercepting supervisor virtual-memory management operations. shadow: msb: 20 lsb: 20 tw: implemented: false description: Supports intercepting the WFI instruction. shadow: msb: 21 lsb: 21 tsr: implemented: false description: Supports intercepting the supervisor exception return instruction. shadow: msb: 22 lsb: 22 sxl: implemented: false description: Controls the value of xlen for Supervisor mode. shadow: msb: 35 lsb: 34 uxl: implemented: false description: Controls the xlen for User mode. shadow: msb: 33 lsb: 32 sd: implemented: true description: Read-only bit that summarizes whether either the FS field or XS field signals the presence of some dirty state. shadow: msb: 63 lsb: 63 type: ro_variable: true description: The mstatus register keeps track of and controls the hart’s current operating state. address: 768 priv_mode: M reset-val: 0 mvendorid: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: ro_constant: 0 description: 32-bit read-only register providing the JEDEC manufacturer ID of the provider of the core. address: 3857 priv_mode: M reset-val: 0 marchid: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: ro_constant: 0 description: MXLEN-bit read-only register encoding the base microarchitecture of the hart. address: 3858 priv_mode: M reset-val: 0 mimpid: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: ro_constant: 0 description: Provides a unique encoding of the version of the processor implementation. address: 3859 priv_mode: M reset-val: 0 mhartid: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: ro_constant: 0 description: MXLEN-bit read-only register containing the integer ID of the hardware thread running the code. address: 3860 priv_mode: M reset-val: 0 mtvec: rv32: accessible: false rv64: accessible: true fields: - mode - base base: implemented: true description: Vector base address. shadow: msb: 63 lsb: 2 type: {ro_constant: 0} mode: implemented: true description: Vector mode. shadow: msb: 1 lsb: 0 type: {ro_constant: 0} description: MXLEN-bit read/write register that holds trap vector configuration. address: 773 priv_mode: M reset-val: 0 mideleg: rv32: accessible: false rv64: accessible: false description: Machine Interrupt delegation Register. address: 771 priv_mode: M reset-val: 0 medeleg: rv32: accessible: false rv64: accessible: false description: Machine Exception delegation Register. address: 770 priv_mode: M reset-val: 0 mip: rv32: accessible: false rv64: accessible: true fields: - usip - ssip - msip - utip - stip - mtip - ueip - seip - meip - - - 2 - - 6 - - 10 - - 12 - 63 usip: implemented: false description: User Software Interrupt Pending. shadow: msb: 0 lsb: 0 ssip: implemented: false description: Supervisor Software Interrupt Pending. shadow: msb: 1 lsb: 1 msip: implemented: true description: Machine Software Interrupt Pending. shadow: msb: 3 lsb: 3 type: ro_variable: true utip: implemented: false description: User Timer Interrupt Pending. shadow: msb: 4 lsb: 4 stip: implemented: false description: Supervisor Timer Interrupt Pending. shadow: msb: 5 lsb: 5 mtip: implemented: true description: Machine Timer Interrupt Pending. shadow: msb: 7 lsb: 7 type: ro_variable: true ueip: implemented: false description: User External Interrupt Pending. shadow: msb: 8 lsb: 8 seip: implemented: false description: Supervisor External Interrupt Pending. shadow: msb: 9 lsb: 9 meip: implemented: true description: Machine External Interrupt Pending. shadow: msb: 11 lsb: 11 type: ro_variable: true description: The mip register is an MXLEN-bit read/write register containing information on pending interrupts. address: 836 priv_mode: M reset-val: 0 mie: rv32: accessible: false rv64: accessible: true fields: - usie - ssie - msie - utie - stie - mtie - ueie - seie - meie - - - 2 - - 6 - - 10 - - 12 - 63 usie: implemented: false description: User Software Interrupt enable. shadow: msb: 0 lsb: 0 ssie: implemented: false description: Supervisor Software Interrupt enable. shadow: msb: 1 lsb: 1 msie: implemented: true description: Machine Software Interrupt enable. shadow: msb: 3 lsb: 3 type: wlrl: - 0x0:0x1 utie: implemented: false description: User Timer Interrupt enable. shadow: msb: 4 lsb: 4 stie: implemented: false description: Supervisor Timer Interrupt enable. shadow: msb: 5 lsb: 5 mtie: implemented: true description: Machine Timer Interrupt enable. shadow: msb: 7 lsb: 7 type: wlrl: - 0:1 ueie: implemented: false description: User External Interrupt enable. shadow: msb: 8 lsb: 8 seie: implemented: false description: Supervisor External Interrupt enable. shadow: msb: 9 lsb: 9 meie: implemented: true description: Machine External Interrupt enable. shadow: msb: 11 lsb: 11 type: wlrl: - 0:1 description: The mie register is an MXLEN-bit read/write register containing interrupt enable bits. address: 772 priv_mode: M reset-val: 0 mscratch: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: warl: dependency_fields: [] legal: - mscratch[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF] wr_illegal: - unchanged description: The mscratch register is an MXLEN-bit read/write register dedicated for use by machine mode. address: 832 priv_mode: M reset-val: 0 mepc: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: warl: dependency_fields: [] legal: - mepc[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF] wr_illegal: - unchanged description: The mepc is a warl register that must be able to hold all valid physical and virtual addresses. address: 0x341 priv_mode: M reset-val: 0 mtval: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: warl: dependency_fields: [] legal: - mtval[63:0] in [0x00000000:0xFFFFFFFFFFFFFFFF] wr_illegal: - unchanged description: The mtval is a warl register that holds the address of the instruction which caused the exception. address: 835 priv_mode: M reset-val: 0 mcause: rv32: accessible: false rv64: accessible: true fields: - exception_code - interrupt interrupt: implemented: true description: Indicates whether the trap was due to an interrupt. shadow: msb: 63 lsb: 63 type: wlrl: - 0:1 exception_code: implemented: true description: Encodes the exception code. shadow: msb: 62 lsb: 0 type: wlrl: - 0:15 description: The mcause register stores the information regarding the trap. address: 834 priv_mode: M reset-val: 0 pmpcfg0: rv32: accessible: false rv64: accessible: true fields: - pmp0cfg - pmp1cfg - pmp2cfg - pmp3cfg - pmp4cfg - pmp5cfg - pmp6cfg - pmp7cfg pmp0cfg: implemented: true description: pmp configuration bits shadow: msb: 7 lsb: 0 type: &id001 ro_constant: 0 pmp1cfg: implemented: true description: pmp configuration bits shadow: msb: 15 lsb: 8 type: &id002 ro_constant: 0 pmp2cfg: implemented: true description: pmp configuration bits shadow: msb: 23 lsb: 16 type: &id003 ro_constant: 0 pmp3cfg: implemented: true description: pmp configuration bits shadow: msb: 31 lsb: 24 type: &id004 ro_constant: 0 pmp4cfg: implemented: true description: pmp configuration bits shadow: msb: 39 lsb: 32 type: &id005 ro_constant: 0 pmp5cfg: implemented: true description: pmp configuration bits shadow: msb: 47 lsb: 40 type: &id006 ro_constant: 0 pmp6cfg: implemented: true description: pmp configuration bits shadow: msb: 55 lsb: 48 type: &id007 ro_constant: 0 pmp7cfg: implemented: true description: pmp configuration bits shadow: msb: 63 lsb: 56 type: &id008 ro_constant: 0 description: PMP configuration register address: 0x3A0 priv_mode: M reset-val: 0 pmpcfg1: rv32: accessible: false rv64: accessible: false description: PMP configuration register address: 0x3A1 priv_mode: M reset-val: 0 pmpcfg2: rv32: accessible: false rv64: accessible: true fields: - pmp8cfg - pmp9cfg - pmp10cfg - pmp11cfg - pmp12cfg - pmp13cfg - pmp14cfg - pmp15cfg pmp8cfg: implemented: true description: pmp configuration bits shadow: msb: 7 lsb: 0 type: *id001 pmp9cfg: implemented: true description: pmp configuration bits shadow: msb: 15 lsb: 8 type: *id002 pmp10cfg: implemented: true description: pmp configuration bits shadow: msb: 23 lsb: 16 type: *id003 pmp11cfg: implemented: true description: pmp configuration bits shadow: msb: 31 lsb: 24 type: *id004 pmp12cfg: implemented: true description: pmp configuration bits shadow: msb: 39 lsb: 32 type: *id005 pmp13cfg: implemented: true description: pmp configuration bits shadow: msb: 47 lsb: 40 type: *id006 pmp14cfg: implemented: true description: pmp configuration bits shadow: msb: 55 lsb: 48 type: *id007 pmp15cfg: implemented: true description: pmp configuration bits shadow: msb: 63 lsb: 56 type: *id008 description: PMP configuration register address: 0x3A2 priv_mode: M reset-val: 0 pmpcfg3: rv32: accessible: false rv64: accessible: false description: PMP configuration register address: 0x3A3 priv_mode: M reset-val: 0 pmpcfg4: rv32: accessible: false rv64: accessible: true fields: - pmp16cfg - pmp17cfg - pmp18cfg - pmp19cfg - pmp20cfg - pmp21cfg - pmp22cfg - pmp23cfg pmp16cfg: implemented: true description: pmp configuration bits shadow: msb: 7 lsb: 0 type: *id001 pmp17cfg: implemented: true description: pmp configuration bits shadow: msb: 15 lsb: 8 type: *id002 pmp18cfg: implemented: true description: pmp configuration bits shadow: msb: 23 lsb: 16 type: *id003 pmp19cfg: implemented: true description: pmp configuration bits shadow: msb: 31 lsb: 24 type: *id004 pmp20cfg: implemented: true description: pmp configuration bits shadow: msb: 39 lsb: 32 type: *id005 pmp21cfg: implemented: true description: pmp configuration bits shadow: msb: 47 lsb: 40 type: *id006 pmp22cfg: implemented: true description: pmp configuration bits shadow: msb: 55 lsb: 48 type: *id007 pmp23cfg: implemented: true description: pmp configuration bits shadow: msb: 63 lsb: 56 type: *id008 description: PMP configuration register address: 0x3A4 priv_mode: M reset-val: 0 pmpcfg5: rv32: accessible: false rv64: accessible: false description: PMP configuration register address: 0x3A5 priv_mode: M reset-val: 0 pmpcfg6: rv32: accessible: false rv64: accessible: true fields: - pmp24cfg - pmp25cfg - pmp26cfg - pmp27cfg - pmp28cfg - pmp29cfg - pmp30cfg - pmp31cfg pmp24cfg: implemented: true description: pmp configuration bits shadow: msb: 7 lsb: 0 type: *id001 pmp25cfg: implemented: true description: pmp configuration bits shadow: msb: 15 lsb: 8 type: *id002 pmp26cfg: implemented: true description: pmp configuration bits shadow: msb: 23 lsb: 16 type: *id003 pmp27cfg: implemented: true description: pmp configuration bits shadow: msb: 31 lsb: 24 type: *id004 pmp28cfg: implemented: true description: pmp configuration bits shadow: msb: 39 lsb: 32 type: *id005 pmp29cfg: implemented: true description: pmp configuration bits shadow: msb: 47 lsb: 40 type: *id006 pmp30cfg: implemented: true description: pmp configuration bits shadow: msb: 55 lsb: 48 type: *id007 pmp31cfg: implemented: true description: pmp configuration bits shadow: msb: 63 lsb: 56 type: *id008 description: PMP configuration register address: 0x3A6 priv_mode: M reset-val: 0 pmpcfg7: rv32: accessible: false rv64: accessible: false description: PMP configuration register address: 0x3A7 priv_mode: M reset-val: 0 pmpcfg8: rv32: accessible: false rv64: accessible: true fields: - pmp32cfg - pmp33cfg - pmp34cfg - pmp35cfg - pmp36cfg - pmp37cfg - pmp38cfg - pmp39cfg pmp32cfg: implemented: true description: pmp configuration bits shadow: msb: 7 lsb: 0 type: *id001 pmp33cfg: implemented: true description: pmp configuration bits shadow: msb: 15 lsb: 8 type: *id002 pmp34cfg: implemented: true description: pmp configuration bits shadow: msb: 23 lsb: 16 type: *id003 pmp35cfg: implemented: true description: pmp configuration bits shadow: msb: 31 lsb: 24 type: *id004 pmp36cfg: implemented: true description: pmp configuration bits shadow: msb: 39 lsb: 32 type: *id005 pmp37cfg: implemented: true description: pmp configuration bits shadow: msb: 47 lsb: 40 type: *id006 pmp38cfg: implemented: true description: pmp configuration bits shadow: msb: 55 lsb: 48 type: *id007 pmp39cfg: implemented: true description: pmp configuration bits shadow: msb: 63 lsb: 56 type: *id008 description: PMP configuration register address: 0x3A8 priv_mode: M reset-val: 0 pmpcfg9: rv32: accessible: false rv64: accessible: false description: PMP configuration register address: 0x3A9 priv_mode: M reset-val: 0 pmpcfg10: rv32: accessible: false rv64: accessible: true fields: - pmp40cfg - pmp41cfg - pmp42cfg - pmp43cfg - pmp44cfg - pmp45cfg - pmp46cfg - pmp47cfg pmp40cfg: implemented: true description: pmp configuration bits shadow: msb: 7 lsb: 0 type: *id001 pmp41cfg: implemented: true description: pmp configuration bits shadow: msb: 15 lsb: 8 type: *id002 pmp42cfg: implemented: true description: pmp configuration bits shadow: msb: 23 lsb: 16 type: *id003 pmp43cfg: implemented: true description: pmp configuration bits shadow: msb: 31 lsb: 24 type: *id004 pmp44cfg: implemented: true description: pmp configuration bits shadow: msb: 39 lsb: 32 type: *id005 pmp45cfg: implemented: true description: pmp configuration bits shadow: msb: 47 lsb: 40 type: *id006 pmp46cfg: implemented: true description: pmp configuration bits shadow: msb: 55 lsb: 48 type: *id007 pmp47cfg: implemented: true description: pmp configuration bits shadow: msb: 63 lsb: 56 type: *id008 description: PMP configuration register address: 0x3AA priv_mode: M reset-val: 0 pmpcfg11: rv32: accessible: false rv64: accessible: false description: PMP configuration register address: 0x3AB priv_mode: M reset-val: 0 pmpcfg12: rv32: accessible: false rv64: accessible: true fields: - pmp48cfg - pmp49cfg - pmp50cfg - pmp51cfg - pmp52cfg - pmp53cfg - pmp54cfg - pmp55cfg pmp48cfg: implemented: true description: pmp configuration bits shadow: msb: 7 lsb: 0 type: *id001 pmp49cfg: implemented: true description: pmp configuration bits shadow: msb: 15 lsb: 8 type: *id002 pmp50cfg: implemented: true description: pmp configuration bits shadow: msb: 23 lsb: 16 type: *id003 pmp51cfg: implemented: true description: pmp configuration bits shadow: msb: 31 lsb: 24 type: *id004 pmp52cfg: implemented: true description: pmp configuration bits shadow: msb: 39 lsb: 32 type: *id005 pmp53cfg: implemented: true description: pmp configuration bits shadow: msb: 47 lsb: 40 type: *id006 pmp54cfg: implemented: true description: pmp configuration bits shadow: msb: 55 lsb: 48 type: *id007 pmp55cfg: implemented: true description: pmp configuration bits shadow: msb: 63 lsb: 56 type: *id008 description: PMP configuration register address: 0x3AC priv_mode: M reset-val: 0 pmpcfg13: rv32: accessible: false rv64: accessible: false description: PMP configuration register address: 0x3AD priv_mode: M reset-val: 0 pmpcfg14: rv32: accessible: false rv64: accessible: true fields: - pmp56cfg - pmp57cfg - pmp58cfg - pmp59cfg - pmp60cfg - pmp61cfg - pmp62cfg - pmp63cfg pmp56cfg: implemented: true description: pmp configuration bits shadow: msb: 7 lsb: 0 type: *id001 pmp57cfg: implemented: true description: pmp configuration bits shadow: msb: 15 lsb: 8 type: *id002 pmp58cfg: implemented: true description: pmp configuration bits shadow: msb: 23 lsb: 16 type: *id003 pmp59cfg: implemented: true description: pmp configuration bits shadow: msb: 31 lsb: 24 type: *id004 pmp60cfg: implemented: true description: pmp configuration bits shadow: msb: 39 lsb: 32 type: *id005 pmp61cfg: implemented: true description: pmp configuration bits shadow: msb: 47 lsb: 40 type: *id006 pmp62cfg: implemented: true description: pmp configuration bits shadow: msb: 55 lsb: 48 type: *id007 pmp63cfg: implemented: true description: pmp configuration bits shadow: msb: 63 lsb: 56 type: *id008 description: PMP configuration register address: 0x3AE priv_mode: M reset-val: 0 pmpcfg15: rv32: accessible: false rv64: accessible: false description: PMP configuration register address: 0x3AF priv_mode: M reset-val: 0 pmpaddr0: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: &id009 ro_constant: 0 description: Physical memory protection address register address: 0x3B0 priv_mode: M reset-val: 0 pmpaddr1: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3B1 priv_mode: M reset-val: 0 pmpaddr2: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3B2 priv_mode: M reset-val: 0 pmpaddr3: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3B3 priv_mode: M reset-val: 0 pmpaddr4: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3B4 priv_mode: M reset-val: 0 pmpaddr5: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3B5 priv_mode: M reset-val: 0 pmpaddr6: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3B6 priv_mode: M reset-val: 0 pmpaddr7: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3B7 priv_mode: M reset-val: 0 pmpaddr8: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3B8 priv_mode: M reset-val: 0 pmpaddr9: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3B9 priv_mode: M reset-val: 0 pmpaddr10: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3BA priv_mode: M reset-val: 0 pmpaddr11: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3BB priv_mode: M reset-val: 0 pmpaddr12: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3BC priv_mode: M reset-val: 0 pmpaddr13: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3BD priv_mode: M reset-val: 0 pmpaddr14: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3BE priv_mode: M reset-val: 0 pmpaddr15: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3BF priv_mode: M reset-val: 0 pmpaddr16: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3C0 priv_mode: M reset-val: 0 pmpaddr17: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3C1 priv_mode: M reset-val: 0 pmpaddr18: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3C2 priv_mode: M reset-val: 0 pmpaddr19: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3C3 priv_mode: M reset-val: 0 pmpaddr20: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3C4 priv_mode: M reset-val: 0 pmpaddr21: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3C5 priv_mode: M reset-val: 0 pmpaddr22: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3C6 priv_mode: M reset-val: 0 pmpaddr23: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3C7 priv_mode: M reset-val: 0 pmpaddr24: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3C8 priv_mode: M reset-val: 0 pmpaddr25: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3C9 priv_mode: M reset-val: 0 pmpaddr26: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3CA priv_mode: M reset-val: 0 pmpaddr27: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3CB priv_mode: M reset-val: 0 pmpaddr28: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3CC priv_mode: M reset-val: 0 pmpaddr29: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3CD priv_mode: M reset-val: 0 pmpaddr30: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3CE priv_mode: M reset-val: 0 pmpaddr31: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3CF priv_mode: M reset-val: 0 pmpaddr32: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3D0 priv_mode: M reset-val: 0 pmpaddr33: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3D1 priv_mode: M reset-val: 0 pmpaddr34: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3D2 priv_mode: M reset-val: 0 pmpaddr35: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3D3 priv_mode: M reset-val: 0 pmpaddr36: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3D4 priv_mode: M reset-val: 0 pmpaddr37: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3D5 priv_mode: M reset-val: 0 pmpaddr38: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3D6 priv_mode: M reset-val: 0 pmpaddr39: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3D7 priv_mode: M reset-val: 0 pmpaddr40: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3D8 priv_mode: M reset-val: 0 pmpaddr41: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3D9 priv_mode: M reset-val: 0 pmpaddr42: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3DA priv_mode: M reset-val: 0 pmpaddr43: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3DB priv_mode: M reset-val: 0 pmpaddr44: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3DC priv_mode: M reset-val: 0 pmpaddr45: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3DD priv_mode: M reset-val: 0 pmpaddr46: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3DE priv_mode: M reset-val: 0 pmpaddr47: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3DF priv_mode: M reset-val: 0 pmpaddr48: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3E0 priv_mode: M reset-val: 0 pmpaddr49: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3E1 priv_mode: M reset-val: 0 pmpaddr50: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3E2 priv_mode: M reset-val: 0 pmpaddr51: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3E3 priv_mode: M reset-val: 0 pmpaddr52: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3E4 priv_mode: M reset-val: 0 pmpaddr53: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3E5 priv_mode: M reset-val: 0 pmpaddr54: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3E6 priv_mode: M reset-val: 0 pmpaddr55: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3E7 priv_mode: M reset-val: 0 pmpaddr56: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3E8 priv_mode: M reset-val: 0 pmpaddr57: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3E9 priv_mode: M reset-val: 0 pmpaddr58: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3EA priv_mode: M reset-val: 0 pmpaddr59: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3EB priv_mode: M reset-val: 0 pmpaddr60: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3EC priv_mode: M reset-val: 0 pmpaddr61: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3ED priv_mode: M reset-val: 0 pmpaddr62: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3EE priv_mode: M reset-val: 0 pmpaddr63: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Physical memory protection address register address: 0x3EF priv_mode: M reset-val: 0 mcounteren: rv32: accessible: false rv64: accessible: false description: The mcounteren is a 32-bit register that controls the availability of the hardware performance-monitoring counters to the next-lowest privileged mode. address: 0x306 priv_mode: M reset-val: 0 mcountinhibit: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 31 lsb: 0 type: ro_constant: 0 description: The mcountinhibit is a 32-bit WARL register that controls which of the hardware performance-monitoring counters increment. address: 0x320 priv_mode: M reset-val: 0 mcycle: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Counts the number of clock cycles executed from an arbitrary point in time. address: 0xB00 priv_mode: M reset-val: 0 mcycleh: rv32: accessible: false rv64: accessible: false description: upper 32 bits of mcycle address: 0xB80 priv_mode: M reset-val: 0 minstret: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: Counts the number of instructions completed from an arbitrary point in time. address: 0xB02 priv_mode: M reset-val: 0 minstreth: rv32: accessible: false rv64: accessible: false description: Upper 32 bits of minstret. address: 0xB82 priv_mode: M reset-val: 0 mhpmevent3: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent3 is a MXLEN-bit event register which controls mhpmcounter3. address: 0x323 priv_mode: M reset-val: 0 mhpmcounter3: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter3 is a 64-bit counter. Returns lower 32 bits in RV32I mode. address: 0xB03 priv_mode: M reset-val: 0 mhpmcounter3h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter3h returns the upper half word in RV32I systems. address: 0xB83 priv_mode: M reset-val: 0 mhpmevent4: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent4 is a MXLEN-bit event register which controls mhpmcounter4. address: 0x324 priv_mode: M reset-val: 0 mhpmcounter4: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter4 is a 64-bit counter. Returns lower 42 bits in RV42I mode. address: 0xB04 priv_mode: M reset-val: 0 mhpmcounter4h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter4h returns the upper half word in RV42I systems. address: 0xB84 priv_mode: M reset-val: 0 mhpmevent5: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent5 is a MXLEN-bit event register which controls mhpmcounter5. address: 0x325 priv_mode: M reset-val: 0 mhpmcounter5: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter5 is a 64-bit counter. Returns lower 52 bits in RV52I mode. address: 0xB05 priv_mode: M reset-val: 0 mhpmcounter5h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter5h returns the upper half word in RV52I systems. address: 0xB85 priv_mode: M reset-val: 0 mhpmevent6: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent6 is a MXLEN-bit event register which controls mhpmcounter6. address: 0x326 priv_mode: M reset-val: 0 mhpmcounter6: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter6 is a 64-bit counter. Returns lower 62 bits in RV62I mode. address: 0xB06 priv_mode: M reset-val: 0 mhpmcounter6h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter6h returns the upper half word in RV62I systems. address: 0xB86 priv_mode: M reset-val: 0 mhpmevent7: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent7 is a MXLEN-bit event register which controls mhpmcounter7. address: 0x327 priv_mode: M reset-val: 0 mhpmcounter7: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter7 is a 64-bit counter. Returns lower 72 bits in RV72I mode. address: 0xB07 priv_mode: M reset-val: 0 mhpmcounter7h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter7h returns the upper half word in RV72I systems. address: 0xB87 priv_mode: M reset-val: 0 mhpmevent8: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent8 is a MXLEN-bit event register which controls mhpmcounter8. address: 0x328 priv_mode: M reset-val: 0 mhpmcounter8: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter8 is a 64-bit counter. Returns lower 82 bits in RV82I mode. address: 0xB08 priv_mode: M reset-val: 0 mhpmcounter8h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter8h returns the upper half word in RV82I systems. address: 0xB88 priv_mode: M reset-val: 0 mhpmevent9: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent9 is a MXLEN-bit event register which controls mhpmcounter9. address: 0x329 priv_mode: M reset-val: 0 mhpmcounter9: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter9 is a 64-bit counter. Returns lower 32 bits in RV32I mode. address: 0xB09 priv_mode: M reset-val: 0 mhpmcounter9h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter9h returns the upper half word in RV32I systems. address: 0xB89 priv_mode: M reset-val: 0 mhpmevent10: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent10 is a MXLEN-bit event register which controls mhpmcounter10. address: 0x32a priv_mode: M reset-val: 0 mhpmcounter10: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter10 is a 64-bit counter. Returns lower 102 bits in RV102I mode. address: 0xB0A priv_mode: M reset-val: 0 mhpmcounter10h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter10h returns the upper half word in RV102I systems. address: 0xB8A priv_mode: M reset-val: 0 mhpmevent11: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent11 is a MXLEN-bit event register which controls mhpmcounter11. address: 0x32b priv_mode: M reset-val: 0 mhpmcounter11: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter11 is a 64-bit counter. Returns lower 112 bits in RV112I mode. address: 0xB0B priv_mode: M reset-val: 0 mhpmcounter11h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter11h returns the upper half word in RV112I systems. address: 0xB8B priv_mode: M reset-val: 0 mhpmevent12: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent12 is a MXLEN-bit event register which controls mhpmcounter12. address: 0x32c priv_mode: M reset-val: 0 mhpmcounter12: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter12 is a 64-bit counter. Returns lower 122 bits in RV122I mode. address: 0xB0C priv_mode: M reset-val: 0 mhpmcounter12h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter12h returns the upper half word in RV122I systems. address: 0xB8C priv_mode: M reset-val: 0 mhpmevent13: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent13 is a MXLEN-bit event register which controls mhpmcounter13. address: 0x32d priv_mode: M reset-val: 0 mhpmcounter13: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter13 is a 64-bit counter. Returns lower 132 bits in RV132I mode. address: 0xB0D priv_mode: M reset-val: 0 mhpmcounter13h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter13h returns the upper half word in RV132I systems. address: 0xB8D priv_mode: M reset-val: 0 mhpmevent14: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent14 is a MXLEN-bit event register which controls mhpmcounter14. address: 0x32e priv_mode: M reset-val: 0 mhpmcounter14: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter14 is a 64-bit counter. Returns lower 142 bits in RV142I mode. address: 0xB0E priv_mode: M reset-val: 0 mhpmcounter14h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter14h returns the upper half word in RV142I systems. address: 0xB8E priv_mode: M reset-val: 0 mhpmevent15: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent15 is a MXLEN-bit event register which controls mhpmcounter15. address: 0x32f priv_mode: M reset-val: 0 mhpmcounter15: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter15 is a 64-bit counter. Returns lower 152 bits in RV152I mode. address: 0xB0F priv_mode: M reset-val: 0 mhpmcounter15h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter15h returns the upper half word in RV152I systems. address: 0xB8F priv_mode: M reset-val: 0 mhpmevent16: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent16 is a MXLEN-bit event register which controls mhpmcounter16. address: 0x330 priv_mode: M reset-val: 0 mhpmcounter16: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter16 is a 64-bit counter. Returns lower 162 bits in RV162I mode. address: 0xB10 priv_mode: M reset-val: 0 mhpmcounter16h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter16h returns the upper half word in RV162I systems. address: 0xB90 priv_mode: M reset-val: 0 mhpmevent17: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent17 is a MXLEN-bit event register which controls mhpmcounter17. address: 0x331 priv_mode: M reset-val: 0 mhpmcounter17: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter17 is a 64-bit counter. Returns lower 172 bits in RV172I mode. address: 0xB11 priv_mode: M reset-val: 0 mhpmcounter17h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter17h returns the upper half word in RV172I systems. address: 0xB91 priv_mode: M reset-val: 0 mhpmevent18: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent18 is a MXLEN-bit event register which controls mhpmcounter18. address: 0x332 priv_mode: M reset-val: 0 mhpmcounter18: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter18 is a 64-bit counter. Returns lower 182 bits in RV182I mode. address: 0xB12 priv_mode: M reset-val: 0 mhpmcounter18h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter18h returns the upper half word in RV182I systems. address: 0xB92 priv_mode: M reset-val: 0 mhpmevent19: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent19 is a MXLEN-bit event register which controls mhpmcounter19. address: 0x333 priv_mode: M reset-val: 0 mhpmcounter19: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter19 is a 64-bit counter. Returns lower 32 bits in RV32I mode. address: 0xB13 priv_mode: M reset-val: 0 mhpmcounter19h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter19h returns the upper half word in RV32I systems. address: 0xB93 priv_mode: M reset-val: 0 mhpmevent20: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent20 is a MXLEN-bit event register which controls mhpmcounter20. address: 0x334 priv_mode: M reset-val: 0 mhpmcounter20: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter20 is a 64-bit counter. Returns lower 202 bits in RV202I mode. address: 0xB14 priv_mode: M reset-val: 0 mhpmcounter20h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter20h returns the upper half word in RV202I systems. address: 0xB94 priv_mode: M reset-val: 0 mhpmevent21: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent21 is a MXLEN-bit event register which controls mhpmcounter21. address: 0x335 priv_mode: M reset-val: 0 mhpmcounter21: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter21 is a 64-bit counter. Returns lower 212 bits in RV212I mode. address: 0xB15 priv_mode: M reset-val: 0 mhpmcounter21h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter21h returns the upper half word in RV212I systems. address: 0xB95 priv_mode: M reset-val: 0 mhpmevent22: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent22 is a MXLEN-bit event register which controls mhpmcounter22. address: 0x336 priv_mode: M reset-val: 0 mhpmcounter22: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter22 is a 64-bit counter. Returns lower 222 bits in RV222I mode. address: 0xB16 priv_mode: M reset-val: 0 mhpmcounter22h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter22h returns the upper half word in RV222I systems. address: 0xB96 priv_mode: M reset-val: 0 mhpmevent23: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent23 is a MXLEN-bit event register which controls mhpmcounter23. address: 0x337 priv_mode: M reset-val: 0 mhpmcounter23: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter23 is a 64-bit counter. Returns lower 232 bits in RV232I mode. address: 0xB17 priv_mode: M reset-val: 0 mhpmcounter23h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter23h returns the upper half word in RV232I systems. address: 0xB97 priv_mode: M reset-val: 0 mhpmevent24: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent24 is a MXLEN-bit event register which controls mhpmcounter24. address: 0x338 priv_mode: M reset-val: 0 mhpmcounter24: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter24 is a 64-bit counter. Returns lower 242 bits in RV242I mode. address: 0xB18 priv_mode: M reset-val: 0 mhpmcounter24h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter24h returns the upper half word in RV242I systems. address: 0xB98 priv_mode: M reset-val: 0 mhpmevent25: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent25 is a MXLEN-bit event register which controls mhpmcounter25. address: 0x339 priv_mode: M reset-val: 0 mhpmcounter25: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter25 is a 64-bit counter. Returns lower 252 bits in RV252I mode. address: 0xB19 priv_mode: M reset-val: 0 mhpmcounter25h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter25h returns the upper half word in RV252I systems. address: 0xB99 priv_mode: M reset-val: 0 mhpmevent26: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent26 is a MXLEN-bit event register which controls mhpmcounter26. address: 0x33a priv_mode: M reset-val: 0 mhpmcounter26: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter26 is a 64-bit counter. Returns lower 262 bits in RV262I mode. address: 0xB1A priv_mode: M reset-val: 0 mhpmcounter26h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter26h returns the upper half word in RV262I systems. address: 0xB9A priv_mode: M reset-val: 0 mhpmevent27: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent27 is a MXLEN-bit event register which controls mhpmcounter27. address: 0x33b priv_mode: M reset-val: 0 mhpmcounter27: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter27 is a 64-bit counter. Returns lower 272 bits in RV272I mode. address: 0xB1B priv_mode: M reset-val: 0 mhpmcounter27h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter27h returns the upper half word in RV272I systems. address: 0xB9B priv_mode: M reset-val: 0 mhpmevent28: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent28 is a MXLEN-bit event register which controls mhpmcounter28. address: 0x33c priv_mode: M reset-val: 0 mhpmcounter28: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter28 is a 64-bit counter. Returns lower 282 bits in RV282I mode. address: 0xB1C priv_mode: M reset-val: 0 mhpmcounter28h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter28h returns the upper half word in RV282I systems. address: 0xB9C priv_mode: M reset-val: 0 mhpmevent29: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent29 is a MXLEN-bit event register which controls mhpmcounter29. address: 0x33d priv_mode: M reset-val: 0 mhpmcounter29: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter29 is a 64-bit counter. Returns lower 32 bits in RV32I mode. address: 0xB1D priv_mode: M reset-val: 0 mhpmcounter29h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter29h returns the upper half word in RV32I systems. address: 0xB9D priv_mode: M reset-val: 0 mhpmevent30: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent30 is a MXLEN-bit event register which controls mhpmcounter30. address: 0x33e priv_mode: M reset-val: 0 mhpmcounter30: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter30 is a 64-bit counter. Returns lower 302 bits in RV302I mode. address: 0xB1E priv_mode: M reset-val: 0 mhpmcounter30h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter30h returns the upper half word in RV302I systems. address: 0xB9E priv_mode: M reset-val: 0 mhpmevent31: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmevent31 is a MXLEN-bit event register which controls mhpmcounter31. address: 0x33f priv_mode: M reset-val: 0 mhpmcounter31: rv32: accessible: false rv64: accessible: true fields: [] shadow: msb: 63 lsb: 0 type: *id009 description: The mhpmcounter31 is a 64-bit counter. Returns lower 312 bits in RV312I mode. address: 0xB1F priv_mode: M reset-val: 0 mhpmcounter31h: rv32: accessible: false rv64: accessible: false description: The mhpmcounter31h returns the upper half word in RV312I systems. address: 0xB9F priv_mode: M reset-val: 0 fflags: rv32: accessible: false rv64: accessible: false description: 32-bit register to hold floating point accrued exceptions. address: 001 priv_mode: U reset-val: 0 frm: rv32: accessible: false rv64: accessible: false description: 32-bit register to hold Floating-Point Dynamic Rounding Mode. address: 002 priv_mode: U reset-val: 0 fcsr: rv32: accessible: false rv64: accessible: false description: 32-bit register to hold Floating-Point Control and Status Register. address: 003 priv_mode: U reset-val: 0 cycle: rv32: accessible: false rv64: accessible: false description: Captures the number of cycles executed from an arbitrary point in time. priv_mode: U address: 0xC00 reset-val: 0 cycleh: rv32: accessible: false rv64: accessible: false description: Upper 32-bits of the mcycle counter; only for rv32. address: 0xC80 priv_mode: U reset-val: 0 time: rv32: accessible: false rv64: accessible: false description: Timer for RDTIME instruction and RTC in the processor. priv_mode: U address: 0xC01 reset-val: 0 timeh: rv32: accessible: false rv64: accessible: false description: Upper 32-bits of the Timer for RDTIME instruction and RTC in the processor; only for rv32. address: 0xC81 priv_mode: U reset-val: 0 instret: rv32: accessible: false rv64: accessible: false description: Captures the number of instructions executed from an arbitrary point in time. priv_mode: U address: 0xC02 reset-val: 0 instreth: rv32: accessible: false rv64: accessible: false description: Upper 32-bits of the minstret counter; only for rv32. address: 0xC82 priv_mode: U reset-val: 0 hpmcounter3: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter3 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC03 hpmcounter4: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter4 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC04 hpmcounter5: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter5 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC05 hpmcounter6: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter6 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC06 hpmcounter7: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter7 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC07 hpmcounter8: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter8 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC08 hpmcounter9: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter9 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC09 hpmcounter10: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter10 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC0A hpmcounter11: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter11 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC0B hpmcounter12: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter12 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC0C hpmcounter13: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter13 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC0D hpmcounter14: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter14 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC0E hpmcounter15: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter15 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC0F hpmcounter16: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter16 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC10 hpmcounter17: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter17 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC11 hpmcounter18: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter18 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC12 hpmcounter19: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter19 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC13 hpmcounter20: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter20 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC14 hpmcounter21: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter21 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC15 hpmcounter22: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter22 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC16 hpmcounter23: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter23 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC17 hpmcounter24: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter24 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC18 hpmcounter25: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter25 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC19 hpmcounter26: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter26 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC1A hpmcounter27: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter27 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC1B hpmcounter28: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter28 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC1C hpmcounter29: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter29 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC1D hpmcounter30: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter30 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC1E hpmcounter31: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter31 is a 64-bit counter. Returns lower 32 bits in RV32UI mode. address: 0xC1F hpmcounter3h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter3h returns the upper half word in RV32I systems. address: 0xC83 hpmcounter4h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter4h returns the upper half word in RV32I systems. address: 0xC84 hpmcounter5h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter5h returns the upper half word in RV32I systems. address: 0xC85 hpmcounter6h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter6h returns the upper half word in RV32I systems. address: 0xC86 hpmcounter7h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter7h returns the upper half word in RV32I systems. address: 0xC87 hpmcounter8h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter8h returns the upper half word in RV32I systems. address: 0xC88 hpmcounter9h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter9h returns the upper half word in RV32I systems. address: 0xC89 hpmcounter10h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter10h returns the upper half word in RV32I systems. address: 0xC8A hpmcounter11h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter11h returns the upper half word in RV32I systems. address: 0xC8B hpmcounter12h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter12h returns the upper half word in RV32I systems. address: 0xC8C hpmcounter13h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter13h returns the upper half word in RV32I systems. address: 0xC8D hpmcounter14h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter14h returns the upper half word in RV32I systems. address: 0xC8E hpmcounter15h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter15h returns the upper half word in RV32I systems. address: 0xC8F hpmcounter16h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter16h returns the upper half word in RV32I systems. address: 0xC90 hpmcounter17h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter17h returns the upper half word in RV32I systems. address: 0xC91 hpmcounter18h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter18h returns the upper half word in RV32I systems. address: 0xC92 hpmcounter19h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter19h returns the upper half word in RV32I systems. address: 0xC93 hpmcounter20h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter20h returns the upper half word in RV32I systems. address: 0xC94 hpmcounter21h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter21h returns the upper half word in RV32I systems. address: 0xC95 hpmcounter22h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter22h returns the upper half word in RV32I systems. address: 0xC96 hpmcounter23h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter23h returns the upper half word in RV32I systems. address: 0xC97 hpmcounter24h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter24h returns the upper half word in RV32I systems. address: 0xC98 hpmcounter25h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter25h returns the upper half word in RV32I systems. address: 0xC99 hpmcounter26h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter26h returns the upper half word in RV32I systems. address: 0xC9A hpmcounter27h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter27h returns the upper half word in RV32I systems. address: 0xC9B hpmcounter28h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter28h returns the upper half word in RV32I systems. address: 0xC9C hpmcounter29h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter29h returns the upper half word in RV32I systems. address: 0xC9D hpmcounter30h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter30h returns the upper half word in RV32I systems. address: 0xC9E hpmcounter31h: rv32: accessible: false rv64: accessible: false priv_mode: U reset-val: 0 description: The hpmcounter31h returns the upper half word in RV32I systems. address: 0xC9F sstatus: rv32: accessible: false rv64: accessible: false description: The sstatus register keeps track of the processor’s current operating state. address: 0x100 priv_mode: S reset-val: 0 sie: rv32: accessible: false rv64: accessible: false description: The sie register is an SXLEN-bit read/write register containing interrupt enable bits. address: 0x104 priv_mode: S reset-val: 0 sip: rv32: accessible: false rv64: accessible: false description: The sip register is an SXLEN-bit read/write register containing interrupt pending bits. address: 0x144 priv_mode: S reset-val: 0 sepc: rv32: accessible: false rv64: accessible: false description: The sepc is a warl register that must be able to hold all valid physical and virtual addresses. address: 0x141 priv_mode: S reset-val: 0 stval: rv32: accessible: false rv64: accessible: false description: The stval is a warl register that holds the address of the instruction which caused the exception. address: 0x143 priv_mode: S reset-val: 0 scause: rv32: accessible: false rv64: accessible: false description: The scause register stores the information regarding the trap. address: 0x142 priv_mode: M reset-val: 0 stvec: rv32: accessible: false rv64: accessible: false description: SXLEN-bit read/write register that holds trap vector configuration. address: 0x105 priv_mode: S reset-val: 0 satp: rv32: accessible: false rv64: accessible: false description: SXLEN-bit register which controls supervisor-mode address translation and protection address: 0x180 priv_mode: S reset-val: 0
/scratch/git-repo/incoresemi/riscof/riscof_work/sail_platform_checked.yaml
nmi: label: nmi_vector reset: label: reset_vector mtime: implemented: false mtimecmp: implemented: false mcause_non_standard: implemented: true mtval_condition_writes: implemented: false scause_non_standard: implemented: false stval_condition_writes: implemented: false

Please visit YAML specifications for more information.

## Test Stats

Test Name | Mem Footprint (Bytes) | Code size (Bytes) | Data size (Bytes) | Sign size (Bytes) | Covergroups
--- | --- | --- | --- | --- | ---
/scratch/git-repo/github/riscv-compliance/riscv-test-suite/rv64i_m/privilege/src/ebreak.S | 6908 | 36 | 144 | 32 | {'ebreak'}
/scratch/git-repo/github/riscv-compliance/riscv-test-suite/rv64i_m/privilege/src/ecall.S | 6908 | 36 | 144 | 32 | {'ecall'}
/scratch/git-repo/github/riscv-compliance/riscv-test-suite/rv64i_m/privilege/src/misalign-beq-01.S | 7456 | 84 | 148 | 528 | {'misalign-beq'}
/scratch/git-repo/github/riscv-compliance/riscv-test-suite/rv64i_m/privilege/src/misalign-bge-01.S | 7492 | 132 | 148 | 528 | {'misalign-bge'}
/scratch/git-repo/github/riscv-compliance/riscv-test-suite/rv64i_m/privilege/src/misalign-bgeu-01.S | 7492 | 132 | 148 | 528 | {'misalign-bgeu'}
/scratch/git-repo/github/riscv-compliance/riscv-test-suite/rv64i_m/privilege/src/misalign-blt-01.S | 7460 | 84 | 148 | 528 | {'misalign-blt'}
/scratch/git-repo/github/riscv-compliance/riscv-test-suite/rv64i_m/privilege/src/misalign-bltu-01.S | 7452 | 68 | 148 | 528 | {'misalign-bltu'}
/scratch/git-repo/github/riscv-compliance/riscv-test-suite/rv64i_m/privilege/src/misalign-bne-01.S | 7464 | 84 | 148 | 528 | {'misalign-bne'}
/scratch/git-repo/github/riscv-compliance/riscv-test-suite/rv64i_m/privilege/src/misalign-jal-01.S | 7496 | 116 | 148 | 528 | {'misalign-jal'}
/scratch/git-repo/github/riscv-compliance/riscv-test-suite/rv64i_m/privilege/src/misalign-ld-01.S | 7552 | 180 | 148 | 576 | {'misalign-ld'}
/scratch/git-repo/github/riscv-compliance/riscv-test-suite/rv64i_m/privilege/src/misalign-lh-01.S | 7424 | 36 | 148 | 528 | {'misalign-lh'}
/scratch/git-repo/github/riscv-compliance/riscv-test-suite/rv64i_m/privilege/src/misalign-lhu-01.S | 7424 | 36 | 148 | 528 | {'misalign-lhu'}
/scratch/git-repo/github/riscv-compliance/riscv-test-suite/rv64i_m/privilege/src/misalign-lw-01.S | 7456 | 84 | 148 | 544 | {'misalign-lw'}
/scratch/git-repo/github/riscv-compliance/riscv-test-suite/rv64i_m/privilege/src/misalign-lwu-01.S | 7456 | 84 | 148 | 544 | {'misalign-lwu'}
/scratch/git-repo/github/riscv-compliance/riscv-test-suite/rv64i_m/privilege/src/misalign-sd-01.S | 7624 | 260 | 148 | 576 | {'misalign-sd'}
/scratch/git-repo/github/riscv-compliance/riscv-test-suite/rv64i_m/privilege/src/misalign-sh-01.S | 7420 | 36 | 148 | 528 | {'misalign-sh'}
/scratch/git-repo/github/riscv-compliance/riscv-test-suite/rv64i_m/privilege/src/misalign-sw-01.S | 7484 | 100 | 148 | 544 | {'misalign-sw'}
/scratch/git-repo/github/riscv-compliance/riscv-test-suite/rv64i_m/privilege/src/misalign1-jalr-01.S | 7464 | 84 | 148 | 528 | {'misalign1-jalr'}
/scratch/git-repo/github/riscv-compliance/riscv-test-suite/rv64i_m/privilege/src/misalign2-jalr-01.S | 7460 | 84 | 148 | 528 | {'misalign2-jalr'}

## Coverage Report ( Total Coverpoints: 54 )

Coverage Label | (Covered-points)/(Total-points) | Percentage
--- | --- | ---
ecall | 1/1 | 100.00%
coverage: 1/1 opcode: coverage: 1/1 detail: - ecall: 1
ebreak | 1/1 | 100.00%
coverage: 1/1 opcode: coverage: 1/1 detail: - ebreak: 1
misalign-lh | 2/2 | 100.00%
coverage: 2/2 opcode: coverage: 1/1 detail: - lh: 1 val_comb: coverage: 1/1 detail: - ea_align == 1: 1
misalign-lhu | 2/2 | 100.00%
coverage: 2/2 opcode: coverage: 1/1 detail: - lhu: 1 val_comb: coverage: 1/1 detail: - ea_align == 1: 1
misalign-lwu | 4/4 | 100.00%
coverage: 4/4 opcode: coverage: 1/1 detail: - lwu: 3 val_comb: coverage: 3/3 detail: - ea_align == 1: 1 - ea_align == 2: 1 - ea_align == 3: 1
misalign-sd | 8/8 | 100.00%
coverage: 8/8 opcode: coverage: 1/1 detail: - sd: 7 val_comb: coverage: 7/7 detail: - ea_align == 1: 1 - ea_align == 2: 1 - ea_align == 3: 1 - ea_align == 4: 1 - ea_align == 5: 1 - ea_align == 6: 1 - ea_align == 7: 1
misalign-ld | 8/8 | 100.00%
coverage: 8/8 opcode: coverage: 1/1 detail: - ld: 7 val_comb: coverage: 7/7 detail: - ea_align == 1: 1 - ea_align == 2: 1 - ea_align == 3: 1 - ea_align == 4: 1 - ea_align == 5: 1 - ea_align == 6: 1 - ea_align == 7: 1
misalign-lw | 4/4 | 100.00%
coverage: 4/4 opcode: coverage: 1/1 detail: - lw: 3 val_comb: coverage: 3/3 detail: - ea_align == 1: 1 - ea_align == 2: 1 - ea_align == 3: 1
misalign-sh | 2/2 | 100.00%
coverage: 2/2 opcode: coverage: 1/1 detail: - sh: 1 val_comb: coverage: 1/1 detail: - ea_align == 1: 1
misalign-sw | 4/4 | 100.00%
coverage: 4/4 opcode: coverage: 1/1 detail: - sw: 3 val_comb: coverage: 3/3 detail: - ea_align == 1: 1 - ea_align == 2: 1 - ea_align == 3: 1
misalign2-jalr | 2/2 | 100.00%
coverage: 2/2 opcode: coverage: 1/1 detail: - jalr: 1 val_comb: coverage: 1/1 detail: - ea_align == 2: 1
misalign1-jalr | 2/2 | 100.00%
coverage: 2/2 opcode: coverage: 1/1 detail: - jalr: 1 val_comb: coverage: 1/1 detail: - ea_align == 1: 1
misalign-jal | 2/2 | 100.00%
coverage: 2/2 opcode: coverage: 1/1 detail: - jal: 1 val_comb: coverage: 1/1 detail: - ea_align == 2: 1
misalign-bge | 2/2 | 100.00%
coverage: 2/2 opcode: coverage: 1/1 detail: - bge: 1 val_comb: coverage: 1/1 detail: - rs1_val>rs2_val and ea_align == 2: 1
misalign-bgeu | 2/2 | 100.00%
coverage: 2/2 opcode: coverage: 1/1 detail: - bgeu: 1 val_comb: coverage: 1/1 detail: - rs1_val>rs2_val and ea_align == 2: 1
misalign-blt | 2/2 | 100.00%
coverage: 2/2 opcode: coverage: 1/1 detail: - blt: 1 val_comb: coverage: 1/1 detail: - rs1_val
misalign-bltu | 2/2 | 100.00%
coverage: 2/2 opcode: coverage: 1/1 detail: - bltu: 1 val_comb: coverage: 1/1 detail: - rs1_val
misalign-bne | 2/2 | 100.00%
coverage: 2/2 opcode: coverage: 1/1 detail: - bne: 1 val_comb: coverage: 1/1 detail: - rs1_val!=rs2_val and ea_align == 2: 1
misalign-beq | 2/2 | 100.00%
coverage: 2/2 opcode: coverage: 1/1 detail: - beq: 1 val_comb: coverage: 1/1 detail: - rs1_val==rs2_val and ea_align == 2: 1