
// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version   : 0.4.1
// timestamp : Wed Dec 16 08:50:23 2020 GMT
// usage     : riscv_ctg \
//                  -- cgf ('/scratch/git-repo/incoresemi/riscv-compliance/riscv_ctg/sample_cgfs/dataset.cgf', '/scratch/git-repo/incoresemi/riscv-compliance/riscv_ctg/sample_cgfs/rv64i_priv.cgf') \
//                  -- xlen 64 \
// -----------
//
// -----------
// Copyright (c) 2020. RISC-V International. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the ld instruction of the RISC-V I extension for the misalign-ld covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV64I")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*); check hw_data_misaligned_support:=True; def rvtest_mtrap_routine=True;def TEST_CASE_1=True;",misalign-ld)

RVTEST_CASE(1,"//check ISA:=regex(.*64.*);check ISA:=regex(.*I.*Zicsr.*); check hw_data_misaligned_support:=False; def rvtest_mtrap_routine=True;def TEST_CASE_1=True;",misalign-ld)

RVTEST_SIGBASE( x1,signature_x1_1)

inst_0:
// ea_align == 1, 
// opcode:ld op1:x10; dest:x11; immval:0x80; align:1
TEST_LOAD(x1,x2,0,x10,x11,0x80,0,ld,1)

inst_1:
// ea_align == 2, 
// opcode:ld op1:x10; dest:x11; immval:-0x400; align:2
TEST_LOAD(x1,x2,0,x10,x11,-0x400,8,ld,2)

inst_2:
// ea_align == 3, 
// opcode:ld op1:x10; dest:x11; immval:0x400; align:3
TEST_LOAD(x1,x2,0,x10,x11,0x400,16,ld,3)

inst_3:
// ea_align == 4, 
// opcode:ld op1:x10; dest:x11; immval:0x200; align:4
TEST_LOAD(x1,x2,0,x10,x11,0x200,24,ld,4)

inst_4:
// ea_align == 5, 
// opcode:ld op1:x10; dest:x11; immval:0x200; align:5
TEST_LOAD(x1,x2,0,x10,x11,0x200,32,ld,5)

inst_5:
// ea_align == 6, 
// opcode:ld op1:x10; dest:x11; immval:0x9; align:6
TEST_LOAD(x1,x2,0,x10,x11,0x9,40,ld,6)

inst_6:
// ea_align == 7, 
// opcode:ld op1:x10; dest:x11; immval:0x40; align:7
TEST_LOAD(x1,x2,0,x10,x11,0x40,48,ld,7)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END

RVMODEL_DATA_BEGIN


signature_x1_0:
    .fill 0*(XLEN/32),4,0xdeadbeef


signature_x1_1:
    .fill 7*(XLEN/32),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*(XLEN/32),4,0xdeadbeef

#endif

RVMODEL_DATA_END
