// -----------
// This file was generated by riscv_ctg (https://gitlab.com/incoresemi/riscv-compliance/riscv_ctg)
// version   : 0.4.5
// timestamp : Thu May 20 05:54:26 2021 GMT
// usage     : riscv_ctg \
//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/dataset.cgf \
//                  --cgf /scratch/git-repo/github/riscv-ctg/sample_cgfs/rv32i_k.cgf \
//                  --base-isa rv32i \
//                  --randomize
// -----------
//
// -----------
// Copyright (c) 2021. Indian Institute of Technology Madras. All rights reserved.
// SPDX-License-Identifier: BSD-3-Clause
// -----------
//
// This assembly file tests the sm3p1 instruction of the RISC-V  extension for the sm3p1 covergroup.
// 
#include "model_test.h"
#include "arch_test.h"
RVTEST_ISA("RV32I_Zks")

.section .text.init
.globl rvtest_entry_point
rvtest_entry_point:
RVMODEL_BOOT
RVTEST_CODE_BEGIN

#ifdef TEST_CASE_1

RVTEST_CASE(0,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*K.*);def TEST_CASE_1=True;",sm3p1)

RVTEST_CASE(1,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*ZKn.*);def TEST_CASE_1=True;",sm3p1)

RVTEST_CASE(2,"//check ISA:=regex(.*32.*);check ISA:=regex(.*I.*ZKsh.*);def TEST_CASE_1=True;",sm3p1)

RVTEST_SIGBASE( x3,signature_x3_1)

inst_0:
// rs1 != rd, rs1==x5, rd==x24, rs1_val == 0x254a9493 
// opcode: sm3p1 ; op1:x5; dest:x24; op1val:0x254a9493;
li x5, 0x254a9493
sm3p1 x24, x5
sw x24, 0(x3)
RVMODEL_IO_ASSERT_GPR_EQ(x6, x24, 0x00000000)

inst_1:
// rs1 == rd, rs1==x10, rd==x10, rs1_val == 2147483647, 
// opcode: sm3p1 ; op1:x10; dest:x10; op1val:0x7fffffff;
li x10, 0x7fffffff
sm3p1 x10, x10
sw x10, 4(x3)
RVMODEL_IO_ASSERT_GPR_EQ(x6, x10, 0x00000000)

inst_2:
// rs1==x21, rd==x29, rs1_val == 3221225471, 
// opcode: sm3p1 ; op1:x21; dest:x29; op1val:0xbfffffff;
li x21, 0xbfffffff
sm3p1 x29, x21
sw x29, 8(x3)
RVMODEL_IO_ASSERT_GPR_EQ(x6, x29, 0x00000000)

inst_3:
// rs1==x29, rd==x9, rs1_val == 3758096383, 
// opcode: sm3p1 ; op1:x29; dest:x9; op1val:0xdfffffff;
li x29, 0xdfffffff
sm3p1 x9, x29
sw x9, 12(x3)
RVMODEL_IO_ASSERT_GPR_EQ(x6, x9, 0x00000000)

inst_4:
// rs1==x8, rd==x16, rs1_val == 4026531839, 
// opcode: sm3p1 ; op1:x8; dest:x16; op1val:0xefffffff;
li x8, 0xefffffff
sm3p1 x16, x8
sw x16, 16(x3)
RVMODEL_IO_ASSERT_GPR_EQ(x6, x16, 0x00000000)

inst_5:
// rs1==x4, rd==x8, rs1_val == 4160749567, 
// opcode: sm3p1 ; op1:x4; dest:x8; op1val:0xf7ffffff;
li x4, 0xf7ffffff
sm3p1 x8, x4
sw x8, 20(x3)
RVMODEL_IO_ASSERT_GPR_EQ(x6, x8, 0x00000000)

inst_6:
// rs1==x30, rd==x14, rs1_val == 4227858431, 
// opcode: sm3p1 ; op1:x30; dest:x14; op1val:0xfbffffff;
li x30, 0xfbffffff
sm3p1 x14, x30
sw x14, 24(x3)
RVMODEL_IO_ASSERT_GPR_EQ(x6, x14, 0x00000000)

inst_7:
// rs1==x17, rd==x1, rs1_val == 4261412863, 
// opcode: sm3p1 ; op1:x17; dest:x1; op1val:0xfdffffff;
li x17, 0xfdffffff
sm3p1 x1, x17
sw x1, 28(x3)
RVMODEL_IO_ASSERT_GPR_EQ(x6, x1, 0x00000000)

inst_8:
// rs1==x27, rd==x23, rs1_val == 4278190079, 
// opcode: sm3p1 ; op1:x27; dest:x23; op1val:0xfeffffff;
li x27, 0xfeffffff
sm3p1 x23, x27
sw x23, 32(x3)
RVMODEL_IO_ASSERT_GPR_EQ(x6, x23, 0x00000000)

inst_9:
// rs1==x22, rd==x17, rs1_val == 4286578687, 
// opcode: sm3p1 ; op1:x22; dest:x17; op1val:0xff7fffff;
li x22, 0xff7fffff
sm3p1 x17, x22
sw x17, 36(x3)
RVMODEL_IO_ASSERT_GPR_EQ(x6, x17, 0x00000000)

inst_10:
// rs1==x7, rd==x18, rs1_val == 4290772991, 
// opcode: sm3p1 ; op1:x7; dest:x18; op1val:0xffbfffff;
li x7, 0xffbfffff
sm3p1 x18, x7
sw x18, 40(x3)
RVMODEL_IO_ASSERT_GPR_EQ(x6, x18, 0x00000000)

inst_11:
// rs1==x16, rd==x21, rs1_val == 4292870143, 
// opcode: sm3p1 ; op1:x16; dest:x21; op1val:0xffdfffff;
li x16, 0xffdfffff
sm3p1 x21, x16
sw x21, 44(x3)
RVMODEL_IO_ASSERT_GPR_EQ(x6, x21, 0x00000000)

inst_12:
// rs1==x1, rd==x26, rs1_val == 4293918719, 
// opcode: sm3p1 ; op1:x1; dest:x26; op1val:0xffefffff;
li x1, 0xffefffff
sm3p1 x26, x1
sw x26, 48(x3)
RVMODEL_IO_ASSERT_GPR_EQ(x6, x26, 0x00000000)

inst_13:
// rs1==x9, rd==x19, rs1_val == 4294443007, 
// opcode: sm3p1 ; op1:x9; dest:x19; op1val:0xfff7ffff;
li x9, 0xfff7ffff
sm3p1 x19, x9
sw x19, 52(x3)
RVMODEL_IO_ASSERT_GPR_EQ(x6, x19, 0x00000000)

inst_14:
// rs1==x26, rd==x22, rs1_val == 4294705151, 
// opcode: sm3p1 ; op1:x26; dest:x22; op1val:0xfffbffff;
li x26, 0xfffbffff
sm3p1 x22, x26
sw x22, 56(x3)
RVMODEL_IO_ASSERT_GPR_EQ(x6, x22, 0x00000000)

inst_15:
// rs1==x2, rd==x15, rs1_val == 4294836223, 
// opcode: sm3p1 ; op1:x2; dest:x15; op1val:0xfffdffff;
li x2, 0xfffdffff
sm3p1 x15, x2
sw x15, 60(x3)
RVMODEL_IO_ASSERT_GPR_EQ(x6, x15, 0x00000000)

inst_16:
// rs1==x15, rd==x4, rs1_val == 4294901759, 
// opcode: sm3p1 ; op1:x15; dest:x4; op1val:0xfffeffff;
li x15, 0xfffeffff
sm3p1 x4, x15
sw x4, 64(x3)
RVMODEL_IO_ASSERT_GPR_EQ(x6, x4, 0x00000000)

inst_17:
// rs1==x25, rd==x20, rs1_val == 4294934527, 
// opcode: sm3p1 ; op1:x25; dest:x20; op1val:0xffff7fff;
li x25, 0xffff7fff
sm3p1 x20, x25
sw x20, 68(x3)
RVMODEL_IO_ASSERT_GPR_EQ(x6, x20, 0x00000000)

inst_18:
// rs1==x14, rd==x12, rs1_val == 4294950911, 
// opcode: sm3p1 ; op1:x14; dest:x12; op1val:0xffffbfff;
li x14, 0xffffbfff
sm3p1 x12, x14
sw x12, 72(x3)
RVMODEL_IO_ASSERT_GPR_EQ(x6, x12, 0x00000000)

inst_19:
// rs1==x12, rd==x7, rs1_val == 4294959103, 
// opcode: sm3p1 ; op1:x12; dest:x7; op1val:0xffffdfff;
li x12, 0xffffdfff
sm3p1 x7, x12
sw x7, 76(x3)
RVMODEL_IO_ASSERT_GPR_EQ(x6, x7, 0x00000000)

inst_20:
// rs1==x13, rd==x27, rs1_val == 4294963199, 
// opcode: sm3p1 ; op1:x13; dest:x27; op1val:0xffffefff;
li x13, 0xffffefff
sm3p1 x27, x13
sw x27, 80(x3)
RVMODEL_IO_ASSERT_GPR_EQ(x6, x27, 0x00000000)

inst_21:
// rs1==x19, rd==x31, rs1_val == 4294965247, 
// opcode: sm3p1 ; op1:x19; dest:x31; op1val:0xfffff7ff;
li x19, 0xfffff7ff
sm3p1 x31, x19
sw x31, 84(x3)
RVMODEL_IO_ASSERT_GPR_EQ(x6, x31, 0x00000000)

inst_22:
// rs1==x28, rd==x6, rs1_val == 4294966271, 
// opcode: sm3p1 ; op1:x28; dest:x6; op1val:0xfffffbff;
li x28, 0xfffffbff
sm3p1 x6, x28
sw x6, 88(x3)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x6, 0x00000000)
RVTEST_SIGBASE( x1,signature_x1_0)

inst_23:
// rs1==x6, rd==x11, rs1_val == 4294966783, 
// opcode: sm3p1 ; op1:x6; dest:x11; op1val:0xfffffdff;
li x6, 0xfffffdff
sm3p1 x11, x6
sw x11, 0(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_24:
// rs1==x11, rd==x25, rs1_val == 4294967039, 
// opcode: sm3p1 ; op1:x11; dest:x25; op1val:0xfffffeff;
li x11, 0xfffffeff
sm3p1 x25, x11
sw x25, 4(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x25, 0x00000000)

inst_25:
// rs1==x3, rd==x0, rs1_val == 4294967167, 
// opcode: sm3p1 ; op1:x3; dest:x0; op1val:0xffffff7f;
li x3, 0xffffff7f
sm3p1 x0, x3
sw x0, 8(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x0, 0x00000000)

inst_26:
// rs1==x24, rd==x5, rs1_val == 4294967231, 
// opcode: sm3p1 ; op1:x24; dest:x5; op1val:0xffffffbf;
li x24, 0xffffffbf
sm3p1 x5, x24
sw x5, 12(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x5, 0x00000000)

inst_27:
// rs1==x23, rd==x13, rs1_val == 4294967263, 
// opcode: sm3p1 ; op1:x23; dest:x13; op1val:0xffffffdf;
li x23, 0xffffffdf
sm3p1 x13, x23
sw x13, 16(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x13, 0x00000000)

inst_28:
// rs1==x0, rd==x28, rs1_val == 4294967279, 
// opcode: sm3p1 ; op1:x0; dest:x28; op1val:0x0;
li x0, 0x0
sm3p1 x28, x0
sw x28, 20(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x28, 0x00000000)

inst_29:
// rs1==x20, rd==x3, rs1_val == 4294967287, 
// opcode: sm3p1 ; op1:x20; dest:x3; op1val:0xfffffff7;
li x20, 0xfffffff7
sm3p1 x3, x20
sw x3, 24(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x3, 0x00000000)

inst_30:
// rs1==x18, rd==x2, rs1_val == 4294967291, 
// opcode: sm3p1 ; op1:x18; dest:x2; op1val:0xfffffffb;
li x18, 0xfffffffb
sm3p1 x2, x18
sw x2, 28(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x2, 0x00000000)

inst_31:
// rs1==x31, rd==x30, rs1_val == 4294967293, 
// opcode: sm3p1 ; op1:x31; dest:x30; op1val:0xfffffffd;
li x31, 0xfffffffd
sm3p1 x30, x31
sw x30, 32(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x30, 0x00000000)

inst_32:
// rs1_val == 4294967294, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xfffffffe;
li x10, 0xfffffffe
sm3p1 x11, x10
sw x11, 36(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_33:
// rs1_val == 2147483648, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x80000000;
li x10, 0x80000000
sm3p1 x11, x10
sw x11, 40(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_34:
// rs1_val == 1073741824, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x40000000;
li x10, 0x40000000
sm3p1 x11, x10
sw x11, 44(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_35:
// rs1_val == 536870912, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x20000000;
li x10, 0x20000000
sm3p1 x11, x10
sw x11, 48(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_36:
// rs1_val == 268435456, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x10000000;
li x10, 0x10000000
sm3p1 x11, x10
sw x11, 52(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_37:
// rs1_val == 134217728, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x8000000;
li x10, 0x8000000
sm3p1 x11, x10
sw x11, 56(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_38:
// rs1_val == 67108864, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x4000000;
li x10, 0x4000000
sm3p1 x11, x10
sw x11, 60(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_39:
// rs1_val == 33554432, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x2000000;
li x10, 0x2000000
sm3p1 x11, x10
sw x11, 64(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_40:
// rs1_val == 16777216, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x1000000;
li x10, 0x1000000
sm3p1 x11, x10
sw x11, 68(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_41:
// rs1_val == 8388608, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x800000;
li x10, 0x800000
sm3p1 x11, x10
sw x11, 72(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_42:
// rs1_val == 4194304, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x400000;
li x10, 0x400000
sm3p1 x11, x10
sw x11, 76(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_43:
// rs1_val == 2097152, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x200000;
li x10, 0x200000
sm3p1 x11, x10
sw x11, 80(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_44:
// rs1_val == 1048576, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x100000;
li x10, 0x100000
sm3p1 x11, x10
sw x11, 84(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_45:
// rs1_val == 524288, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x80000;
li x10, 0x80000
sm3p1 x11, x10
sw x11, 88(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_46:
// rs1_val == 262144, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x40000;
li x10, 0x40000
sm3p1 x11, x10
sw x11, 92(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_47:
// rs1_val == 131072, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x20000;
li x10, 0x20000
sm3p1 x11, x10
sw x11, 96(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_48:
// rs1_val == 65536, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x10000;
li x10, 0x10000
sm3p1 x11, x10
sw x11, 100(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_49:
// rs1_val == 32768, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x8000;
li x10, 0x8000
sm3p1 x11, x10
sw x11, 104(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_50:
// rs1_val == 16384, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x4000;
li x10, 0x4000
sm3p1 x11, x10
sw x11, 108(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_51:
// rs1_val == 8192, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x2000;
li x10, 0x2000
sm3p1 x11, x10
sw x11, 112(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_52:
// rs1_val == 4096, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x1000;
li x10, 0x1000
sm3p1 x11, x10
sw x11, 116(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_53:
// rs1_val == 1, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x1;
li x10, 0x1
sm3p1 x11, x10
sw x11, 120(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_54:
// rs1_val == 0x3150e5fa 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x3150e5fa;
li x10, 0x3150e5fa
sm3p1 x11, x10
sw x11, 124(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_55:
// rs1_val == 0x90efb625 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x90efb625;
li x10, 0x90efb625
sm3p1 x11, x10
sw x11, 128(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_56:
// rs1_val == 0x65408c73 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x65408c73;
li x10, 0x65408c73
sm3p1 x11, x10
sw x11, 132(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_57:
// rs1_val == 0x1fc493ca 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x1fc493ca;
li x10, 0x1fc493ca
sm3p1 x11, x10
sw x11, 136(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_58:
// rs1_val == 0xd169a3f8 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xd169a3f8;
li x10, 0xd169a3f8
sm3p1 x11, x10
sw x11, 140(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_59:
// rs1_val == 0x8e2eac2a 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x8e2eac2a;
li x10, 0x8e2eac2a
sm3p1 x11, x10
sw x11, 144(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_60:
// rs1_val == 0xf4c30307 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xf4c30307;
li x10, 0xf4c30307
sm3p1 x11, x10
sw x11, 148(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_61:
// rs1_val == 0x35f9377f 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x35f9377f;
li x10, 0x35f9377f
sm3p1 x11, x10
sw x11, 152(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_62:
// rs1_val == 0xa0569d76 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xa0569d76;
li x10, 0xa0569d76
sm3p1 x11, x10
sw x11, 156(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_63:
// rs1_val == 0x58d548aa 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x58d548aa;
li x10, 0x58d548aa
sm3p1 x11, x10
sw x11, 160(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_64:
// rs1_val == 0x2daf9ac7 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x2daf9ac7;
li x10, 0x2daf9ac7
sm3p1 x11, x10
sw x11, 164(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_65:
// rs1_val == 0x55d98c6e 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x55d98c6e;
li x10, 0x55d98c6e
sm3p1 x11, x10
sw x11, 168(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_66:
// rs1_val == 0xf273b44c 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xf273b44c;
li x10, 0xf273b44c
sm3p1 x11, x10
sw x11, 172(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_67:
// rs1_val == 0x74b8de87 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x74b8de87;
li x10, 0x74b8de87
sm3p1 x11, x10
sw x11, 176(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_68:
// rs1_val == 0x886c3a30 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x886c3a30;
li x10, 0x886c3a30
sm3p1 x11, x10
sw x11, 180(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_69:
// rs1_val == 0xccce240c 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xccce240c;
li x10, 0xccce240c
sm3p1 x11, x10
sw x11, 184(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_70:
// rs1_val == 0xbb61a9cd 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xbb61a9cd;
li x10, 0xbb61a9cd
sm3p1 x11, x10
sw x11, 188(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_71:
// rs1_val == 0xb49c83dc 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xb49c83dc;
li x10, 0xb49c83dc
sm3p1 x11, x10
sw x11, 192(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_72:
// rs1_val == 0xc5521660 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xc5521660;
li x10, 0xc5521660
sm3p1 x11, x10
sw x11, 196(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_73:
// rs1_val == 2048, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x800;
li x10, 0x800
sm3p1 x11, x10
sw x11, 200(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_74:
// rs1_val == 1024, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x400;
li x10, 0x400
sm3p1 x11, x10
sw x11, 204(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_75:
// rs1_val == 512, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x200;
li x10, 0x200
sm3p1 x11, x10
sw x11, 208(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_76:
// rs1_val == 256, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x100;
li x10, 0x100
sm3p1 x11, x10
sw x11, 212(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_77:
// rs1_val == 128, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x80;
li x10, 0x80
sm3p1 x11, x10
sw x11, 216(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_78:
// rs1_val == 64, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x40;
li x10, 0x40
sm3p1 x11, x10
sw x11, 220(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_79:
// rs1_val == 32, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x20;
li x10, 0x20
sm3p1 x11, x10
sw x11, 224(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_80:
// rs1_val == 16, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x10;
li x10, 0x10
sm3p1 x11, x10
sw x11, 228(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_81:
// rs1_val == 8, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x8;
li x10, 0x8
sm3p1 x11, x10
sw x11, 232(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_82:
// rs1_val == 4, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x4;
li x10, 0x4
sm3p1 x11, x10
sw x11, 236(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_83:
// rs1_val == 2, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0x2;
li x10, 0x2
sm3p1 x11, x10
sw x11, 240(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_84:
// rs1_val == 4294967167, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xffffff7f;
li x10, 0xffffff7f
sm3p1 x11, x10
sw x11, 244(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)

inst_85:
// rs1_val == 4294967279, 
// opcode: sm3p1 ; op1:x10; dest:x11; op1val:0xffffffef;
li x10, 0xffffffef
sm3p1 x11, x10
sw x11, 248(x1)
RVMODEL_IO_ASSERT_GPR_EQ(x4, x11, 0x00000000)
#endif


RVTEST_CODE_END
RVMODEL_HALT

RVTEST_DATA_BEGIN
.align 4
rvtest_data:
.word 0xbabecafe
RVTEST_DATA_END

RVMODEL_DATA_BEGIN


signature_x3_0:
    .fill 0*(XLEN/32),4,0xdeadbeef


signature_x3_1:
    .fill 23*(XLEN/32),4,0xdeadbeef


signature_x1_0:
    .fill 63*(XLEN/32),4,0xdeadbeef

#ifdef rvtest_mtrap_routine

mtrap_sigptr:
    .fill 64*(XLEN/32),4,0xdeadbeef

#endif

#ifdef rvtest_gpr_save

gpr_save:
    .fill 32*(XLEN/32),4,0xdeadbeef

#endif

RVMODEL_DATA_END
