Console Output

Started by user Gabriel Cabral
[Pipeline] Start of Pipeline
[Pipeline] node
Still waiting to schedule task
Waiting for next available executor
Running on Jenkins in /var/jenkins_home/workspace/serv
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf serv
[Pipeline] sh
+ git clone --recursive --depth=1 https://github.com/olofk/serv serv
Cloning into 'serv'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/jenkins_home/workspace/serv/serv
[Pipeline] {
[Pipeline] sh
+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s serv_top rtl/serv_aligner.v rtl/serv_alu.v rtl/serv_bufreg.v rtl/serv_bufreg2.v rtl/serv_compdec.v rtl/serv_csr.v rtl/serv_ctrl.v rtl/serv_decode.v rtl/serv_immdec.v rtl/serv_mem_if.v rtl/serv_rf_if.v rtl/serv_rf_ram.v rtl/serv_rf_ram_if.v rtl/serv_rf_top.v rtl/serv_state.v rtl/serv_synth_wrapper.v rtl/serv_top.v
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Utilities)
[Pipeline] dir
Running in /var/jenkins_home/workspace/serv/serv
[Pipeline] {
[Pipeline] sh
+ pwd
+ python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/serv/serv -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels.json
Results saved to /jenkins/processor_ci_utils/labels.json
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_nexys4_ddr)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_nexys4_ddr)
[Pipeline] lock
Trying to acquire lock on [Resource: colorlight_i9]
The resource [colorlight_i9] is locked by build riscado-v #103 #103 since Feb 5, 2025, 3:20 PM.
[Resource: colorlight_i9] is not free, waiting for execution ...
[Required resources: [colorlight_i9]] added into queue at position 0
[Pipeline] lock
Trying to acquire lock on [Resource: digilent_nexys4_ddr]
Resource [digilent_nexys4_ddr] did not exist. Created.
Lock acquired on [Resource: digilent_nexys4_ddr]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] dir
Running in /var/jenkins_home/workspace/serv/serv
[Pipeline] {
[Pipeline] echo
Starting synthesis for FPGA digilent_nexys4_ddr.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p serv -b digilent_nexys4_ddr
Final configuration file generated at /var/jenkins_home/workspace/serv/serv/build_digilent_nexys4_ddr.tcl
Error executing Makefile.
ERROR: [Common 17-55] 'set_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
make: *** [/eda/processor_ci/makefiles/digilent_nexys4_ddr.mk:12: digilent_nexys4_ddr.bit] Error 1

Traceback (most recent call last):
  File "/eda/processor_ci/main.py", line 135, in <module>
    main(
  File "/eda/processor_ci/main.py", line 82, in main
    build(build_file_path, board_name, toolchain_path)
  File "/eda/processor_ci/core/fpga.py", line 215, in build
    raise subprocess.CalledProcessError(process.returncode, 'make')
subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_nexys4_ddr)
Stage "Flash digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test digilent_nexys4_ddr)
Stage "Test digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_nexys4_ddr]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Failed in branch digilent_nexys4_ddr
Lock acquired on [Resource: colorlight_i9]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] dir
Running in /var/jenkins_home/workspace/serv/serv
[Pipeline] {
[Pipeline] echo
Starting synthesis for FPGA colorlight_i9.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p serv -b colorlight_i9
Final configuration file generated at /var/jenkins_home/workspace/serv/serv/build_colorlight_i9.tcl
Makefile executed successfully.
Makefile output:
/eda/oss-cad-suite/bin/yosys -c /var/jenkins_home/workspace/serv/serv/build_colorlight_i9.tcl -DID=0x6a6a6a6a -DCLOCK_FREQ=25000000 -DMEMORY_SIZE=4096

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.45+139 (git sha1 4d581a97d, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3)

-- Running command `read -define ID=0x6a6a6a6a CLOCK_FREQ=25000000 MEMORY_SIZE=4096' --

1. Executing Verilog-2005 frontend: /eda/processor_ci/rtl/serv.v
Parsing Verilog input from `/eda/processor_ci/rtl/serv.v' to AST representation.
Generating RTLIL representation for module `\processorci_top'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/serv/serv/rtl/serv_aligner.v
Parsing Verilog input from `/var/jenkins_home/workspace/serv/serv/rtl/serv_aligner.v' to AST representation.
Generating RTLIL representation for module `\serv_aligner'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/serv/serv/rtl/serv_alu.v
Parsing Verilog input from `/var/jenkins_home/workspace/serv/serv/rtl/serv_alu.v' to AST representation.
Generating RTLIL representation for module `\serv_alu'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/serv/serv/rtl/serv_bufreg.v
Parsing Verilog input from `/var/jenkins_home/workspace/serv/serv/rtl/serv_bufreg.v' to AST representation.
Generating RTLIL representation for module `\serv_bufreg'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/serv/serv/rtl/serv_bufreg2.v
Parsing Verilog input from `/var/jenkins_home/workspace/serv/serv/rtl/serv_bufreg2.v' to AST representation.
Generating RTLIL representation for module `\serv_bufreg2'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/serv/serv/rtl/serv_compdec.v
Parsing Verilog input from `/var/jenkins_home/workspace/serv/serv/rtl/serv_compdec.v' to AST representation.
Generating RTLIL representation for module `\serv_compdec'.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/serv/serv/rtl/serv_csr.v
Parsing Verilog input from `/var/jenkins_home/workspace/serv/serv/rtl/serv_csr.v' to AST representation.
Generating RTLIL representation for module `\serv_csr'.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/serv/serv/rtl/serv_ctrl.v
Parsing Verilog input from `/var/jenkins_home/workspace/serv/serv/rtl/serv_ctrl.v' to AST representation.
Generating RTLIL representation for module `\serv_ctrl'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/serv/serv/rtl/serv_decode.v
Parsing Verilog input from `/var/jenkins_home/workspace/serv/serv/rtl/serv_decode.v' to AST representation.
Generating RTLIL representation for module `\serv_decode'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/serv/serv/rtl/serv_immdec.v
Parsing Verilog input from `/var/jenkins_home/workspace/serv/serv/rtl/serv_immdec.v' to AST representation.
Generating RTLIL representation for module `\serv_immdec'.
Successfully finished Verilog frontend.

11. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/serv/serv/rtl/serv_mem_if.v
Parsing Verilog input from `/var/jenkins_home/workspace/serv/serv/rtl/serv_mem_if.v' to AST representation.
Generating RTLIL representation for module `\serv_mem_if'.
Successfully finished Verilog frontend.

12. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/serv/serv/rtl/serv_rf_if.v
Parsing Verilog input from `/var/jenkins_home/workspace/serv/serv/rtl/serv_rf_if.v' to AST representation.
Generating RTLIL representation for module `\serv_rf_if'.
Successfully finished Verilog frontend.

13. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/serv/serv/rtl/serv_rf_ram.v
Parsing Verilog input from `/var/jenkins_home/workspace/serv/serv/rtl/serv_rf_ram.v' to AST representation.
Generating RTLIL representation for module `\serv_rf_ram'.
/var/jenkins_home/workspace/serv/serv/rtl/serv_rf_ram.v:35: Warning: Range [5:-1] select out of bounds on signal `\i_raddr': Setting 5 LSB bits to undef.
Successfully finished Verilog frontend.

14. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/serv/serv/rtl/serv_rf_ram_if.v
Parsing Verilog input from `/var/jenkins_home/workspace/serv/serv/rtl/serv_rf_ram_if.v' to AST representation.
Generating RTLIL representation for module `\serv_rf_ram_if'.
Successfully finished Verilog frontend.

15. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/serv/serv/rtl/serv_rf_top.v
Parsing Verilog input from `/var/jenkins_home/workspace/serv/serv/rtl/serv_rf_top.v' to AST representation.
Generating RTLIL representation for module `\serv_rf_top'.
Successfully finished Verilog frontend.

16. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/serv/serv/rtl/serv_state.v
Parsing Verilog input from `/var/jenkins_home/workspace/serv/serv/rtl/serv_state.v' to AST representation.
Generating RTLIL representation for module `\serv_state'.
Successfully finished Verilog frontend.

17. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/serv/serv/rtl/serv_synth_wrapper.v
Parsing Verilog input from `/var/jenkins_home/workspace/serv/serv/rtl/serv_synth_wrapper.v' to AST representation.
Generating RTLIL representation for module `\serv_synth_wrapper'.
Successfully finished Verilog frontend.

18. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/serv/serv/rtl/serv_top.v
Parsing Verilog input from `/var/jenkins_home/workspace/serv/serv/rtl/serv_top.v' to AST representation.
Generating RTLIL representation for module `\serv_top'.
Successfully finished Verilog frontend.

19. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/uart.v
Parsing Verilog input from `/eda/processor-ci-controller/modules/uart.v' to AST representation.
Generating RTLIL representation for module `\UART'.
Successfully finished Verilog frontend.

20. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v' to AST representation.
Generating RTLIL representation for module `\uart_rx'.
Successfully finished Verilog frontend.

21. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v
Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v' to AST representation.
Generating RTLIL representation for module `\uart_tx'.
Successfully finished Verilog frontend.

22. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/fifo.v
Parsing Verilog input from `/eda/processor-ci-controller/src/fifo.v' to AST representation.
Generating RTLIL representation for module `\FIFO'.
Successfully finished Verilog frontend.

23. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/reset.v
Parsing Verilog input from `/eda/processor-ci-controller/src/reset.v' to AST representation.
Generating RTLIL representation for module `\ResetBootSystem'.
Successfully finished Verilog frontend.

24. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/clk_divider.v
Parsing Verilog input from `/eda/processor-ci-controller/src/clk_divider.v' to AST representation.
Generating RTLIL representation for module `\ClkDivider'.
Successfully finished Verilog frontend.

25. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/memory.v
Parsing Verilog input from `/eda/processor-ci-controller/src/memory.v' to AST representation.
Generating RTLIL representation for module `\Memory'.
Successfully finished Verilog frontend.

26. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/interpreter.v
Parsing Verilog input from `/eda/processor-ci-controller/src/interpreter.v' to AST representation.
Generating RTLIL representation for module `\Interpreter'.
Successfully finished Verilog frontend.

27. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/controller.v
Parsing Verilog input from `/eda/processor-ci-controller/src/controller.v' to AST representation.
Generating RTLIL representation for module `\Controller'.
Successfully finished Verilog frontend.

28. Executing SYNTH_ECP5 pass.

28.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\DP16KD'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

28.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCUA'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Successfully finished Verilog frontend.

28.3. Executing HIERARCHY pass (managing design hierarchy).

28.3.1. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     \ResetBootSystem
Used module:     \Controller
Used module:         \Memory
Used module:         \UART
Used module:             \uart_tx
Used module:             \uart_rx
Used module:             \FIFO
Used module:         \Interpreter
Used module:         \ClkDivider
Parameter \CYCLES = 20

28.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'.
Parameter \CYCLES = 20
Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \WORD_SIZE_BY = 4
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

28.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Controller'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \WORD_SIZE_BY = 4
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

28.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4

28.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4
Generating RTLIL representation for module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 12
Parameter \BUS_WIDTH = 32
Parameter \ID = 1
Parameter \RESET_CLK_CYCLES = 20

28.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 12
Parameter \BUS_WIDTH = 32
Parameter \ID = 1
Parameter \RESET_CLK_CYCLES = 20
Generating RTLIL representation for module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 12

28.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 12
Generating RTLIL representation for module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

28.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

28.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8

28.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

28.3.11. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         \Memory
Used module:         \UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \Interpreter
Used module:         \ClkDivider
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4

28.3.12. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4
Generating RTLIL representation for module `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20

28.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20
Generating RTLIL representation for module `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 32

28.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 32
Generating RTLIL representation for module `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider'.

28.3.15. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory
Used module:         $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART
Used module:             \uart_tx
Used module:             \uart_rx
Used module:             \FIFO
Used module:         $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter
Used module:         $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

28.3.16. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

28.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

28.3.18. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory
Used module:         $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter
Used module:         $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider

28.3.19. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory
Used module:         $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter
Used module:         $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'.
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'.
Removing unused module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'.
Removing unused module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'.
Removing unused module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'.
Removing unused module `\Controller'.
Removing unused module `\Interpreter'.
Removing unused module `\Memory'.
Removing unused module `\ClkDivider'.
Removing unused module `\ResetBootSystem'.
Removing unused module `\FIFO'.
Removing unused module `\uart_tx'.
Removing unused module `\uart_rx'.
Removing unused module `\UART'.
Removing unused module `\serv_top'.
Removing unused module `\serv_synth_wrapper'.
Removing unused module `\serv_state'.
Removing unused module `\serv_rf_top'.
Removing unused module `\serv_rf_ram_if'.
Removing unused module `\serv_rf_ram'.
Removing unused module `\serv_rf_if'.
Removing unused module `\serv_mem_if'.
Removing unused module `\serv_immdec'.
Removing unused module `\serv_decode'.
Removing unused module `\serv_ctrl'.
Removing unused module `\serv_csr'.
Removing unused module `\serv_compdec'.
Removing unused module `\serv_bufreg2'.
Removing unused module `\serv_bufreg'.
Removing unused module `\serv_alu'.
Removing unused module `\serv_aligner'.
Removed 31 unused modules.

28.4. Executing PROC pass (convert processes to netlists).

28.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$957'.
Found and cleaned up 1 empty switch in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$1139'.
Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$1139'.
Cleaned up 2 empty switches.

28.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$1064 in module TRELLIS_FF.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$1016 in module DPR16X4C.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$958 in module TRELLIS_DPR16X4.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:36$1319 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:25$1311 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1512 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1510 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1502 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1499 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1493 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1488 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1483 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1474 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1461 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1459 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1451 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1437 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1431 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1426 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:57$1413 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:36$1404 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
Marked 15 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/interpreter.v:116$1368 in module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.
Removed 1 dead cases from process $proc$/eda/processor-ci-controller/modules/uart.v:203$1360 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:203$1360 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:187$1355 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:132$1350 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:74$1345 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/memory.v:36$1128 in module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/controller.v:113$1117 in module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.
Marked 5 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/reset.v:25$1067 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Removed a total of 1 dead cases.

28.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 4 redundant assignments.
Promoted 84 assignments to connections.

28.4.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$1065'.
  Set init value: \Q = 1'0
Found init rule in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1344'.
  Set init value: \read_ptr = 6'000000
  Set init value: \write_ptr = 6'000000
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1514'.
  Set init value: \i = 0
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1467'.
  Set init value: \i = 0
Found init rule in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1419'.
  Set init value: \clk_o_auto = 1'0
  Set init value: \clk_counter = 0
  Set init value: \pulse_counter = 0
Found init rule in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1397'.
  Set init value: \state = 8'00000000
  Set init value: \counter = 8'00000000
  Set init value: \read_buffer = 0
  Set init value: \timeout = 0
  Set init value: \accumulator = 64'0000000000000000000000000000000000000000000000000000000000000000
Found init rule in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1367'.
  Set init value: \read_response = 1'0
  Set init value: \write_response = 1'0
  Set init value: \read_data = 0
  Set init value: \uart_tx_en = 1'0
  Set init value: \tx_fifo_read = 1'0
  Set init value: \tx_fifo_write = 1'0
  Set init value: \rx_fifo_read = 1'0
  Set init value: \rx_fifo_write = 1'0
  Set init value: \uart_tx_data = 8'00000000
  Set init value: \tx_fifo_write_data = 8'00000000
  Set init value: \rx_fifo_write_data = 8'00000000
  Set init value: \counter_write = 3'000
  Set init value: \counter_read = 3'000
  Set init value: \state_read = 4'0000
  Set init value: \state_write = 4'0000
Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$1074'.
  Set init value: \reset_o = 1'0
  Set init value: \state = 2'01
  Set init value: \counter = 6'000000

28.4.5. Executing PROC_ARST pass (detect async resets in processes).

28.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~93 debug messages>

28.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$1065'.
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$1064'.
     1/1: $0\Q[0:0]
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$1039'.
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$1016'.
     1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$1015_EN[3:0]$1022
     2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$1015_DATA[3:0]$1021
     3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$1015_ADDR[3:0]$1020
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$982'.
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$958'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$956_EN[3:0]$964
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$956_DATA[3:0]$963
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$956_ADDR[3:0]$962
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$957'.
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1344'.
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1319'.
     1/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_EN[7:0]$1331
     2/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_DATA[7:0]$1330
     3/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_ADDR[5:0]$1329
     4/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_EN[7:0]$1325
     5/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_DATA[7:0]$1324
     6/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_ADDR[5:0]$1323
     7/7: $0\write_ptr[5:0]
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1311'.
     1/2: $0\read_ptr[5:0]
     2/2: $0\read_data[7:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1514'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1512'.
     1/2: $0\rxd_reg_0[0:0]
     2/2: $0\rxd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1510'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1502'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1499'.
     1/1: $0\bit_sample[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1493'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1488'.
     1/11: $3\i[31:0]
     2/11: $0\recieved_data[7:0] [1]
     3/11: $0\recieved_data[7:0] [0]
     4/11: $0\recieved_data[7:0] [2]
     5/11: $0\recieved_data[7:0] [3]
     6/11: $0\recieved_data[7:0] [4]
     7/11: $0\recieved_data[7:0] [5]
     8/11: $0\recieved_data[7:0] [6]
     9/11: $0\recieved_data[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1483'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1474'.
     1/1: $0\uart_rx_data[7:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1467'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1461'.
     1/1: $0\txd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1459'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1451'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1437'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1431'.
     1/11: $3\i[31:0]
     2/11: $0\data_to_send[7:0] [1]
     3/11: $0\data_to_send[7:0] [0]
     4/11: $0\data_to_send[7:0] [2]
     5/11: $0\data_to_send[7:0] [3]
     6/11: $0\data_to_send[7:0] [4]
     7/11: $0\data_to_send[7:0] [5]
     8/11: $0\data_to_send[7:0] [6]
     9/11: $0\data_to_send[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1426'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1419'.
Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1413'.
     1/1: $0\pulse_counter[31:0]
Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1404'.
     1/2: $0\clk_counter[31:0]
     2/2: $0\clk_o_auto[0:0]
Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1397'.
Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
     1/28: $0\state[7:0]
     2/28: $0\reset_bus[0:0]
     3/28: $0\memory_write[0:0]
     4/28: $0\memory_read[0:0]
     5/28: $0\write_pulse[0:0]
     6/28: $0\core_reset[0:0]
     7/28: $0\communication_write[0:0]
     8/28: $0\communication_read[0:0]
     9/28: $0\temp_buffer[63:0]
    10/28: $0\accumulator[63:0]
    11/28: $0\timeout_counter[31:0]
    12/28: $0\timeout[31:0]
    13/28: $0\read_buffer[31:0]
    14/28: $0\communication_buffer[31:0]
    15/28: $0\num_of_positions[23:0]
    16/28: $0\num_of_pages[23:0]
    17/28: $0\return_state[7:0]
    18/28: $0\memory_page_number[23:0]
    19/28: $0\memory_mux_selector[0:0]
    20/28: $0\end_position[31:0]
    21/28: $0\memory_page_size[23:0]
    22/28: $0\bus_mode[0:0]
    23/28: $0\num_of_cycles_to_pulse[31:0]
    24/28: $0\core_clk_enable[0:0]
    25/28: $0\communication_write_data[31:0]
    26/28: $0\counter[7:0]
    27/28: $0\write_data[31:0]
    28/28: $0\address[31:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1367'.
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1360'.
     1/4: $0\tx_fifo_read[0:0]
     2/4: $0\uart_tx_en[0:0]
     3/4: $0\tx_fifo_read_state[1:0]
     4/4: $0\uart_tx_data[7:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1355'.
     1/2: $0\rx_fifo_write[0:0]
     2/2: $0\rx_fifo_write_data[7:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1350'.
     1/6: $0\tx_fifo_write[0:0]
     2/6: $0\write_response[0:0]
     3/6: $0\state_write[3:0]
     4/6: $0\counter_write[2:0]
     5/6: $0\write_data_buffer[31:0]
     6/6: $0\tx_fifo_write_data[7:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1345'.
     1/5: $0\read_response[0:0]
     2/5: $0\rx_fifo_read[0:0]
     3/5: $0\state_read[3:0]
     4/5: $0\counter_read[2:0]
     5/5: $0\read_data[31:0]
Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$1138'.
Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1128'.
     1/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1137
     2/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_DATA[31:0]$1136
     3/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_ADDR[31:0]$1135
     4/4: $0\read_sync[31:0]
Creating decoders for process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$1117'.
     1/1: $0\finish_execution[0:0]
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$1074'.
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$1067'.
     1/3: $0\counter[5:0]
     2/3: $0\state[1:0]
     3/3: $0\reset_o[0:0]

28.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1483'.
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1426'.

28.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$1064'.
  created $dff cell `$procdff$2848' with positive edge clock.
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$1039'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$1000_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$1039'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$1001_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$1039'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$1002_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$1039'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$1003_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$1039'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$1004_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$1039'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$1005_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$1039'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$1006_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$1039'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$1007_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$1039'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$1008_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$1039'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$1009_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$1039'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$1010_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$1039'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$1011_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$1039'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$1012_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$1039'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$1013_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$1039'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$1014_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$1039'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$1015_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$1016'.
  created $dff cell `$procdff$2849' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$1015_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$1016'.
  created $dff cell `$procdff$2850' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$1015_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$1016'.
  created $dff cell `$procdff$2851' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$982'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$940_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$982'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$941_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$982'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$942_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$982'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$943_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$982'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$944_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$982'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$945_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$982'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$946_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$982'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$947_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$982'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$948_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$982'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$949_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$982'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$950_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$982'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$951_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$982'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$952_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$982'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$953_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$982'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$954_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$982'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$955_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$982'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$956_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$958'.
  created $dff cell `$procdff$2852' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$956_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$958'.
  created $dff cell `$procdff$2853' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$956_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$958'.
  created $dff cell `$procdff$2854' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$957'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\write_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1319'.
  created $dff cell `$procdff$2855' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_ADDR' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1319'.
  created $dff cell `$procdff$2856' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_DATA' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1319'.
  created $dff cell `$procdff$2857' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_EN' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1319'.
  created $dff cell `$procdff$2858' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_data' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1311'.
  created $dff cell `$procdff$2859' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1311'.
  created $dff cell `$procdff$2860' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1512'.
  created $dff cell `$procdff$2861' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1512'.
  created $dff cell `$procdff$2862' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1510'.
  created $dff cell `$procdff$2863' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1502'.
  created $dff cell `$procdff$2864' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1499'.
  created $dff cell `$procdff$2865' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1493'.
  created $dff cell `$procdff$2866' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1488'.
  created $dff cell `$procdff$2867' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1488'.
  created $dff cell `$procdff$2868' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1474'.
  created $dff cell `$procdff$2869' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1461'.
  created $dff cell `$procdff$2870' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1459'.
  created $dff cell `$procdff$2871' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1451'.
  created $dff cell `$procdff$2872' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1437'.
  created $dff cell `$procdff$2873' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1431'.
  created $dff cell `$procdff$2874' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1431'.
  created $dff cell `$procdff$2875' with positive edge clock.
Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\pulse_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1413'.
  created $dff cell `$procdff$2876' with positive edge clock.
Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_o_auto' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1404'.
  created $dff cell `$procdff$2877' with positive edge clock.
Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1404'.
  created $dff cell `$procdff$2878' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2879' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2880' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\address' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2881' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2882' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2883' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2884' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2885' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2886' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2887' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2888' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_clk_enable' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2889' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_reset' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2890' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_cycles_to_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2891' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\reset_bus' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2892' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\bus_mode' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2893' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_size' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2894' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\end_position' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2895' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_mux_selector' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2896' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_number' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2897' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\return_state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2898' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_pages' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2899' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_positions' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2900' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2901' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\read_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2902' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2903' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout_counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2904' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\accumulator' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2905' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\temp_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
  created $dff cell `$procdff$2906' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_en' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1360'.
  created $dff cell `$procdff$2907' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1360'.
  created $dff cell `$procdff$2908' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1360'.
  created $dff cell `$procdff$2909' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read_state' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1360'.
  created $dff cell `$procdff$2910' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1355'.
  created $dff cell `$procdff$2911' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1355'.
  created $dff cell `$procdff$2912' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1350'.
  created $dff cell `$procdff$2913' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1350'.
  created $dff cell `$procdff$2914' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1350'.
  created $dff cell `$procdff$2915' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_data_buffer' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1350'.
  created $dff cell `$procdff$2916' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1350'.
  created $dff cell `$procdff$2917' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1350'.
  created $dff cell `$procdff$2918' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1345'.
  created $dff cell `$procdff$2919' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1345'.
  created $dff cell `$procdff$2920' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1345'.
  created $dff cell `$procdff$2921' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1345'.
  created $dff cell `$procdff$2922' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1345'.
  created $dff cell `$procdff$2923' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_write_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$1138'.
  created $dff cell `$procdff$2924' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_read_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$1138'.
  created $dff cell `$procdff$2925' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\read_sync' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1128'.
  created $dff cell `$procdff$2926' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_ADDR' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1128'.
  created $dff cell `$procdff$2927' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_DATA' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1128'.
  created $dff cell `$procdff$2928' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1128'.
  created $dff cell `$procdff$2929' with positive edge clock.
Creating register for signal `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.\finish_execution' using process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$1117'.
  created $dff cell `$procdff$2930' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$1067'.
  created $dff cell `$procdff$2931' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$1067'.
  created $dff cell `$procdff$2932' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$1067'.
  created $dff cell `$procdff$2933' with positive edge clock.

28.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

28.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$1065'.
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$1064'.
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$1064'.
Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$1039'.
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$1016'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$982'.
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$958'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$957'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1344'.
Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1319'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1319'.
Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1311'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1311'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1514'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1512'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1512'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1510'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1510'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1502'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1502'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1499'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1499'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1493'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1493'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1488'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1488'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1483'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1483'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1474'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1474'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1467'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1461'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1461'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1459'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1459'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1451'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1451'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1437'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1437'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1431'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1431'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1426'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1426'.
Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1419'.
Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1413'.
Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1413'.
Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1404'.
Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1404'.
Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1397'.
Found and cleaned up 15 empty switches in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1368'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1367'.
Found and cleaned up 3 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1360'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1360'.
Found and cleaned up 2 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1355'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1355'.
Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1350'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1350'.
Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1345'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1345'.
Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$1138'.
Found and cleaned up 2 empty switches in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1128'.
Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$1128'.
Found and cleaned up 4 empty switches in `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$1117'.
Removing empty process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$1117'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$1074'.
Found and cleaned up 6 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$1067'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$1067'.
Cleaned up 93 empty switches.

28.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
<suppressed ~5 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
<suppressed ~21 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
<suppressed ~19 debug messages>
Optimizing module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
<suppressed ~9 debug messages>
Optimizing module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.
<suppressed ~15 debug messages>
Optimizing module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
<suppressed ~24 debug messages>
Optimizing module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.
<suppressed ~3 debug messages>
Optimizing module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.
<suppressed ~26 debug messages>
Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
<suppressed ~8 debug messages>
Optimizing module processorci_top.

28.5. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Deleting now unused module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
Deleting now unused module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.
Deleting now unused module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Deleting now unused module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.
Deleting now unused module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.
Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
<suppressed ~11 debug messages>

28.6. Executing TRIBUF pass.

28.7. Executing DEMINOUT pass (demote inout ports to input or output).

28.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~49 debug messages>

28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 123 unused cells and 630 unused wires.
<suppressed ~158 debug messages>

28.10. Executing CHECK pass (checking for obvious problems).
Checking module processorci_top...
Warning: Wire processorci_top.\miso is used but has no driver.
Warning: Wire processorci_top.\intr is used but has no driver.
Warning: Wire processorci_top.\ResetBootSystem.start is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [31] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [30] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [29] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [28] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [27] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [26] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [25] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [24] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [23] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [22] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [21] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [20] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [19] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [18] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [17] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [16] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [15] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [14] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [13] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [12] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [11] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [10] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [9] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [8] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [7] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [6] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [5] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [4] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [3] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [2] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [1] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [0] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_memory_data is used but has no driver.
Warning: Wire processorci_top.\Controller.core_read_memory is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [31] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [30] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [29] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [28] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [27] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [26] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [25] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [24] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [23] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [22] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [21] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [20] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [19] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [18] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [17] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [16] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [15] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [14] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [13] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [12] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [11] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [10] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [9] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [8] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [7] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [6] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [5] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [4] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [3] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [2] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [1] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [0] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [31] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [30] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [29] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [28] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [27] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [26] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [25] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [24] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [23] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [22] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [21] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [20] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [19] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [18] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [17] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [16] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [15] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [14] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [13] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [12] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [11] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [10] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [9] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [8] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [7] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [6] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [5] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [4] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [3] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [2] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [1] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [0] is used but has no driver.
Found and reported 101 problems.

28.11. Executing OPT pass (performing simple optimizations).

28.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

28.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~387 debug messages>
Removed a total of 129 cells.

28.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1542.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1548.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1554.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1542.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1548.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1554.
Removed 6 multiplexer ports.
<suppressed ~102 debug messages>

28.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1978: $auto$opt_reduce.cc:134:opt_pmux$2948
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2002: $auto$opt_reduce.cc:134:opt_pmux$2950
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2024: $auto$opt_reduce.cc:134:opt_pmux$2952
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2125: $auto$opt_reduce.cc:134:opt_pmux$2954
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2150: { $flatten\Controller.\Interpreter.$procmux$1918_CMP $auto$opt_reduce.cc:134:opt_pmux$2956 $flatten\Controller.\Interpreter.$procmux$1908_CMP }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2203: { $auto$opt_reduce.cc:134:opt_pmux$2960 $auto$opt_reduce.cc:134:opt_pmux$2958 }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Data_Memory.$procmux$2788:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0]
      New connections: $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [31:1] = { $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2272: $auto$opt_reduce.cc:134:opt_pmux$2962
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2297: { $flatten\Controller.\Interpreter.$procmux$1918_CMP $auto$opt_reduce.cc:134:opt_pmux$2964 $flatten\Controller.\Interpreter.$procmux$1908_CMP }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2325: { $flatten\Controller.\Interpreter.$procmux$1904_CMP $flatten\Controller.\Interpreter.$procmux$1897_CMP $flatten\Controller.\Interpreter.$procmux$1886_CMP $flatten\Controller.\Interpreter.$procmux$1880_CMP $auto$opt_reduce.cc:134:opt_pmux$2966 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2357: { $auto$opt_reduce.cc:134:opt_pmux$2970 $auto$opt_reduce.cc:134:opt_pmux$2968 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2439: { $flatten\Controller.\Interpreter.$procmux$1898_CMP $auto$opt_reduce.cc:134:opt_pmux$2972 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2536: { $auto$opt_reduce.cc:134:opt_pmux$2974 $flatten\Controller.\Interpreter.$procmux$1937_CMP }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2560: { $flatten\Controller.\Interpreter.$procmux$2005_CMP $flatten\Controller.\Interpreter.$procmux$2004_CMP $auto$opt_reduce.cc:134:opt_pmux$2976 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1878: { $flatten\Controller.\Interpreter.$procmux$1972_CMP $flatten\Controller.\Interpreter.$procmux$1968_CMP $flatten\Controller.\Interpreter.$procmux$1964_CMP $flatten\Controller.\Interpreter.$procmux$1938_CMP $flatten\Controller.\Interpreter.$procmux$1937_CMP $flatten\Controller.\Interpreter.$procmux$1933_CMP $flatten\Controller.\Interpreter.$procmux$1932_CMP $flatten\Controller.\Interpreter.$procmux$1928_CMP $flatten\Controller.\Interpreter.$procmux$1918_CMP $flatten\Controller.\Interpreter.$procmux$1914_CMP $auto$opt_reduce.cc:134:opt_pmux$2984 $flatten\Controller.\Interpreter.$procmux$1909_CMP $flatten\Controller.\Interpreter.$procmux$1908_CMP $auto$opt_reduce.cc:134:opt_pmux$2982 $flatten\Controller.\Interpreter.$procmux$1903_CMP $flatten\Controller.\Interpreter.$procmux$1902_CMP $flatten\Controller.\Interpreter.$procmux$1897_CMP $flatten\Controller.\Interpreter.$procmux$1893_CMP $flatten\Controller.\Interpreter.$procmux$1892_CMP $auto$opt_reduce.cc:134:opt_pmux$2980 $flatten\Controller.\Interpreter.$procmux$1886_CMP $flatten\Controller.\Interpreter.$procmux$1885_CMP $flatten\Controller.\Interpreter.$procmux$1884_CMP $auto$opt_reduce.cc:134:opt_pmux$2978 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2586: { $auto$opt_reduce.cc:134:opt_pmux$2986 $flatten\Controller.\Interpreter.$procmux$2004_CMP $flatten\Controller.\Interpreter.$procmux$1923_CMP $flatten\Controller.\Interpreter.$procmux$1918_CMP $flatten\Controller.\Interpreter.$procmux$1908_CMP }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Memory.$procmux$2788:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0]
      New connections: $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [31:1] = { $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_EN[31:0]$1131 [0] }
    New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2656: $auto$opt_reduce.cc:134:opt_pmux$2988
    New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2720: $auto$opt_reduce.cc:134:opt_pmux$2990
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1539:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1539_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1539_Y [0]
      New connections: $flatten\Controller.\Uart.\RX_FIFO.$procmux$1539_Y [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$procmux$1539_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1539_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1539_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1539_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1539_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1539_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1539_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1539:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1539_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1539_Y [0]
      New connections: $flatten\Controller.\Uart.\TX_FIFO.$procmux$1539_Y [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$procmux$1539_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1539_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1539_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1539_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1539_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1539_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1539_Y [0] }
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1557:
      Old ports: A=$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_EN[7:0]$1331, B=8'00000000, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_EN[7:0]$1322
      New ports: A=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1539_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_EN[7:0]$1322 [0]
      New connections: $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_EN[7:0]$1322 [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_EN[7:0]$1322 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_EN[7:0]$1322 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_EN[7:0]$1322 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_EN[7:0]$1322 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_EN[7:0]$1322 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_EN[7:0]$1322 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_EN[7:0]$1322 [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1557:
      Old ports: A=$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_EN[7:0]$1331, B=8'00000000, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_EN[7:0]$1322
      New ports: A=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1539_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_EN[7:0]$1322 [0]
      New connections: $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_EN[7:0]$1322 [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_EN[7:0]$1322 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_EN[7:0]$1322 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_EN[7:0]$1322 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_EN[7:0]$1322 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_EN[7:0]$1322 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_EN[7:0]$1322 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_EN[7:0]$1322 [0] }
  Optimizing cells in module \processorci_top.
Performed a total of 23 changes.

28.11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~18 debug messages>
Removed a total of 6 cells.

28.11.6. Executing OPT_DFF pass (perform DFF optimizations).

28.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 159 unused wires.
<suppressed ~19 debug messages>

28.11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

28.11.9. Rerunning OPT passes. (Maybe there is more to do..)

28.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~102 debug messages>

28.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2150: { $auto$opt_reduce.cc:134:opt_pmux$2956 $auto$opt_reduce.cc:134:opt_pmux$2992 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2297: { $auto$opt_reduce.cc:134:opt_pmux$2956 $auto$opt_reduce.cc:134:opt_pmux$2994 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2586: { $auto$opt_reduce.cc:134:opt_pmux$2986 $flatten\Controller.\Interpreter.$procmux$2004_CMP $flatten\Controller.\Interpreter.$procmux$1923_CMP $auto$opt_reduce.cc:134:opt_pmux$2996 }
  Optimizing cells in module \processorci_top.
Performed a total of 3 changes.

28.11.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

28.11.13. Executing OPT_DFF pass (perform DFF optimizations).

28.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 2 unused wires.
<suppressed ~1 debug messages>

28.11.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

28.11.16. Rerunning OPT passes. (Maybe there is more to do..)

28.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~102 debug messages>

28.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

28.11.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

28.11.20. Executing OPT_DFF pass (perform DFF optimizations).

28.11.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

28.11.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

28.11.23. Finished OPT passes. (There is nothing left to do.)

28.12. Executing FSM pass (extract and optimize FSM).

28.12.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking processorci_top.Controller.Interpreter.return_state as FSM state register:
    Users of register don't seem to benefit from recoding.
Found FSM state register processorci_top.Controller.Uart.i_uart_rx.fsm_state.
Not marking processorci_top.Controller.Uart.i_uart_tx.fsm_state as FSM state register:
    Users of register don't seem to benefit from recoding.
Not marking processorci_top.Controller.Uart.state_read as FSM state register:
    Register has an initialization value.
Not marking processorci_top.Controller.Uart.state_write as FSM state register:
    Register has an initialization value.
Found FSM state register processorci_top.Controller.Uart.tx_fifo_read_state.
Not marking processorci_top.ResetBootSystem.state as FSM state register:
    Register has an initialization value.
    Circuit seems to be self-resetting.

28.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\Controller.Uart.i_uart_rx.fsm_state' from module `\processorci_top'.
  found $dff cell for state register: $flatten\Controller.\Uart.\i_uart_rx.$procdff$2863
  root of input selection tree: $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1478_Y
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1491_Y
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1504_Y
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1490_Y
  found state code: 3'000
  found ctrl input: \Controller.Uart.i_uart_rx.next_bit
  found state code: 3'011
  found ctrl input: \Controller.Uart.i_uart_rx.payload_done
  found state code: 3'010
  found state code: 3'001
  found ctrl input: \Controller.Uart.i_uart_rx.rxd_reg
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1504_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1495_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1491_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1490_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1478_Y
  ctrl inputs: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.rxd_reg \Controller.Uart.i_uart_rx.next_bit \Controller.Uart.i_uart_rx.payload_done }
  ctrl outputs: { $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1478_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1490_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1491_Y $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1495_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1504_Y $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] }
  transition:      3'000 4'00-- ->      3'001 8'01010001
  transition:      3'000 4'01-- ->      3'000 8'01010000
  transition:      3'000 4'1--- ->      3'000 8'01010000
  transition:      3'010 4'0--0 ->      3'010 8'00100010
  transition:      3'010 4'0--1 ->      3'011 8'00100011
  transition:      3'010 4'1--- ->      3'000 8'00100000
  transition:      3'001 4'0-0- ->      3'001 8'00011001
  transition:      3'001 4'0-1- ->      3'010 8'00011010
  transition:      3'001 4'1--- ->      3'000 8'00011000
  transition:      3'011 4'0-0- ->      3'011 8'10010011
  transition:      3'011 4'0-1- ->      3'000 8'10010000
  transition:      3'011 4'1--- ->      3'000 8'10010000
Extracting FSM `\Controller.Uart.tx_fifo_read_state' from module `\processorci_top'.
  found $dff cell for state register: $flatten\Controller.\Uart.$procdff$2910
  root of input selection tree: $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0]
  found reset state: 2'00 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\Controller.\Uart.$procmux$2617_CMP
  found ctrl input: $flatten\Controller.\Uart.$procmux$2612_CMP
  found ctrl input: $flatten\Controller.\Uart.$procmux$2619_CMP
  found ctrl input: $flatten\Controller.\Uart.$procmux$2606_CMP
  found state code: 2'00
  found state code: 2'11
  found state code: 2'10
  found ctrl input: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1364_Y
  found state code: 2'01
  found ctrl output: $flatten\Controller.\Uart.$procmux$2606_CMP
  found ctrl output: $flatten\Controller.\Uart.$procmux$2612_CMP
  found ctrl output: $flatten\Controller.\Uart.$procmux$2617_CMP
  found ctrl output: $flatten\Controller.\Uart.$procmux$2619_CMP
  ctrl inputs: { \ResetBootSystem.reset_o $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1364_Y }
  ctrl outputs: { $flatten\Controller.\Uart.$procmux$2619_CMP $flatten\Controller.\Uart.$procmux$2617_CMP $flatten\Controller.\Uart.$procmux$2612_CMP $flatten\Controller.\Uart.$procmux$2606_CMP $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] }
  transition:       2'00 2'00 ->       2'00 6'000100
  transition:       2'00 2'01 ->       2'01 6'000101
  transition:       2'00 2'1- ->       2'00 6'000100
  transition:       2'10 2'0- ->       2'11 6'001011
  transition:       2'10 2'1- ->       2'00 6'001000
  transition:       2'01 2'0- ->       2'10 6'100010
  transition:       2'01 2'1- ->       2'00 6'100000
  transition:       2'11 2'0- ->       2'00 6'010000
  transition:       2'11 2'1- ->       2'00 6'010000

28.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$3004' from module `\processorci_top'.
  Merging pattern 2'0- and 2'1- from group (3 0 6'010000).
  Merging pattern 2'1- and 2'0- from group (3 0 6'010000).
Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$2997' from module `\processorci_top'.

28.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 15 unused cells and 15 unused wires.
<suppressed ~16 debug messages>

28.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$2997' from module `\processorci_top'.
  Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0].
  Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1].
  Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2].
Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$3004' from module `\processorci_top'.
  Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [0].
  Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [1].
  Removing unused output signal $flatten\Controller.\Uart.$procmux$2617_CMP.
  Removing unused output signal $flatten\Controller.\Uart.$procmux$2619_CMP.

28.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$2997' from module `\processorci_top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ---1
  010 -> --1-
  001 -> -1--
  011 -> 1---
Recoding FSM `$fsm$\Controller.Uart.tx_fifo_read_state$3004' from module `\processorci_top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  00 -> ---1
  10 -> --1-
  01 -> -1--
  11 -> 1---

28.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$2997' from module `processorci_top':
-------------------------------------

  Information on FSM $fsm$\Controller.Uart.i_uart_rx.fsm_state$2997 (\Controller.Uart.i_uart_rx.fsm_state):

  Number of input signals:    4
  Number of output signals:   5
  Number of state bits:       4

  Input signals:
    0: \Controller.Uart.i_uart_rx.payload_done
    1: \Controller.Uart.i_uart_rx.next_bit
    2: \Controller.Uart.i_uart_rx.rxd_reg
    3: \ResetBootSystem.reset_o

  Output signals:
    0: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1504_Y
    1: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1495_Y
    2: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1491_Y
    3: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1490_Y
    4: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1478_Y

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 4'01--   ->     0 5'01010
      1:     0 4'1---   ->     0 5'01010
      2:     0 4'00--   ->     2 5'01010
      3:     1 4'1---   ->     0 5'00100
      4:     1 4'0--0   ->     1 5'00100
      5:     1 4'0--1   ->     3 5'00100
      6:     2 4'1---   ->     0 5'00011
      7:     2 4'0-1-   ->     1 5'00011
      8:     2 4'0-0-   ->     2 5'00011
      9:     3 4'0-1-   ->     0 5'10010
     10:     3 4'1---   ->     0 5'10010
     11:     3 4'0-0-   ->     3 5'10010

-------------------------------------

FSM `$fsm$\Controller.Uart.tx_fifo_read_state$3004' from module `processorci_top':
-------------------------------------

  Information on FSM $fsm$\Controller.Uart.tx_fifo_read_state$3004 (\Controller.Uart.tx_fifo_read_state):

  Number of input signals:    2
  Number of output signals:   2
  Number of state bits:       4

  Input signals:
    0: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1364_Y
    1: \ResetBootSystem.reset_o

  Output signals:
    0: $flatten\Controller.\Uart.$procmux$2606_CMP
    1: $flatten\Controller.\Uart.$procmux$2612_CMP

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 2'00   ->     0 2'01
      1:     0 2'1-   ->     0 2'01
      2:     0 2'01   ->     2 2'01
      3:     1 2'1-   ->     0 2'10
      4:     1 2'0-   ->     3 2'10
      5:     2 2'1-   ->     0 2'00
      6:     2 2'0-   ->     1 2'00
      7:     3 2'--   ->     0 2'00

-------------------------------------

28.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$2997' from module `\processorci_top'.
Mapping FSM `$fsm$\Controller.Uart.tx_fifo_read_state$3004' from module `\processorci_top'.

28.13. Executing OPT pass (performing simple optimizations).

28.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~9 debug messages>

28.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~9 debug messages>
Removed a total of 3 cells.

28.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~100 debug messages>

28.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

28.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

28.13.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2933 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2931 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$2875 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1828_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1822_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1813_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1804_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1795_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1786_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1768_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1777_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3092 ($sdff) from module processorci_top (D = \Controller.Uart.uart_tx_data [7], Q = \Controller.Uart.i_uart_tx.data_to_send [7]).
Adding EN signal on $auto$ff.cc:266:slice$3092 ($sdff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1822_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1813_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1804_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1795_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1786_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1768_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1777_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send [6:0]).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$2873 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1744_Y, Q = \Controller.Uart.i_uart_tx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$3097 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1744_Y, Q = \Controller.Uart.i_uart_tx.bit_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$2872 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1733_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$3103 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1458_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$2871 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_tx.n_fsm_state, Q = \Controller.Uart.i_uart_tx.fsm_state, rval = 3'000).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$2870 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1722_Y, Q = \Controller.Uart.i_uart_tx.txd_reg, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$3108 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1722_Y, Q = \Controller.Uart.i_uart_tx.txd_reg).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$2869 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1711_Y, Q = \Controller.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3114 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.recieved_data, Q = \Controller.Uart.i_uart_rx.uart_rx_data).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$2867 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_rx.$procmux$1688_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1679_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1670_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1661_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1652_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1643_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1625_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1634_Y }, Q = \Controller.Uart.i_uart_rx.recieved_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3116 ($sdff) from module processorci_top (D = { \Controller.Uart.i_uart_rx.bit_sample \Controller.Uart.i_uart_rx.recieved_data [7:1] }, Q = \Controller.Uart.i_uart_rx.recieved_data).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$2866 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1607_Y, Q = \Controller.Uart.i_uart_rx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$3120 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1498_Y, Q = \Controller.Uart.i_uart_rx.bit_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$2865 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1602_Y, Q = \Controller.Uart.i_uart_rx.bit_sample, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3124 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg, Q = \Controller.Uart.i_uart_rx.bit_sample).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$2864 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1594_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$3126 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1509_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$2862 ($dff) from module processorci_top (D = \rx, Q = \Controller.Uart.i_uart_rx.rxd_reg_0, rval = 1'1).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$2861 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg_0, Q = \Controller.Uart.i_uart_rx.rxd_reg, rval = 1'1).
Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$2860 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1571_Y, Q = \Controller.Uart.TX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3132 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1318_Y [5:0], Q = \Controller.Uart.TX_FIFO.read_ptr).
Adding EN signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$2859 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1315_DATA, Q = \Controller.Uart.TX_FIFO.read_data).
Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$2855 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1566_Y, Q = \Controller.Uart.TX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3139 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1334_Y [5:0], Q = \Controller.Uart.TX_FIFO.write_ptr).
Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$2860 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1571_Y, Q = \Controller.Uart.RX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3141 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1318_Y [5:0], Q = \Controller.Uart.RX_FIFO.read_ptr).
Adding EN signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$2859 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1315_DATA, Q = \Controller.Uart.RX_FIFO.read_data).
Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$2855 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1566_Y, Q = \Controller.Uart.RX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$3148 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1334_Y [5:0], Q = \Controller.Uart.RX_FIFO.write_ptr).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2923 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2742_Y, Q = \Controller.Uart.state_read, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$3150 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2742_Y, Q = \Controller.Uart.state_read).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2922 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2767_Y, Q = \Controller.Uart.counter_read, rval = 3'000).
Adding EN signal on $auto$ff.cc:266:slice$3154 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2767_Y, Q = \Controller.Uart.counter_read).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2921 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2731_Y, Q = \Controller.Uart.rx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2920 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2782_Y, Q = \Controller.Uart.read_data, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3171 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2780_Y, Q = \Controller.Uart.read_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2919 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2720_Y, Q = \Controller.Uart.read_response, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2918 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2664_Y, Q = \Controller.Uart.state_write, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$3178 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2664_Y, Q = \Controller.Uart.state_write).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2917 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2686_Y, Q = \Controller.Uart.counter_write, rval = 3'000).
Adding EN signal on $auto$ff.cc:266:slice$3182 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2686_Y, Q = \Controller.Uart.counter_write).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2916 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2700_Y, Q = \Controller.Uart.write_data_buffer, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3192 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2700_Y, Q = \Controller.Uart.write_data_buffer).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2915 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2714_Y, Q = \Controller.Uart.tx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3202 ($sdff) from module processorci_top (D = \Controller.Uart.write_data_buffer [31:24], Q = \Controller.Uart.tx_fifo_write_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2914 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2646_Y, Q = \Controller.Uart.tx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2913 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2656_Y, Q = \Controller.Uart.write_response, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2912 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2637_Y, Q = \Controller.Uart.rx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3216 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.uart_rx_data, Q = \Controller.Uart.rx_fifo_write_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2911 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2632_Y, Q = \Controller.Uart.rx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2909 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2627_Y, Q = \Controller.Uart.uart_tx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3219 ($sdff) from module processorci_top (D = \Controller.Uart.TX_FIFO.read_data, Q = \Controller.Uart.uart_tx_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2908 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2603_Y, Q = \Controller.Uart.tx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$2907 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2611_Y, Q = \Controller.Uart.uart_tx_en, rval = 1'0).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$2906 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2150_Y, Q = \Controller.Interpreter.temp_buffer).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2905 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2193_Y, Q = \Controller.Interpreter.accumulator, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$3236 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2193_Y [63:8], Q = \Controller.Interpreter.accumulator [63:8]).
Adding EN signal on $auto$ff.cc:266:slice$3236 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2193_Y [7:0], Q = \Controller.Interpreter.accumulator [7:0]).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2904 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2203_Y, Q = \Controller.Interpreter.timeout_counter, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3251 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2203_Y, Q = \Controller.Interpreter.timeout_counter).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$2903 ($dff) from module processorci_top (D = { 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, Q = \Controller.Interpreter.timeout).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$2902 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2244_Y, Q = \Controller.Interpreter.read_buffer).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2901 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2272_Y, Q = \Controller.Interpreter.communication_buffer, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3267 ($sdff) from module processorci_top (D = \Controller.Uart.read_data, Q = \Controller.Interpreter.communication_buffer).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$2900 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2297_Y, Q = \Controller.Interpreter.num_of_positions).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2899 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2319_Y, Q = \Controller.Interpreter.num_of_pages, rval = 24'000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$3278 ($sdff) from module processorci_top (D = \Controller.Interpreter.communication_buffer [31:8], Q = \Controller.Interpreter.num_of_pages).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2898 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2325_Y, Q = \Controller.Interpreter.return_state, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3280 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2325_Y, Q = \Controller.Interpreter.return_state).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$2897 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2349_Y, Q = \Controller.Interpreter.memory_page_number).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2896 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2357_Y, Q = \Controller.Interpreter.memory_mux_selector, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3295 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2357_Y, Q = \Controller.Interpreter.memory_mux_selector).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2895 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2397_Y, Q = \Controller.Interpreter.end_position, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$3299 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2397_Y, Q = \Controller.Interpreter.end_position).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2893 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2439_Y, Q = \Controller.Interpreter.bus_mode, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3303 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2439_Y, Q = \Controller.Interpreter.bus_mode).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2892 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1978_Y, Q = \Controller.Interpreter.reset_bus, rval = 1'1).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$2888 ($dff) from module processorci_top (D = \Controller.Interpreter.read_buffer, Q = \Controller.Interpreter.communication_write_data).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2887 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2102_Y, Q = \Controller.Interpreter.communication_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2886 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2125_Y, Q = \Controller.Interpreter.communication_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2884 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2536_Y, Q = \Controller.Interpreter.counter, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$3315 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2536_Y, Q = \Controller.Interpreter.counter).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$2883 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2560_Y, Q = \Controller.Interpreter.write_data).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2882 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1878_Y, Q = \Controller.Interpreter.state, rval = 8'00000000).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$2881 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2586_Y, Q = \Controller.Interpreter.address).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2880 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2002_Y, Q = \Controller.Interpreter.memory_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$2879 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2024_Y, Q = \Controller.Interpreter.memory_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.$procdff$2930 ($dff) from module processorci_top (D = $flatten\Controller.$procmux$2803_Y, Q = \Controller.finish_execution, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$3338 ($sdff) from module processorci_top (D = $flatten\Controller.$procmux$2803_Y, Q = \Controller.finish_execution).
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$3255 ($dffe) from module processorci_top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$3255 ($dffe) from module processorci_top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$3255 ($dffe) from module processorci_top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$3255 ($dffe) from module processorci_top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$3255 ($dffe) from module processorci_top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$3255 ($dffe) from module processorci_top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$3255 ($dffe) from module processorci_top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$3255 ($dffe) from module processorci_top.

28.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 121 unused cells and 126 unused wires.
<suppressed ~122 debug messages>

28.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~25 debug messages>

28.13.9. Rerunning OPT passes. (Maybe there is more to do..)

28.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~74 debug messages>

28.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$3122: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.fsm_state [3:2] \Controller.Uart.i_uart_rx.fsm_state [0] }
  Optimizing cells in module \processorci_top.
Performed a total of 1 changes.

28.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~57 debug messages>
Removed a total of 19 cells.

28.13.13. Executing OPT_DFF pass (perform DFF optimizations).

28.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 1 unused cells and 20 unused wires.
<suppressed ~2 debug messages>

28.13.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

28.13.16. Rerunning OPT passes. (Maybe there is more to do..)

28.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~74 debug messages>

28.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

28.13.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

28.13.20. Executing OPT_DFF pass (perform DFF optimizations).

28.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

28.13.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

28.13.23. Finished OPT passes. (There is nothing left to do.)

28.14. Executing WREDUCE pass (reducing word size of cells).
Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Data_Memory.$auto$proc_memwr.cc:45:proc_memwr$2935 (Controller.Data_Memory.memory).
Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$1125 (Controller.Data_Memory.memory).
Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Memory.$auto$proc_memwr.cc:45:proc_memwr$2935 (Controller.Memory.memory).
Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$1125 (Controller.Memory.memory).
Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$2934 (Controller.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1315 (Controller.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$2934 (Controller.Uart.TX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1315 (Controller.Uart.TX_FIFO.memory).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$3044 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$3069 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$3082 ($ne).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$3019 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:219$1373 ($eq).
Removed top 6 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1377 ($add).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1380 ($add).
Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1389 ($lt).
Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1394 ($eq).
Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1396 ($ge).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1879_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1880_CMP0 ($eq).
Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1882 ($mux).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1884_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1885_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1886_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1887_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1888_CMP0 ($eq).
Removed top 5 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1890 ($mux).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1892_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1893_CMP0 ($eq).
Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1895 ($mux).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1897_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1898_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1902_CMP0 ($eq).
Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1903_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1904_CMP0 ($eq).
Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1906 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1908_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1909_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1910_CMP0 ($eq).
Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1912 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1914_CMP0 ($eq).
Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1916 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1918_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1919_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1920_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1921_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1922_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1923_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1924_CMP0 ($eq).
Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1926 ($mux).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1928_CMP0 ($eq).
Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1930 ($mux).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1932_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1933_CMP0 ($eq).
Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1935 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1937_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1938_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1941_CMP0 ($eq).
Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1940 ($pmux).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1942_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1943_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1944_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1945_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1946_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1947_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1948_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1949_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1950_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1951_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1952_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1953_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1954_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1955_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1956_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1957_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1958_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1959_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1960_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1961_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1962_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1963_CMP0 ($eq).
Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1964_CMP0 ($eq).
Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1966 ($mux).
Removed top 7 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1968_CMP0 ($eq).
Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1970 ($mux).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2004_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2005_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2006_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2194_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2195_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2196_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2239_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$3343 ($ne).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2365_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2398_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2399_CMP0 ($eq).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:95$1347 ($lt).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:159$1352 ($lt).
Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2651_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2657_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2658_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2670_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2672 ($mux).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2721_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2722_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2736_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2744_CMP0 ($eq).
Removed top 3 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2752 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1563 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1551 ($mux).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1335 ($sub).
Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1335 ($sub).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1334 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1333 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$1332 ($eq).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1318 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1317 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$1316 ($eq).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1563 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1551 ($mux).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1335 ($sub).
Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1335 ($sub).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1334 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1333 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$1332 ($eq).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1318 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1317 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$1316 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$3030 ($eq).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1487 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:119$1486 ($mux).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1485 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1484 ($mux).
Removed top 2 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:110$1479 ($eq).
Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:108$1477 ($eq).
Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:152$1453 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:137$1445 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:135$1443 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1440 ($ne).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1439 ($ne).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:120$1435 ($eq).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1430 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1429 ($mux).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1428 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1427 ($mux).
Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:94$1423 ($eq).
Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:92$1421 ($eq).
Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Memory.$procmux$2794 ($mux).
Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Data_Memory.$procmux$2794 ($mux).
Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:96$1102 ($mux).
Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$1086 ($mux).
Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$1085 ($mux).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\ResetBootSystem.$procmux$2820_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$1072 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$1071 ($add).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$1071 ($add).
Removed top 27 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$1070 ($lt).
Removed top 20 bits (of 32) from wire processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$1085_Y.
Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_ADDR[31:0]$1129.
Removed top 1 bits (of 32) from wire processorci_top.$flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$1125_DATA.
Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1882_Y.
Removed top 5 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1890_Y.
Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1895_Y.
Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1906_Y.
Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1912_Y.
Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1916_Y.
Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1926_Y.
Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1930_Y.
Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1935_Y.
Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1940_Y.
Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1966_Y.
Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1970_Y.
Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$1123_ADDR[31:0]$1129.
Removed top 1 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2672_Y.
Removed top 3 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2752_Y.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_ADDR[5:0]$1320.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_ADDR[5:0]$1329.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1317_Y.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_ADDR[5:0]$1320.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1310_ADDR[5:0]$1329.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1317_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1333_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1334_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1484_Y.
Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1485_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:119$1486_Y.
Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1487_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1427_Y.
Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1428_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1429_Y.
Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1430_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$1071_Y.

28.15. Executing PEEPOPT pass (run peephole optimizers).

28.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 35 unused wires.
<suppressed ~1 debug messages>

28.17. Executing SHARE pass (SAT-based resource sharing).
Found 2 cells in module processorci_top that may be considered for resource sharing.
  Analyzing resource sharing options for $flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$1125 ($memrd):
    Found 1 activation_patterns using ctrl signal { \Controller.Memory.memory_read $flatten\Controller.\Interpreter.$procmux$1922_CMP \Controller.Interpreter.address [31] \Controller.Interpreter.memory_mux_selector }.
    No candidates found.
  Analyzing resource sharing options for $flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$1125 ($memrd):
    Found 1 activation_patterns using ctrl signal { \Controller.Data_Memory.memory_read $flatten\Controller.\Interpreter.$procmux$1922_CMP \Controller.Interpreter.address [31] \Controller.Interpreter.memory_mux_selector }.
    No candidates found.

28.18. Executing TECHMAP pass (map to technology primitives).

28.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

28.18.2. Continuing TECHMAP pass.
Using template $paramod$141b0f41d8ab4b936f42c52ead39f1f9a7c93200\_90_lut_cmp_ for cells of type $lt.
No more expansions possible.
<suppressed ~119 debug messages>

28.19. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

28.20. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 6 unused wires.
<suppressed ~1 debug messages>

28.21. Executing TECHMAP pass (map to technology primitives).

28.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.

28.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation.
Generating RTLIL representation for module `\$__MUL18X18'.
Successfully finished Verilog frontend.

28.21.3. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~5 debug messages>

28.22. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module processorci_top:
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1372 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1376 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1377 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1380 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1387 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1391 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1379 ($sub).
  creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1354 ($add).
  creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1349 ($add).
  creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1317 ($add).
  creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1333 ($add).
  creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1335 ($sub).
  creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1317 ($add).
  creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1333 ($add).
  creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1335 ($sub).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1498 ($add).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1509 ($add).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1447 ($add).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1458 ($add).
  creating $macc model for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$1071 ($add).
  creating $alu model for $macc $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$1071.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1458.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1447.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1509.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1498.
  creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1335.
  creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1333.
  creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1317.
  creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1335.
  creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1333.
  creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1317.
  creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1349.
  creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1354.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1379.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1391.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1387.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1380.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1377.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1376.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1372.
  creating $alu model for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1396 ($ge): new $alu
  creating $alu model for $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1389 ($lt): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1396.
  creating $alu model for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$1070 ($lt): new $alu
  creating $alu model for $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1394 ($eq): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1396.
  creating $alu model for $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$1072 ($eq): merged with $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$1070.
  creating $alu cell for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$1070, $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$1072: $auto$alumacc.cc:485:replace_alu$3388
  creating $alu cell for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1396, $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1389, $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1394: $auto$alumacc.cc:485:replace_alu$3399
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1372: $auto$alumacc.cc:485:replace_alu$3412
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1376: $auto$alumacc.cc:485:replace_alu$3415
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1377: $auto$alumacc.cc:485:replace_alu$3418
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1380: $auto$alumacc.cc:485:replace_alu$3421
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1387: $auto$alumacc.cc:485:replace_alu$3424
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1391: $auto$alumacc.cc:485:replace_alu$3427
  creating $alu cell for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1379: $auto$alumacc.cc:485:replace_alu$3430
  creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1354: $auto$alumacc.cc:485:replace_alu$3433
  creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1349: $auto$alumacc.cc:485:replace_alu$3436
  creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1317: $auto$alumacc.cc:485:replace_alu$3439
  creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1333: $auto$alumacc.cc:485:replace_alu$3442
  creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1335: $auto$alumacc.cc:485:replace_alu$3445
  creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1317: $auto$alumacc.cc:485:replace_alu$3448
  creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1333: $auto$alumacc.cc:485:replace_alu$3451
  creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1335: $auto$alumacc.cc:485:replace_alu$3454
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1498: $auto$alumacc.cc:485:replace_alu$3457
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1509: $auto$alumacc.cc:485:replace_alu$3460
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1447: $auto$alumacc.cc:485:replace_alu$3463
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1458: $auto$alumacc.cc:485:replace_alu$3466
  creating $alu cell for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$1071: $auto$alumacc.cc:485:replace_alu$3469
  created 22 $alu and 0 $macc cells.

28.23. Executing OPT pass (performing simple optimizations).

28.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~2 debug messages>

28.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

28.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~74 debug messages>

28.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

28.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

28.23.6. Executing OPT_DFF pass (perform DFF optimizations).

28.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 7 unused wires.
<suppressed ~1 debug messages>

28.23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

28.23.9. Rerunning OPT passes. (Maybe there is more to do..)

28.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~74 debug messages>

28.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

28.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

28.23.13. Executing OPT_DFF pass (perform DFF optimizations).

28.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

28.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

28.23.16. Finished OPT passes. (There is nothing left to do.)

28.24. Executing MEMORY pass.

28.24.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

28.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

28.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing processorci_top.Controller.Data_Memory.memory write port 0.
  Analyzing processorci_top.Controller.Memory.memory write port 0.
  Analyzing processorci_top.Controller.Uart.RX_FIFO.memory write port 0.
  Analyzing processorci_top.Controller.Uart.TX_FIFO.memory write port 0.

28.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

28.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no output FF found.
Checking read port `\Controller.Memory.memory'[0] in module `\processorci_top': no output FF found.
Checking read port `\Controller.Uart.RX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\Controller.Uart.TX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port address `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no address FF found.
Checking read port address `\Controller.Memory.memory'[0] in module `\processorci_top': no address FF found.

28.24.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 2 unused cells and 18 unused wires.
<suppressed ~3 debug messages>

28.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

28.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

28.24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

28.24.10. Executing MEMORY_COLLECT pass (generating $mem cells).

28.25. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

28.26. Executing MEMORY_LIBMAP pass (mapping memories to cells).
mapping memory processorci_top.Controller.Data_Memory.memory via $__TRELLIS_DPR16X4_
mapping memory processorci_top.Controller.Memory.memory via $__TRELLIS_DPR16X4_
mapping memory processorci_top.Controller.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of processorci_top.Controller.Uart.RX_FIFO.memory: $\Controller.Uart.RX_FIFO.memory$rdreg[0]
mapping memory processorci_top.Controller.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of processorci_top.Controller.Uart.TX_FIFO.memory: $\Controller.Uart.TX_FIFO.memory$rdreg[0]
<suppressed ~1098 debug messages>

28.27. Executing TECHMAP pass (map to technology primitives).

28.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.

28.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD_'.
Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'.
Successfully finished Verilog frontend.

28.27.3. Continuing TECHMAP pass.
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
No more expansions possible.
<suppressed ~1046 debug messages>

28.28. Executing OPT pass (performing simple optimizations).

28.28.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~175 debug messages>

28.28.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

28.28.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $flatten\ResetBootSystem.$procdff$2932 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state).
Adding SRST signal on $auto$ff.cc:266:slice$3288 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1391_Y, Q = \Controller.Interpreter.memory_page_number, rval = 24'000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$3227 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2150_Y [1:0], Q = \Controller.Interpreter.temp_buffer [1:0]).
Adding SRST signal on $auto$ff.cc:266:slice$3076 ($dffe) from module processorci_top (D = $flatten\ResetBootSystem.$procmux$2817_Y, Q = \ResetBootSystem.counter, rval = 6'000000).

28.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 2 unused cells and 7266 unused wires.
<suppressed ~3 debug messages>

28.28.5. Rerunning OPT passes. (Removed registers in this run.)

28.28.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~10 debug messages>

28.28.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

28.28.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$5828 ($sdffce) from module processorci_top (D = $auto$wreduce.cc:461:run$3381 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000).

28.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 1 unused cells and 8 unused wires.
<suppressed ~2 debug messages>

28.28.10. Rerunning OPT passes. (Removed registers in this run.)

28.28.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

28.28.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

28.28.13. Executing OPT_DFF pass (perform DFF optimizations).

28.28.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

28.28.15. Finished fast OPT passes.

28.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

28.30. Executing OPT pass (performing simple optimizations).

28.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

28.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

28.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~44 debug messages>

28.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$5826: { $auto$opt_dff.cc:194:make_patterns_logic$5823 $auto$opt_dff.cc:194:make_patterns_logic$3228 $auto$opt_dff.cc:194:make_patterns_logic$3230 $auto$fsm_map.cc:74:implement_pattern_cache$3064 }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1890:
      Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:461:run$3351 [2:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$3351 [2] $auto$wreduce.cc:461:run$3351 [0] }
      New connections: $auto$wreduce.cc:461:run$3351 [1] = $auto$wreduce.cc:461:run$3351 [0]
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1895:
      Old ports: A=7'1010010, B=7'0010101, Y=$auto$wreduce.cc:461:run$3352 [6:0]
      New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$3352 [1:0]
      New connections: $auto$wreduce.cc:461:run$3352 [6:2] = { $auto$wreduce.cc:461:run$3352 [1] 3'010 $auto$wreduce.cc:461:run$3352 [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1906:
      Old ports: A=4'1100, B=4'0000, Y=$auto$wreduce.cc:461:run$3353 [3:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3353 [2]
      New connections: { $auto$wreduce.cc:461:run$3353 [3] $auto$wreduce.cc:461:run$3353 [1:0] } = { $auto$wreduce.cc:461:run$3353 [2] 2'00 }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1916:
      Old ports: A=4'1001, B=4'0000, Y=$auto$wreduce.cc:461:run$3355 [3:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3355 [0]
      New connections: $auto$wreduce.cc:461:run$3355 [3:1] = { $auto$wreduce.cc:461:run$3355 [0] 2'00 }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1930:
      Old ports: A=7'0000110, B=7'1010111, Y=$auto$wreduce.cc:461:run$3357 [6:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3357 [0]
      New connections: $auto$wreduce.cc:461:run$3357 [6:1] = { $auto$wreduce.cc:461:run$3357 [0] 1'0 $auto$wreduce.cc:461:run$3357 [0] 3'011 }
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$2325:
      Old ports: A=8'00001011, B=302978816, Y=$flatten\Controller.\Interpreter.$procmux$2325_Y
      New ports: A=5'01011, B=20'10010011111011100000, Y=$flatten\Controller.\Interpreter.$procmux$2325_Y [4:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$2325_Y [7:5] = 3'000
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2664:
      Old ports: A=4'0000, B={ 1'0 $auto$wreduce.cc:461:run$3363 [2:0] 12'000100100011 }, Y=$flatten\Controller.\Uart.$procmux$2664_Y
      New ports: A=3'000, B={ $auto$wreduce.cc:461:run$3363 [2:0] 9'001010011 }, Y=$flatten\Controller.\Uart.$procmux$2664_Y [2:0]
      New connections: $flatten\Controller.\Uart.$procmux$2664_Y [3] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2672:
      Old ports: A=3'000, B=3'100, Y=$auto$wreduce.cc:461:run$3363 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$3363 [2]
      New connections: $auto$wreduce.cc:461:run$3363 [1:0] = 2'00
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2748:
      Old ports: A=4'0010, B=4'0100, Y=$flatten\Controller.\Uart.$procmux$2748_Y
      New ports: A=2'01, B=2'10, Y=$flatten\Controller.\Uart.$procmux$2748_Y [2:1]
      New connections: { $flatten\Controller.\Uart.$procmux$2748_Y [3] $flatten\Controller.\Uart.$procmux$2748_Y [0] } = 2'00
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_rx.$procmux$1706:
      Old ports: A=3'000, B={ 2'00 $auto$wreduce.cc:461:run$3373 [0] 1'0 $auto$wreduce.cc:461:run$3374 [1:0] 2'01 \Controller.Uart.i_uart_rx.payload_done 1'0 $auto$wreduce.cc:461:run$3376 [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state
      New ports: A=2'00, B={ 1'0 $auto$wreduce.cc:461:run$3373 [0] $auto$wreduce.cc:461:run$3374 [1:0] 1'1 \Controller.Uart.i_uart_rx.payload_done $auto$wreduce.cc:461:run$3376 [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state [1:0]
      New connections: \Controller.Uart.i_uart_rx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1487:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$3376 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3376 [0]
      New connections: $auto$wreduce.cc:461:run$3376 [1] = $auto$wreduce.cc:461:run$3376 [0]
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_tx.$procmux$1843:
      Old ports: A=3'000, B={ 2'00 \Controller.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$3378 [1:0] 2'01 \Controller.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$3380 [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state
      New ports: A=2'00, B={ 1'0 \Controller.Uart.uart_tx_en $auto$wreduce.cc:461:run$3378 [1:0] 1'1 \Controller.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$3380 [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state [1:0]
      New connections: \Controller.Uart.i_uart_tx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1430:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$3380 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$3380 [0]
      New connections: $auto$wreduce.cc:461:run$3380 [1] = $auto$wreduce.cc:461:run$3380 [0]
    New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$2828: { $flatten\ResetBootSystem.$procmux$2821_CMP $flatten\ResetBootSystem.$procmux$2820_CMP }
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2831:
      Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$2831_Y
      New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$2831_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2831_Y [0] = 1'0
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2742:
      Old ports: A=4'0000, B={ 3'000 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2748_Y 8'00010011 }, Y=$flatten\Controller.\Uart.$procmux$2742_Y
      New ports: A=3'000, B={ 2'00 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2748_Y [2:1] 7'0001011 }, Y=$flatten\Controller.\Uart.$procmux$2742_Y [2:0]
      New connections: $flatten\Controller.\Uart.$procmux$2742_Y [3] = 1'0
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2837:
      Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$2831_Y, Y=$flatten\ResetBootSystem.$procmux$2837_Y
      New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$2831_Y [1], Y=$flatten\ResetBootSystem.$procmux$2837_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2837_Y [0] = 1'0
  Optimizing cells in module \processorci_top.
Performed a total of 18 changes.

28.30.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

28.30.6. Executing OPT_DFF pass (perform DFF optimizations).

28.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

28.30.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~1 debug messages>

28.30.9. Rerunning OPT passes. (Maybe there is more to do..)

28.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~44 debug messages>

28.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

28.30.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

28.30.13. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$3107 ($sdff) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$3151 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$3179 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$3281 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$3281 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$3281 ($sdffe) from module processorci_top.

28.30.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

28.30.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~4 debug messages>

28.30.16. Rerunning OPT passes. (Maybe there is more to do..)

28.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~44 debug messages>

28.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1900:
      Old ports: A=8'00000100, B={ 3'000 \Controller.Interpreter.return_state [4:0] }, Y=$flatten\Controller.\Interpreter.$procmux$1900_Y
      New ports: A=5'00100, B=\Controller.Interpreter.return_state [4:0], Y=$flatten\Controller.\Interpreter.$procmux$1900_Y [4:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$1900_Y [7:5] = 3'000
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$1878:
      Old ports: A=8'00000000, B={ 7'0000000 $auto$wreduce.cc:461:run$3361 [0] 6'000000 $auto$wreduce.cc:461:run$3354 [1:0] 1'0 $auto$wreduce.cc:461:run$3359 [6:0] 14'00001101000011 $auto$wreduce.cc:461:run$3358 [1:0] 3'000 \Controller.Interpreter.return_state [4:0] 1'0 $auto$wreduce.cc:461:run$3357 [6] 1'0 $auto$wreduce.cc:461:run$3357 [6] 3'011 $auto$wreduce.cc:461:run$3357 [6] 7'0000011 \Controller.Uart.read_response 4'0000 $auto$wreduce.cc:461:run$3353 [3] 2'00 $auto$wreduce.cc:461:run$3353 [3] 6'000010 $auto$wreduce.cc:461:run$3354 [1:0] 20'00001000000010110000 $auto$wreduce.cc:461:run$3353 [3] $auto$wreduce.cc:461:run$3353 [3] 18'000000010100000100 $flatten\Controller.\Interpreter.$procmux$1900_Y 1'0 $auto$wreduce.cc:461:run$3352 [6] 3'010 $auto$wreduce.cc:461:run$3352 [2] $auto$wreduce.cc:461:run$3352 [6] $auto$wreduce.cc:461:run$3352 [2] 13'0001001100010 $auto$wreduce.cc:461:run$3351 [2:1] $auto$wreduce.cc:461:run$3351 [1] 31'0001011001010010000100000001000 $auto$wreduce.cc:461:run$3350 [0] 8'00000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1878_Y
      New ports: A=7'0000000, B={ 6'000000 $auto$wreduce.cc:461:run$3361 [0] 5'00000 $auto$wreduce.cc:461:run$3354 [1:0] $auto$wreduce.cc:461:run$3359 [6:0] 12'000110100011 $auto$wreduce.cc:461:run$3358 [1:0] 2'00 \Controller.Interpreter.return_state [4:0] $auto$wreduce.cc:461:run$3357 [6] 1'0 $auto$wreduce.cc:461:run$3357 [6] 3'011 $auto$wreduce.cc:461:run$3357 [6] 6'000011 \Controller.Uart.read_response 3'000 $auto$wreduce.cc:461:run$3353 [3] 2'00 $auto$wreduce.cc:461:run$3353 [3] 5'00010 $auto$wreduce.cc:461:run$3354 [1:0] 17'00010000001011000 $auto$wreduce.cc:461:run$3353 [3] $auto$wreduce.cc:461:run$3353 [3] 18'000000101000010000 $flatten\Controller.\Interpreter.$procmux$1900_Y [4:0] $auto$wreduce.cc:461:run$3352 [6] 3'010 $auto$wreduce.cc:461:run$3352 [2] $auto$wreduce.cc:461:run$3352 [6] $auto$wreduce.cc:461:run$3352 [2] 11'00100110010 $auto$wreduce.cc:461:run$3351 [2:1] $auto$wreduce.cc:461:run$3351 [1] 27'001011010100100010000001000 $auto$wreduce.cc:461:run$3350 [0] 7'0000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1878_Y [6:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$1878_Y [7] = 1'0
  Optimizing cells in module \processorci_top.
Performed a total of 2 changes.

28.30.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

28.30.20. Executing OPT_DFF pass (perform DFF optimizations).

28.30.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

28.30.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

28.30.23. Rerunning OPT passes. (Maybe there is more to do..)

28.30.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~44 debug messages>

28.30.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

28.30.26. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

28.30.27. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$3326 ($sdff) from module processorci_top.

28.30.28. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

28.30.29. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~1 debug messages>

28.30.30. Rerunning OPT passes. (Maybe there is more to do..)

28.30.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~44 debug messages>

28.30.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

28.30.33. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

28.30.34. Executing OPT_DFF pass (perform DFF optimizations).

28.30.35. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

28.30.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

28.30.37. Finished OPT passes. (There is nothing left to do.)

28.31. Executing TECHMAP pass (map to technology primitives).

28.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

28.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ecp5_alu'.
Successfully finished Verilog frontend.

28.31.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $dffe.
Using extmapper simplemap for cells of type $bmux.
Using template $paramod$eaeb96106163dbf82031649d189817109fe07c69\_90_demux for cells of type $demux.
Using extmapper simplemap for cells of type $sdffe.
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $logic_not.
Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $ne.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $sdff.
Using extmapper simplemap for cells of type $lut.
Using extmapper simplemap for cells of type $or.
Using template $paramod$039520c137afc9cd69dd56c3fb11a4e1fbe5f664\_80_ecp5_alu for cells of type $alu.
Using template $paramod$bdc78fe5225b43c64ccdf13e5eb67d9dcf228e8a\_80_ecp5_alu for cells of type $alu.
Using template $paramod$ff467a932a72bec5a93c27dba04bf3daba067451\_80_ecp5_alu for cells of type $alu.
Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu.
Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu.
Using template $paramod$79aa992f2eb7f354d4aaf651790713cf239111fa\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod$c9511eeb847f2aa95252b1013477609463f67ee0\_80_ecp5_alu for cells of type $alu.
Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ecp5_alu for cells of type $alu.
Using template $paramod$a7b312e4ba8fdc79d4c5e0789e4e6c41ea3896fb\_90_pmux for cells of type $pmux.
Using template $paramod$7a385d5b7a2e603dbc5beef838648775b433f248\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $mux.
Using template $paramod$54a4503cc57b9df40b70c1899504d6aac2650719\_90_pmux for cells of type $pmux.
Using template $paramod$59b03ae2620a41577de8da5f5c97b2919e82362b\_90_pmux for cells of type $pmux.
Using template $paramod$24fb226dd75c9d3f6955ec2ad61d794776778cf6\_90_pmux for cells of type $pmux.
Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux.
Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux.
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux.
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
Using template $paramod$ac45afa5bcd8e16ca475cce13f9d19bb109f1516\_80_ecp5_alu for cells of type $alu.
Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux.
Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $sdffce.
Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux.
Using template $paramod$610911f8769324f781128d641f7fe2120143c328\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux.
Using extmapper simplemap for cells of type $xor.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux.
Using template $paramod$5d1d2614b24accd0f9d06c4779fd9ef771faf494\_90_demux for cells of type $demux.
No more expansions possible.
<suppressed ~2955 debug messages>

28.32. Executing OPT pass (performing simple optimizations).

28.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~9083 debug messages>

28.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~2220 debug messages>
Removed a total of 740 cells.

28.32.3. Executing OPT_DFF pass (perform DFF optimizations).
Removing always-active EN on $auto$ff.cc:266:slice$14703 ($_SDFFE_PP0P_) from module processorci_top.

28.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 1033 unused cells and 3342 unused wires.
<suppressed ~1043 debug messages>

28.32.5. Rerunning OPT passes. (Removed registers in this run.)

28.32.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

28.32.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

28.32.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$14800 ($_DFFE_PP_) from module processorci_top (D = $flatten\ResetBootSystem.$procmux$2828.B_AND_S [1], Q = \ResetBootSystem.state [1], rval = 1'0).
Adding SRST signal on $auto$ff.cc:266:slice$14799 ($_DFFE_PP_) from module processorci_top (D = $flatten\ResetBootSystem.$procmux$2828.B_AND_S [2], Q = \ResetBootSystem.state [0], rval = 1'0).
Adding SRST signal on $auto$ff.cc:266:slice$13494 ($_SDFF_PP0_) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1878.Y_B [6], Q = \Controller.Interpreter.state [6], rval = 1'0).
Adding SRST signal on $auto$ff.cc:266:slice$13493 ($_SDFF_PP0_) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1878.B_AND_S [152], Q = \Controller.Interpreter.state [5], rval = 1'0).
Adding SRST signal on $auto$ff.cc:266:slice$13492 ($_SDFF_PP0_) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1878.Y_B [4], Q = \Controller.Interpreter.state [4], rval = 1'0).
Adding SRST signal on $auto$ff.cc:266:slice$13491 ($_SDFF_PP0_) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1878.Y_B [3], Q = \Controller.Interpreter.state [3], rval = 1'0).
Adding SRST signal on $auto$ff.cc:266:slice$13490 ($_SDFF_PP0_) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1878.Y_B [2], Q = \Controller.Interpreter.state [2], rval = 1'0).
Adding SRST signal on $auto$ff.cc:266:slice$13489 ($_SDFF_PP0_) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1878.Y_B [1], Q = \Controller.Interpreter.state [1], rval = 1'0).
Adding SRST signal on $auto$ff.cc:266:slice$13488 ($_SDFF_PP0_) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1878.Y_B [0], Q = \Controller.Interpreter.state [0], rval = 1'0).

28.32.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 9 unused cells and 9 unused wires.
<suppressed ~10 debug messages>

28.32.10. Rerunning OPT passes. (Removed registers in this run.)

28.32.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

28.32.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~36 debug messages>
Removed a total of 12 cells.

28.32.13. Executing OPT_DFF pass (perform DFF optimizations).

28.32.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 12 unused wires.
<suppressed ~1 debug messages>

28.32.15. Finished fast OPT passes.

28.33. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

28.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

28.35. Executing TECHMAP pass (map to technology primitives).

28.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

28.35.2. Continuing TECHMAP pass.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_.
No more expansions possible.
<suppressed ~691 debug messages>

28.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~100 debug messages>

28.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).

28.38. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in processorci_top.

28.39. Executing ATTRMVCP pass (move or copy attributes).

28.40. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 3214 unused wires.
<suppressed ~1 debug messages>

28.41. Executing TECHMAP pass (map to technology primitives).

28.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

28.41.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>

28.42. Executing ABC9 pass.

28.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

28.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

28.42.3. Executing PROC pass (convert processes to netlists).

28.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27115'.
Cleaned up 1 empty switch.

28.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27116 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

28.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

28.42.3.4. Executing PROC_INIT pass (extract init attributes).

28.42.3.5. Executing PROC_ARST pass (detect async resets in processes).

28.42.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

28.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27140'.
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27116'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27114_EN[3:0]$27122
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27114_DATA[3:0]$27121
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27114_ADDR[3:0]$27120
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27115'.

28.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

28.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27140'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27112_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27140'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27102_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27140'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27101_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27140'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27106_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27140'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27109_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27140'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27108_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27140'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27104_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27140'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27107_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27140'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27110_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27140'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27103_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27140'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27098_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27140'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27113_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27140'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27100_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27140'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27111_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27140'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27105_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27140'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$27099_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27140'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27114_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27116'.
  created $dff cell `$procdff$27166' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27114_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27116'.
  created $dff cell `$procdff$27167' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$27114_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27116'.
  created $dff cell `$procdff$27168' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27115'.
  created direct connection (no actual register cell created).

28.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

28.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$27140'.
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$27116'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$27115'.
Cleaned up 1 empty switch.

28.42.3.12. Executing OPT_EXPR pass (perform const folding).

28.42.4. Executing SCC pass (detecting logic loops).
Found an SCC: $auto$ff.cc:266:slice$14322 $auto$opt_expr.cc:617:replace_const_cells$25679 $auto$ff.cc:266:slice$14324 $auto$simplemap.cc:126:simplemap_reduce$14527 $auto$simplemap.cc:126:simplemap_reduce$14542 $auto$ff.cc:266:slice$14323 $auto$opt_expr.cc:617:replace_const_cells$25695 $auto$simplemap.cc:267:simplemap_mux$22981 $auto$simplemap.cc:126:simplemap_reduce$22966 $auto$simplemap.cc:126:simplemap_reduce$22963 $auto$simplemap.cc:75:simplemap_bitop$22979 $auto$simplemap.cc:267:simplemap_mux$14513 $auto$simplemap.cc:225:simplemap_logbin$14516 $auto$simplemap.cc:196:simplemap_lognot$14531 $auto$simplemap.cc:126:simplemap_reduce$14529 $auto$simplemap.cc:126:simplemap_reduce$14526 $auto$opt_expr.cc:617:replace_const_cells$25681 $auto$simplemap.cc:196:simplemap_lognot$14546 $auto$simplemap.cc:126:simplemap_reduce$14544 $auto$simplemap.cc:126:simplemap_reduce$14541 $auto$ff.cc:266:slice$14321 $auto$simplemap.cc:126:simplemap_reduce$8323 $auto$simplemap.cc:126:simplemap_reduce$8321 $auto$simplemap.cc:225:simplemap_logbin$14472 $auto$simplemap.cc:196:simplemap_lognot$14482 $auto$simplemap.cc:126:simplemap_reduce$14480 $auto$opt_expr.cc:617:replace_const_cells$25693 $auto$simplemap.cc:267:simplemap_mux$22980 $auto$simplemap.cc:126:simplemap_reduce$22971 $auto$simplemap.cc:126:simplemap_reduce$22968 $auto$simplemap.cc:75:simplemap_bitop$22976
Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$14941 $auto$ff.cc:266:slice$14912 $auto$ff.cc:479:convert_ce_over_srst$26422 $auto$simplemap.cc:38:simplemap_not$17182 $auto$ff.cc:266:slice$14911 $auto$ff.cc:479:convert_ce_over_srst$26420 $auto$simplemap.cc:126:simplemap_reduce$8369 $auto$simplemap.cc:38:simplemap_not$17181 $auto$alumacc.cc:485:replace_alu$3388.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$3388.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$14944 $auto$simplemap.cc:126:simplemap_reduce$14940 $auto$ff.cc:266:slice$14910 $auto$ff.cc:479:convert_ce_over_srst$26418 $auto$simplemap.cc:126:simplemap_reduce$14938 $auto$ff.cc:266:slice$14914 $auto$ff.cc:479:convert_ce_over_srst$26426 $auto$simplemap.cc:38:simplemap_not$10510 $auto$alumacc.cc:485:replace_alu$3388.slice[4].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$14907 $auto$opt_expr.cc:617:replace_const_cells$25725 $auto$simplemap.cc:196:simplemap_lognot$14918 $auto$simplemap.cc:167:logic_reduce$14917 $auto$simplemap.cc:126:simplemap_reduce$8295 $auto$simplemap.cc:126:simplemap_reduce$8265 $auto$simplemap.cc:126:simplemap_reduce$8287 $auto$simplemap.cc:196:simplemap_lognot$14928 $auto$simplemap.cc:126:simplemap_reduce$14926 $auto$ff.cc:266:slice$26319 $auto$dfflegalize.cc:941:flip_pol$26432 $auto$ff.cc:485:convert_ce_over_srst$26430 $auto$simplemap.cc:126:simplemap_reduce$14852 $auto$simplemap.cc:126:simplemap_reduce$14890 $auto$simplemap.cc:126:simplemap_reduce$14946 $auto$simplemap.cc:126:simplemap_reduce$14942 $auto$simplemap.cc:126:simplemap_reduce$8371 $auto$simplemap.cc:38:simplemap_not$23016 $auto$ff.cc:266:slice$14915 $auto$ff.cc:479:convert_ce_over_srst$26428 $auto$simplemap.cc:126:simplemap_reduce$14936 $auto$simplemap.cc:75:simplemap_bitop$10511 $auto$simplemap.cc:126:simplemap_reduce$8375 $auto$simplemap.cc:126:simplemap_reduce$8373 $auto$simplemap.cc:126:simplemap_reduce$8370 $auto$simplemap.cc:38:simplemap_not$17184 $auto$ff.cc:266:slice$14913 $auto$ff.cc:479:convert_ce_over_srst$26424 $auto$simplemap.cc:126:simplemap_reduce$8299 $auto$simplemap.cc:126:simplemap_reduce$8297 $auto$simplemap.cc:126:simplemap_reduce$8268 $auto$simplemap.cc:126:simplemap_reduce$8266 $auto$simplemap.cc:38:simplemap_not$8409
Found an SCC: $auto$opt_expr.cc:617:replace_const_cells$25709 $auto$ff.cc:266:slice$14159 $auto$opt_expr.cc:617:replace_const_cells$25719 $auto$ff.cc:266:slice$14160 $auto$opt_expr.cc:617:replace_const_cells$25715 $auto$ff.cc:266:slice$14157 $auto$simplemap.cc:126:simplemap_reduce$14266 $auto$simplemap.cc:126:simplemap_reduce$14297 $auto$opt_expr.cc:617:replace_const_cells$25717 $auto$ff.cc:266:slice$14158 $auto$ff.cc:266:slice$14155 $auto$simplemap.cc:126:simplemap_reduce$14265 $auto$opt_expr.cc:617:replace_const_cells$25705 $auto$simplemap.cc:126:simplemap_reduce$14296 $auto$ff.cc:266:slice$14156 $auto$ff.cc:266:slice$14162 $auto$simplemap.cc:126:simplemap_reduce$14270 $auto$simplemap.cc:126:simplemap_reduce$14267 $auto$simplemap.cc:126:simplemap_reduce$14301 $auto$simplemap.cc:126:simplemap_reduce$14298 $auto$opt_expr.cc:617:replace_const_cells$25721 $auto$ff.cc:266:slice$14161 $auto$simplemap.cc:196:simplemap_lognot$14276 $auto$simplemap.cc:126:simplemap_reduce$14274 $auto$simplemap.cc:126:simplemap_reduce$14272 $auto$simplemap.cc:126:simplemap_reduce$14269 $auto$simplemap.cc:126:simplemap_reduce$14264 $auto$simplemap.cc:196:simplemap_lognot$14307 $auto$simplemap.cc:126:simplemap_reduce$14305 $auto$simplemap.cc:126:simplemap_reduce$14303 $auto$simplemap.cc:126:simplemap_reduce$14300 $auto$simplemap.cc:126:simplemap_reduce$14295 $auto$opt_expr.cc:617:replace_const_cells$25713 $auto$ff.cc:266:slice$14154 $auto$simplemap.cc:167:logic_reduce$8244 $auto$simplemap.cc:225:simplemap_logbin$14248 $auto$simplemap.cc:225:simplemap_logbin$14249
Found an SCC: $auto$opt_expr.cc:617:replace_const_cells$25893 $auto$ff.cc:266:slice$26328 $auto$simplemap.cc:126:simplemap_reduce$12726 $auto$simplemap.cc:126:simplemap_reduce$13000 $auto$opt_expr.cc:617:replace_const_cells$26195 $auto$simplemap.cc:126:simplemap_reduce$13155 $auto$simplemap.cc:126:simplemap_reduce$13209 $auto$ff.cc:266:slice$26335 $auto$opt_expr.cc:617:replace_const_cells$26209 $auto$ff.cc:266:slice$26342 $auto$simplemap.cc:126:simplemap_reduce$11829 $auto$simplemap.cc:126:simplemap_reduce$12833 $auto$simplemap.cc:126:simplemap_reduce$13128 $auto$simplemap.cc:126:simplemap_reduce$13208 $auto$opt_expr.cc:617:replace_const_cells$26213 $auto$ff.cc:266:slice$26349 $auto$opt_expr.cc:617:replace_const_cells$26205 $auto$ff.cc:266:slice$26356 $auto$simplemap.cc:126:simplemap_reduce$11786 $auto$simplemap.cc:126:simplemap_reduce$11986 $auto$simplemap.cc:126:simplemap_reduce$12031 $auto$simplemap.cc:126:simplemap_reduce$12651 $auto$simplemap.cc:126:simplemap_reduce$12647 $auto$simplemap.cc:126:simplemap_reduce$11832 $auto$simplemap.cc:167:logic_reduce$12685 $auto$simplemap.cc:126:simplemap_reduce$12926 $auto$simplemap.cc:126:simplemap_reduce$13211 $auto$simplemap.cc:126:simplemap_reduce$13207 $auto$simplemap.cc:126:simplemap_reduce$11810 $auto$simplemap.cc:126:simplemap_reduce$12055 $auto$simplemap.cc:126:simplemap_reduce$12836 $auto$simplemap.cc:126:simplemap_reduce$12948 $auto$simplemap.cc:126:simplemap_reduce$12944 $auto$simplemap.cc:126:simplemap_reduce$11742 $auto$simplemap.cc:126:simplemap_reduce$12706 $auto$simplemap.cc:126:simplemap_reduce$12750 $auto$simplemap.cc:126:simplemap_reduce$13131 $auto$simplemap.cc:126:simplemap_reduce$13127 $auto$opt_expr.cc:617:replace_const_cells$26203 $auto$ff.cc:266:slice$26363 $auto$simplemap.cc:196:simplemap_lognot$11364 $auto$simplemap.cc:126:simplemap_reduce$11362 $auto$simplemap.cc:126:simplemap_reduce$14309 $auto$simplemap.cc:196:simplemap_lognot$11451 $auto$simplemap.cc:126:simplemap_reduce$11449 $auto$simplemap.cc:196:simplemap_lognot$11473 $auto$simplemap.cc:126:simplemap_reduce$11471 $auto$simplemap.cc:196:simplemap_lognot$11539 $auto$simplemap.cc:126:simplemap_reduce$11537 $auto$simplemap.cc:196:simplemap_lognot$11561 $auto$simplemap.cc:126:simplemap_reduce$11559 $auto$simplemap.cc:196:simplemap_lognot$11585 $auto$simplemap.cc:126:simplemap_reduce$11583 $auto$simplemap.cc:196:simplemap_lognot$11607 $auto$simplemap.cc:126:simplemap_reduce$11605 $auto$simplemap.cc:126:simplemap_reduce$20983 $auto$simplemap.cc:196:simplemap_lognot$11631 $auto$simplemap.cc:126:simplemap_reduce$11629 $auto$simplemap.cc:126:simplemap_reduce$11627 $auto$simplemap.cc:196:simplemap_lognot$11495 $auto$simplemap.cc:126:simplemap_reduce$11493 $auto$simplemap.cc:196:simplemap_lognot$11680 $auto$simplemap.cc:126:simplemap_reduce$11678 $auto$simplemap.cc:126:simplemap_reduce$21299 $auto$simplemap.cc:196:simplemap_lognot$11702 $auto$simplemap.cc:126:simplemap_reduce$11700 $auto$simplemap.cc:196:simplemap_lognot$11724 $auto$simplemap.cc:126:simplemap_reduce$11722 $auto$simplemap.cc:196:simplemap_lognot$11747 $auto$simplemap.cc:126:simplemap_reduce$11745 $auto$simplemap.cc:196:simplemap_lognot$11791 $auto$simplemap.cc:126:simplemap_reduce$11789 $auto$simplemap.cc:196:simplemap_lognot$11815 $auto$simplemap.cc:126:simplemap_reduce$11813 $auto$simplemap.cc:126:simplemap_reduce$21302 $auto$simplemap.cc:196:simplemap_lognot$11837 $auto$simplemap.cc:126:simplemap_reduce$11835 $auto$simplemap.cc:196:simplemap_lognot$11925 $auto$simplemap.cc:126:simplemap_reduce$11923 $auto$simplemap.cc:196:simplemap_lognot$11991 $auto$simplemap.cc:126:simplemap_reduce$11989 $auto$simplemap.cc:196:simplemap_lognot$12036 $auto$simplemap.cc:126:simplemap_reduce$12034 $auto$simplemap.cc:126:simplemap_reduce$21304 $auto$simplemap.cc:196:simplemap_lognot$12060 $auto$simplemap.cc:126:simplemap_reduce$12058 $auto$simplemap.cc:196:simplemap_lognot$12656 $auto$simplemap.cc:126:simplemap_reduce$12654 $auto$simplemap.cc:196:simplemap_lognot$12678 $auto$simplemap.cc:126:simplemap_reduce$12676 $auto$simplemap.cc:167:logic_reduce$12688 $auto$simplemap.cc:126:simplemap_reduce$12751 $auto$simplemap.cc:126:simplemap_reduce$20981 $auto$simplemap.cc:196:simplemap_lognot$11517 $auto$simplemap.cc:126:simplemap_reduce$11515 $auto$simplemap.cc:126:simplemap_reduce$14311 $auto$simplemap.cc:196:simplemap_lognot$11903 $auto$simplemap.cc:126:simplemap_reduce$11901 $auto$simplemap.cc:126:simplemap_reduce$12729 $auto$simplemap.cc:126:simplemap_reduce$21312 $auto$simplemap.cc:126:simplemap_reduce$21072 $auto$simplemap.cc:196:simplemap_lognot$12014 $auto$simplemap.cc:126:simplemap_reduce$12012 $auto$simplemap.cc:126:simplemap_reduce$21305 $auto$simplemap.cc:196:simplemap_lognot$12082 $auto$simplemap.cc:126:simplemap_reduce$12080 $auto$simplemap.cc:126:simplemap_reduce$13003 $auto$simplemap.cc:126:simplemap_reduce$14430 $auto$simplemap.cc:196:simplemap_lognot$11859 $auto$simplemap.cc:126:simplemap_reduce$11857 $auto$simplemap.cc:126:simplemap_reduce$21308 $auto$simplemap.cc:126:simplemap_reduce$21295 $auto$simplemap.cc:126:simplemap_reduce$13678 $auto$simplemap.cc:126:simplemap_reduce$14313 $auto$simplemap.cc:126:simplemap_reduce$14310 $auto$simplemap.cc:196:simplemap_lognot$11881 $auto$simplemap.cc:126:simplemap_reduce$11879 $auto$simplemap.cc:126:simplemap_reduce$13158 $auto$simplemap.cc:126:simplemap_reduce$21315 $auto$simplemap.cc:126:simplemap_reduce$20994 $auto$simplemap.cc:126:simplemap_reduce$20982 $auto$simplemap.cc:126:simplemap_reduce$13231 $auto$simplemap.cc:196:simplemap_lognot$11653 $auto$simplemap.cc:126:simplemap_reduce$11651 $auto$simplemap.cc:126:simplemap_reduce$21311 $auto$simplemap.cc:126:simplemap_reduce$21014 $auto$simplemap.cc:196:simplemap_lognot$11769 $auto$simplemap.cc:126:simplemap_reduce$11767 $auto$simplemap.cc:126:simplemap_reduce$14192 $auto$simplemap.cc:196:simplemap_lognot$11947 $auto$simplemap.cc:126:simplemap_reduce$11945 $auto$simplemap.cc:126:simplemap_reduce$21319 $auto$simplemap.cc:126:simplemap_reduce$21316 $auto$simplemap.cc:126:simplemap_reduce$21310 $auto$simplemap.cc:126:simplemap_reduce$21300 $auto$simplemap.cc:126:simplemap_reduce$14194 $auto$simplemap.cc:196:simplemap_lognot$11969 $auto$simplemap.cc:126:simplemap_reduce$11967 $auto$simplemap.cc:126:simplemap_reduce$13212 $auto$opt_expr.cc:617:replace_const_cells$26215 $auto$ff.cc:266:slice$26321 $auto$simplemap.cc:126:simplemap_reduce$26327 $auto$opt_dff.cc:248:combine_resets$26322 $auto$simplemap.cc:126:simplemap_reduce$21321 $auto$simplemap.cc:126:simplemap_reduce$21317 $auto$simplemap.cc:126:simplemap_reduce$21313 $auto$simplemap.cc:126:simplemap_reduce$21306 $auto$simplemap.cc:196:simplemap_lognot$12689
Found an SCC: $auto$ff.cc:266:slice$14326 $auto$opt_expr.cc:617:replace_const_cells$25687 $auto$ff.cc:266:slice$14329 $auto$ff.cc:266:slice$14327 $auto$simplemap.cc:126:simplemap_reduce$14563 $auto$ff.cc:266:slice$14330 $auto$opt_expr.cc:617:replace_const_cells$25689 $auto$ff.cc:266:slice$14331 $auto$simplemap.cc:126:simplemap_reduce$14567 $auto$simplemap.cc:126:simplemap_reduce$14564 $auto$opt_expr.cc:617:replace_const_cells$25691 $auto$ff.cc:266:slice$14332 $auto$ff.cc:266:slice$14333 $auto$simplemap.cc:126:simplemap_reduce$14562 $auto$opt_expr.cc:617:replace_const_cells$25685 $auto$ff.cc:266:slice$14328 $auto$simplemap.cc:126:simplemap_reduce$14571 $auto$simplemap.cc:126:simplemap_reduce$14569 $auto$simplemap.cc:126:simplemap_reduce$14566 $auto$simplemap.cc:126:simplemap_reduce$14561 $auto$opt_expr.cc:617:replace_const_cells$25683 $auto$ff.cc:266:slice$14325 $auto$simplemap.cc:126:simplemap_reduce$8327 $auto$simplemap.cc:196:simplemap_lognot$14573
Found 5 SCCs in module processorci_top.
Found 5 SCCs.

28.42.5. Executing ABC9_OPS pass (helper functions for ABC9).

28.42.6. Executing PROC pass (convert processes to netlists).

28.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

28.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

28.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

28.42.6.4. Executing PROC_INIT pass (extract init attributes).

28.42.6.5. Executing PROC_ARST pass (detect async resets in processes).

28.42.6.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

28.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

28.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches).

28.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs).

28.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

28.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

28.42.6.12. Executing OPT_EXPR pass (perform const folding).

28.42.7. Executing TECHMAP pass (map to technology primitives).

28.42.7.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

28.42.7.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~162 debug messages>

28.42.8. Executing OPT pass (performing simple optimizations).

28.42.8.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.

28.42.8.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

28.42.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

28.42.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Performed a total of 0 changes.

28.42.8.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

28.42.8.6. Executing OPT_DFF pass (perform DFF optimizations).

28.42.8.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..

28.42.8.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.

28.42.8.9. Finished OPT passes. (There is nothing left to do.)

28.42.9. Executing TECHMAP pass (map to technology primitives).

28.42.9.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.

28.42.9.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
No more expansions possible.
<suppressed ~1031 debug messages>

28.42.10. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.

28.42.11. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

28.42.12. Executing ABC9_OPS pass (helper functions for ABC9).

28.42.13. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

28.42.14. Executing TECHMAP pass (map to technology primitives).

28.42.14.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

28.42.14.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~201 debug messages>

28.42.15. Executing OPT pass (performing simple optimizations).

28.42.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~18 debug messages>

28.42.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

28.42.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

28.42.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

28.42.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

28.42.15.6. Executing OPT_DFF pass (perform DFF optimizations).

28.42.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 55 unused wires.
<suppressed ~1 debug messages>

28.42.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

28.42.15.9. Rerunning OPT passes. (Maybe there is more to do..)

28.42.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

28.42.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

28.42.15.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

28.42.15.13. Executing OPT_DFF pass (perform DFF optimizations).

28.42.15.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

28.42.15.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

28.42.15.16. Finished OPT passes. (There is nothing left to do.)

28.42.16. Executing AIGMAP pass (map logic to AIG).
Module processorci_top: replaced 18 cells with 120 new cells, skipped 39 cells.
  replaced 3 cell types:
       2 $_OR_
       2 $_XOR_
      14 $_MUX_
  not replaced 3 cell types:
      31 $specify2
       4 $_NOT_
       4 $_AND_

28.42.17. Executing AIGMAP pass (map logic to AIG).
Module processorci_top: replaced 5415 cells with 35783 new cells, skipped 3561 cells.
  replaced 4 cell types:
     706 $_OR_
      82 $_XOR_
       1 $_ORNOT_
    4626 $_MUX_
  not replaced 8 cell types:
      11 $scopeinfo
     233 $_NOT_
     542 $_AND_
     576 TRELLIS_FF
    1028 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4
     142 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
    1028 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
       1 $__ABC9_SCC_BREAKER

28.42.17.1. Executing ABC9_OPS pass (helper functions for ABC9).

28.42.17.2. Executing ABC9_OPS pass (helper functions for ABC9).

28.42.17.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 15373 AND gates and 46410 wires from module `processorci_top' to a netlist network with 4700 inputs and 837 outputs.

28.42.17.4. Executing ABC9_EXE pass (technology mapping using ABC9).

28.42.17.5. Executing ABC9.
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_lut <abc-temp-dir>/input.lut 
ABC: + read_box <abc-temp-dir>/input.box 
ABC: + &read <abc-temp-dir>/input.xaig 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   4700/    837  and =   14590  lev =   20 (0.33)  mem = 0.47 MB  box = 1170  bb = 1028
ABC: + &scorr 
ABC: Warning: The network is combinational.
ABC: + &sweep 
ABC: + &dc2 
ABC: + &dch -f 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   4700/    837  and =   17623  lev =   17 (0.31)  mem = 0.50 MB  ch = 1472  box = 1170  bb = 1028
ABC: + &if -W 300 -v 
ABC: K = 7. Memory (bytes): Truth =    0. Cut =   64. Obj =  148. Set =  672. CutMin = no
ABC: Node =   17623.  Ch =   868.  Total mem =    5.82 MB. Peak cut mem =    0.11 MB.
ABC: P:  Del = 4196.00.  Ar =   12302.0.  Edge =    15707.  Cut =   199698.  T =     0.09 sec
ABC: P:  Del = 4196.00.  Ar =   12316.0.  Edge =    15684.  Cut =   197287.  T =     0.09 sec
ABC: P:  Del = 4196.00.  Ar =    6161.0.  Edge =    14673.  Cut =   500117.  T =     0.21 sec
ABC: F:  Del = 4196.00.  Ar =    5051.0.  Edge =    14448.  Cut =   311418.  T =     0.14 sec
ABC: A:  Del = 4196.00.  Ar =    4681.0.  Edge =    14164.  Cut =   320909.  T =     0.23 sec
ABC: A:  Del = 4196.00.  Ar =    4592.0.  Edge =    14144.  Cut =   308919.  T =     0.21 sec
ABC: Total time =     0.98 sec
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + &mfs 
ABC: + &ps -l 
ABC: <abc-temp-dir>/input : i/o =   4700/    837  and =   11236  lev =   19 (0.32)  mem = 0.43 MB  box = 1170  bb = 1028
ABC: Mapping (K=7)  :  lut =   3532  edge =   14116  lev =    8 (0.20)  Boxes are not in a topological order. Switching to level computation without boxes.
ABC: levB =   19  mem = 0.20 MB
ABC: LUT = 3532 : 2=272 7.7 %  3=256 7.2 %  4=2368 67.0 %  5=541 15.3 %  6=38 1.1 %  7=57 1.6 %  Ave = 4.00
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + time 
ABC: elapse: 5.64 seconds, total: 5.64 seconds

28.42.17.6. Executing AIGER frontend.
<suppressed ~11086 debug messages>
Removed 14440 unused cells and 38498 unused wires.

28.42.17.7. Executing ABC9_OPS pass (helper functions for ABC9).
ABC RESULTS:              $lut cells:     3542
ABC RESULTS:   $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells:      142
ABC RESULTS:   $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells:     1028
ABC RESULTS:           input signals:     1084
ABC RESULTS:          output signals:      175
Removing temp directory.

28.42.18. Executing TECHMAP pass (map to technology primitives).

28.42.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.

28.42.18.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000000111 for cells of type $__ABC9_SCC_BREAKER.
No more expansions possible.
<suppressed ~2218 debug messages>
Removed 210 unused cells and 61134 unused wires.

28.43. Executing TECHMAP pass (map to technology primitives).

28.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

28.43.2. Continuing TECHMAP pass.
Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut.
Using template $paramod$ce23c8cef76b1a8b8b143bfa07ff3a4e4564b99e\$lut for cells of type $lut.
Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut.
Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut.
Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod$57cf7fbf84518d9e7604ec42b59ba9511e1f3caf\$lut for cells of type $lut.
Using template $paramod$b86b68a00733dbecb31d58a14a13683475a2002a\$lut for cells of type $lut.
Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut.
Using template $paramod$992bdc10cff2c6edd722994f0e1044bc863f79f7\$lut for cells of type $lut.
Using template $paramod$504c9f1ca6facbed70a8a05210386b24177f23fe\$lut for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod$28573d64e05cfef986b669757c9bc724facdf28b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut.
Using template $paramod$983adbc56c7400f95b406f02e82bd0da8b98fd00\$lut for cells of type $lut.
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut.
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
Using template $paramod$78b4324556f6321a85bd440441a5392f271ea218\$lut for cells of type $lut.
Using template $paramod$6e424bd4a747f8421ac946af3d9bb3a47fd0b233\$lut for cells of type $lut.
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
Using template $paramod$a81cf453a316218febe7a33c0cf3157f69dfa7dc\$lut for cells of type $lut.
Using template $paramod$d7ec878ecfa8f5f7604d3e91692b5d4c2ee758ad\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod$b45308ffeb4031bc5d55ef31b149afd94d3d7565\$lut for cells of type $lut.
Using template $paramod$3b5254987c40811dd8e1369413ae1ee16abe3076\$lut for cells of type $lut.
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut.
Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut.
Using template $paramod$c66e7b215e6f80c1915bda1df6f2ae95d0bda68c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod$9a269ffb0efb6ad342cb106a4e0636e23fdfd547\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
Using template $paramod$7ca4db46d3cd57dbe2541a389808e6d33af02319\$lut for cells of type $lut.
Using template $paramod$47671b68495b53d6eea5a9dd67c114907e17980b\$lut for cells of type $lut.
Using template $paramod$9e354de8d358bf081aa0c089488ea3bc5b7c2fd9\$lut for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
Using template $paramod$6e64c13666511ae2ccc90ab6ddaf8be09bda5af2\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut.
Using template $paramod$c6932d0419018208e5384761d78f0ead9bcc772f\$lut for cells of type $lut.
Using template $paramod$58bd588a49a6a3b9d057d75f907cb4932e1635f6\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut.
Using template $paramod$bdddf4a24964e2e96968085b76d17d67519d6d9c\$lut for cells of type $lut.
Using template $paramod$d8a6058f97335646f000496287ca88987ac437c1\$lut for cells of type $lut.
Using template $paramod$682d73aad51495e04fdc02b61a63353f780d484d\$lut for cells of type $lut.
Using template $paramod$b45e5cb971154e30a797eecb0461619c3eeae12d\$lut for cells of type $lut.
Using template $paramod$51da077e4bf37b6b4b0961a4797af73831856ba1\$lut for cells of type $lut.
Using template $paramod$ecb83b3ee175d0b56cdac6c6fa19a7c550767e64\$lut for cells of type $lut.
Using template $paramod$8fd8efe0a495790cc9ddc97266933ea8a8cd7b45\$lut for cells of type $lut.
Using template $paramod$55a6884cb3e83f29b2244a55ba767f14d41b0a52\$lut for cells of type $lut.
Using template $paramod$56aad51fb7b279620a0eb687a16eaf1fb92f4a75\$lut for cells of type $lut.
Using template $paramod$d21d214a5aa271f2d9da3f90f22432c0ecee130f\$lut for cells of type $lut.
Using template $paramod$00ffcc628ccb870304683cac36ad3a16cc41b6a4\$lut for cells of type $lut.
Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut.
Using template $paramod$b2e8d279775d333b39e310bd45fd5952acdde290\$lut for cells of type $lut.
Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut.
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut.
Using template $paramod$bde0f4b82f0bb2e27f01f1b9f1880ce2bb4a21a4\$lut for cells of type $lut.
Using template $paramod$3f2774da7ec4a6417559f6fb965247f349599d51\$lut for cells of type $lut.
Using template $paramod$8ae5e24171bca0b8d12d43741a6723f274290f92\$lut for cells of type $lut.
Using template $paramod$605876bca07653c76fa56445c7bd38128937776f\$lut for cells of type $lut.
Using template $paramod$92c85719f6d2e4353d548934f8798d47c710debc\$lut for cells of type $lut.
Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut.
Using template $paramod$11c86b7a6cb6e98dcfb16c5f4d4cc1052b93d8a4\$lut for cells of type $lut.
Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut.
Using template $paramod$2e9afba29670cc6475874639e7c1b3979c8ebde3\$lut for cells of type $lut.
Using template $paramod$060fe3a9a87c070316bade86e73c95c5eaa2139d\$lut for cells of type $lut.
Using template $paramod$a4bbe892a28ec0471eac4c548ab7ee6abbaf1e36\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod$3258fabf91107b4a007ae89b2246a16c31e8ae28\$lut for cells of type $lut.
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut.
Using template $paramod$ce15874c299a587dd16825ec2d2d2759b547554e\$lut for cells of type $lut.
Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut.
Using template $paramod$3d7168c8134c4765b84a7b86d5ef7e1e65bbf4a0\$lut for cells of type $lut.
Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut.
Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut.
Using template $paramod$7ea2352f8f054781a715aeddf3e67f1db65f005a\$lut for cells of type $lut.
Using template $paramod$f3e1547c4b47e64c590e75cf09078b2507c8cc75\$lut for cells of type $lut.
Using template $paramod$89de210e11c16138f89688ab911d555676147dc8\$lut for cells of type $lut.
Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut.
Using template $paramod$e718d2f5eb562e6029d6a1b1e060511bf1c65df1\$lut for cells of type $lut.
Using template $paramod$edb78bf6097bd1610bf429917d83de43c0242af1\$lut for cells of type $lut.
Using template $paramod$db4421b8cd8e111f0252332f4864a714ac72aaf0\$lut for cells of type $lut.
Using template $paramod$e4857636d35dc9b5293045a985a317a436a4713f\$lut for cells of type $lut.
Using template $paramod$a564887bbf2c017c6e8cdcc3ce6ce49e00810266\$lut for cells of type $lut.
Using template $paramod$dbdbcb07b9994e498bb1324e5c006c6aa08a7a37\$lut for cells of type $lut.
Using template $paramod$784dd5f01e5de46d9c485bef5a2222c42876a5fc\$lut for cells of type $lut.
Using template $paramod$172562782b29adf13eed00aa5949ba18b75fb966\$lut for cells of type $lut.
Using template $paramod$adce9c89515a4e83641fc3471eb3c01ec7b082ff\$lut for cells of type $lut.
Using template $paramod$2fd3c42461376c704c07117e7368b2ed8179d1e0\$lut for cells of type $lut.
Using template $paramod$cfcc41897735ad5ea14a1f12fcee73dcacb20e30\$lut for cells of type $lut.
Using template $paramod$90d040213a8233db7241b749c7c2e3ba613c2f3c\$lut for cells of type $lut.
Using template $paramod$f503ae6dd13af4ce255f26a38c5b2bb42d3444fc\$lut for cells of type $lut.
Using template $paramod$b761c69662421e13d5be7219a1f373b15179f3ec\$lut for cells of type $lut.
Using template $paramod$7da6a3d375590798104e6970494bd85e29d896ab\$lut for cells of type $lut.
Using template $paramod$537548f56755f8ddd1df8aa86663373d814c3e00\$lut for cells of type $lut.
Using template $paramod$2157aabf670011015aa238ec0ba78dbe04a49145\$lut for cells of type $lut.
Using template $paramod$987baf4906062f2e8ba7ad0180e4762c3464e7f0\$lut for cells of type $lut.
Using template $paramod$20f82dd03802038bc013e5804609eaebb5d257db\$lut for cells of type $lut.
Using template $paramod$7b809938766c3068dc017c276033f224fcfb7189\$lut for cells of type $lut.
Using template $paramod$b4d0f4738a5ce50c7f36c2aa2ecc09cfb874f2b6\$lut for cells of type $lut.
Using template $paramod$f610396a8c1614f373f4d73e3d1e988bc93e396c\$lut for cells of type $lut.
Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut.
Using template $paramod$037be5c00d8a02858cdb1ab049b58a0133287ff1\$lut for cells of type $lut.
Using template $paramod$6f9324703e8fcc3b6df2bc2bec54ec19a446ae96\$lut for cells of type $lut.
Using template $paramod$620586420e818d3afa7e5b51fcf19f5c6ea83ad4\$lut for cells of type $lut.
Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut.
Using template $paramod$5afdc7428159757eedf89ce514f7efa32b31c8e7\$lut for cells of type $lut.
Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut.
Using template $paramod$a47d3f6fd9a7aebdb1b556bc977da3380a17c8cf\$lut for cells of type $lut.
Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d\$lut for cells of type $lut.
Using template $paramod$2de23df76a24087ecc0fa38a78ecc970cd3f2492\$lut for cells of type $lut.
Using template $paramod$a648edd7290dbdc60b4277769ac1653dae6fd74c\$lut for cells of type $lut.
Using template $paramod$5afe21d6fdc7c33aeb338fdb508ea02813207bfd\$lut for cells of type $lut.
Using template $paramod$faf4b69e2195a9ce52b7c3bce83fa5ea343bc378\$lut for cells of type $lut.
Using template $paramod$fa254e5a5e12471740ff9a5ef1037af91b1b75ff\$lut for cells of type $lut.
Using template $paramod$25003f26a78bb2f583f23824f1e0b8cc16b88761\$lut for cells of type $lut.
Using template $paramod$332530260df33f1e6567b344a898a29636fd4f0f\$lut for cells of type $lut.
Using template $paramod$ac55070e8b3414cb6367f4fbf77a92d6c4390901\$lut for cells of type $lut.
Using template $paramod$779ce1856232fd2857259a50e6832c67ad66128e\$lut for cells of type $lut.
Using template $paramod$2754a21a217ccdc1a0cbf27b2e8b19266cadc23f\$lut for cells of type $lut.
Using template $paramod$dd351332a44263d6274369352ca1bd334f12f053\$lut for cells of type $lut.
Using template $paramod$3f9dab019f2e70ee6e3b52f2d62327c5461dd5ee\$lut for cells of type $lut.
Using template $paramod$5b9b67101e84873179c1020607cf83696439bb98\$lut for cells of type $lut.
Using template $paramod$76b69988499323c223a91b64a512926500d4c698\$lut for cells of type $lut.
Using template $paramod$9eaabafe459be125f48a5e46558dd0084a2c0d60\$lut for cells of type $lut.
Using template $paramod$aa117dc02d4f218ed5974b258634c3f38264f15f\$lut for cells of type $lut.
Using template $paramod$8af1d7de486caf60eeec1cdcefc1d5b70c13b855\$lut for cells of type $lut.
Using template $paramod$eb837796285502ed8b7061260f0495beb2e164d2\$lut for cells of type $lut.
Using template $paramod$4a5cb9a6822416135c3ccf2a28bcf23a857f7920\$lut for cells of type $lut.
Using template $paramod$654e1fa515df2c4b0f94d9252a24c02f70ca2783\$lut for cells of type $lut.
Using template $paramod$9dbe36982f6b8ca20db05cfcd5650178f13179f3\$lut for cells of type $lut.
Using template $paramod$b7792e1962fb8b65865c48433cacb9941e24b485\$lut for cells of type $lut.
Using template $paramod$1df184be438c7f1377f3400a91d761a3a7e89b05\$lut for cells of type $lut.
Using template $paramod$84a8f8f5c4fc3ca4ab76818073b00098bddce155\$lut for cells of type $lut.
Using template $paramod$2bde02b8b9e7d4618088fbf4dd7d45ed8df60d20\$lut for cells of type $lut.
Using template $paramod$0588a56d956de2ef39b1ca190e1d8667770312f4\$lut for cells of type $lut.
Using template $paramod$ee01f8aaa86cdcd4b779fec0dec9c9062f5b2128\$lut for cells of type $lut.
Using template $paramod$eadbfb46c348c82b7975ec20f659a19c59a68112\$lut for cells of type $lut.
Using template $paramod$1078665aa144cf7ff525a892db61e5cee078ce7c\$lut for cells of type $lut.
Using template $paramod$beae4210b922fc9ba2fcc4008a7474b475e38c50\$lut for cells of type $lut.
Using template $paramod$32cc1610a260980476319a9eeced1c7da2a0d9bd\$lut for cells of type $lut.
Using template $paramod$eff99b84f09f2f71ad0a4e53aae928e3f2d7fa64\$lut for cells of type $lut.
Using template $paramod$88042169380e5061327dbbab80daa18c75c82b9b\$lut for cells of type $lut.
Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut.
Using template $paramod$498558d1a0ecb16ce1aadbc71fc2da14abb64614\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut.
Using template $paramod$eb0b7b796486150424969057dee3cec0b7ea7771\$lut for cells of type $lut.
Using template $paramod$903b13a78e0201d81ee2cb5e579e213337de2eac\$lut for cells of type $lut.
Using template $paramod$2a3aee6f1b16b87fae5ad552f211bb1ef99dfafe\$lut for cells of type $lut.
Using template $paramod$1488806498d73f20197d075f0e1ebc39c9c2a1c6\$lut for cells of type $lut.
Using template $paramod$98d1d1b4f56004de25b54240d0728f41161a0d28\$lut for cells of type $lut.
Using template $paramod$7f4670b933e9d0d313fe2dbe752fa82b1cf04d5c\$lut for cells of type $lut.
Using template $paramod$e134ec2a47a2462a591072e65d34fb15b81c90e0\$lut for cells of type $lut.
Using template $paramod$99b39be87c2f30094d7b98aa59ed3f9ca5f8e57c\$lut for cells of type $lut.
Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314\$lut for cells of type $lut.
Using template $paramod$7c23e972ef849866e44c7d62ca1a4590fc68205a\$lut for cells of type $lut.
Using template $paramod$9a9b1eb93cf8cae3712704918bfa4b29d6a116b2\$lut for cells of type $lut.
Using template $paramod$81c2e473ba00a9cfa3dfe1d42c1fabf3cd269a21\$lut for cells of type $lut.
Using template $paramod$f464e8ee635b255785618aa5657b4cb388e7c29e\$lut for cells of type $lut.
Using template $paramod$96d8ef52e687eb6c720fc8b18a97d024135e48d7\$lut for cells of type $lut.
Using template $paramod$5c6d01824df27a97c3776b3694e8814e23c197cd\$lut for cells of type $lut.
Using template $paramod$46969734f619307bdfb8ca4ad5af273b11115f8d\$lut for cells of type $lut.
Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut.
Using template $paramod$4fa54c26ed1828223450420ca53d4097fddd10ed\$lut for cells of type $lut.
Using template $paramod$3b2c503c102bb07247f26b1b6d6fbab937af0f71\$lut for cells of type $lut.
Using template $paramod$8b25a0e3033321678cbff73fe65c3ba174af15ab\$lut for cells of type $lut.
Using template $paramod$1c30d08c403f38fa94ec53dfc832770bdc564fe4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001010 for cells of type $lut.
Using template $paramod$f258f431a7c2fc52205873e71cd6683fdc689824\$lut for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut.
Using template $paramod$dd37cd23134cff028f2f6c89a8b24252334214d8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod$1e9d7896e1dd3d2af9633eefc9c29afb478cef41\$lut for cells of type $lut.
Using template $paramod$77eba90f08fef1f04e121480501078ac12ffbebb\$lut for cells of type $lut.
Using template $paramod$176a6ceafa512d807921d7dfc76320dfbbfb5fe4\$lut for cells of type $lut.
Using template $paramod$0d3ac82cf5b8a192d5ff4c23e3143360366ae882\$lut for cells of type $lut.
Using template $paramod$8be603794459732f9a374f76041b510fc63b115b\$lut for cells of type $lut.
Using template $paramod$d4ec4fc98a126cb45cb0ebae696e4f56b4d0460c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
Using template $paramod$fddfaafad20e385d20971828336f8fb14f3d4f32\$lut for cells of type $lut.
Using template $paramod$7295da7c5b19f528a428229f2570e0a23ad372af\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut.
Using template $paramod$47b2f5a9f58cb4be072657772748a1ab82d6819a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011101 for cells of type $lut.
Using template $paramod$5dc745bb48e2cf535179547ba13f0fe5364d6d54\$lut for cells of type $lut.
Using template $paramod$ff4dd96a8adc011bb838ebb9d645764e57a15653\$lut for cells of type $lut.
Using template $paramod$cce6b847e730f5f1cfb4a8ef6c78f9f44e4f1145\$lut for cells of type $lut.
Using template $paramod$50222e4d0527635d5cf211ed95d1ccfc839e99e8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221\$lut for cells of type $lut.
Using template $paramod$6e4a86e6f1a5dc8f826898a131e83cdba4a4fc9e\$lut for cells of type $lut.
Using template $paramod$fca82610c4582bae0c561edc640eb928b48fbdcf\$lut for cells of type $lut.
Using template $paramod$18e50808df562b188523e13714b96fedec6427c1\$lut for cells of type $lut.
Using template $paramod$a988852add2bdce7c1dfac786401ba7c7bc832c1\$lut for cells of type $lut.
Using template $paramod$b18f60dfd13c21d3e472b89652353f3f5342b450\$lut for cells of type $lut.
Using template $paramod$8e01d13e078e8177912f721c32dbabb20f78322d\$lut for cells of type $lut.
Using template $paramod$722bfd9af0ae56ca9d1d12a221cb5ede16461f26\$lut for cells of type $lut.
Using template $paramod$3ea1653073c31f2ca4b26ae811cefd3adaf51c2c\$lut for cells of type $lut.
Using template $paramod$326da126efd404fbb9e78b0519f9c270d0c75183\$lut for cells of type $lut.
Using template $paramod$929c423ec3a91c0a8d61ccde91ce3fda786dddbb\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
Using template $paramod$c24d0e2a94559837d969df5b5aaf84188feaf3d8\$lut for cells of type $lut.
Using template $paramod$e4723c78131b859cdb296cc7099a965ce6bf28d9\$lut for cells of type $lut.
Using template $paramod$f4c8a73f62510ba2ae4fd921bd5cdb75a13f02e4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011100 for cells of type $lut.
Using template $paramod$8c13ad014d500c3a349fa680995aa7f6f9eaaf87\$lut for cells of type $lut.
Using template $paramod$fdb61c7c613ba40ec1f7cb3a6e1f35d0fc57666f\$lut for cells of type $lut.
Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut.
Using template $paramod$ead66ba22839f96e739c8f1b5a09bc1717b3be02\$lut for cells of type $lut.
Using template $paramod$58f99f02725c8dce1b7300215b15fb389f806c1e\$lut for cells of type $lut.
Using template $paramod$c78b28b0674e1f0605658e28384d11f25f372de7\$lut for cells of type $lut.
Using template $paramod$ca4d41379eb122514d1cb539e5736325e45c4a88\$lut for cells of type $lut.
No more expansions possible.
<suppressed ~6878 debug messages>

28.44. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in processorci_top.
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100334.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100352.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100388.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100397.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$20326.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$20253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$20253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$20253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$20253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$20253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$20253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$20180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$20180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$20180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$20180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$20180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$20180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$20159.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$20159.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$20159.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$20159.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$20159.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$20159.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19404.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$19237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19097.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19027.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$18785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$18727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$18701.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18701.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18701.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18701.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18701.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18701.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18701.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$18679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$18679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$16956.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16956.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16956.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16956.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16956.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16956.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$16947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$16879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$16845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$16845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$16836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16619.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16305.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$15683.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$15683.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$15675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$15675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$15675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$15661.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$15655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$15655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$15655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$15643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$15643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$15643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$15643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$15643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$15605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$15590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$15590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$15590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$15581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$15581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$15581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$15581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$15557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$15549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$15549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$15549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$15531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$15531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$15522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$15522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$15522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$15522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$14733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14677.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$14671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$14632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$14632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$14613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14571.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14571.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14571.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14571.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14571.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14571.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14571.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$14078.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$14078.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$14049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$14049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14037.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$14037.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14037.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14037.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14037.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$14015.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$14010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$13999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$13999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$13978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$13978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$13959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$13959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$13959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$13939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$13939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$13939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$13939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$13291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$13291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$13291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$13291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$11456.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11456.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11456.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11456.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11456.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11456.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$11447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$11380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$11380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$11371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$11342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11323.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$11318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11146.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11024.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11024.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11024.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11024.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11024.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11024.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$10999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$10999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$10999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$10999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$10979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$10979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$10979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$10959.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$10606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$10606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$10573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$10573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$10573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$10573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$10562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$10562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$10553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$10553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$9300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$9300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$9300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$9300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$9300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$9300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$9253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$9253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$9253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$9247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$9247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$9284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$9284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$9293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$9293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$9271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$9271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10256.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$100227$lut$auto$opt_dff.cc:219:make_patterns_logic$3083.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$9271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$9293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$9284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$9300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$10431.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$10438.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10445.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10464.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$10480.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$10537.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10553.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$10562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$10573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$10573.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$10606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$10627.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$10631.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$10638.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10680.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$10687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10701.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$10752.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10800.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10878.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$10885.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10892.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10911.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$10927.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$10963.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$10979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$10983.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$10999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11006.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$11024.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11024.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11044.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11060.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11080.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11087.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11150.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$11167.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11209.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11225.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11249.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11259.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11275.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11318.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$11327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11342.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11348.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11352.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$11359.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11380.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11384.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11394.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$11426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11426.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11447.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11456.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$11461.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$11512.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11596.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11603.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11613.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11654.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11723.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11756.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11772.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11788.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11816.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11823.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11852.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$11888.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11904.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11911.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11921.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11937.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11955.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$11988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12004.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12011.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12057.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$12107.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12117.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12124.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12155.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12198.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$12205.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12215.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12325.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12392.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12408.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12425.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12441.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12451.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12458.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12486.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12525.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$12532.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12542.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12549.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12583.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12685.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12719.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12732.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12745.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$12752.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12768.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12778.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12844.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$12851.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12861.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12868.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12902.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12971.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$12997.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$13004.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13020.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13071.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13087.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$13104.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$13170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$13186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$13211.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13222.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$13229.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$13273.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$13291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13301.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13308.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13369.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13385.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13401.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13463.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$13470.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13480.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13487.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13521.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13623.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13639.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13657.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13673.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13680.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13723.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$13783.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$13841.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$13858.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$13865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13875.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13891.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$13898.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13905.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13939.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$13944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$13944.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$13959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$13966.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$13966.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$13978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13983.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13994.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$13999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14010.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14019.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14037.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$14037.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$14049.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14078.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14078.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$14084.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$14092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$14092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$14138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14155.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14265.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14291.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$14298.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14345.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14358.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$14365.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14381.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14391.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14429.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14471.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14504.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14511.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14521.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14537.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14551.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14571.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14575.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14596.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$14596.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$14613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$14620.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$14632.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14638.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$14638.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$14648.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14653.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$14660.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14671.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$14681.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14693.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14697.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$14704.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$14738.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$14780.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14805.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14821.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14837.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14862.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14869.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14873.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$14880.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14905.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$14948.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$14982.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15041.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15048.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15090.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$15097.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15107.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15148.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15250.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15266.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15284.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15300.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15307.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15317.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15333.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15340.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15385.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15427.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$15443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$15460.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$15467.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15477.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15493.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$15500.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15507.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15522.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$15531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$15549.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15557.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$15562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$15569.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15581.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$15590.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15594.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$15605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15605.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15618.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$15618.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$15625.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$15643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$15655.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15661.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$15665.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15675.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15683.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$15683.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15689.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$15697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$15697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$15743.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$15750.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15760.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15767.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15801.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15870.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15903.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15937.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15953.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15970.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$15999.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16003.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$16039.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16046.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16072.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16106.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16122.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16171.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16178.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$16194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16194.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16214.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16232.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16239.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16288.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16295.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16309.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$16350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16357.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16383.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16417.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16450.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16478.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16512.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$16528.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16553.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16560.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16602.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16609.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16623.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$16662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16704.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16720.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16737.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16744.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16754.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16770.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16777.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16784.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16820.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16824.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$16836.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16845.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16849.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16859.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$16879.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$16883.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16893.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$16926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16926.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16947.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16956.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$16961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$16961.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$17006.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17022.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17029.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17072.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17095.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17135.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$17175.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$17225.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17235.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17242.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17273.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17338.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17357.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17373.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17389.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17405.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17459.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17502.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$17509.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17519.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17526.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17557.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17609.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$17616.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17626.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17633.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17667.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17736.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17749.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$17769.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17785.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17803.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17836.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17852.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$17917.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$17924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17934.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17941.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$17975.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18044.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18057.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$18077.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18127.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18160.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18167.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18177.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$18203.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18229.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$18236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18285.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18304.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18339.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18355.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18380.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18399.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18439.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18467.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18471.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$18496.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18538.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18554.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18571.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18588.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18611.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18618.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$18670.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$18683.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18701.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18707.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$18707.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$18727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$18727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$18743.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18776.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18785.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$18790.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$18833.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18840.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18847.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18866.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18882.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18907.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18914.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18939.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18946.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$18950.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$18979.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$18984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19007.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19017.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19031.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19080.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19087.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19101.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$19130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19137.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19144.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19163.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$19225.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19237.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$19270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19270.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19313.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19331.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19338.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19345.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19387.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19394.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19408.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$19453.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19460.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19470.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19477.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19511.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19580.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19596.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19603.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19613.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19639.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$19646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19672.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19679.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19695.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19702.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19709.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19713.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19756.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19763.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19773.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19780.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19814.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19883.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19899.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19915.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$19950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19966.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19973.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19983.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$19999.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$20006.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$20016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$20058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$20065.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$20072.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$20091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$20107.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$20125.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$20141.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$20159.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$20159.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$20180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$20180.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$20226.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$20253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$20253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$20260.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$20267.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$20309.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$20316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$20330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$9247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$9253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$9261.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$9247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$9271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$9261.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$9284.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$9293.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$100227$lut$aiger100226$9300.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$9318.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$9325.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$9337.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$9344.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$9382.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10697.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$9468.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$9531.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$9551.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$9588.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10606.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$9606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$9622.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$100227$lut$aiger100226$9652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$100227$lut$aiger100226$9671.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$9687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$9764.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$9784.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$9807.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$9946.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$9995.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$9839.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$auto$opt_dff.cc:219:make_patterns_logic$3162.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$100227$lut$auto$opt_dff.cc:219:make_patterns_logic$3334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$flatten\Controller.\Interpreter.$procmux$2325.Y[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$100227$lut$aiger100226$10372.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$100227$lut$auto$fsm_map.cc:170:map_fsm$3010[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100430.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100280.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100288.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100294.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100298.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100302.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100302.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100306.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100312.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100316.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100339.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100329.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100333.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100288.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100329.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100327.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100339.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100322.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100354.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100347.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100347.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100351.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100352.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100354.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100355.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100360.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100360.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100361.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100365.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100371.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100371.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100373.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100373.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100375.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100379.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100381.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100384.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100384.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100386.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100388.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100395.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100396.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100397.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100401.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100406.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100406.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100407.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100411.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100411.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100413.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100420.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100423.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100423.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$100430.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Removed 0 unused cells and 11341 unused wires.

28.45. Executing AUTONAME pass.
Renamed 110843 objects in module processorci_top (108 iterations).
<suppressed ~11819 debug messages>

28.46. Executing HIERARCHY pass (managing design hierarchy).

28.46.1. Analyzing design hierarchy..
Top module:  \processorci_top

28.46.2. Analyzing design hierarchy..
Top module:  \processorci_top
Removed 0 unused modules.

28.47. Printing statistics.

=== processorci_top ===

   Number of wires:               5611
   Number of wire bits:          17155
   Number of public wires:        5611
   Number of public wire bits:   17155
   Number of ports:                 10
   Number of port bits:             10
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               7408
     $scopeinfo                     11
     CCU2C                         142
     L6MUX21                       209
     LUT4                         4597
     PFUMX                         845
     TRELLIS_DPR16X4              1028
     TRELLIS_FF                    576

28.48. Executing CHECK pass (checking for obvious problems).
Checking module processorci_top...
Found and reported 0 problems.

28.49. Executing JSON backend.

Warnings: 102 unique messages, 102 total
End of script. Logfile hash: aaf0377a0b, CPU: user 16.74s system 0.14s, MEM: 165.90 MB peak
Yosys 0.45+139 (git sha1 4d581a97d, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3)
Time spent: 25% 1x abc9_exe (5 sec), 14% 11x techmap (3 sec), ...
/eda/oss-cad-suite/bin/nextpnr-ecp5 --json colorlight_i9.json --write colorlight_i9_pnr.json --45k \
	--lpf /eda/processor_ci/constraints/colorlight_i9.lpf --textcfg colorlight_i9.config --package CABGA381 \
	--speed 6 --lpf-allow-unconstrained  --ignore-loops
/eda/oss-cad-suite/bin/ecppack --compress --input colorlight_i9.config  --bit colorlight_i9.bit

[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
[Pipeline] dir
Running in /var/jenkins_home/workspace/serv/serv
[Pipeline] {
[Pipeline] echo
Flashing FPGA colorlight_i9.
[Pipeline] sh
+ python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p serv -b colorlight_i9 -l
Final configuration file generated at /var/jenkins_home/workspace/serv/serv/build_colorlight_i9.tcl
Makefile executed successfully.
Makefile output:
/eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 colorlight_i9.bit
empty
Found 1 compatible device:
	0x0d28 0x0204 0x3 (null)
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE

Loading: [=====                                             ] 8.71%
Loading: [=========                                         ] 17.11%
Loading: [=============                                     ] 25.82%
Loading: [==================                                ] 34.54%
Loading: [======================                            ] 43.25%
Loading: [==========================                        ] 51.97%
Loading: [===============================                   ] 60.68%
Loading: [===================================               ] 69.40%
Loading: [========================================          ] 78.11%
Loading: [============================================      ] 86.82%
Loading: [================================================  ] 95.54%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE

[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test colorlight_i9)
[Pipeline] echo
Testing FPGA colorlight_i9.
[Pipeline] dir
Running in /var/jenkins_home/workspace/serv/serv
[Pipeline] {
[Pipeline] sh
+ echo Test for FPGA in /dev/ttyACM0
Test for FPGA in /dev/ttyACM0
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: colorlight_i9]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
No test report files were found. Configuration error?
Error when executing always post condition:
Also:   org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: 0b86ee98-c5b8-4177-8396-d505b247de96
hudson.AbortException: No test report files were found. Configuration error?
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253)
	at hudson.FilePath.act(FilePath.java:1234)
	at hudson.FilePath.act(FilePath.java:1217)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177)
	at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62)
	at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27)
	at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:47)
	at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source)
	at java.base/java.util.concurrent.FutureTask.run(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source)
	at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source)
	at java.base/java.lang.Thread.run(Unknown Source)

[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE