Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date         : Thu Jul 30 22:10:20 2026
| Host         : 685a421e500f running 64-bit unknown
| Command      : report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
| Design       : fpga_top
| Device       : xc7a100t
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Control Set Information

Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Total control sets                                       |    64 |
|    Minimum number of control sets                        |    64 |
|    Addition due to synthesis replication                 |     0 |
|    Addition due to physical synthesis replication        |     0 |
| Unused register locations in slices containing registers |   105 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions


2. Histogram
------------

+--------------------+-------+
|       Fanout       | Count |
+--------------------+-------+
| Total control sets |    64 |
| >= 0 to < 4        |     2 |
| >= 4 to < 6        |    10 |
| >= 6 to < 8        |     2 |
| >= 8 to < 10       |     9 |
| >= 10 to < 12      |     4 |
| >= 12 to < 14      |     4 |
| >= 14 to < 16      |     1 |
| >= 16              |    32 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design


3. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |              32 |           19 |
| No           | No                    | Yes                    |               0 |            0 |
| No           | Yes                   | No                     |              99 |           50 |
| Yes          | No                    | No                     |             269 |          104 |
| Yes          | No                    | Yes                    |              32 |            8 |
| Yes          | Yes                   | No                     |             439 |          127 |
+--------------+-----------------------+------------------------+-----------------+--------------+


4. Detailed Control Set Information
-----------------------------------

+--------------------------------------+--------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+
|             Clock Signal             |                            Enable Signal                           |                       Set/Reset Signal                       | Slice Load Count | Bel Load Count | Bels / Slice |
+--------------------------------------+--------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                   | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_1_n_0             |                1 |              1 |         1.00 |
|  clk_IBUF_BUFG                       |                                                                    |                                                              |                1 |              1 |         1.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/next_bit                          | ptop/u_Controller/Uart/i_uart_rx/bit_counter[3]_i_1__0_n_0   |                1 |              4 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_2__0_n_0         | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_1_n_0      |                1 |              4 |         4.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/serv_rf_top/cpu/state/gen_cnt_w_eq_1.cnt_lsb_reg[3]_2[0]      |                                                              |                1 |              4 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/E[0]                              |                                                              |                1 |              4 |         4.00 |
|  u_Controller/ClkDivider/clk_o_pulse |                                                                    | ptop/serv_rf_top/cpu/decode/SR[0]                            |                2 |              4 |         2.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/serv_rf_top/cpu/decode/gen_pre_register.opcode_reg[4]_1[0]    |                                                              |                2 |              5 |         2.50 |
|  clk_o_BUFG                          |                                                                    |                                                              |                4 |              5 |         1.25 |
|  clk_o_BUFG                          | ResetBootSystem/counter                                            |                                                              |                3 |              5 |         1.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/return_state                         | ResetBootSystem/rst_o_reg_0                                  |                2 |              5 |         2.50 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/serv_rf_top/cpu/decode/E[0]                                   |                                                              |                3 |              5 |         1.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/serv_rf_top/cpu/decode/gen_pre_register.opcode_reg[0]_0[0]    |                                                              |                3 |              6 |         2.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/data_to_send[6]_i_1_n_0           | ResetBootSystem/rst_o_reg_0                                  |                2 |              7 |         3.50 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/E[0]                                | ResetBootSystem/rst_o_reg_0                                  |                4 |              8 |         2.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/E[0]                              | ResetBootSystem/rst_o_reg_0                                  |                2 |              8 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/uart_rx_data[7]_i_1_n_0           | ResetBootSystem/rst_o_reg_0                                  |                3 |              8 |         2.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/recieved_data0                    | ptop/u_Controller/Uart/i_uart_rx/recieved_data[7]_i_1_n_0    |                2 |              8 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/counter                              | ResetBootSystem/rst_o_reg_0                                  |                3 |              8 |         2.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/uart_tx_en                                  | ResetBootSystem/rst_o_reg_0                                  |                4 |              8 |         2.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/accumulator[7]_i_1_n_0               | ResetBootSystem/rst_o_reg_0                                  |                5 |              8 |         1.60 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/serv_rf_top/cpu/state/E[0]                                    |                                                              |                6 |              8 |         1.33 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/serv_rf_top/cpu/decode/gen_pre_register.opcode_reg[2]_0[0]    |                                                              |                3 |              9 |         3.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                   | ResetBootSystem/SR[0]                                        |                2 |             10 |         5.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/cycle_counter0                    | ptop/u_Controller/Uart/i_uart_rx/cycle_counter[9]_i_1__0_n_0 |                2 |             10 |         5.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/rx_fifo/read_ptr0                           | ResetBootSystem/rst_o_reg_0                                  |                3 |             11 |         3.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/read_ptr[2]_i_1_n_0                 | ResetBootSystem/rst_o_reg_0                                  |                3 |             11 |         3.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/address[31]_i_1_n_0                  |                                                              |                7 |             12 |         1.71 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/memory_reg_0_7_0_5_i_1_n_0          |                                                              |                2 |             12 |         6.00 |
|  u_Controller/ClkDivider/clk_o_pulse |                                                                    | ptop/u_Controller/Interpreter/core_reset_reg_0               |                9 |             12 |         1.33 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/rx_fifo/memory_reg_0_7_0_5_i_1__0_n_0       |                                                              |                2 |             12 |         6.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/u_Controller/Interpreter/core_reset_reg_4                     |                                                              |                8 |             14 |         1.75 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/num_of_cycles_to_pulse[23]_i_1_n_0   |                                                              |                8 |             24 |         3.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/num_of_pages                         | ResetBootSystem/rst_o_reg_0                                  |                5 |             24 |         4.80 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/accumulator0                         | ResetBootSystem/rst_o_reg_0                                  |                5 |             24 |         4.80 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/memory_page_number[23]_i_2_n_0       | ptop/u_Controller/Interpreter/memory_page_number[23]_i_1_n_0 |                7 |             24 |         3.43 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/timeout                              | ResetBootSystem/rst_o_reg_0                                  |                9 |             24 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/serv_rf_top/cpu/state/gen_cnt_w_eq_1.cnt_lsb_reg[0]_0[0]      |                                                              |               10 |             24 |         2.40 |
|  u_Controller/ClkDivider/clk_o_pulse |                                                                    |                                                              |               14 |             26 |         1.86 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/serv_rf_top/cpu/decode/bufreg_en                              |                                                              |               12 |             30 |         2.50 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/serv_rf_top/cpu/state/core_reset_reg[0]                       | ptop/u_Controller/Interpreter/core_reset_reg_0               |               11 |             32 |         2.91 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/timeout_counter                      | ResetBootSystem/rst_o_reg_0                                  |                5 |             32 |         6.40 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/rx_fifo/E[0]                                | ResetBootSystem/rst_o_reg_0                                  |                5 |             32 |         6.40 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/communication_buffer[31]_i_1_n_0     | ResetBootSystem/rst_o_reg_0                                  |               10 |             32 |         3.20 |
|  clk_o_BUFG                          | ptop/u_Controller/ClkDivider/pulse_counter[0]_i_1_n_0              | ResetBootSystem/rst_o_reg_0                                  |                8 |             32 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/write_data[31]_i_1_n_0               |                                                              |               15 |             32 |         2.13 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/counter_write_reg[2][0]             | ResetBootSystem/rst_o_reg_0                                  |                7 |             32 |         4.57 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/communication_write_data[31]_i_1_n_0 |                                                              |                8 |             32 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/read_buffer                          | ResetBootSystem/rst_o_reg_0                                  |               13 |             32 |         2.46 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/end_position[31]_i_1_n_0             | ResetBootSystem/rst_o_reg_0                                  |               10 |             32 |         3.20 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/num_of_positions[23]_i_1_n_0         |                                                              |               14 |             55 |         3.93 |
|  clk_o_BUFG                          |                                                                    | ResetBootSystem/rst_o_reg_0                                  |               39 |             83 |         2.13 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/o_ibus_adr_reg[12]_6                 |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/o_ibus_adr_reg[12]_5                 |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/o_ibus_adr_reg[12]_4                 |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/o_ibus_adr_reg[12]_3                 |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/o_ibus_adr_reg[12]_2                 |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/o_ibus_adr_reg[12]_1                 |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/o_ibus_adr_reg[12]                   |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/o_ibus_adr_reg[12]_0                 |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/gen_w_eq_1.data_reg[10]_0            |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/address_reg[11]_0                    |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/gen_w_eq_1.data_reg[10]              |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/address_reg[10]_0                    |                                                              |               32 |            128 |         4.00 |
+--------------------------------------+--------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+


