Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Still waiting to schedule task
Waiting for next available executor
Running on Jenkins in /var/jenkins_home/workspace/simodense
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf simodense
[Pipeline] sh
+ git clone --recursive --depth=1 https://github.com/pphilippos/simodense simodense
Cloning into 'simodense'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/jenkins_home/workspace/simodense/simodense
[Pipeline] {
[Pipeline] sh
+ /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s FPGA_Implementation_AXI_peripheral/MAXI_ip.v FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v FPGA_Implementation_AXI_peripheral/SAXI_ip.v FPGA_Implementation_AXI_peripheral/caches.v FPGA_Implementation_AXI_peripheral/cpu.v FPGA_Implementation_AXI_peripheral/custom.v FPGA_Implementation_AXI_peripheral/system.v Benchmarks/simple_vector_add/custom.v RTL_and_simulation/caches.v RTL_and_simulation/cpu.v RTL_and_simulation/custom.v RTL_and_simulation/system.v RTL_and_simulation/testbench.v
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:17: warning: macro DL2block undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:18: warning: macro DL2block_Log2 undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:49: warning: macro DADDR_bits undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:50: warning: macro DL2subblocks_Log2 undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:51: warning: macro DL2block undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:51: warning: macro DL2subblocks undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:52: warning: macro DL2subblocks_Log2 undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:53: warning: macro DL2block undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:53: warning: macro DL2subblocks undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:185: warning: macro DL2subblocks undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:187: warning: macro DL2subblocks_Log2 undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:368: warning: macro DL2block undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:368: warning: macro DL2subblocks undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:403: warning: macro DL2block undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:403: warning: macro DL2subblocks undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:404: warning: macro DL2block undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:404: warning: macro DL2subblocks undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:427: warning: macro DL2block undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:427: warning: macro DL2subblocks undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/SAXI_ip.v:31: warning: macro DADDR_bits undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/SAXI_ip.v:32: warning: macro DL2subblocks_Log2 undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/SAXI_ip.v:33: warning: macro DL2block undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/SAXI_ip.v:33: warning: macro DL2subblocks undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/SAXI_ip.v:34: warning: macro DL2subblocks_Log2 undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/SAXI_ip.v:35: warning: macro DL2block undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/SAXI_ip.v:35: warning: macro DL2subblocks undefined (and assumed null) at this point.
FPGA_Implementation_AXI_peripheral/MAXI_ip_doublewidth.v:FPGA_Implementation_AXI_peripheral/SAXI_ip.v:546: 17warning: macro IADDR_bits undefined (and assumed null) at this point.
: syntax errorFPGA_Implementation_AXI_peripheral/SAXI_ip.v:547:
warning: macro DADDR_bits undefined (and assumed null) at this point.
I give up.
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Utilities)
Stage "Utilities" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
Stage "FPGA Build Pipeline" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_nexys4_ddr)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
[Pipeline] stage
[Pipeline] { (Synthesis and PnR)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
[Pipeline] stage
[Pipeline] { (Flash digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Test colorlight_i9)
[Pipeline] stage
[Pipeline] { (Test digilent_nexys4_ddr)
Stage "colorlight_i9" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
Stage "digilent_nexys4_ddr" skipped due to earlier failure(s)
[Pipeline] getContext
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
[Pipeline] }
[Pipeline] // stage
[Pipeline] // stage
[Pipeline] }
Failed in branch colorlight_i9
[Pipeline] }
Failed in branch digilent_nexys4_ddr
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
No test report files were found. Configuration error?
Error when executing always post condition:
Also: org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: f071b619-841c-46da-b865-c493e9741418
hudson.AbortException: No test report files were found. Configuration error?
at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253)
at hudson.FilePath.act(FilePath.java:1234)
at hudson.FilePath.act(FilePath.java:1217)
at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146)
at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177)
at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282)
at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62)
at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27)
at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:47)
at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source)
at java.base/java.util.concurrent.FutureTask.run(Unknown Source)
at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source)
at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source)
at java.base/java.lang.Thread.run(Unknown Source)
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 2
Finished: FAILURE