I-ADD-01.elf.objcopy
I-ADD-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 22:57:01 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.290 seconds to compile + .006 seconds to elab + .142 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 22:57 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      4.870 seconds;       Data structure size:   0.1Mb
Thu Nov  5 22:57:17 2020
ok
I-ADDI-01.elf.objcopy
I-ADDI-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 22:57:21 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.064 seconds to compile + .005 seconds to elab + .084 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 22:57 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      4.910 seconds;       Data structure size:   0.1Mb
Thu Nov  5 22:57:36 2020
ok
I-AND-01.elf.objcopy
I-AND-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 22:57:41 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.040 seconds to compile + .005 seconds to elab + .088 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 22:57 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      4.850 seconds;       Data structure size:   0.1Mb
Thu Nov  5 22:57:55 2020
ok
I-ANDI-01.elf.objcopy
I-ANDI-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 22:58:00 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.174 seconds to compile + .003 seconds to elab + .085 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 22:58 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      5.170 seconds;       Data structure size:   0.1Mb
Thu Nov  5 22:58:15 2020
ok
I-AUIPC-01.elf.objcopy
I-AUIPC-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 22:58:20 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.078 seconds to compile + .012 seconds to elab + .085 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 22:58 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      5.040 seconds;       Data structure size:   0.1Mb
Thu Nov  5 22:58:35 2020
ok
I-BEQ-01.elf.objcopy
I-BEQ-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 22:58:40 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.097 seconds to compile + .005 seconds to elab + .079 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 22:58 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      5.100 seconds;       Data structure size:   0.1Mb
Thu Nov  5 22:58:55 2020
ok
I-BGE-01.elf.objcopy
I-BGE-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 22:58:59 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.087 seconds to compile + .004 seconds to elab + .081 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 22:59 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      4.990 seconds;       Data structure size:   0.1Mb
Thu Nov  5 22:59:14 2020
ok
I-BGEU-01.elf.objcopy
I-BGEU-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 22:59:19 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 1.993 seconds to compile + .005 seconds to elab + .084 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 22:59 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      5.290 seconds;       Data structure size:   0.1Mb
Thu Nov  5 22:59:34 2020
ok
I-BLT-01.elf.objcopy
I-BLT-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 22:59:39 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.066 seconds to compile + .004 seconds to elab + .082 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 22:59 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      5.150 seconds;       Data structure size:   0.1Mb
Thu Nov  5 22:59:54 2020
ok
I-BLTU-01.elf.objcopy
I-BLTU-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 22:59:58 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.060 seconds to compile + .006 seconds to elab + .089 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:00 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      4.960 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:00:13 2020
ok
I-BNE-01.elf.objcopy
I-BNE-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:00:18 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.040 seconds to compile + .004 seconds to elab + .086 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:00 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      4.940 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:00:33 2020
ok
I-DELAY_SLOTS-01.elf.objcopy
I-DELAY_SLOTS-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:00:37 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.181 seconds to compile + .005 seconds to elab + .085 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:00 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      5.100 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:00:52 2020
ok
I-EBREAK-01.elf.objcopy
I-EBREAK-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:00:57 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.023 seconds to compile + .003 seconds to elab + .082 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:01 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      5.010 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:01:12 2020
ok
I-ECALL-01.elf.objcopy
I-ECALL-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:01:17 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.085 seconds to compile + .007 seconds to elab + .080 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:01 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      4.980 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:01:32 2020
ok
I-ENDIANESS-01.elf.objcopy
I-ENDIANESS-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:01:36 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.050 seconds to compile + .003 seconds to elab + .079 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:01 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      5.060 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:01:51 2020
ok
I-IO-01.elf.objcopy
I-IO-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:01:56 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.046 seconds to compile + .004 seconds to elab + .090 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:02 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      4.890 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:02:11 2020
ok
I-JAL-01.elf.objcopy
I-JAL-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:02:15 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.133 seconds to compile + .003 seconds to elab + .082 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:02 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      4.920 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:02:30 2020
ok
I-JALR-01.elf.objcopy
I-JALR-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:02:35 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.013 seconds to compile + .004 seconds to elab + .081 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:02 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      5.620 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:02:50 2020
ok
I-LB-01.elf.objcopy
I-LB-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:02:55 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.001 seconds to compile + .036 seconds to elab + .083 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:03 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      5.210 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:03:10 2020
ok
I-LBU-01.elf.objcopy
I-LBU-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:03:14 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.083 seconds to compile + .005 seconds to elab + .079 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:03 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      4.880 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:03:29 2020
ok
I-LH-01.elf.objcopy
I-LH-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:03:34 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.380 seconds to compile + .019 seconds to elab + .082 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:03 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      4.940 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:03:49 2020
ok
I-LHU-01.elf.objcopy
I-LHU-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:03:54 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.014 seconds to compile + .008 seconds to elab + .081 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:04 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      5.090 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:04:09 2020
ok
I-LUI-01.elf.objcopy
I-LUI-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:04:13 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.095 seconds to compile + .003 seconds to elab + .085 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:04 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      5.100 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:04:28 2020
ok
I-LW-01.elf.objcopy
I-LW-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:04:33 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.160 seconds to compile + .004 seconds to elab + .082 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:04 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      4.930 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:04:48 2020
ok
I-MISALIGN_JMP-01.elf.objcopy
I-MISALIGN_JMP-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:04:53 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.206 seconds to compile + .003 seconds to elab + .084 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:05 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      5.100 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:05:08 2020
ok
I-MISALIGN_LDST-01.elf.objcopy
I-MISALIGN_LDST-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:05:12 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 1.972 seconds to compile + .038 seconds to elab + .078 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:05 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      4.880 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:05:27 2020
ok
I-NOP-01.elf.objcopy
I-NOP-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:05:32 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.006 seconds to compile + .004 seconds to elab + .082 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:05 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      5.050 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:05:47 2020
ok
I-OR-01.elf.objcopy
I-OR-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:05:52 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.160 seconds to compile + .005 seconds to elab + .081 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:05 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      5.310 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:06:07 2020
ok
I-ORI-01.elf.objcopy
I-ORI-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:06:12 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.059 seconds to compile + .046 seconds to elab + .076 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:06 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      5.350 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:06:27 2020
ok
I-RF_size-01.elf.objcopy
I-RF_size-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:06:32 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.085 seconds to compile + .012 seconds to elab + .085 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:06 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      4.890 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:06:46 2020
ok
I-RF_width-01.elf.objcopy
I-RF_width-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:06:51 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.029 seconds to compile + .005 seconds to elab + .086 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:06 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      4.830 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:07:06 2020
ok
I-RF_x0-01.elf.objcopy
I-RF_x0-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:07:10 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 1.986 seconds to compile + .006 seconds to elab + .081 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:07 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      4.980 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:07:25 2020
ok
I-SB-01.elf.objcopy
I-SB-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:07:30 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.357 seconds to compile + .005 seconds to elab + .083 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:07 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      4.870 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:07:45 2020
ok
I-SH-01.elf.objcopy
I-SH-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:07:50 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.126 seconds to compile + .005 seconds to elab + .083 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:07 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      4.950 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:08:05 2020
ok
I-SLL-01.elf.objcopy
I-SLL-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:08:09 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.034 seconds to compile + .011 seconds to elab + .082 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:08 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      4.780 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:08:24 2020
ok
I-SLLI-01.elf.objcopy
I-SLLI-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:08:29 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.135 seconds to compile + .004 seconds to elab + .079 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:08 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      4.990 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:08:44 2020
ok
I-SLT-01.elf.objcopy
I-SLT-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:08:48 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.008 seconds to compile + .004 seconds to elab + .084 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:08 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      4.920 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:09:03 2020
ok
I-SLTI-01.elf.objcopy
I-SLTI-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:09:08 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.008 seconds to compile + .005 seconds to elab + .081 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:09 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      5.220 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:09:23 2020
ok
I-SLTIU-01.elf.objcopy
I-SLTIU-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:09:28 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.060 seconds to compile + .002 seconds to elab + .083 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:09 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      5.320 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:09:43 2020
ok
I-SLTU-01.elf.objcopy
I-SLTU-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:09:47 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.114 seconds to compile + .004 seconds to elab + .094 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:09 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      5.010 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:10:02 2020
ok
I-SRA-01.elf.objcopy
I-SRA-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:10:07 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 1.986 seconds to compile + .006 seconds to elab + .088 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:10 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      4.970 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:10:22 2020
ok
I-SRAI-01.elf.objcopy
I-SRAI-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:10:27 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.028 seconds to compile + .020 seconds to elab + .081 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:10 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      5.190 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:10:42 2020
ok
I-SRL-01.elf.objcopy
I-SRL-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:10:46 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.055 seconds to compile + .005 seconds to elab + .087 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:10 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      4.990 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:11:01 2020
ok
I-SRLI-01.elf.objcopy
I-SRLI-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:11:06 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.028 seconds to compile + .006 seconds to elab + .084 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:11 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      5.120 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:11:21 2020
ok
I-SUB-01.elf.objcopy
I-SUB-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:11:26 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.045 seconds to compile + .002 seconds to elab + .084 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:11 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      4.800 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:11:40 2020
ok
I-SW-01.elf.objcopy
I-SW-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:11:45 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.073 seconds to compile + .005 seconds to elab + .085 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:11 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      5.030 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:12:00 2020
ok
I-XOR-01.elf.objcopy
I-XOR-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:12:05 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.077 seconds to compile + .006 seconds to elab + .081 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:12 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      4.980 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:12:19 2020
ok
I-XORI-01.elf.objcopy
I-XORI-01
remove

Warning-[LNX_OS_VERUN] Unsupported Linux version
  Linux version 'CentOS release 6.10 (Final)' is not supported on 'x86_64' 
  officially, assuming linux compatibility by default. Set VCS_ARCH_OVERRIDE 
  to linux or suse32 to override.
  Please refer to release notes for information on supported platforms.

                         Chronologic VCS (TM)
         Version I-2014.03_Full64 -- Thu Nov  5 23:12:24 2020
               Copyright (c) 1991-2014 by Synopsys Inc.
                         ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.


Warning-[LCA_FEATURES_ENABLED] Usage warning
  LCA features enabled by '-lca' argument on the command line.  For more 
  information regarding list of LCA features please refer to Chapter "LCA 
  features" in the VCS/VCS-MX Release Notes

Parsing design file '../../tb/tb.v'
Parsing design file '../../rtl/core/alu.v'
Parsing design file '../../rtl/core/ctrl.v'
Parsing design file '../../rtl/core/dram.v'
Parsing design file '../../rtl/core/id.v'
Parsing design file '../../rtl/core/iram.v'
Parsing design file '../../rtl/core/machine.v'
Parsing design file '../../rtl/core/pc.v'
Parsing design file '../../rtl/core/regs.v'
Parsing design file '../../rtl/core/starsea_core.v'
Parsing design file '../../rtl/core/wb.v'
Parsing design file '../../rtl/soc/fpga_top.v'
Top Level Modules:
       tb
TimeScale is 1 ns / 1 ps

Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 286
"alu u_alu( .clk (clk),  .rst_n (rst_n),  .hazard_rs1 (hazard_rs1),  .hazard_rs2 (hazard_rs2),  .hazard_rs_rd (hazard_rs_rd),  .r_type_funct3_ex (r_type_funct3_ex),  .r_type_funct7_ex (r_type_funct7_ex),  .r_type_ex ((r_type_ex & (~pc_jump_en))),  .rd (rd),  .alu_rd_val (add_res_val),  .rd_dat (rd_dat),  .rs2_dat (rs2_dat),  .rs1_dat_ex (rs1_dat_ex),  .rs2_dat_ex (rs2_dat_ex),  .pc (pc),  .lui_ex ((lui_ex & (~pc_jump_en))),  .auipc_ex ((auipc_ex & (~pc_jump_en))),  .u_type_imm (u_type_imm),  .i_type_ari_funct3_ex (i_type_ari_funct3_ex),  .i_type_ari_funct7_ex (i_type_ari_funct7_ex),  .i_type_ari_ex ((i_type_ari_ex & (~pc_jump_en))),  .rs1_dat (rs1_dat),  .imm (si_type_imm),  .add_res_val (add_res_val),  .add_res (add_res),  .store_ex ((store_ex & (~pc_ju ... "
  The above instance has fewer port connections than the module definition,
  input port 'add_ex' is not connected,
  input port 'sub_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../rtl/core/starsea_core.v, 337
"wb u_wb( .clk (clk),  .sw_en (sw_en),  .add_en (add_en),  .wr_dbus_en (wr_dubs_en),  .wr_rd_en (wr_rd_en));"
  The above instance has fewer port connections than the module definition,
  input port 'rst_n' is not connected,
  input port 'addi_ex' is not connected,
  input port 'andi_ex' is not connected.


Lint-[TFIPC-L] Too few instance port connections
../../tb/tb.v, 20
"fpga_top u_fpga_top();"
  The above instance has fewer port connections than the module definition,
  all ports are not connected.

Starting vcs inline pass...
3 modules and 0 UDP read.
	However, due to incremental compilation, no re-compilation is necessary.
rm -f _csrc*.so amd64_scvhdl_*.so pre_vcsobj_*.so share_vcsobj_*.so
ld -shared -o .//../simv.daidir//_csrc0.so SIM_l.o 5NrI_d.o 5NrIB_d.o  
ld -shared -o .//../simv.daidir//pre_vcsobj_1_1.so --whole-archive pre_vcsobj_1_1.a --no-whole-archive
ld -shared -o .//../simv.daidir//pre_vcsobj_1_2.so --whole-archive pre_vcsobj_1_2.a --no-whole-archive
if [ -x ../simv ]; then chmod -x ../simv; fi
g++  -o ../simv    -Wl,-rpath-link=./ -Wl,-rpath='$ORIGIN'/simv.daidir/ -Wl,-rpath='$ORIGIN'/simv.daidir//scsim.db.dir  _csrc0.so   pre_vcsobj_1_1.so pre_vcsobj_1_2.so  rmapats_mop.o rmapats.o rmar.o           /opt/Synopsys/VCS2014/amd64/lib/libzerosoft_rt_stubs.so /opt/Synopsys/VCS2014/amd64/lib/libvirsim.so /opt/Synopsys/VCS2014/amd64/lib/liberrorinf.so /opt/Synopsys/VCS2014/amd64/lib/libsnpsmalloc.so /opt/Synopsys/Verdi2015/share/PLI/VCS/LINUX64/pli.a    /opt/Synopsys/VCS2014/amd64/lib/libvcsnew.so /opt/Synopsys/VCS2014/amd64/lib/libuclinative.so   -Wl,-whole-archive /opt/Synopsys/VCS2014/amd64/lib/libvcsucli.so -Wl,-no-whole-archive          /opt/Synopsys/VCS2014/amd64/lib/vcs_save_restore_new.o -ldl -lm -lm  -lc -lpthread -ldl 
../simv up to date
CPU time: 2.007 seconds to compile + .004 seconds to elab + .082 seconds to link
Notice: timing checks disabled with +notimingcheck at compile-time
Chronologic VCS simulator copyright 1991-2014
Contains Synopsys proprietary information.
Compiler version I-2014.03_Full64; Runtime version I-2014.03_Full64;  Nov  5 23:12 2020
*Verdi3* Loading libsscore_vcs201403.so
*Verdi3* : Enable Parallel Dumping.
FSDB Dumper for VCS, Release Verdi3_K-2015.09-SP1-1, Linux x86_64/64bit, 01/21/2016
(C) 1996 - 2016 by Synopsys, Inc.
*Verdi3* FSDB WARNING: The FSDB file already exists. Overwriting the FSDB file may crash the programs that are using this file.
*Verdi3* : Create FSDB file 'test.fsdb'
*Verdi3* : Begin traversing the scope (tb), layer (0).
*Verdi3* : End of traversing.
*Verdi3* : Begin traversing the MDAs under scope (tb), layer (0).
*Verdi3* : Enable +mda and +packedmda dumping.
*Verdi3* : End of traversing the MDAs.
$finish called from file "../../tb/tb.v", line 24.
$finish at simulation time           5000000000
           V C S   S i m u l a t i o n   R e p o r t 
Time: 5000000000 ps
CPU Time:      4.950 seconds;       Data structure size:   0.1Mb
Thu Nov  5 23:12:39 2020
ok
