Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version     : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date             : Thu Sep  3 00:37:00 2026
| Host             : 685a421e500f running 64-bit unknown
| Command          : report_power -file digilent_arty_a7_power.rpt
| Design           : fpga_top
| Device           : xc7a100tcsg324-1
| Design State     : routed
| Grade            : commercial
| Process          : typical
| Characterization : Production
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Power Report

Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy

1. Summary
----------

+--------------------------+--------------+
| Total On-Chip Power (W)  | 0.121        |
| Design Power Budget (W)  | Unspecified* |
| Power Budget Margin (W)  | NA           |
| Dynamic (W)              | 0.024        |
| Device Static (W)        | 0.097        |
| Effective TJA (C/W)      | 4.6          |
| Max Ambient (C)          | 84.4         |
| Junction Temperature (C) | 25.6         |
| Confidence Level         | Low          |
| Setting File             | ---          |
| Simulation Activity File | ---          |
| Design Nets Matched      | NA           |
+--------------------------+--------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>


1.1 On-Chip Components
----------------------

+--------------------------+-----------+----------+-----------+-----------------+
| On-Chip                  | Power (W) | Used     | Available | Utilization (%) |
+--------------------------+-----------+----------+-----------+-----------------+
| Clocks                   |    <0.001 |        4 |       --- |             --- |
| Slice Logic              |     0.011 |     8133 |       --- |             --- |
|   LUT as Logic           |     0.010 |     2960 |     63400 |            4.67 |
|   CARRY4                 |    <0.001 |      218 |     15850 |            1.38 |
|   LUT as Distributed RAM |    <0.001 |     1136 |     19000 |            5.98 |
|   Register               |    <0.001 |     2353 |    126800 |            1.86 |
|   BUFG                   |    <0.001 |        3 |        32 |            9.38 |
|   F7/F8 Muxes            |    <0.001 |      785 |     63400 |            1.24 |
|   Others                 |     0.000 |       51 |       --- |             --- |
| Signals                  |     0.012 |     5407 |       --- |             --- |
| Block RAM                |    <0.001 |        2 |       135 |            1.48 |
| I/O                      |    <0.001 |        5 |       210 |            2.38 |
| Static Power             |     0.097 |          |           |                 |
| Total                    |     0.121 |          |           |                 |
+--------------------------+-----------+----------+-----------+-----------------+


1.2 Power Supply Summary
------------------------

+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) | Powerup (A) | Budget (A)  | Margin (A) |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+
| Vccint    |       1.000 |     0.039 |       0.024 |      0.015 |       NA    | Unspecified | NA         |
| Vccaux    |       1.800 |     0.018 |       0.000 |      0.018 |       NA    | Unspecified | NA         |
| Vcco33    |       3.300 |     0.004 |       0.000 |      0.004 |       NA    | Unspecified | NA         |
| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco18    |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccbram   |       1.000 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |       NA    | Unspecified | NA         |
| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |       NA    | Unspecified | NA         |
+-----------+-------------+-----------+-------------+------------+-------------+-------------+------------+


1.3 Confidence Level
--------------------

+-----------------------------+------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| User Input Data             | Confidence | Details                                               | Action                                                                                                             |
+-----------------------------+------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| Design implementation state | High       | Design is routed                                      |                                                                                                                    |
| Clock nodes activity        | Low        | User specified less than 75% of clocks                | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
| I/O nodes activity          | Medium     | More than 5% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view           |
| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes        | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views         |
| Device models               | High       | Device models are Production                          |                                                                                                                    |
|                             |            |                                                       |                                                                                                                    |
| Overall confidence level    | Low        |                                                       |                                                                                                                    |
+-----------------------------+------------+-------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+


2. Settings
-----------

2.1 Environment
---------------

+-----------------------+--------------------------+
| Ambient Temp (C)      | 25.0                     |
| ThetaJA (C/W)         | 4.6                      |
| Airflow (LFM)         | 250                      |
| Heat Sink             | medium (Medium Profile)  |
| ThetaSA (C/W)         | 4.6                      |
| Board Selection       | medium (10"x10")         |
| # of Board Layers     | 12to15 (12 to 15 Layers) |
| Board Temperature (C) | 25.0                     |
+-----------------------+--------------------------+


2.2 Clock Constraints
---------------------

+-------------+--------+-----------------+
| Clock       | Domain | Constraint (ns) |
+-------------+--------+-----------------+
| sys_clk_pin | clk    |            10.0 |
+-------------+--------+-----------------+


3. Detailed Reports
-------------------

3.1 By Hierarchy
----------------

+-----------------------------+-----------+
| Name                        | Power (W) |
+-----------------------------+-----------+
| fpga_top                    |     0.024 |
|   ptop                      |     0.023 |
|     u_Controller            |     0.001 |
|       Interpreter           |     0.001 |
|     u_pp_potato             |     0.021 |
|       icache_enabled.icache |     0.003 |
|       processor             |     0.018 |
+-----------------------------+-----------+


