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Started by user Gabriel Cabral [Pipeline] Start of Pipeline [Pipeline] node Running on Jenkins in /var/jenkins_home/workspace/tinyriscv [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -rf tinyriscv [Pipeline] sh + git clone --recursive --depth=1 https://github.com/liangkangnan/tinyriscv tinyriscv Cloning into 'tinyriscv'... [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Simulation) [Pipeline] dir Running in /var/jenkins_home/workspace/tinyriscv/tinyriscv [Pipeline] { [Pipeline] sh + /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s tinyriscv -I rtl/core/ rtl/core/clint.v rtl/core/csr_reg.v rtl/core/ctrl.v rtl/core/div.v rtl/core/ex.v rtl/core/id.v rtl/core/id_ex.v rtl/core/if_id.v rtl/core/pc_reg.v rtl/core/regs.v rtl/core/rib.v rtl/core/tinyriscv.v rtl/utils/gen_dff.v [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Utilities) [Pipeline] dir Running in /var/jenkins_home/workspace/tinyriscv/tinyriscv [Pipeline] { [Pipeline] sh + pwd + python3 /eda/processor_ci/core/labeler_prototype.py -d /var/jenkins_home/workspace/tinyriscv/tinyriscv -c /eda/processor_ci/config.json -o /jenkins/processor_ci_utils/labels.json WARNING: Error reading file /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v with encoding utf-8: 'utf-8' codec can't decode byte 0xba in position 1074: invalid start byte WARNING: Error writing to JSON file: [Errno 2] No such file or directory: '/jenkins/processor_ci_utils/labels.json' Trying to read file: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/tinyriscv.v Trying to read file: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Build Pipeline) [Pipeline] parallel [Pipeline] { (Branch: colorlight_i9) [Pipeline] { (Branch: digilent_nexys4_ddr) [Pipeline] stage [Pipeline] { (colorlight_i9) [Pipeline] stage [Pipeline] { (digilent_nexys4_ddr) [Pipeline] lock Trying to acquire lock on [Resource: colorlight_i9] Resource [colorlight_i9] did not exist. Created. Lock acquired on [Resource: colorlight_i9] [Pipeline] { [Pipeline] lock Trying to acquire lock on [Resource: digilent_nexys4_ddr] Resource [digilent_nexys4_ddr] did not exist. Created. Lock acquired on [Resource: digilent_nexys4_ddr] [Pipeline] { [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] dir Running in /var/jenkins_home/workspace/tinyriscv/tinyriscv [Pipeline] { [Pipeline] dir Running in /var/jenkins_home/workspace/tinyriscv/tinyriscv [Pipeline] { [Pipeline] echo Starting synthesis for FPGA colorlight_i9. [Pipeline] sh [Pipeline] echo Starting synthesis for FPGA digilent_nexys4_ddr. + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p tinyriscv -b colorlight_i9 [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p tinyriscv -b digilent_nexys4_ddr Final configuration file generated at /var/jenkins_home/workspace/tinyriscv/tinyriscv/build_digilent_nexys4_ddr.tcl Error executing Makefile. ERROR: [Common 17-55] 'set_property' expects at least one object. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. make: *** [/eda/processor_ci/makefiles/digilent_nexys4_ddr.mk:12: digilent_nexys4_ddr.bit] Error 1 Traceback (most recent call last): File "/eda/processor_ci/main.py", line 135, in <module> main( File "/eda/processor_ci/main.py", line 82, in main build(build_file_path, board_name, toolchain_path) File "/eda/processor_ci/core/fpga.py", line 215, in build raise subprocess.CalledProcessError(process.returncode, 'make') subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2. [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash digilent_nexys4_ddr) Stage "Flash digilent_nexys4_ddr" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test digilent_nexys4_ddr) Stage "Test digilent_nexys4_ddr" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: digilent_nexys4_ddr] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } Failed in branch digilent_nexys4_ddr Final configuration file generated at /var/jenkins_home/workspace/tinyriscv/tinyriscv/build_colorlight_i9.tcl Makefile executed successfully. Makefile output: /eda/oss-cad-suite/bin/yosys -c /var/jenkins_home/workspace/tinyriscv/tinyriscv/build_colorlight_i9.tcl -DID=0x6a6a6a6a -DCLOCK_FREQ=25000000 -DMEMORY_SIZE=4096 /----------------------------------------------------------------------------\ | yosys -- Yosys Open SYnthesis Suite | | Copyright (C) 2012 - 2024 Claire Xenia Wolf <claire@yosyshq.com> | | Distributed under an ISC-like license, type "license" to see terms | \----------------------------------------------------------------------------/ Yosys 0.45+139 (git sha1 4d581a97d, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3) -- Running command `read -define ID=0x6a6a6a6a CLOCK_FREQ=25000000 MEMORY_SIZE=4096' -- 1. Executing Verilog-2005 frontend: /eda/processor_ci/rtl/tinyriscv.v Parsing Verilog input from `/eda/processor_ci/rtl/tinyriscv.v' to AST representation. Generating RTLIL representation for module `\processorci_top'. Successfully finished Verilog frontend. 2. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v Parsing Verilog input from `/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v' to AST representation. Generating RTLIL representation for module `\clint'. Successfully finished Verilog frontend. 3. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v Parsing Verilog input from `/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v' to AST representation. Generating RTLIL representation for module `\csr_reg'. Successfully finished Verilog frontend. 4. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v Parsing Verilog input from `/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v' to AST representation. Generating RTLIL representation for module `\ctrl'. Successfully finished Verilog frontend. 5. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v Parsing Verilog input from `/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v' to AST representation. Generating RTLIL representation for module `\div'. Successfully finished Verilog frontend. 6. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v Parsing Verilog input from `/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v' to AST representation. Generating RTLIL representation for module `\ex'. Successfully finished Verilog frontend. 7. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v Parsing Verilog input from `/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v' to AST representation. Generating RTLIL representation for module `\id'. Successfully finished Verilog frontend. 8. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id_ex.v Parsing Verilog input from `/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id_ex.v' to AST representation. Generating RTLIL representation for module `\id_ex'. Successfully finished Verilog frontend. 9. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/if_id.v Parsing Verilog input from `/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/if_id.v' to AST representation. Generating RTLIL representation for module `\if_id'. Successfully finished Verilog frontend. 10. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v Parsing Verilog input from `/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v' to AST representation. Generating RTLIL representation for module `\pc_reg'. Successfully finished Verilog frontend. 11. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v Parsing Verilog input from `/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v' to AST representation. Generating RTLIL representation for module `\regs'. Successfully finished Verilog frontend. 12. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/rib.v Parsing Verilog input from `/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/rib.v' to AST representation. Generating RTLIL representation for module `\rib'. Successfully finished Verilog frontend. 13. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/tinyriscv.v Parsing Verilog input from `/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/tinyriscv.v' to AST representation. Generating RTLIL representation for module `\tinyriscv'. Successfully finished Verilog frontend. 14. Executing Verilog-2005 frontend: /var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v Parsing Verilog input from `/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v' to AST representation. Generating RTLIL representation for module `\gen_pipe_dff'. Generating RTLIL representation for module `\gen_rst_0_dff'. Generating RTLIL representation for module `\gen_rst_1_dff'. Generating RTLIL representation for module `\gen_rst_def_dff'. Generating RTLIL representation for module `\gen_en_dff'. Successfully finished Verilog frontend. 15. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/uart.v Parsing Verilog input from `/eda/processor-ci-controller/modules/uart.v' to AST representation. Generating RTLIL representation for module `\UART'. Successfully finished Verilog frontend. 16. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v' to AST representation. Generating RTLIL representation for module `\uart_rx'. Successfully finished Verilog frontend. 17. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v' to AST representation. Generating RTLIL representation for module `\uart_tx'. Successfully finished Verilog frontend. 18. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/fifo.v Parsing Verilog input from `/eda/processor-ci-controller/src/fifo.v' to AST representation. Generating RTLIL representation for module `\FIFO'. Successfully finished Verilog frontend. 19. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/reset.v Parsing Verilog input from `/eda/processor-ci-controller/src/reset.v' to AST representation. Generating RTLIL representation for module `\ResetBootSystem'. Successfully finished Verilog frontend. 20. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/clk_divider.v Parsing Verilog input from `/eda/processor-ci-controller/src/clk_divider.v' to AST representation. Generating RTLIL representation for module `\ClkDivider'. Successfully finished Verilog frontend. 21. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/memory.v Parsing Verilog input from `/eda/processor-ci-controller/src/memory.v' to AST representation. Generating RTLIL representation for module `\Memory'. Successfully finished Verilog frontend. 22. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/interpreter.v Parsing Verilog input from `/eda/processor-ci-controller/src/interpreter.v' to AST representation. Generating RTLIL representation for module `\Interpreter'. Successfully finished Verilog frontend. 23. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/controller.v Parsing Verilog input from `/eda/processor-ci-controller/src/controller.v' to AST representation. Generating RTLIL representation for module `\Controller'. Successfully finished Verilog frontend. 24. Executing SYNTH_ECP5 pass. 24.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation. Generating RTLIL representation for module `\LUT4'. Generating RTLIL representation for module `\$__ABC9_LUT5'. Generating RTLIL representation for module `\$__ABC9_LUT6'. Generating RTLIL representation for module `\$__ABC9_LUT7'. Generating RTLIL representation for module `\L6MUX21'. Generating RTLIL representation for module `\CCU2C'. Generating RTLIL representation for module `\TRELLIS_RAM16X2'. Generating RTLIL representation for module `\PFUMX'. Generating RTLIL representation for module `\TRELLIS_DPR16X4'. Generating RTLIL representation for module `\DPR16X4C'. Generating RTLIL representation for module `\LUT2'. Generating RTLIL representation for module `\TRELLIS_FF'. Generating RTLIL representation for module `\TRELLIS_IO'. Generating RTLIL representation for module `\INV'. Generating RTLIL representation for module `\TRELLIS_COMB'. Generating RTLIL representation for module `\DP16KD'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 24.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation. Generating RTLIL representation for module `\MULT18X18D'. Generating RTLIL representation for module `\ALU54B'. Generating RTLIL representation for module `\EHXPLLL'. Generating RTLIL representation for module `\DTR'. Generating RTLIL representation for module `\OSCG'. Generating RTLIL representation for module `\USRMCLK'. Generating RTLIL representation for module `\JTAGG'. Generating RTLIL representation for module `\DELAYF'. Generating RTLIL representation for module `\DELAYG'. Generating RTLIL representation for module `\IDDRX1F'. Generating RTLIL representation for module `\IDDRX2F'. Generating RTLIL representation for module `\IDDR71B'. Generating RTLIL representation for module `\IDDRX2DQA'. Generating RTLIL representation for module `\ODDRX1F'. Generating RTLIL representation for module `\ODDRX2F'. Generating RTLIL representation for module `\ODDR71B'. Generating RTLIL representation for module `\OSHX2A'. Generating RTLIL representation for module `\ODDRX2DQA'. Generating RTLIL representation for module `\ODDRX2DQSB'. Generating RTLIL representation for module `\TSHX2DQA'. Generating RTLIL representation for module `\TSHX2DQSA'. Generating RTLIL representation for module `\DQSBUFM'. Generating RTLIL representation for module `\DDRDLLA'. Generating RTLIL representation for module `\DLLDELD'. Generating RTLIL representation for module `\CLKDIVF'. Generating RTLIL representation for module `\ECLKSYNCB'. Generating RTLIL representation for module `\ECLKBRIDGECS'. Generating RTLIL representation for module `\DCCA'. Generating RTLIL representation for module `\DCSC'. Generating RTLIL representation for module `\DCUA'. Generating RTLIL representation for module `\EXTREFB'. Generating RTLIL representation for module `\PCSCLKDIV'. Generating RTLIL representation for module `\PUR'. Generating RTLIL representation for module `\GSR'. Generating RTLIL representation for module `\SGSR'. Generating RTLIL representation for module `\PDPW16KD'. Successfully finished Verilog frontend. 24.3. Executing HIERARCHY pass (managing design hierarchy). 24.3.1. Analyzing design hierarchy.. Top module: \processorci_top Used module: \ResetBootSystem Used module: \tinyriscv Used module: \clint Used module: \div Used module: \ex Used module: \id_ex Used module: \gen_pipe_dff Used module: \id Used module: \if_id Used module: \csr_reg Used module: \regs Used module: \ctrl Used module: \pc_reg Used module: \Controller Used module: \Memory Used module: \UART Used module: \uart_tx Used module: \uart_rx Used module: \FIFO Used module: \Interpreter Used module: \ClkDivider Parameter \CYCLES = 20 24.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'. Parameter \CYCLES = 20 Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \WORD_SIZE_BY = 4 Parameter \ID = 0 Parameter \RESET_CLK_CYCLES = 20 Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 24.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Controller'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \WORD_SIZE_BY = 4 Parameter \ID = 0 Parameter \RESET_CLK_CYCLES = 20 Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Generating RTLIL representation for module `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 24.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 24.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 9600 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 Generating RTLIL representation for module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'. Parameter \CLK_FREQ = 25000000 Parameter \PULSE_CONTROL_BITS = 12 Parameter \BUS_WIDTH = 32 Parameter \ID = 1 Parameter \RESET_CLK_CYCLES = 20 24.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'. Parameter \CLK_FREQ = 25000000 Parameter \PULSE_CONTROL_BITS = 12 Parameter \BUS_WIDTH = 32 Parameter \ID = 1 Parameter \RESET_CLK_CYCLES = 20 Generating RTLIL representation for module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 12 24.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 12 Generating RTLIL representation for module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'. Parameter 1 (\DW) = 32 24.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\gen_pipe_dff'. Parameter 1 (\DW) = 32 Generating RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'. Parameter 1 (\DW) = 32 Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'. Parameter 1 (\DW) = 32 Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'. Parameter 1 (\DW) = 32 Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'. Parameter 1 (\DW) = 32 Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'. Parameter 1 (\DW) = 32 Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'. Parameter 1 (\DW) = 1 24.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\gen_pipe_dff'. Parameter 1 (\DW) = 1 Generating RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001'. Parameter 1 (\DW) = 32 Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'. Parameter 1 (\DW) = 32 Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'. Parameter 1 (\DW) = 5 24.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\gen_pipe_dff'. Parameter 1 (\DW) = 5 Generating RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101'. Parameter 1 (\DW) = 1 Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001'. Parameter 1 (\DW) = 32 Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'. Parameter 1 (\DW) = 32 Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'. Parameter 1 (\DW) = 8 24.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\gen_pipe_dff'. Parameter 1 (\DW) = 8 Generating RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000'. Parameter 1 (\DW) = 32 Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'. Parameter 1 (\DW) = 32 Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 24.3.12. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 24.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. Parameter \BIT_RATE = 9600 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 24.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. 24.3.15. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: \tinyriscv Used module: \clint Used module: \div Used module: \ex Used module: \id_ex Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000 Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001 Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101 Used module: \id Used module: \if_id Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000 Used module: \csr_reg Used module: \regs Used module: \ctrl Used module: \pc_reg Used module: $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller Used module: \Memory Used module: \UART Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx Used module: $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: \Interpreter Used module: \ClkDivider Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \MEMORY_FILE = { } Parameter \MEMORY_SIZE = 4096 Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 24.3.16. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'. Parameter \CLK_FREQ = 25000000 Parameter \BIT_RATE = 115200 Parameter \PAYLOAD_BITS = 8 Parameter \BUFFER_SIZE = 8 Parameter \WORD_SIZE_BY = 4 Generating RTLIL representation for module `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART'. Parameter \CLK_FREQ = 25000000 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \ID = 0 Parameter \RESET_CLK_CYCLES = 20 24.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'. Parameter \CLK_FREQ = 25000000 Parameter \PULSE_CONTROL_BITS = 32 Parameter \BUS_WIDTH = 32 Parameter \ID = 0 Parameter \RESET_CLK_CYCLES = 20 Generating RTLIL representation for module `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 32 24.3.18. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'. Parameter \COUNTER_BITS = 32 Parameter \PULSE_CONTROL_BITS = 32 Generating RTLIL representation for module `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider'. 24.3.19. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: \tinyriscv Used module: \clint Used module: \div Used module: \ex Used module: \id_ex Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000 Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001 Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101 Used module: \id Used module: \if_id Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000 Used module: \csr_reg Used module: \regs Used module: \ctrl Used module: \pc_reg Used module: $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller Used module: $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory Used module: $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART Used module: \uart_tx Used module: \uart_rx Used module: \FIFO Used module: $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter Used module: $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 24.3.20. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 24.3.21. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'. Parameter \BIT_RATE = 115200 Parameter \CLK_HZ = 25000000 Parameter \PAYLOAD_BITS = 8 Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. Parameter \DEPTH = 8 Parameter \WIDTH = 8 Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'. 24.3.22. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: \tinyriscv Used module: \clint Used module: \div Used module: \ex Used module: \id_ex Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000 Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001 Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101 Used module: \id Used module: \if_id Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000 Used module: \csr_reg Used module: \regs Used module: \ctrl Used module: \pc_reg Used module: $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller Used module: $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory Used module: $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter Used module: $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider 24.3.23. Analyzing design hierarchy.. Top module: \processorci_top Used module: $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100 Used module: \tinyriscv Used module: \clint Used module: \div Used module: \ex Used module: \id_ex Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000 Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001 Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101 Used module: \id Used module: \if_id Used module: $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000 Used module: \csr_reg Used module: \regs Used module: \ctrl Used module: \pc_reg Used module: $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller Used module: $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory Used module: $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx Used module: $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx Used module: $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO Used module: $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter Used module: $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'. Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'. Removing unused module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'. Removing unused module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'. Removing unused module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'. Removing unused module `\Controller'. Removing unused module `\Interpreter'. Removing unused module `\Memory'. Removing unused module `\ClkDivider'. Removing unused module `\ResetBootSystem'. Removing unused module `\FIFO'. Removing unused module `\uart_tx'. Removing unused module `\uart_rx'. Removing unused module `\UART'. Removing unused module `\gen_en_dff'. Removing unused module `\gen_rst_def_dff'. Removing unused module `\gen_rst_1_dff'. Removing unused module `\gen_rst_0_dff'. Removing unused module `\gen_pipe_dff'. Removing unused module `\rib'. Removed 20 unused modules. Mapping positional arguments of cell if_id.int_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000). Mapping positional arguments of cell if_id.inst_addr_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000). Mapping positional arguments of cell if_id.inst_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000). Mapping positional arguments of cell id_ex.op2_jump_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000). Mapping positional arguments of cell id_ex.op1_jump_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000). Mapping positional arguments of cell id_ex.op2_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000). Mapping positional arguments of cell id_ex.op1_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000). Mapping positional arguments of cell id_ex.csr_rdata_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000). Mapping positional arguments of cell id_ex.csr_waddr_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000). Mapping positional arguments of cell id_ex.csr_we_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001). Mapping positional arguments of cell id_ex.reg2_rdata_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000). Mapping positional arguments of cell id_ex.reg1_rdata_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000). Mapping positional arguments of cell id_ex.reg_waddr_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101). Mapping positional arguments of cell id_ex.reg_we_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001). Mapping positional arguments of cell id_ex.inst_addr_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000). Mapping positional arguments of cell id_ex.inst_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000). 24.4. Executing PROC pass (convert processes to netlists). 24.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$681'. Found and cleaned up 1 empty switch in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$863'. Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$863'. Cleaned up 2 empty switches. 24.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$788 in module TRELLIS_FF. Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$740 in module DPR16X4C. Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$682 in module TRELLIS_DPR16X4. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:36$1055 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:25$1047 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1248 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1246 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1238 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1235 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1229 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1224 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1219 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1210 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1197 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1195 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1187 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1173 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1167 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1162 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$948 in module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$945 in module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$942 in module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$939 in module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:57$1149 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:36$1140 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. Marked 15 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/interpreter.v:116$1104 in module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter. Removed 1 dead cases from process $proc$/eda/processor-ci-controller/modules/uart.v:203$1096 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:203$1096 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:187$1091 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:132$1086 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:74$1081 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/memory.v:36$852 in module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory. Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/controller.v:113$841 in module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller. Marked 5 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/reset.v:25$791 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:91$265 in module regs. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:79$259 in module regs. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:67$253 in module regs. Marked 3 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$224 in module regs. Marked 3 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:35$215 in module pc_reg. Removed 3 dead cases from process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$208 in module id. Marked 10 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$208 in module id. Removed 2 dead cases from process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$145 in module ex. Marked 21 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$145 in module ex. Marked 4 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$139 in module ex. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:172$129 in module ex. Marked 15 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$67 in module div. Marked 3 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v:48$49 in module ctrl. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:179$45 in module csr_reg. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:141$41 in module csr_reg. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$37 in module csr_reg. Marked 1 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:66$34 in module csr_reg. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:218$30 in module clint. Marked 2 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:177$28 in module clint. Marked 8 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:111$18 in module clint. Marked 5 switch rules as full_case in process $proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:89$8 in module clint. Removed a total of 6 dead cases. 24.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 15 redundant assignments. Promoted 140 assignments to connections. 24.4.4. Executing PROC_INIT pass (extract init attributes). Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$789'. Set init value: \Q = 1'0 Found init rule in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1080'. Set init value: \read_ptr = 6'000000 Set init value: \write_ptr = 6'000000 Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1250'. Set init value: \i = 0 Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1203'. Set init value: \i = 0 Found init rule in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1155'. Set init value: \clk_o_auto = 1'0 Set init value: \clk_counter = 0 Set init value: \pulse_counter = 0 Found init rule in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1133'. Set init value: \state = 8'00000000 Set init value: \counter = 8'00000000 Set init value: \read_buffer = 0 Set init value: \timeout = 0 Set init value: \accumulator = 64'0000000000000000000000000000000000000000000000000000000000000000 Found init rule in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1103'. Set init value: \read_response = 1'0 Set init value: \write_response = 1'0 Set init value: \read_data = 0 Set init value: \uart_tx_en = 1'0 Set init value: \tx_fifo_read = 1'0 Set init value: \tx_fifo_write = 1'0 Set init value: \rx_fifo_read = 1'0 Set init value: \rx_fifo_write = 1'0 Set init value: \uart_tx_data = 8'00000000 Set init value: \tx_fifo_write_data = 8'00000000 Set init value: \rx_fifo_write_data = 8'00000000 Set init value: \counter_write = 3'000 Set init value: \counter_read = 3'000 Set init value: \state_read = 4'0000 Set init value: \state_write = 4'0000 Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$798'. Set init value: \reset_o = 1'0 Set init value: \state = 2'01 Set init value: \counter = 6'000000 24.4.5. Executing PROC_ARST pass (detect async resets in processes). 24.4.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~193 debug messages> 24.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$789'. Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$788'. 1/1: $0\Q[0:0] Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$763'. Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$740'. 1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$739_EN[3:0]$746 2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$739_DATA[3:0]$745 3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$739_ADDR[3:0]$744 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$706'. Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$682'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$680_EN[3:0]$688 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$680_DATA[3:0]$687 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$680_ADDR[3:0]$686 Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$681'. Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1080'. Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1055'. 1/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1067 2/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_DATA[7:0]$1066 3/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_ADDR[5:0]$1065 4/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1061 5/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_DATA[7:0]$1060 6/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_ADDR[5:0]$1059 7/7: $0\write_ptr[5:0] Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1047'. 1/2: $0\read_ptr[5:0] 2/2: $0\read_data[7:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1250'. Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1248'. 1/2: $0\rxd_reg_0[0:0] 2/2: $0\rxd_reg[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1246'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1238'. 1/1: $0\cycle_counter[8:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1235'. 1/1: $0\bit_sample[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1229'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1224'. 1/11: $3\i[31:0] 2/11: $0\recieved_data[7:0] [1] 3/11: $0\recieved_data[7:0] [0] 4/11: $0\recieved_data[7:0] [2] 5/11: $0\recieved_data[7:0] [3] 6/11: $0\recieved_data[7:0] [4] 7/11: $0\recieved_data[7:0] [5] 8/11: $0\recieved_data[7:0] [6] 9/11: $0\recieved_data[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1219'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1210'. 1/1: $0\uart_rx_data[7:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1203'. Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1197'. 1/1: $0\txd_reg[0:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1195'. 1/1: $0\fsm_state[2:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1187'. 1/1: $0\cycle_counter[8:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1173'. 1/1: $0\bit_counter[3:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1167'. 1/11: $3\i[31:0] 2/11: $0\data_to_send[7:0] [1] 3/11: $0\data_to_send[7:0] [0] 4/11: $0\data_to_send[7:0] [2] 5/11: $0\data_to_send[7:0] [3] 6/11: $0\data_to_send[7:0] [4] 7/11: $0\data_to_send[7:0] [5] 8/11: $0\data_to_send[7:0] [6] 9/11: $0\data_to_send[7:0] [7] 10/11: $1\i[31:0] 11/11: $2\i[31:0] Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1162'. 1/1: $1\n_fsm_state[2:0] Creating decoders for process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$948'. 1/1: $0\qout_r[7:0] Creating decoders for process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$945'. 1/1: $0\qout_r[4:0] Creating decoders for process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$942'. 1/1: $0\qout_r[0:0] Creating decoders for process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$939'. 1/1: $0\qout_r[31:0] Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1155'. Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1149'. 1/1: $0\pulse_counter[31:0] Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1140'. 1/2: $0\clk_counter[31:0] 2/2: $0\clk_o_auto[0:0] Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1133'. Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. 1/28: $0\state[7:0] 2/28: $0\reset_bus[0:0] 3/28: $0\memory_write[0:0] 4/28: $0\memory_read[0:0] 5/28: $0\write_pulse[0:0] 6/28: $0\core_reset[0:0] 7/28: $0\communication_write[0:0] 8/28: $0\communication_read[0:0] 9/28: $0\temp_buffer[63:0] 10/28: $0\accumulator[63:0] 11/28: $0\timeout_counter[31:0] 12/28: $0\timeout[31:0] 13/28: $0\read_buffer[31:0] 14/28: $0\communication_buffer[31:0] 15/28: $0\num_of_positions[23:0] 16/28: $0\num_of_pages[23:0] 17/28: $0\return_state[7:0] 18/28: $0\memory_page_number[23:0] 19/28: $0\memory_mux_selector[0:0] 20/28: $0\end_position[31:0] 21/28: $0\memory_page_size[23:0] 22/28: $0\bus_mode[0:0] 23/28: $0\num_of_cycles_to_pulse[31:0] 24/28: $0\core_clk_enable[0:0] 25/28: $0\communication_write_data[31:0] 26/28: $0\counter[7:0] 27/28: $0\write_data[31:0] 28/28: $0\address[31:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1103'. Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1096'. 1/4: $0\tx_fifo_read[0:0] 2/4: $0\uart_tx_en[0:0] 3/4: $0\tx_fifo_read_state[1:0] 4/4: $0\uart_tx_data[7:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1091'. 1/2: $0\rx_fifo_write[0:0] 2/2: $0\rx_fifo_write_data[7:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1086'. 1/6: $0\tx_fifo_write[0:0] 2/6: $0\write_response[0:0] 3/6: $0\state_write[3:0] 4/6: $0\counter_write[2:0] 5/6: $0\write_data_buffer[31:0] 6/6: $0\tx_fifo_write_data[7:0] Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1081'. 1/5: $0\read_response[0:0] 2/5: $0\rx_fifo_read[0:0] 3/5: $0\state_read[3:0] 4/5: $0\counter_read[2:0] 5/5: $0\read_data[31:0] Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$862'. Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$852'. 1/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$861 2/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_DATA[31:0]$860 3/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_ADDR[31:0]$859 4/4: $0\read_sync[31:0] Creating decoders for process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$841'. 1/1: $0\finish_execution[0:0] Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$798'. Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$791'. 1/3: $0\counter[5:0] 2/3: $0\state[1:0] 3/3: $0\reset_o[0:0] Creating decoders for process `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:91$265'. 1/1: $1\jtag_data_o[31:0] Creating decoders for process `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:79$259'. 1/2: $2\rdata2_o[31:0] 2/2: $1\rdata2_o[31:0] Creating decoders for process `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:67$253'. 1/2: $2\rdata1_o[31:0] 2/2: $1\rdata1_o[31:0] Creating decoders for process `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$224'. 1/15: $3$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$223_EN[31:0]$252 2/15: $3$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$223_DATA[31:0]$251 3/15: $3$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$223_ADDR[4:0]$250 4/15: $2$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$243 5/15: $2$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_DATA[31:0]$242 6/15: $2$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_ADDR[4:0]$241 7/15: $2$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$223_EN[31:0]$246 8/15: $2$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$223_DATA[31:0]$245 9/15: $2$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$223_ADDR[4:0]$244 10/15: $1$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$223_EN[31:0]$237 11/15: $1$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$223_DATA[31:0]$236 12/15: $1$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$223_ADDR[4:0]$235 13/15: $1$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$234 14/15: $1$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_DATA[31:0]$233 15/15: $1$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_ADDR[4:0]$232 Creating decoders for process `\pc_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:35$215'. 1/1: $0\pc_o[31:0] Creating decoders for process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$208'. 1/72: $2\csr_we_o[0:0] 2/72: $10\reg_waddr_o[4:0] 3/72: $10\reg_we_o[0:0] 4/72: $10\reg2_raddr_o[4:0] 5/72: $10\reg1_raddr_o[4:0] 6/72: $5\op2_jump_o[31:0] 7/72: $5\op1_jump_o[31:0] 8/72: $9\op2_o[31:0] 9/72: $9\op1_o[31:0] 10/72: $9\reg_waddr_o[4:0] 11/72: $9\reg_we_o[0:0] 12/72: $9\reg2_raddr_o[4:0] 13/72: $9\reg1_raddr_o[4:0] 14/72: $8\op2_o[31:0] 15/72: $8\op1_o[31:0] 16/72: $8\reg_waddr_o[4:0] 17/72: $8\reg_we_o[0:0] 18/72: $8\reg2_raddr_o[4:0] 19/72: $8\reg1_raddr_o[4:0] 20/72: $7\op2_o[31:0] 21/72: $7\op1_o[31:0] 22/72: $7\reg_waddr_o[4:0] 23/72: $7\reg_we_o[0:0] 24/72: $7\reg2_raddr_o[4:0] 25/72: $7\reg1_raddr_o[4:0] 26/72: $6\op2_o[31:0] 27/72: $6\op1_o[31:0] 28/72: $6\reg2_raddr_o[4:0] 29/72: $6\reg1_raddr_o[4:0] 30/72: $6\reg_waddr_o[4:0] 31/72: $6\reg_we_o[0:0] 32/72: $4\op2_jump_o[31:0] 33/72: $4\op1_jump_o[31:0] 34/72: $3\op2_jump_o[31:0] 35/72: $3\op1_jump_o[31:0] 36/72: $5\op2_o[31:0] 37/72: $5\op1_o[31:0] 38/72: $5\reg2_raddr_o[4:0] 39/72: $5\reg1_raddr_o[4:0] 40/72: $5\reg_we_o[0:0] 41/72: $5\reg_waddr_o[4:0] 42/72: $4\op2_o[31:0] 43/72: $4\op1_o[31:0] 44/72: $4\reg2_raddr_o[4:0] 45/72: $4\reg1_raddr_o[4:0] 46/72: $4\reg_waddr_o[4:0] 47/72: $4\reg_we_o[0:0] 48/72: $3\op2_o[31:0] 49/72: $3\op1_o[31:0] 50/72: $3\reg2_raddr_o[4:0] 51/72: $3\reg1_raddr_o[4:0] 52/72: $3\reg_we_o[0:0] 53/72: $3\reg_waddr_o[4:0] 54/72: $2\op2_jump_o[31:0] 55/72: $2\op1_jump_o[31:0] 56/72: $2\op2_o[31:0] 57/72: $2\op1_o[31:0] 58/72: $2\reg2_raddr_o[4:0] 59/72: $2\reg1_raddr_o[4:0] 60/72: $2\reg_waddr_o[4:0] 61/72: $2\reg_we_o[0:0] 62/72: $1\op2_o[31:0] 63/72: $1\op1_o[31:0] 64/72: $1\reg2_raddr_o[4:0] 65/72: $1\reg1_raddr_o[4:0] 66/72: $1\reg_we_o[0:0] 67/72: $1\reg_waddr_o[4:0] 68/72: $1\op2_jump_o[31:0] 69/72: $1\op1_jump_o[31:0] 70/72: $1\csr_raddr_o[31:0] 71/72: $1\csr_waddr_o[31:0] 72/72: $1\csr_we_o[0:0] Creating decoders for process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$145'. 1/96: $19\reg_wdata[31:0] 2/96: $2\csr_wdata_o[31:0] 3/96: $10\mem_we[0:0] 4/96: $10\jump_addr[31:0] 5/96: $10\jump_flag[0:0] 6/96: $10\hold_flag[0:0] 7/96: $10\mem_waddr_o[31:0] 8/96: $10\mem_raddr_o[31:0] 9/96: $12\mem_wdata_o[31:0] 10/96: $9\jump_addr[31:0] 11/96: $9\jump_flag[0:0] 12/96: $18\reg_wdata[31:0] 13/96: $9\mem_we[0:0] 14/96: $9\mem_waddr_o[31:0] 15/96: $9\mem_raddr_o[31:0] 16/96: $11\mem_wdata_o[31:0] 17/96: $9\hold_flag[0:0] 18/96: $10\mem_wdata_o[31:0] 19/96: $9\mem_wdata_o[31:0] 20/96: $8\mem_wdata_o[31:0] 21/96: $8\mem_raddr_o[31:0] 22/96: $8\mem_waddr_o[31:0] 23/96: $3\mem_req[0:0] 24/96: $8\mem_we[0:0] 25/96: $17\reg_wdata[31:0] 26/96: $8\jump_addr[31:0] 27/96: $8\hold_flag[0:0] 28/96: $8\jump_flag[0:0] 29/96: $16\reg_wdata[31:0] 30/96: $15\reg_wdata[31:0] 31/96: $14\reg_wdata[31:0] 32/96: $13\reg_wdata[31:0] 33/96: $12\reg_wdata[31:0] 34/96: $7\mem_raddr_o[31:0] 35/96: $2\mem_req[0:0] 36/96: $7\mem_we[0:0] 37/96: $7\mem_waddr_o[31:0] 38/96: $7\mem_wdata_o[31:0] 39/96: $7\jump_addr[31:0] 40/96: $7\hold_flag[0:0] 41/96: $7\jump_flag[0:0] 42/96: $11\reg_wdata[31:0] 43/96: $10\reg_wdata[31:0] 44/96: $9\reg_wdata[31:0] 45/96: $6\mem_we[0:0] 46/96: $6\mem_waddr_o[31:0] 47/96: $6\mem_raddr_o[31:0] 48/96: $6\mem_wdata_o[31:0] 49/96: $6\jump_addr[31:0] 50/96: $6\hold_flag[0:0] 51/96: $6\jump_flag[0:0] 52/96: $5\mem_we[0:0] 53/96: $5\jump_addr[31:0] 54/96: $5\jump_flag[0:0] 55/96: $5\hold_flag[0:0] 56/96: $8\reg_wdata[31:0] 57/96: $5\mem_waddr_o[31:0] 58/96: $5\mem_raddr_o[31:0] 59/96: $5\mem_wdata_o[31:0] 60/96: $7\reg_wdata[31:0] 61/96: $6\reg_wdata[31:0] 62/96: $5\reg_wdata[31:0] 63/96: $4\mem_we[0:0] 64/96: $4\mem_waddr_o[31:0] 65/96: $4\mem_raddr_o[31:0] 66/96: $4\mem_wdata_o[31:0] 67/96: $4\jump_addr[31:0] 68/96: $4\hold_flag[0:0] 69/96: $4\jump_flag[0:0] 70/96: $3\mem_we[0:0] 71/96: $3\jump_addr[31:0] 72/96: $3\jump_flag[0:0] 73/96: $3\hold_flag[0:0] 74/96: $4\reg_wdata[31:0] 75/96: $3\mem_waddr_o[31:0] 76/96: $3\mem_raddr_o[31:0] 77/96: $3\mem_wdata_o[31:0] 78/96: $3\reg_wdata[31:0] 79/96: $2\reg_wdata[31:0] 80/96: $2\mem_we[0:0] 81/96: $2\mem_waddr_o[31:0] 82/96: $2\mem_raddr_o[31:0] 83/96: $2\mem_wdata_o[31:0] 84/96: $2\jump_addr[31:0] 85/96: $2\hold_flag[0:0] 86/96: $2\jump_flag[0:0] 87/96: $1\mem_we[0:0] 88/96: $1\jump_addr[31:0] 89/96: $1\jump_flag[0:0] 90/96: $1\hold_flag[0:0] 91/96: $1\reg_wdata[31:0] 92/96: $1\mem_waddr_o[31:0] 93/96: $1\mem_raddr_o[31:0] 94/96: $1\mem_wdata_o[31:0] 95/96: $1\mem_req[0:0] 96/96: $1\csr_wdata_o[31:0] Creating decoders for process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$139'. 1/19: $3\div_we[0:0] 2/19: $3\div_waddr[4:0] 3/19: $3\div_wdata[31:0] 4/19: $3\div_hold_flag[0:0] 5/19: $2\div_waddr[4:0] 6/19: $2\div_wdata[31:0] 7/19: $2\div_we[0:0] 8/19: $3\div_start[0:0] 9/19: $2\div_jump_addr[31:0] 10/19: $2\div_hold_flag[0:0] 11/19: $2\div_jump_flag[0:0] 12/19: $2\div_start[0:0] 13/19: $1\div_start[0:0] 14/19: $1\div_jump_addr[31:0] 15/19: $1\div_jump_flag[0:0] 16/19: $1\div_hold_flag[0:0] 17/19: $1\div_waddr[4:0] 18/19: $1\div_wdata[31:0] 19/19: $1\div_we[0:0] Creating decoders for process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:172$129'. 1/4: $2\mul_op2[31:0] 2/4: $2\mul_op1[31:0] 3/4: $1\mul_op2[31:0] 4/4: $1\mul_op1[31:0] Creating decoders for process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$67'. 1/13: $0\invert_result[0:0] 2/13: $0\minuend[31:0] 3/13: $0\div_remain[31:0] 4/13: $0\div_result[31:0] 5/13: $0\count[31:0] 6/13: $0\state[3:0] 7/13: $0\op_r[2:0] 8/13: $0\divisor_r[31:0] 9/13: $0\dividend_r[31:0] 10/13: $0\reg_waddr_o[4:0] 11/13: $0\busy_o[0:0] 12/13: $0\ready_o[0:0] 13/13: $0\result_o[31:0] Creating decoders for process `\ctrl.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v:48$49'. 1/3: $3\hold_flag_o[2:0] 2/3: $2\hold_flag_o[2:0] 3/3: $1\hold_flag_o[2:0] Creating decoders for process `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:179$45'. 1/2: $2\clint_data_o[31:0] 2/2: $1\clint_data_o[31:0] Creating decoders for process `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:141$41'. 1/2: $2\data_o[31:0] 2/2: $1\data_o[31:0] Creating decoders for process `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$37'. 1/6: $0\mscratch[31:0] 2/6: $0\mstatus[31:0] 3/6: $0\mie[31:0] 4/6: $0\mepc[31:0] 5/6: $0\mcause[31:0] 6/6: $0\mtvec[31:0] Creating decoders for process `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:66$34'. 1/1: $0\cycle[63:0] Creating decoders for process `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:218$30'. 1/2: $0\int_addr_o[31:0] 2/2: $0\int_assert_o[0:0] Creating decoders for process `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:177$28'. 1/3: $0\data_o[31:0] 2/3: $0\waddr_o[31:0] 3/3: $0\we_o[0:0] Creating decoders for process `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:111$18'. 1/3: $0\cause[31:0] 2/3: $0\inst_addr[31:0] 3/3: $0\csr_state[4:0] Creating decoders for process `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:89$8'. 1/5: $5\int_state[3:0] 2/5: $4\int_state[3:0] 3/5: $3\int_state[3:0] 4/5: $2\int_state[3:0] 5/5: $1\int_state[3:0] 24.4.8. Executing PROC_DLATCH pass (convert process syncs to latches). No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1219'. No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1162'. No latch inferred for signal `\regs.\jtag_data_o' from process `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:91$265'. No latch inferred for signal `\regs.\rdata2_o' from process `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:79$259'. No latch inferred for signal `\regs.\rdata1_o' from process `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:67$253'. No latch inferred for signal `\id.\reg_waddr_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$208'. No latch inferred for signal `\id.\reg_we_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$208'. No latch inferred for signal `\id.\csr_we_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$208'. No latch inferred for signal `\id.\csr_waddr_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$208'. No latch inferred for signal `\id.\reg1_raddr_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$208'. No latch inferred for signal `\id.\reg2_raddr_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$208'. No latch inferred for signal `\id.\csr_raddr_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$208'. No latch inferred for signal `\id.\op1_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$208'. No latch inferred for signal `\id.\op2_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$208'. No latch inferred for signal `\id.\op1_jump_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$208'. No latch inferred for signal `\id.\op2_jump_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$208'. No latch inferred for signal `\id.\inst_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$208'. No latch inferred for signal `\id.\inst_addr_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$208'. No latch inferred for signal `\id.\reg1_rdata_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$208'. No latch inferred for signal `\id.\reg2_rdata_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$208'. No latch inferred for signal `\id.\csr_rdata_o' from process `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$208'. No latch inferred for signal `\ex.\mem_wdata_o' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$145'. No latch inferred for signal `\ex.\mem_raddr_o' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$145'. No latch inferred for signal `\ex.\mem_waddr_o' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$145'. No latch inferred for signal `\ex.\csr_wdata_o' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$145'. No latch inferred for signal `\ex.\reg_wdata' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$145'. No latch inferred for signal `\ex.\reg_we' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$145'. No latch inferred for signal `\ex.\reg_waddr' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$145'. No latch inferred for signal `\ex.\hold_flag' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$145'. No latch inferred for signal `\ex.\jump_flag' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$145'. No latch inferred for signal `\ex.\jump_addr' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$145'. No latch inferred for signal `\ex.\mem_we' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$145'. No latch inferred for signal `\ex.\mem_req' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$145'. No latch inferred for signal `\ex.\div_dividend_o' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$139'. No latch inferred for signal `\ex.\div_divisor_o' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$139'. No latch inferred for signal `\ex.\div_op_o' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$139'. No latch inferred for signal `\ex.\div_reg_waddr_o' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$139'. No latch inferred for signal `\ex.\div_wdata' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$139'. No latch inferred for signal `\ex.\div_we' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$139'. No latch inferred for signal `\ex.\div_waddr' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$139'. No latch inferred for signal `\ex.\div_hold_flag' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$139'. No latch inferred for signal `\ex.\div_jump_flag' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$139'. No latch inferred for signal `\ex.\div_jump_addr' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$139'. No latch inferred for signal `\ex.\div_start' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$139'. No latch inferred for signal `\ex.\mul_op1' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:172$129'. No latch inferred for signal `\ex.\mul_op2' from process `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:172$129'. No latch inferred for signal `\ctrl.\hold_flag_o' from process `\ctrl.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v:48$49'. No latch inferred for signal `\ctrl.\jump_flag_o' from process `\ctrl.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v:48$49'. No latch inferred for signal `\ctrl.\jump_addr_o' from process `\ctrl.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v:48$49'. No latch inferred for signal `\csr_reg.\clint_data_o' from process `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:179$45'. No latch inferred for signal `\csr_reg.\data_o' from process `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:141$41'. No latch inferred for signal `\clint.\int_state' from process `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:89$8'. 24.4.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$788'. created $dff cell `$procdff$6023' with positive edge clock. Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$724_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$725_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$726_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$727_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$728_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$729_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$730_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$731_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$732_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$733_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$734_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$735_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$736_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$737_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$738_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$763'. created direct connection (no actual register cell created). Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$739_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$740'. created $dff cell `$procdff$6024' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$739_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$740'. created $dff cell `$procdff$6025' with positive edge clock. Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$739_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$740'. created $dff cell `$procdff$6026' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$664_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$665_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$666_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$667_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$668_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$669_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$670_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$671_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$672_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$673_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$674_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$675_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$676_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$677_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$678_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$679_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$706'. created direct connection (no actual register cell created). Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$680_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$682'. created $dff cell `$procdff$6027' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$680_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$682'. created $dff cell `$procdff$6028' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$680_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$682'. created $dff cell `$procdff$6029' with positive edge clock. Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$681'. created direct connection (no actual register cell created). Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\write_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1055'. created $dff cell `$procdff$6030' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_ADDR' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1055'. created $dff cell `$procdff$6031' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_DATA' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1055'. created $dff cell `$procdff$6032' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1055'. created $dff cell `$procdff$6033' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_data' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1047'. created $dff cell `$procdff$6034' with positive edge clock. Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1047'. created $dff cell `$procdff$6035' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1248'. created $dff cell `$procdff$6036' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1248'. created $dff cell `$procdff$6037' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1246'. created $dff cell `$procdff$6038' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1238'. created $dff cell `$procdff$6039' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1235'. created $dff cell `$procdff$6040' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1229'. created $dff cell `$procdff$6041' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1224'. created $dff cell `$procdff$6042' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1224'. created $dff cell `$procdff$6043' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1210'. created $dff cell `$procdff$6044' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1197'. created $dff cell `$procdff$6045' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1195'. created $dff cell `$procdff$6046' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1187'. created $dff cell `$procdff$6047' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1173'. created $dff cell `$procdff$6048' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1167'. created $dff cell `$procdff$6049' with positive edge clock. Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1167'. created $dff cell `$procdff$6050' with positive edge clock. Creating register for signal `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000.\qout_r' using process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$948'. created $dff cell `$procdff$6051' with positive edge clock. Creating register for signal `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101.\qout_r' using process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$945'. created $dff cell `$procdff$6052' with positive edge clock. Creating register for signal `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001.\qout_r' using process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$942'. created $dff cell `$procdff$6053' with positive edge clock. Creating register for signal `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000.\qout_r' using process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$939'. created $dff cell `$procdff$6054' with positive edge clock. Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\pulse_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1149'. created $dff cell `$procdff$6055' with positive edge clock. Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_o_auto' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1140'. created $dff cell `$procdff$6056' with positive edge clock. Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1140'. created $dff cell `$procdff$6057' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\address' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6058' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6059' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6060' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6061' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6062' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6063' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6064' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6065' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6066' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6067' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_clk_enable' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6068' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_reset' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6069' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_cycles_to_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6070' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\reset_bus' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6071' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\bus_mode' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6072' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_size' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6073' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\end_position' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6074' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_mux_selector' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6075' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_number' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6076' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\return_state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6077' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_pages' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6078' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_positions' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6079' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6080' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\read_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6081' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6082' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout_counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6083' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\accumulator' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6084' with positive edge clock. Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\temp_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. created $dff cell `$procdff$6085' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_en' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1096'. created $dff cell `$procdff$6086' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1096'. created $dff cell `$procdff$6087' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1096'. created $dff cell `$procdff$6088' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read_state' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1096'. created $dff cell `$procdff$6089' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1091'. created $dff cell `$procdff$6090' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1091'. created $dff cell `$procdff$6091' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1086'. created $dff cell `$procdff$6092' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1086'. created $dff cell `$procdff$6093' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1086'. created $dff cell `$procdff$6094' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_data_buffer' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1086'. created $dff cell `$procdff$6095' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1086'. created $dff cell `$procdff$6096' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1086'. created $dff cell `$procdff$6097' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1081'. created $dff cell `$procdff$6098' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1081'. created $dff cell `$procdff$6099' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1081'. created $dff cell `$procdff$6100' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1081'. created $dff cell `$procdff$6101' with positive edge clock. Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1081'. created $dff cell `$procdff$6102' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_write_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$862'. created $dff cell `$procdff$6103' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_read_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$862'. created $dff cell `$procdff$6104' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\read_sync' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$852'. created $dff cell `$procdff$6105' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_ADDR' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$852'. created $dff cell `$procdff$6106' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_DATA' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$852'. created $dff cell `$procdff$6107' with positive edge clock. Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$852'. created $dff cell `$procdff$6108' with positive edge clock. Creating register for signal `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.\finish_execution' using process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$841'. created $dff cell `$procdff$6109' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$791'. created $dff cell `$procdff$6110' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$791'. created $dff cell `$procdff$6111' with positive edge clock. Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$791'. created $dff cell `$procdff$6112' with positive edge clock. Creating register for signal `\regs.$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_ADDR' using process `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$224'. created $dff cell `$procdff$6113' with positive edge clock. Creating register for signal `\regs.$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_DATA' using process `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$224'. created $dff cell `$procdff$6114' with positive edge clock. Creating register for signal `\regs.$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN' using process `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$224'. created $dff cell `$procdff$6115' with positive edge clock. Creating register for signal `\regs.$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$223_ADDR' using process `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$224'. created $dff cell `$procdff$6116' with positive edge clock. Creating register for signal `\regs.$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$223_DATA' using process `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$224'. created $dff cell `$procdff$6117' with positive edge clock. Creating register for signal `\regs.$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$223_EN' using process `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$224'. created $dff cell `$procdff$6118' with positive edge clock. Creating register for signal `\pc_reg.\pc_o' using process `\pc_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:35$215'. created $dff cell `$procdff$6119' with positive edge clock. Creating register for signal `\div.\result_o' using process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$67'. created $dff cell `$procdff$6120' with positive edge clock. Creating register for signal `\div.\ready_o' using process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$67'. created $dff cell `$procdff$6121' with positive edge clock. Creating register for signal `\div.\busy_o' using process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$67'. created $dff cell `$procdff$6122' with positive edge clock. Creating register for signal `\div.\reg_waddr_o' using process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$67'. created $dff cell `$procdff$6123' with positive edge clock. Creating register for signal `\div.\dividend_r' using process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$67'. created $dff cell `$procdff$6124' with positive edge clock. Creating register for signal `\div.\divisor_r' using process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$67'. created $dff cell `$procdff$6125' with positive edge clock. Creating register for signal `\div.\op_r' using process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$67'. created $dff cell `$procdff$6126' with positive edge clock. Creating register for signal `\div.\state' using process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$67'. created $dff cell `$procdff$6127' with positive edge clock. Creating register for signal `\div.\count' using process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$67'. created $dff cell `$procdff$6128' with positive edge clock. Creating register for signal `\div.\div_result' using process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$67'. created $dff cell `$procdff$6129' with positive edge clock. Creating register for signal `\div.\div_remain' using process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$67'. created $dff cell `$procdff$6130' with positive edge clock. Creating register for signal `\div.\minuend' using process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$67'. created $dff cell `$procdff$6131' with positive edge clock. Creating register for signal `\div.\invert_result' using process `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$67'. created $dff cell `$procdff$6132' with positive edge clock. Creating register for signal `\csr_reg.\mtvec' using process `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$37'. created $dff cell `$procdff$6133' with positive edge clock. Creating register for signal `\csr_reg.\mcause' using process `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$37'. created $dff cell `$procdff$6134' with positive edge clock. Creating register for signal `\csr_reg.\mepc' using process `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$37'. created $dff cell `$procdff$6135' with positive edge clock. Creating register for signal `\csr_reg.\mie' using process `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$37'. created $dff cell `$procdff$6136' with positive edge clock. Creating register for signal `\csr_reg.\mstatus' using process `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$37'. created $dff cell `$procdff$6137' with positive edge clock. Creating register for signal `\csr_reg.\mscratch' using process `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$37'. created $dff cell `$procdff$6138' with positive edge clock. Creating register for signal `\csr_reg.\cycle' using process `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:66$34'. created $dff cell `$procdff$6139' with positive edge clock. Creating register for signal `\clint.\int_addr_o' using process `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:218$30'. created $dff cell `$procdff$6140' with positive edge clock. Creating register for signal `\clint.\int_assert_o' using process `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:218$30'. created $dff cell `$procdff$6141' with positive edge clock. Creating register for signal `\clint.\we_o' using process `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:177$28'. created $dff cell `$procdff$6142' with positive edge clock. Creating register for signal `\clint.\waddr_o' using process `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:177$28'. created $dff cell `$procdff$6143' with positive edge clock. Creating register for signal `\clint.\data_o' using process `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:177$28'. created $dff cell `$procdff$6144' with positive edge clock. Creating register for signal `\clint.\csr_state' using process `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:111$18'. created $dff cell `$procdff$6145' with positive edge clock. Creating register for signal `\clint.\inst_addr' using process `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:111$18'. created $dff cell `$procdff$6146' with positive edge clock. Creating register for signal `\clint.\cause' using process `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:111$18'. created $dff cell `$procdff$6147' with positive edge clock. 24.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$789'. Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$788'. Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$788'. Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$763'. Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$740'. Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$706'. Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$682'. Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$681'. Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1080'. Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1055'. Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1055'. Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1047'. Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1047'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1250'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1248'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1248'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1246'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1246'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1238'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1238'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1235'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1235'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1229'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1229'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1224'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1224'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1219'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1219'. Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1210'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1210'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1203'. Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1197'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1197'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1195'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1195'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1187'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1187'. Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1173'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1173'. Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1167'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1167'. Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1162'. Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1162'. Found and cleaned up 1 empty switch in `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$948'. Removing empty process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$948'. Found and cleaned up 1 empty switch in `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$945'. Removing empty process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$945'. Found and cleaned up 1 empty switch in `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$942'. Removing empty process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$942'. Found and cleaned up 1 empty switch in `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$939'. Removing empty process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$939'. Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1155'. Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1149'. Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1149'. Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1140'. Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1140'. Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1133'. Found and cleaned up 15 empty switches in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1104'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1103'. Found and cleaned up 3 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1096'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1096'. Found and cleaned up 2 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1091'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1091'. Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1086'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1086'. Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1081'. Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1081'. Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$862'. Found and cleaned up 2 empty switches in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$852'. Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$852'. Found and cleaned up 4 empty switches in `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$841'. Removing empty process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$841'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$798'. Found and cleaned up 6 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$791'. Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$791'. Found and cleaned up 1 empty switch in `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:91$265'. Removing empty process `regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:91$265'. Found and cleaned up 2 empty switches in `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:79$259'. Removing empty process `regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:79$259'. Found and cleaned up 2 empty switches in `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:67$253'. Removing empty process `regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:67$253'. Found and cleaned up 3 empty switches in `\regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$224'. Removing empty process `regs.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$224'. Found and cleaned up 3 empty switches in `\pc_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:35$215'. Removing empty process `pc_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:35$215'. Found and cleaned up 10 empty switches in `\id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$208'. Removing empty process `id.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$208'. Found and cleaned up 21 empty switches in `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$145'. Removing empty process `ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$145'. Found and cleaned up 4 empty switches in `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$139'. Removing empty process `ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$139'. Found and cleaned up 2 empty switches in `\ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:172$129'. Removing empty process `ex.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:172$129'. Found and cleaned up 17 empty switches in `\div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$67'. Removing empty process `div.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$67'. Found and cleaned up 3 empty switches in `\ctrl.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v:48$49'. Removing empty process `ctrl.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v:48$49'. Found and cleaned up 2 empty switches in `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:179$45'. Removing empty process `csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:179$45'. Found and cleaned up 2 empty switches in `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:141$41'. Removing empty process `csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:141$41'. Found and cleaned up 5 empty switches in `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$37'. Removing empty process `csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$37'. Found and cleaned up 1 empty switch in `\csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:66$34'. Removing empty process `csr_reg.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:66$34'. Found and cleaned up 2 empty switches in `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:218$30'. Removing empty process `clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:218$30'. Found and cleaned up 2 empty switches in `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:177$28'. Removing empty process `clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:177$28'. Found and cleaned up 9 empty switches in `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:111$18'. Removing empty process `clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:111$18'. Found and cleaned up 5 empty switches in `\clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:89$8'. Removing empty process `clint.$proc$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:89$8'. Cleaned up 193 empty switches. 24.4.12. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. <suppressed ~5 debug messages> Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. <suppressed ~21 debug messages> Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. <suppressed ~19 debug messages> Optimizing module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000. Optimizing module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101. Optimizing module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001. Optimizing module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000. Optimizing module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. <suppressed ~9 debug messages> Optimizing module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter. <suppressed ~15 debug messages> Optimizing module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. <suppressed ~24 debug messages> Optimizing module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory. <suppressed ~3 debug messages> Optimizing module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller. <suppressed ~26 debug messages> Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. <suppressed ~8 debug messages> Optimizing module tinyriscv. <suppressed ~1 debug messages> Optimizing module regs. <suppressed ~10 debug messages> Optimizing module pc_reg. <suppressed ~3 debug messages> Optimizing module if_id. Optimizing module id_ex. Optimizing module id. <suppressed ~36 debug messages> Optimizing module ex. <suppressed ~67 debug messages> Optimizing module div. <suppressed ~23 debug messages> Optimizing module ctrl. <suppressed ~5 debug messages> Optimizing module csr_reg. <suppressed ~14 debug messages> Optimizing module clint. <suppressed ~24 debug messages> Optimizing module processorci_top. 24.5. Executing FLATTEN pass (flatten design). Deleting now unused module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO. Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx. Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx. Deleting now unused module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000. Deleting now unused module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101. Deleting now unused module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001. Deleting now unused module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000. Deleting now unused module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider. Deleting now unused module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter. Deleting now unused module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART. Deleting now unused module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory. Deleting now unused module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller. Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100. Deleting now unused module tinyriscv. Deleting now unused module regs. Deleting now unused module pc_reg. Deleting now unused module if_id. Deleting now unused module id_ex. Deleting now unused module id. Deleting now unused module ex. Deleting now unused module div. Deleting now unused module ctrl. Deleting now unused module csr_reg. Deleting now unused module clint. <suppressed ~38 debug messages> 24.6. Executing TRIBUF pass. 24.7. Executing DEMINOUT pass (demote inout ports to input or output). 24.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~72 debug messages> 24.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 115 unused cells and 1427 unused wires. <suppressed ~148 debug messages> 24.10. Executing CHECK pass (checking for obvious problems). Checking module processorci_top... Warning: Wire processorci_top.\miso is used but has no driver. Warning: Wire processorci_top.\intr is used but has no driver. Warning: Wire processorci_top.\ResetBootSystem.start is used but has no driver. Found and reported 3 problems. 24.11. Executing OPT pass (performing simple optimizations). 24.11.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 24.11.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~2979 debug messages> Removed a total of 993 cells. 24.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Replacing known input bits on port A of cell $flatten\u_tinyriscv.\u_ex.$ternary$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:185$138: \u_tinyriscv.u_id_ex.reg2_rdata_ff.qout_r -> { 1'0 \u_tinyriscv.u_id_ex.reg2_rdata_ff.qout_r [30:0] } Replacing known input bits on port A of cell $flatten\u_tinyriscv.\u_ex.$ternary$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:184$136: \u_tinyriscv.u_id_ex.reg1_rdata_ff.qout_r -> { 1'0 \u_tinyriscv.u_id_ex.reg1_rdata_ff.qout_r [30:0] } Replacing known input bits on port A of cell $flatten\u_tinyriscv.\u_ex.$ternary$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:180$134: \u_tinyriscv.u_id_ex.reg1_rdata_ff.qout_r -> { 1'0 \u_tinyriscv.u_id_ex.reg1_rdata_ff.qout_r [30:0] } Replacing known input bits on port A of cell $flatten\u_tinyriscv.\u_div.$procmux$5590: \u_tinyriscv.u_div.divisor_r -> { 1'0 \u_tinyriscv.u_div.divisor_r [30:0] } Replacing known input bits on port A of cell $flatten\u_tinyriscv.\u_div.$procmux$5617: \u_tinyriscv.u_div.dividend_r -> { 1'0 \u_tinyriscv.u_div.dividend_r [30:0] } Replacing known input bits on port A of cell $flatten\u_tinyriscv.\u_div.$procmux$5483: { 31'0000000000000000000000000000000 \u_tinyriscv.u_div.dividend_r [31] } -> 0 Analyzing evaluation results. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3776. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3787. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3797. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3807. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3817. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3827. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3837. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3847. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3857. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3873. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3889. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3904. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3919. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3934. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3949. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3964. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3979. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3993. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$3995. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4012. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4014. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4028. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4042. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4056. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4070. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4084. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4097. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4110. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4123. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4136. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4150. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4152. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4169. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4171. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4188. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4190. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4210. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4212. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4229. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4246. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4263. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4279. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4295. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4311. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4327. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4343. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4359. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4375. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4377. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4380. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4382. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4401. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4403. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4406. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4408. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4426. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4429. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4431. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4448. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4451. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4453. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4470. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4473. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4475. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4492. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4495. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4497. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4514. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4517. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4519. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4536. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4539. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4541. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4558. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4561. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4563. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4580. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4583. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4585. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4600. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4602. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4617. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4619. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4634. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4636. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4651. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4653. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4668. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4670. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4685. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4687. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4702. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4704. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4719. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4721. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4738. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4740. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4742. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4764. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4766. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4768. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4789. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4791. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4812. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4814. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4835. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4837. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4858. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4860. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4881. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4883. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4904. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4906. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4927. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4929. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4950. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4952. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4966. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4980. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$4994. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5008. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5022. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5036. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5050. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5064. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5079. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5081. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5102. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5123. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5144. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5165. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5186. dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1278. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5207. dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1284. dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1290. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5228. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5249. dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1278. dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1284. dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1290. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5338. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5341. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5347. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5350. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5356. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5359. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5365. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5371. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5377. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5383. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5389. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5395. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5401. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5407. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5413. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5440. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_ex.$procmux$5447. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2712. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2719. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2726. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2732. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2739. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2752. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2765. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2778. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2791. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2803. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2815. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2828. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2841. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2855. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2869. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2882. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2895. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2909. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2923. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2938. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2953. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2968. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2983. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$2997. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3012. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3029. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3032. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3034. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3051. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3054. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3056. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3073. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3076. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3078. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3095. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3098. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3100. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3117. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3120. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3122. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3139. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3142. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3144. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3161. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3164. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3166. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3183. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3186. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3188. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3205. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3207. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3224. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3226. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3243. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3245. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3262. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3264. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3281. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3283. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3300. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3302. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3319. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3321. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3338. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3340. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3356. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3358. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3374. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3376. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3392. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3394. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_clint.$procmux$5988. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_clint.$procmux$5991. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_clint.$procmux$5994. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3410. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3412. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_clint.$procmux$6000. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_clint.$procmux$6003. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_clint.$procmux$6009. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_clint.$procmux$6012. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_clint.$procmux$6018. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3428. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3430. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3446. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3448. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3464. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3480. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3496. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3512. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3528. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3544. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3560. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3576. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_csr_reg.$procmux$5770. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3592. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3608. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3624. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3640. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3656. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_id.$procmux$3672. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ctrl.$procmux$5732. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_ctrl.$procmux$5738. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_regs.$procmux$2603. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_regs.$procmux$2612. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_regs.$procmux$2622. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_regs.$procmux$2624. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_regs.$procmux$2648. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_regs.$procmux$2654. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_regs.$procmux$2660. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_regs.$procmux$2666. Removed 268 multiplexer ports. <suppressed ~188 debug messages> 24.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4398: $auto$opt_reduce.cc:134:opt_pmux$6191 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2308: { $flatten\Controller.\Interpreter.$procmux$1753_CMP $flatten\Controller.\Interpreter.$procmux$1752_CMP $auto$opt_reduce.cc:134:opt_pmux$6193 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1626: { $flatten\Controller.\Interpreter.$procmux$1720_CMP $flatten\Controller.\Interpreter.$procmux$1716_CMP $flatten\Controller.\Interpreter.$procmux$1712_CMP $flatten\Controller.\Interpreter.$procmux$1686_CMP $flatten\Controller.\Interpreter.$procmux$1685_CMP $flatten\Controller.\Interpreter.$procmux$1681_CMP $flatten\Controller.\Interpreter.$procmux$1680_CMP $flatten\Controller.\Interpreter.$procmux$1676_CMP $flatten\Controller.\Interpreter.$procmux$1666_CMP $flatten\Controller.\Interpreter.$procmux$1662_CMP $auto$opt_reduce.cc:134:opt_pmux$6201 $flatten\Controller.\Interpreter.$procmux$1657_CMP $flatten\Controller.\Interpreter.$procmux$1656_CMP $auto$opt_reduce.cc:134:opt_pmux$6199 $flatten\Controller.\Interpreter.$procmux$1651_CMP $flatten\Controller.\Interpreter.$procmux$1650_CMP $flatten\Controller.\Interpreter.$procmux$1645_CMP $flatten\Controller.\Interpreter.$procmux$1641_CMP $flatten\Controller.\Interpreter.$procmux$1640_CMP $auto$opt_reduce.cc:134:opt_pmux$6197 $flatten\Controller.\Interpreter.$procmux$1634_CMP $flatten\Controller.\Interpreter.$procmux$1633_CMP $flatten\Controller.\Interpreter.$procmux$1632_CMP $auto$opt_reduce.cc:134:opt_pmux$6195 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2334: { $auto$opt_reduce.cc:134:opt_pmux$6203 $flatten\Controller.\Interpreter.$procmux$1752_CMP $flatten\Controller.\Interpreter.$procmux$1671_CMP $flatten\Controller.\Interpreter.$procmux$1666_CMP $flatten\Controller.\Interpreter.$procmux$1656_CMP } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1951: { $auto$opt_reduce.cc:134:opt_pmux$6207 $auto$opt_reduce.cc:134:opt_pmux$6205 } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$3769: $auto$opt_reduce.cc:134:opt_pmux$6209 Consolidated identical input bits for $mux cell $flatten\Controller.\Memory.$procmux$2536: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] New connections: $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [31:1] = { $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4803: $auto$opt_reduce.cc:134:opt_pmux$6211 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4826: $auto$opt_reduce.cc:134:opt_pmux$6213 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4849: $auto$opt_reduce.cc:134:opt_pmux$6215 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4872: $auto$opt_reduce.cc:134:opt_pmux$6217 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4895: $auto$opt_reduce.cc:134:opt_pmux$6219 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4918: $auto$opt_reduce.cc:134:opt_pmux$6221 New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2404: $auto$opt_reduce.cc:134:opt_pmux$6223 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4941: $auto$opt_reduce.cc:134:opt_pmux$6225 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2020: $auto$opt_reduce.cc:134:opt_pmux$6227 New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2468: $auto$opt_reduce.cc:134:opt_pmux$6229 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5114: $auto$opt_reduce.cc:134:opt_pmux$6231 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5135: $auto$opt_reduce.cc:134:opt_pmux$6233 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5156: $auto$opt_reduce.cc:134:opt_pmux$6235 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2045: { $flatten\Controller.\Interpreter.$procmux$1666_CMP $auto$opt_reduce.cc:134:opt_pmux$6237 $flatten\Controller.\Interpreter.$procmux$1656_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5177: $auto$opt_reduce.cc:134:opt_pmux$6239 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5198: $auto$opt_reduce.cc:134:opt_pmux$6241 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1275: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1275_Y New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1275_Y [0] New connections: $flatten\Controller.\Uart.\RX_FIFO.$procmux$1275_Y [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$procmux$1275_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1275_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1275_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1275_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1275_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1275_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1275_Y [0] } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5219: $auto$opt_reduce.cc:134:opt_pmux$6243 Consolidated identical input bits for $mux cell $flatten\Controller.\Data_Memory.$procmux$2536: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] New connections: $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [31:1] = { $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_EN[31:0]$855 [0] } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5240: $auto$opt_reduce.cc:134:opt_pmux$6245 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5252: { $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y $flatten\u_tinyriscv.\u_ex.$procmux$3996_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5260: { $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y $flatten\u_tinyriscv.\u_ex.$procmux$3874_CMP $auto$opt_reduce.cc:134:opt_pmux$6247 } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5270: { $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y $flatten\u_tinyriscv.\u_ex.$procmux$3874_CMP $auto$opt_reduce.cc:134:opt_pmux$6249 } Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1275: Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1275_Y New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1275_Y [0] New connections: $flatten\Controller.\Uart.\TX_FIFO.$procmux$1275_Y [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$procmux$1275_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1275_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1275_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1275_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1275_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1275_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1275_Y [0] } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1898: { $flatten\Controller.\Interpreter.$procmux$1666_CMP $auto$opt_reduce.cc:134:opt_pmux$6251 $flatten\Controller.\Interpreter.$procmux$1656_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5280: { $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5288: { $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y $flatten\u_tinyriscv.\u_ex.$procmux$4153_CMP $auto$opt_reduce.cc:134:opt_pmux$6253 $flatten\u_tinyriscv.\u_ex.$procmux$3777_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5298: { $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y $flatten\u_tinyriscv.\u_ex.$procmux$3996_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5306: { $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y $flatten\u_tinyriscv.\u_ex.$procmux$4153_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3996_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5314: { $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y $flatten\u_tinyriscv.\u_ex.$procmux$3996_CMP } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2073: { $flatten\Controller.\Interpreter.$procmux$1652_CMP $flatten\Controller.\Interpreter.$procmux$1645_CMP $flatten\Controller.\Interpreter.$procmux$1634_CMP $flatten\Controller.\Interpreter.$procmux$1628_CMP $auto$opt_reduce.cc:134:opt_pmux$6255 } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$2709: $auto$opt_reduce.cc:134:opt_pmux$6257 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$2716: $auto$opt_reduce.cc:134:opt_pmux$6259 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$2723: $auto$opt_reduce.cc:134:opt_pmux$6261 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4038: $auto$opt_reduce.cc:134:opt_pmux$6263 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4052: $auto$opt_reduce.cc:134:opt_pmux$6265 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1831: $auto$opt_reduce.cc:134:opt_pmux$6267 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2105: { $auto$opt_reduce.cc:134:opt_pmux$6271 $auto$opt_reduce.cc:134:opt_pmux$6269 } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4066: $auto$opt_reduce.cc:134:opt_pmux$6273 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3026: $auto$opt_reduce.cc:134:opt_pmux$6275 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3048: $auto$opt_reduce.cc:134:opt_pmux$6277 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4080: $auto$opt_reduce.cc:134:opt_pmux$6279 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3070: $auto$opt_reduce.cc:134:opt_pmux$6281 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3092: $auto$opt_reduce.cc:134:opt_pmux$6283 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3114: $auto$opt_reduce.cc:134:opt_pmux$6285 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_clint.$procmux$5888: $auto$opt_reduce.cc:134:opt_pmux$6287 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_clint.$procmux$5904: { $flatten\u_tinyriscv.\u_clint.$procmux$5899_CMP $flatten\u_tinyriscv.\u_clint.$procmux$5883_CMP $auto$opt_reduce.cc:134:opt_pmux$6289 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2187: { $flatten\Controller.\Interpreter.$procmux$1646_CMP $auto$opt_reduce.cc:134:opt_pmux$6291 } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_clint.$procmux$5913: $auto$opt_reduce.cc:134:opt_pmux$6293 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1726: $auto$opt_reduce.cc:134:opt_pmux$6295 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1750: $auto$opt_reduce.cc:134:opt_pmux$6297 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2198: { $flatten\Controller.\Interpreter.$procmux$1787_CMP $flatten\Controller.\Interpreter.$procmux$1686_CMP $auto$opt_reduce.cc:134:opt_pmux$6299 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1873: $auto$opt_reduce.cc:134:opt_pmux$6301 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4240: $auto$opt_reduce.cc:134:opt_pmux$6303 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2208: { $flatten\Controller.\Interpreter.$procmux$1685_CMP $auto$opt_reduce.cc:134:opt_pmux$6307 $auto$opt_reduce.cc:134:opt_pmux$6305 } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4257: $auto$opt_reduce.cc:134:opt_pmux$6309 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3678: { $flatten\u_tinyriscv.\u_id.$procmux$3593_CMP $flatten\u_tinyriscv.\u_id.$procmux$3035_CMP $flatten\u_tinyriscv.\u_id.$procmux$2939_CMP $flatten\u_tinyriscv.\u_id.$procmux$2856_CMP $flatten\u_tinyriscv.\u_id.$procmux$2753_CMP $auto$opt_reduce.cc:134:opt_pmux$6311 $flatten\u_tinyriscv.\u_id.$procmux$3679_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3691: { $flatten\u_tinyriscv.\u_id.$procmux$3593_CMP $flatten\u_tinyriscv.\u_id.$procmux$3035_CMP $flatten\u_tinyriscv.\u_id.$procmux$2939_CMP $flatten\u_tinyriscv.\u_id.$procmux$2856_CMP $flatten\u_tinyriscv.\u_id.$procmux$2753_CMP $flatten\u_tinyriscv.\u_id.$procmux$3693_CMP $auto$opt_reduce.cc:134:opt_pmux$6313 } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3702: { $flatten\u_tinyriscv.\u_id.$procmux$3593_CMP $flatten\u_tinyriscv.\u_id.$procmux$3035_CMP $flatten\u_tinyriscv.\u_id.$procmux$2856_CMP $flatten\u_tinyriscv.\u_id.$procmux$2753_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3719: { $flatten\u_tinyriscv.\u_id.$procmux$3593_CMP $flatten\u_tinyriscv.\u_id.$procmux$3035_CMP $flatten\u_tinyriscv.\u_id.$procmux$2939_CMP $auto$opt_reduce.cc:134:opt_pmux$6315 $flatten\u_tinyriscv.\u_id.$procmux$2713_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3731: { $flatten\u_tinyriscv.\u_id.$procmux$3593_CMP $flatten\u_tinyriscv.\u_id.$procmux$3035_CMP $flatten\u_tinyriscv.\u_id.$procmux$2939_CMP $auto$opt_reduce.cc:134:opt_pmux$6317 $flatten\u_tinyriscv.\u_id.$procmux$2713_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3752: { $flatten\u_tinyriscv.\u_id.$procmux$3035_CMP $flatten\u_tinyriscv.\u_id.$procmux$2753_CMP $flatten\u_tinyriscv.\u_id.$procmux$3680_CMP $auto$opt_reduce.cc:134:opt_pmux$6319 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1772: $auto$opt_reduce.cc:134:opt_pmux$6321 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1783: $auto$opt_reduce.cc:134:opt_pmux$6323 Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_regs.$procmux$2646: Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\u_tinyriscv.\u_regs.$procmux$2646_Y New ports: A=1'0, B=1'1, Y=$flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] New connections: $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [31:1] = { $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] $flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0] } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2284: { $auto$opt_reduce.cc:134:opt_pmux$6325 $flatten\Controller.\Interpreter.$procmux$1685_CMP } Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_regs.$procmux$2664: Old ports: A=$flatten\u_tinyriscv.\u_regs.$3$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$223_EN[31:0]$252, B=0, Y=$flatten\u_tinyriscv.\u_regs.$procmux$2664_Y New connections: $flatten\u_tinyriscv.\u_regs.$procmux$2664_Y = 0 New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$6246: { $flatten\u_tinyriscv.\u_ex.$procmux$5263_CMP $flatten\u_tinyriscv.\u_ex.$procmux$5262_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$6248: { $flatten\u_tinyriscv.\u_ex.$procmux$5263_CMP $flatten\u_tinyriscv.\u_ex.$procmux$5262_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$6252: { $flatten\u_tinyriscv.\u_ex.$procmux$5290_CMP $flatten\u_tinyriscv.\u_ex.$procmux$5263_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$6256: { $flatten\u_tinyriscv.\u_id.$procmux$2711_CMP $flatten\u_tinyriscv.\u_id.$procmux$2710_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$6258: { $flatten\u_tinyriscv.\u_id.$procmux$2711_CMP $flatten\u_tinyriscv.\u_id.$procmux$2710_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$6260: { $flatten\u_tinyriscv.\u_id.$procmux$2711_CMP $flatten\u_tinyriscv.\u_id.$procmux$2710_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$6274: { $flatten\u_tinyriscv.\u_id.$procmux$2751_CMP [2] $flatten\u_tinyriscv.\u_id.$procmux$2751_CMP [0] $flatten\u_tinyriscv.\u_id.$procmux$2711_CMP $flatten\u_tinyriscv.\u_id.$procmux$2710_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$6276: { $flatten\u_tinyriscv.\u_id.$procmux$2751_CMP [2] $flatten\u_tinyriscv.\u_id.$procmux$2751_CMP [0] $flatten\u_tinyriscv.\u_id.$procmux$2711_CMP $flatten\u_tinyriscv.\u_id.$procmux$2710_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$6280: { $flatten\u_tinyriscv.\u_id.$procmux$2751_CMP [2] $flatten\u_tinyriscv.\u_id.$procmux$2751_CMP [0] $flatten\u_tinyriscv.\u_id.$procmux$2711_CMP $flatten\u_tinyriscv.\u_id.$procmux$2710_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$6282: { $flatten\u_tinyriscv.\u_id.$procmux$2751_CMP [2] $flatten\u_tinyriscv.\u_id.$procmux$2751_CMP [0] $flatten\u_tinyriscv.\u_id.$procmux$2711_CMP $flatten\u_tinyriscv.\u_id.$procmux$2710_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$6284: { $flatten\u_tinyriscv.\u_id.$procmux$2751_CMP [2] $flatten\u_tinyriscv.\u_id.$procmux$2751_CMP [0] $flatten\u_tinyriscv.\u_id.$procmux$2711_CMP $flatten\u_tinyriscv.\u_id.$procmux$2710_CMP } Optimizing cells in module \processorci_top. Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1293: Old ports: A=$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1067, B=8'00000000, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 New ports: A=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1275_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] New connections: $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] } Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1293: Old ports: A=$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1067, B=8'00000000, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 New ports: A=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1275_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] New connections: $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_EN[7:0]$1058 [0] } Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_regs.$procmux$2681: Old ports: A=0, B=$flatten\u_tinyriscv.\u_regs.$2$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$223_EN[31:0]$246, Y=$flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$223_EN[31:0]$230 New connections: $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$223_EN[31:0]$230 = 0 Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_regs.$procmux$2690: Old ports: A=0, B=$flatten\u_tinyriscv.\u_regs.$2$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$243, Y=$flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 New ports: A=1'0, B=$flatten\u_tinyriscv.\u_regs.$procmux$2646_Y [0], Y=$flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] New connections: $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [31:1] = { $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] $flatten\u_tinyriscv.\u_regs.$0$memwr$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$222_EN[31:0]$227 [0] } Optimizing cells in module \processorci_top. Performed a total of 96 changes. 24.11.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~210 debug messages> Removed a total of 70 cells. 24.11.6. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 0 on $flatten\u_tinyriscv.\u_if_id.\int_ff.$procdff$6051 ($dff) from module processorci_top. Setting constant 0-bit at position 1 on $flatten\u_tinyriscv.\u_if_id.\int_ff.$procdff$6051 ($dff) from module processorci_top. Setting constant 0-bit at position 2 on $flatten\u_tinyriscv.\u_if_id.\int_ff.$procdff$6051 ($dff) from module processorci_top. Setting constant 0-bit at position 3 on $flatten\u_tinyriscv.\u_if_id.\int_ff.$procdff$6051 ($dff) from module processorci_top. Setting constant 0-bit at position 4 on $flatten\u_tinyriscv.\u_if_id.\int_ff.$procdff$6051 ($dff) from module processorci_top. Setting constant 0-bit at position 5 on $flatten\u_tinyriscv.\u_if_id.\int_ff.$procdff$6051 ($dff) from module processorci_top. Setting constant 0-bit at position 6 on $flatten\u_tinyriscv.\u_if_id.\int_ff.$procdff$6051 ($dff) from module processorci_top. Setting constant 0-bit at position 7 on $flatten\u_tinyriscv.\u_if_id.\int_ff.$procdff$6051 ($dff) from module processorci_top. 24.11.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 3 unused cells and 1140 unused wires. <suppressed ~16 debug messages> 24.11.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~3 debug messages> 24.11.9. Rerunning OPT passes. (Maybe there is more to do..) 24.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. dead port 1/2 on $mux $flatten\u_tinyriscv.\u_csr_reg.$ternary$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:58$33. dead port 2/2 on $mux $flatten\u_tinyriscv.\u_csr_reg.$ternary$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:58$33. Removed 2 multiplexer ports. <suppressed ~201 debug messages> 24.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1898: { $auto$opt_reduce.cc:134:opt_pmux$6237 $auto$opt_reduce.cc:134:opt_pmux$6327 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2045: { $auto$opt_reduce.cc:134:opt_pmux$6237 $auto$opt_reduce.cc:134:opt_pmux$6329 } New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2334: { $auto$opt_reduce.cc:134:opt_pmux$6203 $flatten\Controller.\Interpreter.$procmux$1752_CMP $flatten\Controller.\Interpreter.$procmux$1671_CMP $auto$opt_reduce.cc:134:opt_pmux$6331 } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_div.$procmux$5670: { $flatten\u_tinyriscv.\u_div.$procmux$5467_CMP $auto$opt_reduce.cc:134:opt_pmux$6333 $flatten\u_tinyriscv.\u_div.$procmux$5553_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_div.$procmux$5702: { $flatten\u_tinyriscv.\u_div.$procmux$5467_CMP $auto$opt_reduce.cc:134:opt_pmux$6335 $flatten\u_tinyriscv.\u_div.$procmux$5553_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5444: $auto$opt_reduce.cc:134:opt_pmux$6337 Optimizing cells in module \processorci_top. Performed a total of 6 changes. 24.11.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~9 debug messages> Removed a total of 3 cells. 24.11.13. Executing OPT_DFF pass (perform DFF optimizations). 24.11.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 9 unused wires. <suppressed ~4 debug messages> 24.11.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 24.11.16. Rerunning OPT passes. (Maybe there is more to do..) 24.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~201 debug messages> 24.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 24.11.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 24.11.20. Executing OPT_DFF pass (perform DFF optimizations). 24.11.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 24.11.22. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 24.11.23. Finished OPT passes. (There is nothing left to do.) 24.12. Executing FSM pass (extract and optimize FSM). 24.12.1. Executing FSM_DETECT pass (finding FSMs in design). Not marking processorci_top.Controller.Interpreter.return_state as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register processorci_top.Controller.Uart.i_uart_rx.fsm_state. Not marking processorci_top.Controller.Uart.i_uart_tx.fsm_state as FSM state register: Users of register don't seem to benefit from recoding. Not marking processorci_top.Controller.Uart.state_read as FSM state register: Register has an initialization value. Not marking processorci_top.Controller.Uart.state_write as FSM state register: Register has an initialization value. Found FSM state register processorci_top.Controller.Uart.tx_fifo_read_state. Not marking processorci_top.ResetBootSystem.state as FSM state register: Register has an initialization value. Circuit seems to be self-resetting. Not marking processorci_top.u_tinyriscv.u_clint.cause as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register processorci_top.u_tinyriscv.u_clint.csr_state. Not marking processorci_top.u_tinyriscv.u_clint.waddr_o as FSM state register: Users of register don't seem to benefit from recoding. Found FSM state register processorci_top.u_tinyriscv.u_div.state. 24.12.2. Executing FSM_EXTRACT pass (extracting FSM from design). Extracting FSM `\Controller.Uart.i_uart_rx.fsm_state' from module `\processorci_top'. found $dff cell for state register: $flatten\Controller.\Uart.\i_uart_rx.$procdff$6038 root of input selection tree: $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] found reset state: 3'000 (guessed from mux tree) found ctrl input: \ResetBootSystem.reset_o found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1214_Y found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1227_Y found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1240_Y found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1226_Y found state code: 3'000 found ctrl input: \Controller.Uart.i_uart_rx.next_bit found state code: 3'011 found ctrl input: \Controller.Uart.i_uart_rx.payload_done found state code: 3'010 found state code: 3'001 found ctrl input: \Controller.Uart.i_uart_rx.rxd_reg found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1240_Y found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1231_Y found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1227_Y found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1226_Y found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1214_Y ctrl inputs: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.rxd_reg \Controller.Uart.i_uart_rx.next_bit \Controller.Uart.i_uart_rx.payload_done } ctrl outputs: { $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1214_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1226_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1227_Y $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1231_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1240_Y $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] } transition: 3'000 4'00-- -> 3'001 8'01010001 transition: 3'000 4'01-- -> 3'000 8'01010000 transition: 3'000 4'1--- -> 3'000 8'01010000 transition: 3'010 4'0--0 -> 3'010 8'00100010 transition: 3'010 4'0--1 -> 3'011 8'00100011 transition: 3'010 4'1--- -> 3'000 8'00100000 transition: 3'001 4'0-0- -> 3'001 8'00011001 transition: 3'001 4'0-1- -> 3'010 8'00011010 transition: 3'001 4'1--- -> 3'000 8'00011000 transition: 3'011 4'0-0- -> 3'011 8'10010011 transition: 3'011 4'0-1- -> 3'000 8'10010000 transition: 3'011 4'1--- -> 3'000 8'10010000 Extracting FSM `\Controller.Uart.tx_fifo_read_state' from module `\processorci_top'. found $dff cell for state register: $flatten\Controller.\Uart.$procdff$6089 root of input selection tree: $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] found reset state: 2'00 (guessed from mux tree) found ctrl input: \ResetBootSystem.reset_o found ctrl input: $flatten\Controller.\Uart.$procmux$2365_CMP found ctrl input: $flatten\Controller.\Uart.$procmux$2360_CMP found ctrl input: $flatten\Controller.\Uart.$procmux$2367_CMP found ctrl input: $flatten\Controller.\Uart.$procmux$2354_CMP found state code: 2'00 found state code: 2'11 found state code: 2'10 found ctrl input: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1100_Y found state code: 2'01 found ctrl output: $flatten\Controller.\Uart.$procmux$2354_CMP found ctrl output: $flatten\Controller.\Uart.$procmux$2360_CMP found ctrl output: $flatten\Controller.\Uart.$procmux$2365_CMP found ctrl output: $flatten\Controller.\Uart.$procmux$2367_CMP ctrl inputs: { \ResetBootSystem.reset_o $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1100_Y } ctrl outputs: { $flatten\Controller.\Uart.$procmux$2367_CMP $flatten\Controller.\Uart.$procmux$2365_CMP $flatten\Controller.\Uart.$procmux$2360_CMP $flatten\Controller.\Uart.$procmux$2354_CMP $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] } transition: 2'00 2'00 -> 2'00 6'000100 transition: 2'00 2'01 -> 2'01 6'000101 transition: 2'00 2'1- -> 2'00 6'000100 transition: 2'10 2'0- -> 2'11 6'001011 transition: 2'10 2'1- -> 2'00 6'001000 transition: 2'01 2'0- -> 2'10 6'100010 transition: 2'01 2'1- -> 2'00 6'100000 transition: 2'11 2'0- -> 2'00 6'010000 transition: 2'11 2'1- -> 2'00 6'010000 Extracting FSM `\u_tinyriscv.u_clint.csr_state' from module `\processorci_top'. found $dff cell for state register: $flatten\u_tinyriscv.\u_clint.$procdff$6145 root of input selection tree: $flatten\u_tinyriscv.\u_clint.$0\csr_state[4:0] found reset state: 5'00001 (guessed from mux tree) found ctrl input: \Controller.Interpreter.core_reset found state code: 5'00001 found ctrl input: $flatten\u_tinyriscv.\u_clint.$procmux$5897_CMP found ctrl input: $flatten\u_tinyriscv.\u_clint.$procmux$5899_CMP found ctrl input: $flatten\u_tinyriscv.\u_clint.$procmux$5937_CMP found state code: 5'10000 found state code: 5'00010 found ctrl input: $flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:120$20_Y found ctrl input: $flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:140$23_Y found ctrl input: $flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:153$27_Y found state code: 5'01000 found state code: 5'00100 found ctrl output: $flatten\u_tinyriscv.\u_clint.$ne$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:85$5_Y found ctrl output: $flatten\u_tinyriscv.\u_clint.$procmux$5882_CMP found ctrl output: $flatten\u_tinyriscv.\u_clint.$procmux$5883_CMP found ctrl output: $flatten\u_tinyriscv.\u_clint.$procmux$5897_CMP found ctrl output: $flatten\u_tinyriscv.\u_clint.$procmux$5899_CMP found ctrl output: $flatten\u_tinyriscv.\u_clint.$procmux$5937_CMP ctrl inputs: { $flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:153$27_Y $flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:140$23_Y $flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:120$20_Y \Controller.Interpreter.core_reset } ctrl outputs: { $flatten\u_tinyriscv.\u_clint.$procmux$5937_CMP $flatten\u_tinyriscv.\u_clint.$procmux$5899_CMP $flatten\u_tinyriscv.\u_clint.$procmux$5897_CMP $flatten\u_tinyriscv.\u_clint.$procmux$5883_CMP $flatten\u_tinyriscv.\u_clint.$procmux$5882_CMP $flatten\u_tinyriscv.\u_clint.$0\csr_state[4:0] $flatten\u_tinyriscv.\u_clint.$ne$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:85$5_Y } transition: 5'10000 4'---0 -> 5'00001 11'00010000011 transition: 5'10000 4'---1 -> 5'00001 11'00010000011 transition: 5'01000 4'---0 -> 5'00001 11'00001000011 transition: 5'01000 4'---1 -> 5'00001 11'00001000011 transition: 5'00100 4'---0 -> 5'00001 11'01000000011 transition: 5'00100 4'---1 -> 5'00010 11'01000000101 transition: 5'00010 4'---0 -> 5'00001 11'00100000011 transition: 5'00010 4'---1 -> 5'10000 11'00100100001 transition: 5'00001 4'---0 -> 5'00001 11'10000000010 transition: 5'00001 4'0001 -> 5'00001 11'10000000010 transition: 5'00001 4'1001 -> 5'01000 11'10000010000 transition: 5'00001 4'-101 -> 5'00100 11'10000001000 transition: 5'00001 4'--11 -> 5'00100 11'10000001000 Extracting FSM `\u_tinyriscv.u_div.state' from module `\processorci_top'. found $dff cell for state register: $flatten\u_tinyriscv.\u_div.$procdff$6127 root of input selection tree: $flatten\u_tinyriscv.\u_div.$0\state[3:0] found reset state: 4'0001 (guessed from mux tree) found ctrl input: \Controller.Interpreter.core_reset found state code: 4'0001 found ctrl input: $flatten\u_tinyriscv.\u_div.$procmux$5553_CMP found ctrl input: $flatten\u_tinyriscv.\u_div.$procmux$5479_CMP found ctrl input: $flatten\u_tinyriscv.\u_div.$procmux$5467_CMP found ctrl input: $flatten\u_tinyriscv.\u_div.$procmux$5571_CMP found ctrl input: \u_tinyriscv.u_clint.div_started_i found ctrl input: $flatten\u_tinyriscv.\u_div.$procmux$5475_CMP found state code: 4'1000 found ctrl input: $flatten\u_tinyriscv.\u_div.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:110$71_Y found state code: 4'0100 found state code: 4'0010 found ctrl output: $flatten\u_tinyriscv.\u_div.$procmux$5467_CMP found ctrl output: $flatten\u_tinyriscv.\u_div.$procmux$5479_CMP found ctrl output: $flatten\u_tinyriscv.\u_div.$procmux$5553_CMP found ctrl output: $flatten\u_tinyriscv.\u_div.$procmux$5571_CMP ctrl inputs: { \u_tinyriscv.u_clint.div_started_i $flatten\u_tinyriscv.\u_div.$procmux$5475_CMP $flatten\u_tinyriscv.\u_div.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:110$71_Y \Controller.Interpreter.core_reset } ctrl outputs: { $flatten\u_tinyriscv.\u_div.$procmux$5571_CMP $flatten\u_tinyriscv.\u_div.$procmux$5553_CMP $flatten\u_tinyriscv.\u_div.$procmux$5479_CMP $flatten\u_tinyriscv.\u_div.$procmux$5467_CMP $flatten\u_tinyriscv.\u_div.$0\state[3:0] } transition: 4'1000 4'---0 -> 4'0001 8'01000001 transition: 4'1000 4'---1 -> 4'0001 8'01000001 transition: 4'0100 4'---0 -> 4'0001 8'00100001 transition: 4'0100 4'0--1 -> 4'0001 8'00100001 transition: 4'0100 4'10-1 -> 4'1000 8'00101000 transition: 4'0100 4'11-1 -> 4'0100 8'00100100 transition: 4'0010 4'---0 -> 4'0001 8'00010001 transition: 4'0010 4'0--1 -> 4'0001 8'00010001 transition: 4'0010 4'1-01 -> 4'0100 8'00010100 transition: 4'0010 4'1-11 -> 4'0001 8'00010001 transition: 4'0001 4'---0 -> 4'0001 8'10000001 transition: 4'0001 4'0--1 -> 4'0001 8'10000001 transition: 4'0001 4'1--1 -> 4'0010 8'10000010 24.12.3. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\u_tinyriscv.u_div.state$6359' from module `\processorci_top'. Merging pattern 4'---0 and 4'---1 from group (0 3 8'01000001). Merging pattern 4'---1 and 4'---0 from group (0 3 8'01000001). Optimizing FSM `$fsm$\u_tinyriscv.u_clint.csr_state$6351' from module `\processorci_top'. Merging pattern 4'---0 and 4'---1 from group (0 4 11'00010000011). Merging pattern 4'---1 and 4'---0 from group (0 4 11'00010000011). Merging pattern 4'---0 and 4'---1 from group (1 4 11'00001000011). Merging pattern 4'---1 and 4'---0 from group (1 4 11'00001000011). Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$6345' from module `\processorci_top'. Merging pattern 2'0- and 2'1- from group (3 0 6'010000). Merging pattern 2'1- and 2'0- from group (3 0 6'010000). Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$6338' from module `\processorci_top'. 24.12.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 39 unused cells and 39 unused wires. <suppressed ~40 debug messages> 24.12.5. Executing FSM_OPT pass (simple optimizations of FSMs). Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$6338' from module `\processorci_top'. Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0]. Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1]. Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2]. Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$6345' from module `\processorci_top'. Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [0]. Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [1]. Removing unused output signal $flatten\Controller.\Uart.$procmux$2365_CMP. Removing unused output signal $flatten\Controller.\Uart.$procmux$2367_CMP. Optimizing FSM `$fsm$\u_tinyriscv.u_clint.csr_state$6351' from module `\processorci_top'. Removing unused output signal $flatten\u_tinyriscv.\u_clint.$0\csr_state[4:0] [0]. Removing unused output signal $flatten\u_tinyriscv.\u_clint.$0\csr_state[4:0] [1]. Removing unused output signal $flatten\u_tinyriscv.\u_clint.$0\csr_state[4:0] [2]. Removing unused output signal $flatten\u_tinyriscv.\u_clint.$0\csr_state[4:0] [3]. Removing unused output signal $flatten\u_tinyriscv.\u_clint.$0\csr_state[4:0] [4]. Optimizing FSM `$fsm$\u_tinyriscv.u_div.state$6359' from module `\processorci_top'. Removing unused output signal $flatten\u_tinyriscv.\u_div.$0\state[3:0] [0]. Removing unused output signal $flatten\u_tinyriscv.\u_div.$0\state[3:0] [1]. Removing unused output signal $flatten\u_tinyriscv.\u_div.$0\state[3:0] [2]. Removing unused output signal $flatten\u_tinyriscv.\u_div.$0\state[3:0] [3]. 24.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding). Recoding FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$6338' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 000 -> ---1 010 -> --1- 001 -> -1-- 011 -> 1--- Recoding FSM `$fsm$\Controller.Uart.tx_fifo_read_state$6345' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 00 -> ---1 10 -> --1- 01 -> -1-- 11 -> 1--- Recoding FSM `$fsm$\u_tinyriscv.u_clint.csr_state$6351' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 10000 -> ---1- 01000 -> --1-- 00100 -> -1--- 00010 -> 1---- 00001 -> ----1 Recoding FSM `$fsm$\u_tinyriscv.u_div.state$6359' from module `\processorci_top' using `auto' encoding: mapping auto encoding to `one-hot` for this FSM. 1000 -> --1- 0100 -> -1-- 0010 -> 1--- 0001 -> ---1 24.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells). FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$6338' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\Controller.Uart.i_uart_rx.fsm_state$6338 (\Controller.Uart.i_uart_rx.fsm_state): Number of input signals: 4 Number of output signals: 5 Number of state bits: 4 Input signals: 0: \Controller.Uart.i_uart_rx.payload_done 1: \Controller.Uart.i_uart_rx.next_bit 2: \Controller.Uart.i_uart_rx.rxd_reg 3: \ResetBootSystem.reset_o Output signals: 0: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1240_Y 1: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1231_Y 2: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1227_Y 3: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1226_Y 4: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1214_Y State encoding: 0: 4'---1 <RESET STATE> 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 4'01-- -> 0 5'01010 1: 0 4'1--- -> 0 5'01010 2: 0 4'00-- -> 2 5'01010 3: 1 4'1--- -> 0 5'00100 4: 1 4'0--0 -> 1 5'00100 5: 1 4'0--1 -> 3 5'00100 6: 2 4'1--- -> 0 5'00011 7: 2 4'0-1- -> 1 5'00011 8: 2 4'0-0- -> 2 5'00011 9: 3 4'0-1- -> 0 5'10010 10: 3 4'1--- -> 0 5'10010 11: 3 4'0-0- -> 3 5'10010 ------------------------------------- FSM `$fsm$\Controller.Uart.tx_fifo_read_state$6345' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\Controller.Uart.tx_fifo_read_state$6345 (\Controller.Uart.tx_fifo_read_state): Number of input signals: 2 Number of output signals: 2 Number of state bits: 4 Input signals: 0: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1100_Y 1: \ResetBootSystem.reset_o Output signals: 0: $flatten\Controller.\Uart.$procmux$2354_CMP 1: $flatten\Controller.\Uart.$procmux$2360_CMP State encoding: 0: 4'---1 <RESET STATE> 1: 4'--1- 2: 4'-1-- 3: 4'1--- Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 2'00 -> 0 2'01 1: 0 2'1- -> 0 2'01 2: 0 2'01 -> 2 2'01 3: 1 2'1- -> 0 2'10 4: 1 2'0- -> 3 2'10 5: 2 2'1- -> 0 2'00 6: 2 2'0- -> 1 2'00 7: 3 2'-- -> 0 2'00 ------------------------------------- FSM `$fsm$\u_tinyriscv.u_clint.csr_state$6351' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\u_tinyriscv.u_clint.csr_state$6351 (\u_tinyriscv.u_clint.csr_state): Number of input signals: 4 Number of output signals: 6 Number of state bits: 5 Input signals: 0: \Controller.Interpreter.core_reset 1: $flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:120$20_Y 2: $flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:140$23_Y 3: $flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:153$27_Y Output signals: 0: $flatten\u_tinyriscv.\u_clint.$ne$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:85$5_Y 1: $flatten\u_tinyriscv.\u_clint.$procmux$5882_CMP 2: $flatten\u_tinyriscv.\u_clint.$procmux$5883_CMP 3: $flatten\u_tinyriscv.\u_clint.$procmux$5897_CMP 4: $flatten\u_tinyriscv.\u_clint.$procmux$5899_CMP 5: $flatten\u_tinyriscv.\u_clint.$procmux$5937_CMP State encoding: 0: 5'---1- 1: 5'--1-- 2: 5'-1--- 3: 5'1---- 4: 5'----1 <RESET STATE> Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 4'---- -> 4 6'000101 1: 1 4'---- -> 4 6'000011 2: 2 4'---1 -> 3 6'010001 3: 2 4'---0 -> 4 6'010001 4: 3 4'---1 -> 0 6'001001 5: 3 4'---0 -> 4 6'001001 6: 4 4'1001 -> 1 6'100000 7: 4 4'-101 -> 2 6'100000 8: 4 4'--11 -> 2 6'100000 9: 4 4'---0 -> 4 6'100000 10: 4 4'0001 -> 4 6'100000 ------------------------------------- FSM `$fsm$\u_tinyriscv.u_div.state$6359' from module `processorci_top': ------------------------------------- Information on FSM $fsm$\u_tinyriscv.u_div.state$6359 (\u_tinyriscv.u_div.state): Number of input signals: 4 Number of output signals: 4 Number of state bits: 4 Input signals: 0: \Controller.Interpreter.core_reset 1: $flatten\u_tinyriscv.\u_div.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:110$71_Y 2: $flatten\u_tinyriscv.\u_div.$procmux$5475_CMP 3: \u_tinyriscv.u_clint.div_started_i Output signals: 0: $flatten\u_tinyriscv.\u_div.$procmux$5467_CMP 1: $flatten\u_tinyriscv.\u_div.$procmux$5479_CMP 2: $flatten\u_tinyriscv.\u_div.$procmux$5553_CMP 3: $flatten\u_tinyriscv.\u_div.$procmux$5571_CMP State encoding: 0: 4'--1- 1: 4'-1-- 2: 4'1--- 3: 4'---1 <RESET STATE> Transition Table (state_in, ctrl_in, state_out, ctrl_out): 0: 0 4'---- -> 3 4'0100 1: 1 4'10-1 -> 0 4'0010 2: 1 4'11-1 -> 1 4'0010 3: 1 4'---0 -> 3 4'0010 4: 1 4'0--1 -> 3 4'0010 5: 2 4'1-01 -> 1 4'0001 6: 2 4'---0 -> 3 4'0001 7: 2 4'1-11 -> 3 4'0001 8: 2 4'0--1 -> 3 4'0001 9: 3 4'1--1 -> 2 4'1000 10: 3 4'---0 -> 3 4'1000 11: 3 4'0--1 -> 3 4'1000 ------------------------------------- 24.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic). Mapping FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$6338' from module `\processorci_top'. Mapping FSM `$fsm$\Controller.Uart.tx_fifo_read_state$6345' from module `\processorci_top'. Mapping FSM `$fsm$\u_tinyriscv.u_clint.csr_state$6351' from module `\processorci_top'. Mapping FSM `$fsm$\u_tinyriscv.u_div.state$6359' from module `\processorci_top'. 24.13. Executing OPT pass (performing simple optimizations). 24.13.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~13 debug messages> 24.13.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~15 debug messages> Removed a total of 5 cells. 24.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~197 debug messages> 24.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 24.13.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 24.13.6. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $flatten\u_tinyriscv.\u_pc_reg.$procdff$6119 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_pc_reg.$procmux$2702_Y, Q = \u_tinyriscv.u_pc_reg.pc_o, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6494 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_pc_reg.$procmux$2702_Y, Q = \u_tinyriscv.u_pc_reg.pc_o). Adding SRST signal on $flatten\u_tinyriscv.\u_if_id.\inst_ff.$procdff$6054 ($dff) from module processorci_top (D = \Controller.memory_read_data [31:1], Q = \u_tinyriscv.u_if_id.inst_ff.qout_r [31:1], rval = 31'0000000000000000000000000000000). Adding SRST signal on $flatten\u_tinyriscv.\u_if_id.\inst_ff.$procdff$6054 ($dff) from module processorci_top (D = \u_tinyriscv.u_if_id.inst_ff.din [0], Q = \u_tinyriscv.u_if_id.inst_ff.qout_r [0], rval = 1'1). Adding SRST signal on $flatten\u_tinyriscv.\u_if_id.\inst_addr_ff.$procdff$6054 ($dff) from module processorci_top (D = \u_tinyriscv.u_pc_reg.pc_o, Q = \u_tinyriscv.u_if_id.inst_addr_ff.qout_r, rval = 0). Adding SRST signal on $flatten\u_tinyriscv.\u_id_ex.\reg_we_ff.$procdff$6053 ($dff) from module processorci_top (D = \u_tinyriscv.u_id_ex.reg_we_ff.din, Q = \u_tinyriscv.u_id_ex.reg_we_ff.qout_r, rval = 1'0). Adding SRST signal on $flatten\u_tinyriscv.\u_id_ex.\reg_waddr_ff.$procdff$6052 ($dff) from module processorci_top (D = \u_tinyriscv.u_id_ex.reg_waddr_ff.din, Q = \u_tinyriscv.u_id_ex.reg_waddr_ff.qout_r, rval = 5'00000). Adding SRST signal on $flatten\u_tinyriscv.\u_id_ex.\reg2_rdata_ff.$procdff$6054 ($dff) from module processorci_top (D = \u_tinyriscv.u_id.reg2_rdata_i, Q = \u_tinyriscv.u_id_ex.reg2_rdata_ff.qout_r, rval = 0). Adding SRST signal on $flatten\u_tinyriscv.\u_id_ex.\reg1_rdata_ff.$procdff$6054 ($dff) from module processorci_top (D = \u_tinyriscv.u_id.reg1_rdata_i, Q = \u_tinyriscv.u_id_ex.reg1_rdata_ff.qout_r, rval = 0). Adding SRST signal on $flatten\u_tinyriscv.\u_id_ex.\op2_jump_ff.$procdff$6054 ($dff) from module processorci_top (D = \u_tinyriscv.u_id_ex.op2_jump_ff.din, Q = \u_tinyriscv.u_id_ex.op2_jump_ff.qout_r, rval = 0). Adding SRST signal on $flatten\u_tinyriscv.\u_id_ex.\op2_ff.$procdff$6054 ($dff) from module processorci_top (D = \u_tinyriscv.u_id_ex.op2_ff.din, Q = \u_tinyriscv.u_id_ex.op2_ff.qout_r, rval = 0). Adding SRST signal on $flatten\u_tinyriscv.\u_id_ex.\op1_jump_ff.$procdff$6054 ($dff) from module processorci_top (D = \u_tinyriscv.u_id_ex.op1_jump_ff.din, Q = \u_tinyriscv.u_id_ex.op1_jump_ff.qout_r, rval = 0). Adding SRST signal on $flatten\u_tinyriscv.\u_id_ex.\op1_ff.$procdff$6054 ($dff) from module processorci_top (D = \u_tinyriscv.u_id_ex.op1_ff.din, Q = \u_tinyriscv.u_id_ex.op1_ff.qout_r, rval = 0). Adding SRST signal on $flatten\u_tinyriscv.\u_id_ex.\inst_ff.$procdff$6054 ($dff) from module processorci_top (D = \u_tinyriscv.u_if_id.inst_ff.qout_r, Q = \u_tinyriscv.u_id_ex.inst_ff.qout_r, rval = 1). Adding SRST signal on $flatten\u_tinyriscv.\u_id_ex.\csr_we_ff.$procdff$6053 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_id.$10\reg_we_o[0:0], Q = \u_tinyriscv.u_id_ex.csr_we_ff.qout_r, rval = 1'0). Adding SRST signal on $flatten\u_tinyriscv.\u_id_ex.\csr_waddr_ff.$procdff$6054 ($dff) from module processorci_top (D = { \u_tinyriscv.id_csr_raddr_o [31:12] \u_tinyriscv.u_csr_reg.raddr_i [11:0] }, Q = \u_tinyriscv.u_id_ex.csr_waddr_ff.qout_r, rval = 0). Adding SRST signal on $flatten\u_tinyriscv.\u_id_ex.\csr_rdata_ff.$procdff$6054 ($dff) from module processorci_top (D = \u_tinyriscv.u_id_ex.csr_rdata_ff.din, Q = \u_tinyriscv.u_id_ex.csr_rdata_ff.qout_r, rval = 0). Adding SRST signal on $flatten\u_tinyriscv.\u_div.$procdff$6132 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5466_Y, Q = \u_tinyriscv.u_div.invert_result, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6521 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5459_Y, Q = \u_tinyriscv.u_div.invert_result). Adding SRST signal on $flatten\u_tinyriscv.\u_div.$procdff$6131 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5478_Y, Q = \u_tinyriscv.u_div.minuend, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6527 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5478_Y, Q = \u_tinyriscv.u_div.minuend). Adding SRST signal on $flatten\u_tinyriscv.\u_div.$procdff$6130 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5506_Y, Q = \u_tinyriscv.u_div.div_remain, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6541 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5506_Y, Q = \u_tinyriscv.u_div.div_remain). Adding SRST signal on $flatten\u_tinyriscv.\u_div.$procdff$6129 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5522_Y, Q = \u_tinyriscv.u_div.div_result, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6555 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5522_Y, Q = \u_tinyriscv.u_div.div_result). Adding SRST signal on $flatten\u_tinyriscv.\u_div.$procdff$6128 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5538_Y, Q = \u_tinyriscv.u_div.count, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6567 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5538_Y, Q = \u_tinyriscv.u_div.count). Adding SRST signal on $flatten\u_tinyriscv.\u_div.$procdff$6126 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5581_Y, Q = \u_tinyriscv.u_div.op_r, rval = 3'000). Adding EN signal on $auto$ff.cc:266:slice$6579 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5579_Y, Q = \u_tinyriscv.u_div.op_r). Adding SRST signal on $flatten\u_tinyriscv.\u_div.$procdff$6125 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5599_Y, Q = \u_tinyriscv.u_div.divisor_r, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6581 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5599_Y [30:0], Q = \u_tinyriscv.u_div.divisor_r [30:0]). Adding EN signal on $auto$ff.cc:266:slice$6581 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5599_Y [31], Q = \u_tinyriscv.u_div.divisor_r [31]). Adding SRST signal on $flatten\u_tinyriscv.\u_div.$procdff$6124 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5612_Y, Q = \u_tinyriscv.u_div.dividend_r, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6606 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5612_Y [30:0], Q = \u_tinyriscv.u_div.dividend_r [30:0]). Adding EN signal on $auto$ff.cc:266:slice$6606 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5612_Y [31], Q = \u_tinyriscv.u_div.dividend_r [31]). Adding SRST signal on $flatten\u_tinyriscv.\u_div.$procdff$6123 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5640_Y, Q = \u_tinyriscv.u_div.reg_waddr_o, rval = 5'00000). Adding EN signal on $auto$ff.cc:266:slice$6635 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5638_Y, Q = \u_tinyriscv.u_div.reg_waddr_o). Adding SRST signal on $flatten\u_tinyriscv.\u_div.$procdff$6122 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5647_Y, Q = \u_tinyriscv.u_div.busy_o, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6637 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5647_Y, Q = \u_tinyriscv.u_div.busy_o). Adding SRST signal on $flatten\u_tinyriscv.\u_div.$procdff$6121 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5670_Y, Q = \u_tinyriscv.u_div.ready_o, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6645 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5670_Y, Q = \u_tinyriscv.u_div.ready_o). Adding SRST signal on $flatten\u_tinyriscv.\u_div.$procdff$6120 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5702_Y, Q = \u_tinyriscv.u_div.result_o, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6655 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_div.$procmux$5702_Y, Q = \u_tinyriscv.u_div.result_o). Adding SRST signal on $flatten\u_tinyriscv.\u_csr_reg.$procdff$6139 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_csr_reg.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:70$36_Y, Q = \u_tinyriscv.u_csr_reg.cycle, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). Adding SRST signal on $flatten\u_tinyriscv.\u_csr_reg.$procdff$6138 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_csr_reg.$procmux$5782_Y, Q = \u_tinyriscv.u_csr_reg.mscratch, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6666 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_csr_reg.$procmux$5782_Y, Q = \u_tinyriscv.u_csr_reg.mscratch). Adding SRST signal on $flatten\u_tinyriscv.\u_csr_reg.$procdff$6137 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_csr_reg.$procmux$5796_Y, Q = \u_tinyriscv.u_csr_reg.mstatus, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6676 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_csr_reg.$procmux$5796_Y, Q = \u_tinyriscv.u_csr_reg.mstatus). Adding SRST signal on $flatten\u_tinyriscv.\u_csr_reg.$procdff$6136 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_csr_reg.$procmux$5812_Y, Q = \u_tinyriscv.u_csr_reg.mie, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6686 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_csr_reg.$procmux$5812_Y, Q = \u_tinyriscv.u_csr_reg.mie). Adding SRST signal on $flatten\u_tinyriscv.\u_csr_reg.$procdff$6135 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_csr_reg.$procmux$5830_Y, Q = \u_tinyriscv.u_csr_reg.mepc, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6696 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_csr_reg.$procmux$5830_Y, Q = \u_tinyriscv.u_csr_reg.mepc). Adding SRST signal on $flatten\u_tinyriscv.\u_csr_reg.$procdff$6134 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_csr_reg.$procmux$5850_Y, Q = \u_tinyriscv.u_csr_reg.mcause, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6706 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_csr_reg.$procmux$5850_Y, Q = \u_tinyriscv.u_csr_reg.mcause). Adding SRST signal on $flatten\u_tinyriscv.\u_csr_reg.$procdff$6133 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_csr_reg.$procmux$5872_Y, Q = \u_tinyriscv.u_csr_reg.mtvec, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6716 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_csr_reg.$procmux$5872_Y, Q = \u_tinyriscv.u_csr_reg.mtvec). Adding SRST signal on $flatten\u_tinyriscv.\u_clint.$procdff$6147 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_clint.$procmux$5936_Y, Q = \u_tinyriscv.u_clint.cause, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6726 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_clint.$procmux$5934_Y, Q = \u_tinyriscv.u_clint.cause). Adding SRST signal on $flatten\u_tinyriscv.\u_clint.$procdff$6146 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_clint.$procmux$5961_Y, Q = \u_tinyriscv.u_clint.inst_addr, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6732 ($sdff) from module processorci_top (D = $flatten\u_tinyriscv.\u_clint.$procmux$5959_Y, Q = \u_tinyriscv.u_clint.inst_addr). Adding SRST signal on $flatten\u_tinyriscv.\u_clint.$procdff$6144 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_clint.$procmux$5895_Y, Q = \u_tinyriscv.u_clint.data_o, rval = 0). Adding SRST signal on $flatten\u_tinyriscv.\u_clint.$procdff$6143 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_clint.$procmux$5904_Y, Q = \u_tinyriscv.u_clint.waddr_o, rval = 0). Adding SRST signal on $flatten\u_tinyriscv.\u_clint.$procdff$6142 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_clint.$procmux$5913_Y, Q = \u_tinyriscv.u_clint.we_o, rval = 1'0). Adding SRST signal on $flatten\u_tinyriscv.\u_clint.$procdff$6141 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_clint.$procmux$5888_Y, Q = \u_tinyriscv.u_clint.int_assert_o, rval = 1'0). Adding SRST signal on $flatten\u_tinyriscv.\u_clint.$procdff$6140 ($dff) from module processorci_top (D = $flatten\u_tinyriscv.\u_clint.$procmux$5881_Y, Q = \u_tinyriscv.u_clint.int_addr_o, rval = 0). Adding EN signal on $flatten\ResetBootSystem.$procdff$6112 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter). Adding EN signal on $flatten\ResetBootSystem.$procdff$6110 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$6050 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1564_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1558_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1549_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1540_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1531_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1522_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1504_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1513_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6759 ($sdff) from module processorci_top (D = \Controller.Uart.uart_tx_data [7], Q = \Controller.Uart.i_uart_tx.data_to_send [7]). Adding EN signal on $auto$ff.cc:266:slice$6759 ($sdff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1558_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1549_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1540_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1531_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1522_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1504_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1513_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send [6:0]). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$6048 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1480_Y, Q = \Controller.Uart.i_uart_tx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$6764 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1480_Y, Q = \Controller.Uart.i_uart_tx.bit_counter). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$6047 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1469_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter, rval = 9'000000000). Adding EN signal on $auto$ff.cc:266:slice$6770 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1194_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$6046 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_tx.n_fsm_state, Q = \Controller.Uart.i_uart_tx.fsm_state, rval = 3'000). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$6045 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1458_Y, Q = \Controller.Uart.i_uart_tx.txd_reg, rval = 1'1). Adding EN signal on $auto$ff.cc:266:slice$6775 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1458_Y, Q = \Controller.Uart.i_uart_tx.txd_reg). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$6044 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1447_Y, Q = \Controller.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6781 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.recieved_data, Q = \Controller.Uart.i_uart_rx.uart_rx_data). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$6042 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_rx.$procmux$1424_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1415_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1406_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1397_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1388_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1379_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1361_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1370_Y }, Q = \Controller.Uart.i_uart_rx.recieved_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6783 ($sdff) from module processorci_top (D = { \Controller.Uart.i_uart_rx.bit_sample \Controller.Uart.i_uart_rx.recieved_data [7:1] }, Q = \Controller.Uart.i_uart_rx.recieved_data). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$6041 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1343_Y, Q = \Controller.Uart.i_uart_rx.bit_counter, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$6787 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1234_Y, Q = \Controller.Uart.i_uart_rx.bit_counter). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$6040 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1338_Y, Q = \Controller.Uart.i_uart_rx.bit_sample, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6791 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg, Q = \Controller.Uart.i_uart_rx.bit_sample). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$6039 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1330_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter, rval = 9'000000000). Adding EN signal on $auto$ff.cc:266:slice$6793 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1245_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$6037 ($dff) from module processorci_top (D = \rx, Q = \Controller.Uart.i_uart_rx.rxd_reg_0, rval = 1'1). Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$6036 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg_0, Q = \Controller.Uart.i_uart_rx.rxd_reg, rval = 1'1). Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$6035 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1307_Y, Q = \Controller.Uart.TX_FIFO.read_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$6799 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1054_Y [5:0], Q = \Controller.Uart.TX_FIFO.read_ptr). Adding EN signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$6034 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1051_DATA, Q = \Controller.Uart.TX_FIFO.read_data). Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$6030 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1302_Y, Q = \Controller.Uart.TX_FIFO.write_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$6806 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1070_Y [5:0], Q = \Controller.Uart.TX_FIFO.write_ptr). Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$6035 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1307_Y, Q = \Controller.Uart.RX_FIFO.read_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$6808 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1054_Y [5:0], Q = \Controller.Uart.RX_FIFO.read_ptr). Adding EN signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$6034 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1051_DATA, Q = \Controller.Uart.RX_FIFO.read_data). Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$6030 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1302_Y, Q = \Controller.Uart.RX_FIFO.write_ptr, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$6815 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1070_Y [5:0], Q = \Controller.Uart.RX_FIFO.write_ptr). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6102 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2490_Y, Q = \Controller.Uart.state_read, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$6817 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2490_Y, Q = \Controller.Uart.state_read). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6101 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2515_Y, Q = \Controller.Uart.counter_read, rval = 3'000). Adding EN signal on $auto$ff.cc:266:slice$6821 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2515_Y, Q = \Controller.Uart.counter_read). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6100 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2479_Y, Q = \Controller.Uart.rx_fifo_read, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6099 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2530_Y, Q = \Controller.Uart.read_data, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6838 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2528_Y, Q = \Controller.Uart.read_data). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6098 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2468_Y, Q = \Controller.Uart.read_response, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6097 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2412_Y, Q = \Controller.Uart.state_write, rval = 4'0000). Adding EN signal on $auto$ff.cc:266:slice$6845 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2412_Y, Q = \Controller.Uart.state_write). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6096 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2434_Y, Q = \Controller.Uart.counter_write, rval = 3'000). Adding EN signal on $auto$ff.cc:266:slice$6849 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2434_Y, Q = \Controller.Uart.counter_write). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6095 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2448_Y, Q = \Controller.Uart.write_data_buffer, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6859 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2448_Y, Q = \Controller.Uart.write_data_buffer). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6094 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2462_Y, Q = \Controller.Uart.tx_fifo_write_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6869 ($sdff) from module processorci_top (D = \Controller.Uart.write_data_buffer [31:24], Q = \Controller.Uart.tx_fifo_write_data). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6093 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2394_Y, Q = \Controller.Uart.tx_fifo_write, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6092 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2404_Y, Q = \Controller.Uart.write_response, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6091 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2385_Y, Q = \Controller.Uart.rx_fifo_write_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6883 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.uart_rx_data, Q = \Controller.Uart.rx_fifo_write_data). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6090 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2380_Y, Q = \Controller.Uart.rx_fifo_write, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6088 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2375_Y, Q = \Controller.Uart.uart_tx_data, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6886 ($sdff) from module processorci_top (D = \Controller.Uart.TX_FIFO.read_data, Q = \Controller.Uart.uart_tx_data). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6087 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2351_Y, Q = \Controller.Uart.tx_fifo_read, rval = 1'0). Adding SRST signal on $flatten\Controller.\Uart.$procdff$6086 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2359_Y, Q = \Controller.Uart.uart_tx_en, rval = 1'0). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$6085 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1898_Y, Q = \Controller.Interpreter.temp_buffer). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6084 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1941_Y, Q = \Controller.Interpreter.accumulator, rval = 64'0000000000000000000000000000000000000000000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$6903 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1941_Y [63:8], Q = \Controller.Interpreter.accumulator [63:8]). Adding EN signal on $auto$ff.cc:266:slice$6903 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1941_Y [7:0], Q = \Controller.Interpreter.accumulator [7:0]). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6083 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1951_Y, Q = \Controller.Interpreter.timeout_counter, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6918 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1951_Y, Q = \Controller.Interpreter.timeout_counter). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$6082 ($dff) from module processorci_top (D = { 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, Q = \Controller.Interpreter.timeout). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$6081 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1992_Y, Q = \Controller.Interpreter.read_buffer). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6080 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2020_Y, Q = \Controller.Interpreter.communication_buffer, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6934 ($sdff) from module processorci_top (D = \Controller.Uart.read_data, Q = \Controller.Interpreter.communication_buffer). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$6079 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2045_Y, Q = \Controller.Interpreter.num_of_positions). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6078 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2067_Y, Q = \Controller.Interpreter.num_of_pages, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$6945 ($sdff) from module processorci_top (D = \Controller.Interpreter.communication_buffer [31:8], Q = \Controller.Interpreter.num_of_pages). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6077 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2073_Y, Q = \Controller.Interpreter.return_state, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$6947 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2073_Y, Q = \Controller.Interpreter.return_state). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$6076 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2097_Y, Q = \Controller.Interpreter.memory_page_number). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6075 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2105_Y, Q = \Controller.Interpreter.memory_mux_selector, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6962 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2105_Y, Q = \Controller.Interpreter.memory_mux_selector). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6074 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2145_Y, Q = \Controller.Interpreter.end_position, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$6966 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2145_Y, Q = \Controller.Interpreter.end_position). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6072 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2187_Y, Q = \Controller.Interpreter.bus_mode, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6970 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2187_Y, Q = \Controller.Interpreter.bus_mode). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6071 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1726_Y, Q = \Controller.Interpreter.reset_bus, rval = 1'1). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$6070 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2198_Y, Q = \Controller.Interpreter.num_of_cycles_to_pulse). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6069 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1831_Y, Q = \Controller.Interpreter.core_reset, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6068 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2208_Y, Q = \Controller.Interpreter.core_clk_enable, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$6983 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2208_Y, Q = \Controller.Interpreter.core_clk_enable). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$6067 ($dff) from module processorci_top (D = \Controller.Interpreter.read_buffer, Q = \Controller.Interpreter.communication_write_data). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6066 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1850_Y, Q = \Controller.Interpreter.communication_write, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6065 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1873_Y, Q = \Controller.Interpreter.communication_read, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6064 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1750_Y, Q = \Controller.Interpreter.memory_write, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6063 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1772_Y, Q = \Controller.Interpreter.memory_read, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6062 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1783_Y, Q = \Controller.Interpreter.write_pulse, rval = 1'0). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6061 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2284_Y, Q = \Controller.Interpreter.counter, rval = 8'00000000). Adding EN signal on $auto$ff.cc:266:slice$7001 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2284_Y, Q = \Controller.Interpreter.counter). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$6060 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2308_Y, Q = \Controller.Interpreter.write_data). Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6059 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1626_Y, Q = \Controller.Interpreter.state, rval = 8'00000000). Adding EN signal on $flatten\Controller.\Interpreter.$procdff$6058 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2334_Y, Q = \Controller.Interpreter.address). Adding SRST signal on $flatten\Controller.\ClkDivider.$procdff$6055 ($dff) from module processorci_top (D = $flatten\Controller.\ClkDivider.$procmux$1600_Y, Q = \Controller.ClkDivider.pulse_counter, rval = 0). Adding EN signal on $auto$ff.cc:266:slice$7022 ($sdff) from module processorci_top (D = $flatten\Controller.\ClkDivider.$procmux$1600_Y, Q = \Controller.ClkDivider.pulse_counter). Adding SRST signal on $flatten\Controller.$procdff$6109 ($dff) from module processorci_top (D = $flatten\Controller.$procmux$2551_Y, Q = \Controller.finish_execution, rval = 1'0). Adding EN signal on $auto$ff.cc:266:slice$7030 ($sdff) from module processorci_top (D = $flatten\Controller.$procmux$2551_Y, Q = \Controller.finish_execution). Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$6922 ($dffe) from module processorci_top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$6922 ($dffe) from module processorci_top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$6922 ($dffe) from module processorci_top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$6922 ($dffe) from module processorci_top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$6922 ($dffe) from module processorci_top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$6922 ($dffe) from module processorci_top. Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$6922 ($dffe) from module processorci_top. Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$6922 ($dffe) from module processorci_top. 24.13.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 175 unused cells and 202 unused wires. <suppressed ~180 debug messages> 24.13.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~47 debug messages> 24.13.9. Rerunning OPT passes. (Maybe there is more to do..) 24.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~164 debug messages> 24.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$6789: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.fsm_state [3:2] \Controller.Uart.i_uart_rx.fsm_state [0] } Optimizing cells in module \processorci_top. Performed a total of 1 changes. 24.13.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~186 debug messages> Removed a total of 62 cells. 24.13.13. Executing OPT_DFF pass (perform DFF optimizations). 24.13.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 1 unused cells and 63 unused wires. <suppressed ~2 debug messages> 24.13.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 24.13.16. Rerunning OPT passes. (Maybe there is more to do..) 24.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~166 debug messages> 24.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 24.13.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 24.13.20. Executing OPT_DFF pass (perform DFF optimizations). 24.13.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 24.13.22. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 24.13.23. Finished OPT passes. (There is nothing left to do.) 24.14. Executing WREDUCE pass (reducing word size of cells). Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Data_Memory.$auto$proc_memwr.cc:45:proc_memwr$6149 (Controller.Data_Memory.memory). Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$849 (Controller.Data_Memory.memory). Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Memory.$auto$proc_memwr.cc:45:proc_memwr$6149 (Controller.Memory.memory). Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$849 (Controller.Memory.memory). Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$6148 (Controller.Uart.RX_FIFO.memory). Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1051 (Controller.Uart.RX_FIFO.memory). Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$6148 (Controller.Uart.TX_FIFO.memory). Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1051 (Controller.Uart.TX_FIFO.memory). Removed top 3 bits (of 4) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$6459 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6497 ($ne). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$6492 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$6385 ($eq). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1152 ($gt). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:219$1109 ($eq). Removed top 6 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1113 ($add). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1116 ($add). Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1125 ($lt). Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1130 ($eq). Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1132 ($ge). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1627_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1628_CMP0 ($eq). Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1630 ($mux). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1632_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1633_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1634_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1635_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1636_CMP0 ($eq). Removed top 5 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1638 ($mux). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1640_CMP0 ($eq). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1641_CMP0 ($eq). Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1643 ($mux). Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1645_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1646_CMP0 ($eq). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1650_CMP0 ($eq). Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1651_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1652_CMP0 ($eq). Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1654 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1656_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1657_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1658_CMP0 ($eq). Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1660 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1662_CMP0 ($eq). Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1664 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1666_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1667_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1668_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1669_CMP0 ($eq). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1670_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1671_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1672_CMP0 ($eq). Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1674 ($mux). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1676_CMP0 ($eq). Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1678 ($mux). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1680_CMP0 ($eq). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1681_CMP0 ($eq). Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1683 ($mux). Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1685_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1686_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1689_CMP0 ($eq). Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1688 ($pmux). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1690_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1691_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1692_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1693_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1694_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1695_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1696_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1697_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1698_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1699_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1700_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1701_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1702_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1703_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1704_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1705_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1706_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1707_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1708_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1709_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1710_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1711_CMP0 ($eq). Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1712_CMP0 ($eq). Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1714 ($mux). Removed top 7 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1716_CMP0 ($eq). Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1718 ($mux). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1752_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1753_CMP0 ($eq). Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1754_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1787_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1942_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1943_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1944_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1987_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2113_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2146_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2147_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2220_CMP0 ($eq). Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2221_CMP0 ($eq). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:95$1083 ($lt). Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:159$1088 ($lt). Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2399_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2405_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2406_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2418_CMP0 ($eq). Removed top 1 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2420 ($mux). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2469_CMP0 ($eq). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2470_CMP0 ($eq). Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2484_CMP0 ($eq). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2492_CMP0 ($eq). Removed top 3 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2500 ($mux). Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1299 ($mux). Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1287 ($mux). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1071 ($sub). Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1071 ($sub). Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1070 ($mux). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1069 ($add). Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$1068 ($eq). Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1054 ($mux). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1053 ($add). Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$1052 ($eq). Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1299 ($mux). Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1287 ($mux). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1071 ($sub). Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1071 ($sub). Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1070 ($mux). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1069 ($add). Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$1068 ($eq). Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1054 ($mux). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1053 ($add). Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$1052 ($eq). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1223 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:119$1222 ($mux). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1221 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1220 ($mux). Removed top 2 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:110$1215 ($eq). Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:108$1213 ($eq). Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:152$1189 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:137$1181 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:135$1179 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1176 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1175 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:120$1171 ($eq). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1166 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1165 ($mux). Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1164 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1163 ($mux). Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:94$1159 ($eq). Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:92$1157 ($eq). Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Memory.$procmux$2542 ($mux). Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Data_Memory.$procmux$2542 ($mux). Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:96$826 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:90$816 ($mux). Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$810 ($mux). Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$809 ($mux). Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6699 ($ne). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$6399 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6709 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6719 ($ne). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6749 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$7025 ($ne). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$7035 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6669 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6679 ($ne). Removed top 1 bits (of 3) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6689 ($ne). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\u_tinyriscv.\u_div.$ternary$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:67$65 ($mux). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$6424 ($eq). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\u_tinyriscv.\u_div.$procmux$5483 ($mux). Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\u_tinyriscv.\u_div.$procmux$5485 ($mux). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:134$95 ($add). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:135$97 ($add). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:144$103 ($add). Removed top 30 bits (of 32) from port Y of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:146$104 ($add). Removed top 30 bits (of 32) from port A of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:146$104 ($add). Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:146$104 ($add). Removed top 30 bits (of 32) from port Y of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:147$106 ($add). Removed top 30 bits (of 32) from port A of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:147$106 ($add). Removed top 30 bits (of 32) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:147$106 ($add). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130 ($eq). Removed top 6 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$131 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$161 ($eq). Removed top 27 bits (of 32) from port A of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:843$205 ($or). Removed top 27 bits (of 32) from port A of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$not$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:847$206 ($not). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$procmux$3773_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$procmux$3774_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$procmux$3775_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$procmux$3996_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$procmux$4010_CMP0 ($eq). Removed top 16 bits (of 32) from mux cell processorci_top.$flatten\u_tinyriscv.\u_ex.$procmux$4148 ($mux). Removed top 5 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$procmux$4153_CMP0 ($eq). Removed top 24 bits (of 32) from mux cell processorci_top.$flatten\u_tinyriscv.\u_ex.$procmux$4165 ($pmux). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$procmux$4167_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP0 ($eq). Removed top 3 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$procmux$5262_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$procmux$5290_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_ex.$procmux$5290_CMP1 ($eq). Removed top 20 bits (of 32) from FF cell processorci_top.$auto$ff.cc:266:slice$6519 ($sdff). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_id.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:105$210 ($eq). Removed top 6 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_id.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id.v:122$212 ($eq). Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_id.$procmux$2711_CMP0 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_id.$procmux$2711_CMP1 ($eq). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_id.$procmux$2711_CMP2 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_id.$procmux$2856_CMP0 ($eq). Removed top 5 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_id.$procmux$2939_CMP0 ($eq). Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$6374 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_id.$procmux$3035_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_id.$procmux$3593_CMP0 ($eq). Removed top 2 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_id.$procmux$3679_CMP0 ($eq). Removed top 1 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_id.$procmux$3693_CMP0 ($eq). Removed top 3 bits (of 7) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_id.$procmux$3745_CMP0 ($eq). Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\u_tinyriscv.\u_id.$procmux$3759 ($mux). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5761_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5762_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5763_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5764_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5765_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5766_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5776_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5781_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5789_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5795_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5804_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5811_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5821_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5829_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5840_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5849_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5861_CMP0 ($eq). Removed top 2 bits (of 12) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5871_CMP0 ($eq). Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_pc_reg.$ge$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:43$220 ($ge). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_pc_reg.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:47$221 ($add). Removed top 25 bits (of 32) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:93$10 ($eq). Removed top 11 bits (of 32) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:93$11 ($eq). Removed top 2 bits (of 32) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:102$17 ($eq). Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:120$20 ($eq). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_clint.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:124$22 ($sub). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_clint.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:140$23 ($eq). Removed top 20 bits (of 32) from FF cell processorci_top.$auto$ff.cc:266:slice$6739 ($sdff). Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_clint.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:148$26 ($sub). Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\u_tinyriscv.\u_clint.$procmux$5904 ($pmux). Removed top 28 bits (of 32) from mux cell processorci_top.$flatten\u_tinyriscv.\u_clint.$procmux$5931 ($pmux). Removed top 2 bits (of 4) from mux cell processorci_top.$flatten\u_tinyriscv.\u_clint.$procmux$6007 ($mux). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_id_ex.$ge$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/id_ex.v:57$213 ($ge). Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_if_id.$ge$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/if_id.v:38$214 ($ge). Removed top 1 bits (of 3) from mux cell processorci_top.$flatten\u_tinyriscv.\u_ctrl.$procmux$5741 ($mux). Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\u_tinyriscv.\u_clint.$ne$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:85$4 ($ne). Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\ResetBootSystem.$procmux$2568_CMP0 ($eq). Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$796 ($eq). Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$795 ($add). Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$795 ($add). Removed top 27 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$794 ($lt). Removed top 2 bits (of 12) from FF cell processorci_top.$auto$ff.cc:266:slice$6739 ($sdff). Removed top 2 bits (of 12) from port A of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5776_CMP0 ($eq). Removed top 2 bits (of 12) from port A of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5789_CMP0 ($eq). Removed top 2 bits (of 12) from port A of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5804_CMP0 ($eq). Removed top 2 bits (of 12) from port A of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5821_CMP0 ($eq). Removed top 2 bits (of 12) from port A of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5840_CMP0 ($eq). Removed top 2 bits (of 12) from port A of cell processorci_top.$flatten\u_tinyriscv.\u_csr_reg.$procmux$5861_CMP0 ($eq). Removed top 20 bits (of 32) from wire processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$809_Y. Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_ADDR[31:0]$853. Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1630_Y. Removed top 5 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1638_Y. Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1643_Y. Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1654_Y. Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1660_Y. Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1664_Y. Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1674_Y. Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1678_Y. Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1683_Y. Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1688_Y. Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1714_Y. Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1718_Y. Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$847_ADDR[31:0]$853. Removed top 2 bits (of 32) from wire processorci_top.$flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$849_DATA. Removed top 1 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2420_Y. Removed top 3 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2500_Y. Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_ADDR[5:0]$1056. Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_ADDR[5:0]$1065. Removed top 3 bits (of 8) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_DATA[7:0]$1066. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1053_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1069_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1070_Y. Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_ADDR[5:0]$1056. Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1046_ADDR[5:0]$1065. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1053_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1069_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1054_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1070_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1163_Y. Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1164_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1165_Y. Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1166_Y. Removed top 26 bits (of 32) from wire processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$795_Y. Removed top 2 bits (of 4) from wire processorci_top.$flatten\u_tinyriscv.\u_clint.$3\int_state[3:0]. Removed top 22 bits (of 32) from wire processorci_top.$flatten\u_tinyriscv.\u_clint.$procmux$5904_Y. Removed top 28 bits (of 32) from wire processorci_top.$flatten\u_tinyriscv.\u_clint.$procmux$5931_Y. Removed top 31 bits (of 32) from wire processorci_top.$flatten\u_tinyriscv.\u_div.$procmux$5483_Y. Removed top 24 bits (of 32) from wire processorci_top.$flatten\u_tinyriscv.\u_ex.$15\reg_wdata[31:0]. Removed top 16 bits (of 32) from wire processorci_top.$flatten\u_tinyriscv.\u_ex.$16\reg_wdata[31:0]. Removed top 31 bits (of 32) from wire processorci_top.$flatten\u_tinyriscv.\u_ex.$and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:275$147_Y. Removed top 31 bits (of 32) from wire processorci_top.core_read_data. 24.15. Executing PEEPOPT pass (run peephole optimizers). 24.16. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 45 unused wires. <suppressed ~1 debug messages> 24.17. Executing SHARE pass (SAT-based resource sharing). Found 11 cells in module processorci_top that may be considered for resource sharing. Analyzing resource sharing options for $flatten\u_tinyriscv.\u_regs.$memrd$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:86$264 ($memrd): Found 1 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y }. Found 1 candidates: $flatten\u_tinyriscv.\u_regs.$memrd$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:74$258 Analyzing resource sharing with $flatten\u_tinyriscv.\u_regs.$memrd$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:74$258 ($memrd): Found 1 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y }. Activation pattern for cell $flatten\u_tinyriscv.\u_regs.$memrd$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:86$264: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y } = 2'00 Activation pattern for cell $flatten\u_tinyriscv.\u_regs.$memrd$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:74$258: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y } = 2'00 Size of SAT problem: 0 cells, 1087 variables, 2923 clauses According to the SAT solver this pair of cells can not be shared. Model from SAT solver: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y } = 4'0000 Analyzing resource sharing options for $flatten\u_tinyriscv.\u_regs.$memrd$\regs$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:74$258 ($memrd): Found 1 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y }. No candidates found. Analyzing resource sharing options for $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:129$91 ($shr): Found 3 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$240_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP \Controller.Interpreter.core_reset }. Found 3 candidates: $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:128$90 $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:127$89 $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:126$88 Analyzing resource sharing with $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:128$90 ($shr): Found 3 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$240_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y \Controller.Interpreter.core_reset }. Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:129$91: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP } = 5'10111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:129$91: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP } = 5'10111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:129$91: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$240_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP \Controller.Interpreter.core_reset } = 5'11111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:128$90: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$240_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y \Controller.Interpreter.core_reset } = 6'111111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:128$90: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y } = 6'101111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:128$90: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y } = 6'101111 Size of SAT problem: 0 cells, 1170 variables, 3198 clauses According to the SAT solver this pair of cells can be shared. Activation signal for $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:129$91: $auto$share.cc:987:make_cell_activation_logic$7086 New cell: $auto$share.cc:667:make_supercell$7093 ($shr) Analyzing resource sharing options for $auto$share.cc:667:make_supercell$7093 ($shr): Found 6 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$240_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y \Controller.Interpreter.core_reset }. Found 2 candidates: $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:127$89 $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:126$88 Analyzing resource sharing with $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:127$89 ($shr): Found 3 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$240_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP \Controller.Interpreter.core_reset }. Activation pattern for cell $auto$share.cc:667:make_supercell$7093: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP } = 5'10111 Activation pattern for cell $auto$share.cc:667:make_supercell$7093: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP } = 5'10111 Activation pattern for cell $auto$share.cc:667:make_supercell$7093: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$240_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP \Controller.Interpreter.core_reset } = 5'11111 Activation pattern for cell $auto$share.cc:667:make_supercell$7093: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$240_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y \Controller.Interpreter.core_reset } = 6'111111 Activation pattern for cell $auto$share.cc:667:make_supercell$7093: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y } = 6'101111 Activation pattern for cell $auto$share.cc:667:make_supercell$7093: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y } = 6'101111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:127$89: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP } = 4'1011 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:127$89: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP } = 4'1011 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:127$89: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$240_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP \Controller.Interpreter.core_reset } = 4'1111 Size of SAT problem: 0 cells, 1162 variables, 3173 clauses According to the SAT solver this pair of cells can not be shared. Model from SAT solver: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$240_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y \Controller.Interpreter.core_reset } = 11'10001111100 Analyzing resource sharing with $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:126$88 ($shr): Found 3 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$240_Y $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y \Controller.Interpreter.core_reset }. Activation pattern for cell $auto$share.cc:667:make_supercell$7093: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP } = 5'10111 Activation pattern for cell $auto$share.cc:667:make_supercell$7093: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP } = 5'10111 Activation pattern for cell $auto$share.cc:667:make_supercell$7093: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$240_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP \Controller.Interpreter.core_reset } = 5'11111 Activation pattern for cell $auto$share.cc:667:make_supercell$7093: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$240_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y \Controller.Interpreter.core_reset } = 6'111111 Activation pattern for cell $auto$share.cc:667:make_supercell$7093: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y } = 6'101111 Activation pattern for cell $auto$share.cc:667:make_supercell$7093: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y } = 6'101111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:126$88: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$240_Y $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y \Controller.Interpreter.core_reset } = 5'11111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:126$88: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y } = 5'10111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:126$88: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y } = 5'10111 Size of SAT problem: 0 cells, 1162 variables, 3176 clauses According to the SAT solver this pair of cells can not be shared. Model from SAT solver: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$240_Y \u_tinyriscv.u_id_ex.inst_ff.qout_r [30] $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y \Controller.Interpreter.core_reset } = 11'10001101110 Analyzing resource sharing options for $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:127$89 ($shr): Found 3 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$240_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP \Controller.Interpreter.core_reset }. Found 1 candidates: $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:126$88 Analyzing resource sharing with $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:126$88 ($shr): Found 3 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$240_Y $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y \Controller.Interpreter.core_reset }. Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:127$89: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP } = 4'1011 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:127$89: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP } = 4'1011 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:127$89: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$240_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP \Controller.Interpreter.core_reset } = 4'1111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:126$88: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$240_Y $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y \Controller.Interpreter.core_reset } = 5'11111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:126$88: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y } = 5'10111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:126$88: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y } = 5'10111 Size of SAT problem: 0 cells, 1170 variables, 3189 clauses According to the SAT solver this pair of cells can be shared. Activation signal for $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:127$89: $auto$share.cc:987:make_cell_activation_logic$7100 New cell: $auto$share.cc:667:make_supercell$7107 ($shr) Analyzing resource sharing options for $auto$share.cc:667:make_supercell$7107 ($shr): Found 6 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$240_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y \Controller.Interpreter.core_reset }. No candidates found. Analyzing resource sharing options for $flatten\u_tinyriscv.\u_ex.$shl$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:378$165 ($shl): Found 3 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$240_Y $flatten\u_tinyriscv.\u_ex.$procmux$3775_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y \Controller.Interpreter.core_reset }. Found 1 candidates: $flatten\u_tinyriscv.\u_ex.$shl$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:325$153 Analyzing resource sharing with $flatten\u_tinyriscv.\u_ex.$shl$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:325$153 ($shl): Found 3 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$240_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3775_CMP \Controller.Interpreter.core_reset }. Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shl$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:378$165: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y $flatten\u_tinyriscv.\u_ex.$procmux$3775_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y } = 5'10111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shl$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:378$165: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y $flatten\u_tinyriscv.\u_ex.$procmux$3775_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y } = 5'10111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shl$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:378$165: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$240_Y $flatten\u_tinyriscv.\u_ex.$procmux$3775_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y \Controller.Interpreter.core_reset } = 5'11111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shl$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:325$153: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$240_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3775_CMP \Controller.Interpreter.core_reset } = 4'1111 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shl$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:325$153: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3775_CMP } = 4'1011 Activation pattern for cell $flatten\u_tinyriscv.\u_ex.$shl$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:325$153: { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3775_CMP } = 4'1011 Size of SAT problem: 0 cells, 1171 variables, 3195 clauses According to the SAT solver this pair of cells can be shared. Activation signal for $flatten\u_tinyriscv.\u_ex.$shl$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:325$153: $auto$share.cc:987:make_cell_activation_logic$7114 New cell: $auto$share.cc:667:make_supercell$7121 ($shl) Analyzing resource sharing options for $auto$share.cc:667:make_supercell$7121 ($shl): Found 6 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$240_Y $flatten\u_tinyriscv.\u_ex.$procmux$5082_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3775_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y \Controller.Interpreter.core_reset }. No candidates found. Analyzing resource sharing options for $flatten\u_tinyriscv.\u_ex.$mul$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:143$101 ($mul): Found 12 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$240_Y $flatten\u_tinyriscv.\u_ex.$procmux$3872_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3775_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3774_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3773_CMP $flatten\u_tinyriscv.\u_ex.$logic_or$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:354$162_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$131_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:173$130_Y \Controller.Interpreter.core_reset }. No candidates found. Analyzing resource sharing options for $flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$849 ($memrd): Found 1 activation_patterns using ctrl signal \Controller.Memory.memory_read. No candidates found. Analyzing resource sharing options for $flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$849 ($memrd): Found 39 activation_patterns using ctrl signal { $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:83$263_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:80$260_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:71$257_Y $flatten\u_tinyriscv.\u_regs.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:68$254_Y $flatten\u_tinyriscv.\u_regs.$logic_and$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:58$240_Y $flatten\u_tinyriscv.\u_ex.$procmux$4167_CMP $flatten\u_tinyriscv.\u_ex.$procmux$4166_CMP $flatten\u_tinyriscv.\u_ex.$procmux$4153_CMP $flatten\u_tinyriscv.\u_ex.$procmux$4010_CMP $flatten\u_tinyriscv.\u_ex.$procmux$4009_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3996_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3872_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3870_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3775_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3774_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3772_CMP $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:674$183_Y $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:571$181_Y \Controller.Data_Memory.memory_write \Controller.Data_Memory.memory_read $flatten\Controller.\Interpreter.$procmux$1670_CMP \Controller.Interpreter.address [31] \Controller.Interpreter.memory_mux_selector \Controller.Interpreter.core_reset }. No candidates found. Removing 6 cells in module processorci_top: Removing cell $flatten\u_tinyriscv.\u_ex.$shl$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:325$153 ($shl). Removing cell $flatten\u_tinyriscv.\u_ex.$shl$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:378$165 ($shl). Removing cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:126$88 ($shr). Removing cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:127$89 ($shr). Removing cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:128$90 ($shr). Removing cell $flatten\u_tinyriscv.\u_ex.$shr$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:129$91 ($shr). 24.18. Executing TECHMAP pass (map to technology primitives). 24.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation. Generating RTLIL representation for module `\_90_lut_cmp_'. Successfully finished Verilog frontend. 24.18.2. Continuing TECHMAP pass. Using template $paramod$141b0f41d8ab4b936f42c52ead39f1f9a7c93200\_90_lut_cmp_ for cells of type $lt. Using template $paramod$2b219144165107f7a748973168aee346c2de5671\_90_lut_cmp_ for cells of type $ge. Using template $paramod$47e13f9af9c2f084dc0140c442912baffd5ee164\_90_lut_cmp_ for cells of type $ge. Using template $paramod$3eab19c3b06c9721d9bc60677e7aee18638008e3\_90_lut_cmp_ for cells of type $ge. No more expansions possible. <suppressed ~287 debug messages> 24.19. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~2 debug messages> 24.20. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 21 unused wires. <suppressed ~7 debug messages> 24.21. Executing TECHMAP pass (map to technology primitives). 24.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation. Generating RTLIL representation for module `\_80_mul'. Generating RTLIL representation for module `\_90_soft_mul'. Successfully finished Verilog frontend. 24.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation. Generating RTLIL representation for module `\$__MUL18X18'. Successfully finished Verilog frontend. 24.21.3. Continuing TECHMAP pass. Using template $paramod$550e203a952dbffa6a242dc3ff52d918f7107edc\_80_mul for cells of type $mul. Using template $paramod$20c936a0792f4d1374c5655c28d1183b326ddc16\_80_mul for cells of type $__mul. Using template $paramod$53619bec844f404c540ad98bff25578b57460b55\_80_mul for cells of type $__mul. Using template $paramod$ba1b36458f074a6329f9cad9c8b71be8774bccea\_80_mul for cells of type $__mul. Using template $paramod$6b575be7a871ec606b9b0767ebd93c7f3c2d2c79\_80_mul for cells of type $__mul. Using template $paramod$dea5bd344db76a97cfc2d2ce1e3c016835e6674d\_80_mul for cells of type $__mul. Using template $paramod$2b87aee4ebaafa612245fc7fd7616dd6042fdae6\_80_mul for cells of type $__mul. Using template $paramod$2d2a570e39348c56898214c319f101b20f7da6fb\$__MUL18X18 for cells of type $__MUL18X18. Using template $paramod$8966f1902fe419d84ad9f3abc17827c8390a13bf\$__MUL18X18 for cells of type $__MUL18X18. Using template $paramod$e5ade21dea2c4d51df0cdca72b2a93a08fd8e7d1\$__MUL18X18 for cells of type $__MUL18X18. No more expansions possible. <suppressed ~651 debug messages> 24.22. Executing ALUMACC pass (create $alu and $macc cells). Extracting $alu and $macc cells in module processorci_top: creating $macc model for $techmap$flatten\u_tinyriscv.\u_ex.$mul$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:143$101.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$7142 ($add). creating $macc model for $techmap$flatten\u_tinyriscv.\u_ex.$mul$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:143$101.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$7139 ($add). creating $macc model for $techmap$flatten\u_tinyriscv.\u_ex.$mul$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:143$101.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$7136 ($add). creating $macc model for $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1153 ($sub). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1108 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1112 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1113 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1116 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1123 ($add). creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1127 ($add). creating $macc model for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1115 ($sub). creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1090 ($add). creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1085 ($add). creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1053 ($add). creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1069 ($add). creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1071 ($sub). creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1053 ($add). creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1069 ($add). creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1071 ($sub). creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1234 ($add). creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1245 ($add). creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1183 ($add). creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1194 ($add). creating $macc model for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$795 ($add). creating $macc model for $flatten\u_tinyriscv.\u_clint.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:124$22 ($sub). creating $macc model for $flatten\u_tinyriscv.\u_clint.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:148$26 ($sub). creating $macc model for $flatten\u_tinyriscv.\u_csr_reg.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:70$36 ($add). creating $macc model for $flatten\u_tinyriscv.\u_div.$neg$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:190$86 ($neg). creating $macc model for $flatten\u_tinyriscv.\u_div.$neg$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:196$87 ($neg). creating $macc model for $flatten\u_tinyriscv.\u_div.$neg$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:63$61 ($neg). creating $macc model for $flatten\u_tinyriscv.\u_div.$neg$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:64$62 ($neg). creating $macc model for $flatten\u_tinyriscv.\u_div.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:66$64 ($sub). creating $macc model for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:131$92 ($add). creating $macc model for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:132$93 ($add). creating $macc model for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:134$95 ($add). creating $macc model for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:135$97 ($add). creating $macc model for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:144$103 ($add). creating $macc model for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:146$104 ($add). creating $macc model for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:147$106 ($add). creating $macc model for $flatten\u_tinyriscv.\u_ex.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:367$164 ($sub). creating $macc model for $flatten\u_tinyriscv.\u_pc_reg.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:47$221 ($add). creating $alu model for $macc $flatten\u_tinyriscv.\u_pc_reg.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:47$221. creating $alu model for $macc $flatten\u_tinyriscv.\u_ex.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:367$164. creating $alu model for $macc $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:147$106. creating $alu model for $macc $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:146$104. creating $alu model for $macc $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:144$103. creating $alu model for $macc $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:135$97. creating $alu model for $macc $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:134$95. creating $alu model for $macc $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:132$93. creating $alu model for $macc $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:131$92. creating $alu model for $macc $flatten\u_tinyriscv.\u_div.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:66$64. creating $alu model for $macc $flatten\u_tinyriscv.\u_div.$neg$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:64$62. creating $alu model for $macc $flatten\u_tinyriscv.\u_div.$neg$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:63$61. creating $alu model for $macc $flatten\u_tinyriscv.\u_div.$neg$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:196$87. creating $alu model for $macc $flatten\u_tinyriscv.\u_div.$neg$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:190$86. creating $alu model for $macc $flatten\u_tinyriscv.\u_csr_reg.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:70$36. creating $alu model for $macc $flatten\u_tinyriscv.\u_clint.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:148$26. creating $alu model for $macc $flatten\u_tinyriscv.\u_clint.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:124$22. creating $alu model for $macc $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$795. creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1194. creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1183. creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1245. creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1234. creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1071. creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1069. creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1053. creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1071. creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1069. creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1053. creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1085. creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1090. creating $alu model for $macc $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1115. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1127. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1123. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1116. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1113. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1112. creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1108. creating $alu model for $macc $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1153. creating $alu model for $macc $techmap$flatten\u_tinyriscv.\u_ex.$mul$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:143$101.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$7136. creating $alu model for $macc $techmap$flatten\u_tinyriscv.\u_ex.$mul$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:143$101.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$7139. creating $alu model for $macc $techmap$flatten\u_tinyriscv.\u_ex.$mul$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:143$101.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$7142. creating $alu model for $flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1152 ($gt): new $alu creating $alu model for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1132 ($ge): new $alu creating $alu model for $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1125 ($lt): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1132. creating $alu model for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$794 ($lt): new $alu creating $alu model for $flatten\u_tinyriscv.\u_div.$ge$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:65$63 ($ge): merged with $flatten\u_tinyriscv.\u_div.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:66$64. creating $alu model for $flatten\u_tinyriscv.\u_ex.$ge$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:138$98 ($ge): new $alu creating $alu model for $flatten\u_tinyriscv.\u_ex.$ge$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:140$99 ($ge): merged with $flatten\u_tinyriscv.\u_ex.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:367$164. creating $alu model for $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1130 ($eq): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1132. creating $alu model for $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$796 ($eq): merged with $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$794. creating $alu model for $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:141$100 ($eq): merged with $flatten\u_tinyriscv.\u_ex.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:367$164. creating $alu cell for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$794, $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$796: $auto$alumacc.cc:485:replace_alu$7155 creating $alu cell for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1132, $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1125, $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1130: $auto$alumacc.cc:485:replace_alu$7166 creating $alu cell for $flatten\Controller.\ClkDivider.$gt$/eda/processor-ci-controller/src/clk_divider.v:62$1152: $auto$alumacc.cc:485:replace_alu$7179 creating $alu cell for $techmap$flatten\u_tinyriscv.\u_ex.$mul$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:143$101.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$7142: $auto$alumacc.cc:485:replace_alu$7184 creating $alu cell for $techmap$flatten\u_tinyriscv.\u_ex.$mul$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:143$101.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:230$7139: $auto$alumacc.cc:485:replace_alu$7187 creating $alu cell for $techmap$flatten\u_tinyriscv.\u_ex.$mul$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:143$101.$add$/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v:173$7136: $auto$alumacc.cc:485:replace_alu$7190 creating $alu cell for $flatten\Controller.\ClkDivider.$sub$/eda/processor-ci-controller/src/clk_divider.v:63$1153: $auto$alumacc.cc:485:replace_alu$7193 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1108: $auto$alumacc.cc:485:replace_alu$7196 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1112: $auto$alumacc.cc:485:replace_alu$7199 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1113: $auto$alumacc.cc:485:replace_alu$7202 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1116: $auto$alumacc.cc:485:replace_alu$7205 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1123: $auto$alumacc.cc:485:replace_alu$7208 creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1127: $auto$alumacc.cc:485:replace_alu$7211 creating $alu cell for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1115: $auto$alumacc.cc:485:replace_alu$7214 creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1090: $auto$alumacc.cc:485:replace_alu$7217 creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1085: $auto$alumacc.cc:485:replace_alu$7220 creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1053: $auto$alumacc.cc:485:replace_alu$7223 creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1069: $auto$alumacc.cc:485:replace_alu$7226 creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1071: $auto$alumacc.cc:485:replace_alu$7229 creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1053: $auto$alumacc.cc:485:replace_alu$7232 creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1069: $auto$alumacc.cc:485:replace_alu$7235 creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1071: $auto$alumacc.cc:485:replace_alu$7238 creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1234: $auto$alumacc.cc:485:replace_alu$7241 creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1245: $auto$alumacc.cc:485:replace_alu$7244 creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1183: $auto$alumacc.cc:485:replace_alu$7247 creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1194: $auto$alumacc.cc:485:replace_alu$7250 creating $alu cell for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$795: $auto$alumacc.cc:485:replace_alu$7253 creating $alu cell for $flatten\u_tinyriscv.\u_clint.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:124$22: $auto$alumacc.cc:485:replace_alu$7256 creating $alu cell for $flatten\u_tinyriscv.\u_clint.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:148$26: $auto$alumacc.cc:485:replace_alu$7259 creating $alu cell for $flatten\u_tinyriscv.\u_csr_reg.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:70$36: $auto$alumacc.cc:485:replace_alu$7262 creating $alu cell for $flatten\u_tinyriscv.\u_div.$neg$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:190$86: $auto$alumacc.cc:485:replace_alu$7265 creating $alu cell for $flatten\u_tinyriscv.\u_div.$neg$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:196$87: $auto$alumacc.cc:485:replace_alu$7268 creating $alu cell for $flatten\u_tinyriscv.\u_div.$neg$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:63$61: $auto$alumacc.cc:485:replace_alu$7271 creating $alu cell for $flatten\u_tinyriscv.\u_div.$neg$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:64$62: $auto$alumacc.cc:485:replace_alu$7274 creating $alu cell for $flatten\u_tinyriscv.\u_div.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:66$64, $flatten\u_tinyriscv.\u_div.$ge$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/div.v:65$63: $auto$alumacc.cc:485:replace_alu$7277 creating $alu cell for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:132$93: $auto$alumacc.cc:485:replace_alu$7290 creating $alu cell for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:134$95: $auto$alumacc.cc:485:replace_alu$7293 creating $alu cell for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:135$97: $auto$alumacc.cc:485:replace_alu$7296 creating $alu cell for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:144$103: $auto$alumacc.cc:485:replace_alu$7299 creating $alu cell for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:146$104: $auto$alumacc.cc:485:replace_alu$7302 creating $alu cell for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:147$106: $auto$alumacc.cc:485:replace_alu$7305 creating $alu cell for $flatten\u_tinyriscv.\u_ex.$ge$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:138$98: $auto$alumacc.cc:485:replace_alu$7308 creating $alu cell for $flatten\u_tinyriscv.\u_ex.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:131$92: $auto$alumacc.cc:485:replace_alu$7323 creating $alu cell for $flatten\u_tinyriscv.\u_ex.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:367$164, $flatten\u_tinyriscv.\u_ex.$ge$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:140$99, $flatten\u_tinyriscv.\u_ex.$eq$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:141$100: $auto$alumacc.cc:485:replace_alu$7326 creating $alu cell for $flatten\u_tinyriscv.\u_pc_reg.$add$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:47$221: $auto$alumacc.cc:485:replace_alu$7339 created 45 $alu and 0 $macc cells. 24.23. Executing OPT pass (performing simple optimizations). 24.23.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~3 debug messages> 24.23.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~12 debug messages> Removed a total of 4 cells. 24.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~170 debug messages> 24.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 24.23.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~9 debug messages> Removed a total of 3 cells. 24.23.6. Executing OPT_DFF pass (perform DFF optimizations). 24.23.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 68 unused wires. <suppressed ~1 debug messages> 24.23.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 24.23.9. Rerunning OPT passes. (Maybe there is more to do..) 24.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~171 debug messages> 24.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 24.23.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 24.23.13. Executing OPT_DFF pass (perform DFF optimizations). 24.23.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 24.23.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 24.23.16. Finished OPT passes. (There is nothing left to do.) 24.24. Executing MEMORY pass. 24.24.1. Executing OPT_MEM pass (optimize memories). Performed a total of 1 transformations. 24.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations). Performed a total of 0 transformations. 24.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths). Analyzing processorci_top.Controller.Data_Memory.memory write port 0. Analyzing processorci_top.Controller.Memory.memory write port 0. Analyzing processorci_top.Controller.Uart.RX_FIFO.memory write port 0. Analyzing processorci_top.Controller.Uart.TX_FIFO.memory write port 0. Analyzing processorci_top.u_tinyriscv.u_regs.regs write port 0. 24.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs). 24.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd). Checking read port `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no output FF found. Checking read port `\Controller.Memory.memory'[0] in module `\processorci_top': no output FF found. Checking read port `\Controller.Uart.RX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell. Write port 0: non-transparent. Checking read port `\Controller.Uart.TX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell. Write port 0: non-transparent. Checking read port `\u_tinyriscv.u_regs.regs'[0] in module `\processorci_top': no output FF found. Checking read port `\u_tinyriscv.u_regs.regs'[1] in module `\processorci_top': no output FF found. Checking read port address `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no address FF found. Checking read port address `\Controller.Memory.memory'[0] in module `\processorci_top': no address FF found. Checking read port address `\u_tinyriscv.u_regs.regs'[0] in module `\processorci_top': no address FF found. Checking read port address `\u_tinyriscv.u_regs.regs'[1] in module `\processorci_top': no address FF found. 24.24.6. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 2 unused cells and 18 unused wires. <suppressed ~3 debug messages> 24.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells). Consolidating read ports of memory processorci_top.u_tinyriscv.u_regs.regs by address: 24.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide). Performed a total of 0 transformations. 24.24.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 24.24.10. Executing MEMORY_COLLECT pass (generating $mem cells). 24.25. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 24.26. Executing MEMORY_LIBMAP pass (mapping memories to cells). mapping memory processorci_top.Controller.Data_Memory.memory via $__TRELLIS_DPR16X4_ mapping memory processorci_top.Controller.Memory.memory via $__TRELLIS_DPR16X4_ mapping memory processorci_top.Controller.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of processorci_top.Controller.Uart.RX_FIFO.memory: $\Controller.Uart.RX_FIFO.memory$rdreg[0] mapping memory processorci_top.Controller.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_ Extracted data FF from read port 0 of processorci_top.Controller.Uart.TX_FIFO.memory: $\Controller.Uart.TX_FIFO.memory$rdreg[0] mapping memory processorci_top.u_tinyriscv.u_regs.regs via $__TRELLIS_DPR16X4_ <suppressed ~1170 debug messages> 24.27. Executing TECHMAP pass (map to technology primitives). 24.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation. Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'. Successfully finished Verilog frontend. 24.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation. Generating RTLIL representation for module `\$__ECP5_DP16KD_'. Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'. Successfully finished Verilog frontend. 24.27.3. Continuing TECHMAP pass. Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_. No more expansions possible. <suppressed ~1078 debug messages> 24.28. Executing OPT pass (performing simple optimizations). 24.28.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~248 debug messages> 24.28.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~18 debug messages> Removed a total of 6 cells. 24.28.3. Executing OPT_DFF pass (perform DFF optimizations). Adding EN signal on $flatten\ResetBootSystem.$procdff$6111 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state). Adding SRST signal on $auto$ff.cc:266:slice$6955 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1127_Y, Q = \Controller.Interpreter.memory_page_number, rval = 24'000000000000000000000000). Adding EN signal on $auto$ff.cc:266:slice$6894 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1898_Y [1:0], Q = \Controller.Interpreter.temp_buffer [1:0]). Adding SRST signal on $auto$ff.cc:266:slice$6743 ($dffe) from module processorci_top (D = $flatten\ResetBootSystem.$procmux$2565_Y, Q = \ResetBootSystem.counter, rval = 6'000000). Adding EN signal on $auto$ff.cc:266:slice$6495 ($sdffe) from module processorci_top (D = $flatten\u_tinyriscv.\u_pc_reg.$procmux$2702_Y [1:0], Q = \u_tinyriscv.u_pc_reg.pc_o [1:0]). 24.28.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 9 unused cells and 7587 unused wires. <suppressed ~10 debug messages> 24.28.5. Rerunning OPT passes. (Removed registers in this run.) 24.28.6. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~5 debug messages> 24.28.7. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 24.28.8. Executing OPT_DFF pass (perform DFF optimizations). Adding SRST signal on $auto$ff.cc:266:slice$9794 ($sdffce) from module processorci_top (D = $auto$wreduce.cc:461:run$7073 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000). 24.28.9. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 1 unused cells and 5 unused wires. <suppressed ~2 debug messages> 24.28.10. Rerunning OPT passes. (Removed registers in this run.) 24.28.11. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 24.28.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 24.28.13. Executing OPT_DFF pass (perform DFF optimizations). 24.28.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 24.28.15. Finished fast OPT passes. 24.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops). 24.30. Executing OPT pass (performing simple optimizations). 24.30.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 24.30.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 24.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~113 debug messages> 24.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$9792: { $auto$opt_dff.cc:194:make_patterns_logic$9789 $auto$fsm_map.cc:74:implement_pattern_cache$6419 $auto$opt_dff.cc:194:make_patterns_logic$6897 $auto$opt_dff.cc:194:make_patterns_logic$6895 } Consolidated identical input bits for $mux cell $flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$809: Old ports: A=\u_tinyriscv.u_pc_reg.pc_o [11:0], B={ \Controller.Interpreter.memory_page_number [5:0] \u_tinyriscv.u_pc_reg.pc_o [5:0] }, Y=$auto$wreduce.cc:461:run$7039 [11:0] New ports: A=\u_tinyriscv.u_pc_reg.pc_o [11:6], B=\Controller.Interpreter.memory_page_number [5:0], Y=$auto$wreduce.cc:461:run$7039 [11:6] New connections: $auto$wreduce.cc:461:run$7039 [5:0] = \u_tinyriscv.u_pc_reg.pc_o [5:0] Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1638: Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:461:run$7042 [2:0] New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$7042 [2] $auto$wreduce.cc:461:run$7042 [0] } New connections: $auto$wreduce.cc:461:run$7042 [1] = $auto$wreduce.cc:461:run$7042 [0] Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1643: Old ports: A=7'1010010, B=7'0010101, Y=$auto$wreduce.cc:461:run$7043 [6:0] New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$7043 [1:0] New connections: $auto$wreduce.cc:461:run$7043 [6:2] = { $auto$wreduce.cc:461:run$7043 [1] 3'010 $auto$wreduce.cc:461:run$7043 [0] } Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1654: Old ports: A=4'1100, B=4'0000, Y=$auto$wreduce.cc:461:run$7044 [3:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$7044 [2] New connections: { $auto$wreduce.cc:461:run$7044 [3] $auto$wreduce.cc:461:run$7044 [1:0] } = { $auto$wreduce.cc:461:run$7044 [2] 2'00 } Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1664: Old ports: A=4'1001, B=4'0000, Y=$auto$wreduce.cc:461:run$7046 [3:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$7046 [0] New connections: $auto$wreduce.cc:461:run$7046 [3:1] = { $auto$wreduce.cc:461:run$7046 [0] 2'00 } Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1678: Old ports: A=7'0000110, B=7'1010111, Y=$auto$wreduce.cc:461:run$7048 [6:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$7048 [0] New connections: $auto$wreduce.cc:461:run$7048 [6:1] = { $auto$wreduce.cc:461:run$7048 [0] 1'0 $auto$wreduce.cc:461:run$7048 [0] 3'011 } Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$2073: Old ports: A=8'00001011, B=302978816, Y=$flatten\Controller.\Interpreter.$procmux$2073_Y New ports: A=5'01011, B=20'10010011111011100000, Y=$flatten\Controller.\Interpreter.$procmux$2073_Y [4:0] New connections: $flatten\Controller.\Interpreter.$procmux$2073_Y [7:5] = 3'000 Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$2198: Old ports: A={ 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, B={ 40'0000000000000000000000000001010000000000 \Controller.Interpreter.timeout [23:0] }, Y=$flatten\Controller.\Interpreter.$procmux$2198_Y New ports: A=\Controller.Interpreter.communication_buffer [31:8], B={ 24'000000000000000000010100 \Controller.Interpreter.timeout [23:0] }, Y=$flatten\Controller.\Interpreter.$procmux$2198_Y [23:0] New connections: $flatten\Controller.\Interpreter.$procmux$2198_Y [31:24] = 8'00000000 New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2208: $auto$opt_reduce.cc:134:opt_pmux$6307 Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2412: Old ports: A=4'0000, B={ 1'0 $auto$wreduce.cc:461:run$7055 [2:0] 12'000100100011 }, Y=$flatten\Controller.\Uart.$procmux$2412_Y New ports: A=3'000, B={ $auto$wreduce.cc:461:run$7055 [2:0] 9'001010011 }, Y=$flatten\Controller.\Uart.$procmux$2412_Y [2:0] New connections: $flatten\Controller.\Uart.$procmux$2412_Y [3] = 1'0 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2420: Old ports: A=3'000, B=3'100, Y=$auto$wreduce.cc:461:run$7055 [2:0] New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$7055 [2] New connections: $auto$wreduce.cc:461:run$7055 [1:0] = 2'00 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2496: Old ports: A=4'0010, B=4'0100, Y=$flatten\Controller.\Uart.$procmux$2496_Y New ports: A=2'01, B=2'10, Y=$flatten\Controller.\Uart.$procmux$2496_Y [2:1] New connections: { $flatten\Controller.\Uart.$procmux$2496_Y [3] $flatten\Controller.\Uart.$procmux$2496_Y [0] } = 2'00 Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_rx.$procmux$1442: Old ports: A=3'000, B={ 2'00 $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1220_Y [0] 1'0 $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1221_Y [1:0] 2'01 \Controller.Uart.i_uart_rx.payload_done 1'0 $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1223_Y [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state New ports: A=2'00, B={ 1'0 $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1220_Y [0] $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1221_Y [1:0] 1'1 \Controller.Uart.i_uart_rx.payload_done $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1223_Y [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state [1:0] New connections: \Controller.Uart.i_uart_rx.n_fsm_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1223: Old ports: A=2'11, B=2'00, Y=$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1223_Y [1:0] New ports: A=1'1, B=1'0, Y=$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1223_Y [0] New connections: $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1223_Y [1] = $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1223_Y [0] Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_tx.$procmux$1579: Old ports: A=3'000, B={ 2'00 \Controller.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$7070 [1:0] 2'01 \Controller.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$7072 [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state New ports: A=2'00, B={ 1'0 \Controller.Uart.uart_tx_en $auto$wreduce.cc:461:run$7070 [1:0] 1'1 \Controller.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$7072 [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state [1:0] New connections: \Controller.Uart.i_uart_tx.n_fsm_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1166: Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$7072 [1:0] New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$7072 [0] New connections: $auto$wreduce.cc:461:run$7072 [1] = $auto$wreduce.cc:461:run$7072 [0] New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$2576: { $flatten\ResetBootSystem.$procmux$2569_CMP $flatten\ResetBootSystem.$procmux$2568_CMP } Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2579: Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$2579_Y New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$2579_Y [1] New connections: $flatten\ResetBootSystem.$procmux$2579_Y [0] = 1'0 Consolidated identical input bits for $pmux cell $flatten\u_tinyriscv.\u_clint.$procmux$5904: Old ports: A=10'0000000000, B=30'110100000111010000101100000000, Y=$auto$wreduce.cc:461:run$7075 [9:0] New ports: A=4'0000, B=12'110111101000, Y={ $auto$wreduce.cc:461:run$7075 [8] $auto$wreduce.cc:461:run$7075 [6] $auto$wreduce.cc:461:run$7075 [1:0] } New connections: { $auto$wreduce.cc:461:run$7075 [9] $auto$wreduce.cc:461:run$7075 [7] $auto$wreduce.cc:461:run$7075 [5:2] } = { $auto$wreduce.cc:461:run$7075 [8] 5'00000 } Consolidated identical input bits for $pmux cell $flatten\u_tinyriscv.\u_clint.$procmux$5931: Old ports: A=4'1010, B=8'10110011, Y=$auto$wreduce.cc:461:run$7076 [3:0] New ports: A=2'10, B=4'1101, Y={ $auto$wreduce.cc:461:run$7076 [3] $auto$wreduce.cc:461:run$7076 [0] } New connections: $auto$wreduce.cc:461:run$7076 [2:1] = 2'01 Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_clint.$procmux$5934: Old ports: A=32'10000000000000000000000000000100, B={ 28'0000000000000000000000000000 $auto$wreduce.cc:461:run$7076 [3:0] }, Y=$flatten\u_tinyriscv.\u_clint.$procmux$5934_Y New ports: A=5'10100, B={ 1'0 $auto$wreduce.cc:461:run$7076 [3:0] }, Y={ $flatten\u_tinyriscv.\u_clint.$procmux$5934_Y [31] $flatten\u_tinyriscv.\u_clint.$procmux$5934_Y [3:0] } New connections: $flatten\u_tinyriscv.\u_clint.$procmux$5934_Y [30:4] = 27'000000000000000000000000000 Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_clint.$procmux$5948: Old ports: A=\u_tinyriscv.u_if_id.inst_addr_ff.qout_r, B={ $flatten\u_tinyriscv.\u_clint.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:148$26_Y [31:2] \u_tinyriscv.u_if_id.inst_addr_ff.qout_r [1:0] }, Y=$flatten\u_tinyriscv.\u_clint.$procmux$5948_Y New ports: A=\u_tinyriscv.u_if_id.inst_addr_ff.qout_r [31:2], B=$flatten\u_tinyriscv.\u_clint.$sub$/var/jenkins_home/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:148$26_Y [31:2], Y=$flatten\u_tinyriscv.\u_clint.$procmux$5948_Y [31:2] New connections: $flatten\u_tinyriscv.\u_clint.$procmux$5948_Y [1:0] = \u_tinyriscv.u_if_id.inst_addr_ff.qout_r [1:0] Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_clint.$procmux$5985: Old ports: A=4'0001, B=4'1000, Y=$flatten\u_tinyriscv.\u_clint.$4\int_state[3:0] New ports: A=2'01, B=2'10, Y={ $flatten\u_tinyriscv.\u_clint.$4\int_state[3:0] [3] $flatten\u_tinyriscv.\u_clint.$4\int_state[3:0] [0] } New connections: $flatten\u_tinyriscv.\u_clint.$4\int_state[3:0] [2:1] = 2'00 Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_ctrl.$procmux$5741: Old ports: A=2'00, B=2'11, Y=\u_tinyriscv.u_id_ex.hold_flag_i [1:0] New ports: A=1'0, B=1'1, Y=\u_tinyriscv.u_id_ex.hold_flag_i [0] New connections: \u_tinyriscv.u_id_ex.hold_flag_i [1] = \u_tinyriscv.u_id_ex.hold_flag_i [0] Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_div.$procmux$5538: Old ports: A=1073741824, B={ 1'0 \u_tinyriscv.u_div.count [31:1] }, Y=$flatten\u_tinyriscv.\u_div.$procmux$5538_Y New ports: A=31'1000000000000000000000000000000, B=\u_tinyriscv.u_div.count [31:1], Y=$flatten\u_tinyriscv.\u_div.$procmux$5538_Y [30:0] New connections: $flatten\u_tinyriscv.\u_div.$procmux$5538_Y [31] = 1'0 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_div.$procmux$5647: { \u_tinyriscv.u_div.state [3] $auto$opt_reduce.cc:134:opt_pmux$9807 } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_div.$procmux$5670: $auto$opt_reduce.cc:134:opt_pmux$6333 Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_ex.$procmux$4186: Old ports: A={ \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31:16] }, B={ \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15:0] }, Y=$flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] New ports: A=\u_tinyriscv.u_ex.mem_rdata_i [31:16], B=\u_tinyriscv.u_ex.mem_rdata_i [15:0], Y=$flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15:0] New connections: $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [31:16] = { $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] $flatten\u_tinyriscv.\u_ex.$14\reg_wdata[31:0] [15] } Consolidated identical input bits for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$4206: Old ports: A={ \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31] \u_tinyriscv.u_ex.mem_rdata_i [31:24] }, B={ \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7] \u_tinyriscv.u_ex.mem_rdata_i [7:0] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15] \u_tinyriscv.u_ex.mem_rdata_i [15:8] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23] \u_tinyriscv.u_ex.mem_rdata_i [23:16] }, Y=$flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] New ports: A=\u_tinyriscv.u_ex.mem_rdata_i [31:24], B={ \u_tinyriscv.u_ex.mem_rdata_i [7:0] \u_tinyriscv.u_ex.mem_rdata_i [15:8] \u_tinyriscv.u_ex.mem_rdata_i [23:16] }, Y=$flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7:0] New connections: $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [31:8] = { $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] $flatten\u_tinyriscv.\u_ex.$13\reg_wdata[31:0] [7] } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5252: $flatten\u_tinyriscv.\u_ex.$procmux$3996_CMP New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5260: { $flatten\u_tinyriscv.\u_ex.$procmux$3874_CMP $auto$opt_reduce.cc:134:opt_pmux$6247 } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5270: { $flatten\u_tinyriscv.\u_ex.$procmux$3874_CMP $auto$opt_reduce.cc:134:opt_pmux$6247 } Consolidated identical input bits for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5280: Old ports: A=1'0, B=2'00, Y=\u_tinyriscv.u_ex.hold_flag New connections: \u_tinyriscv.u_ex.hold_flag = 1'0 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5298: $flatten\u_tinyriscv.\u_ex.$procmux$3996_CMP New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5306: { $flatten\u_tinyriscv.\u_ex.$procmux$4153_CMP $flatten\u_tinyriscv.\u_ex.$procmux$3996_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_ex.$procmux$5314: $flatten\u_tinyriscv.\u_ex.$procmux$3996_CMP Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_id.$procmux$2750: Old ports: A=0, B={ \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [7] \u_tinyriscv.u_if_id.inst_ff.qout_r [30:25] \u_tinyriscv.u_if_id.inst_ff.qout_r [11:8] 1'0 }, Y=$flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] New ports: A=12'000000000000, B={ \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [7] \u_tinyriscv.u_if_id.inst_ff.qout_r [30:25] \u_tinyriscv.u_if_id.inst_ff.qout_r [11:8] }, Y=$flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12:1] New connections: { $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [31:13] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [0] } = { $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] 1'0 } Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_id.$procmux$2853: Old ports: A=0, B={ \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31:25] \u_tinyriscv.u_if_id.inst_ff.qout_r [11:7] }, Y=$flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] New ports: A=12'000000000000, B={ \u_tinyriscv.u_if_id.inst_ff.qout_r [31:25] \u_tinyriscv.u_if_id.inst_ff.qout_r [11:7] }, Y=$flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11:0] New connections: $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [31:12] = { $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$8\op2_o[31:0] [11] } Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_id.$procmux$2936: Old ports: A=0, B={ \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31:20] }, Y=$flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] New ports: A=12'000000000000, B=\u_tinyriscv.u_if_id.inst_ff.qout_r [31:20], Y=$flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11:0] New connections: $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [31:12] = { $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] $flatten\u_tinyriscv.\u_id.$7\op2_o[31:0] [11] } Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_id.$procmux$3158: Old ports: A=0, B=4, Y=$flatten\u_tinyriscv.\u_id.$4\op2_jump_o[31:0] New ports: A=1'0, B=1'1, Y=$flatten\u_tinyriscv.\u_id.$4\op2_jump_o[31:0] [2] New connections: { $flatten\u_tinyriscv.\u_id.$4\op2_jump_o[31:0] [31:3] $flatten\u_tinyriscv.\u_id.$4\op2_jump_o[31:0] [1:0] } = 31'0000000000000000000000000000000 New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3702: { $flatten\u_tinyriscv.\u_id.$procmux$3035_CMP $flatten\u_tinyriscv.\u_id.$procmux$2856_CMP $flatten\u_tinyriscv.\u_id.$procmux$2753_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3710: { $flatten\u_tinyriscv.\u_id.$procmux$3035_CMP $flatten\u_tinyriscv.\u_id.$procmux$2939_CMP $flatten\u_tinyriscv.\u_id.$procmux$2856_CMP $flatten\u_tinyriscv.\u_id.$procmux$2753_CMP $auto$opt_reduce.cc:134:opt_pmux$9809 $flatten\u_tinyriscv.\u_id.$procmux$2713_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3719: { $flatten\u_tinyriscv.\u_id.$procmux$3035_CMP $flatten\u_tinyriscv.\u_id.$procmux$2939_CMP $auto$opt_reduce.cc:134:opt_pmux$9811 $flatten\u_tinyriscv.\u_id.$procmux$2713_CMP } New ctrl vector for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3731: { $flatten\u_tinyriscv.\u_id.$procmux$3035_CMP $flatten\u_tinyriscv.\u_id.$procmux$2939_CMP $auto$opt_reduce.cc:134:opt_pmux$9813 $flatten\u_tinyriscv.\u_id.$procmux$2713_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$9810: { $flatten\u_tinyriscv.\u_id.$procmux$3693_CMP $flatten\u_tinyriscv.\u_id.$procmux$3681_CMP $flatten\u_tinyriscv.\u_id.$procmux$3680_CMP $flatten\u_tinyriscv.\u_id.$procmux$3679_CMP $flatten\u_tinyriscv.\u_id.$procmux$3593_CMP } New input vector for $reduce_or cell $auto$opt_reduce.cc:128:opt_pmux$9812: { $flatten\u_tinyriscv.\u_id.$procmux$3693_CMP $flatten\u_tinyriscv.\u_id.$procmux$3681_CMP $flatten\u_tinyriscv.\u_id.$procmux$3680_CMP $flatten\u_tinyriscv.\u_id.$procmux$3679_CMP $flatten\u_tinyriscv.\u_id.$procmux$3593_CMP } Optimizing cells in module \processorci_top. Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2490: Old ports: A=4'0000, B={ 3'000 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2496_Y 8'00010011 }, Y=$flatten\Controller.\Uart.$procmux$2490_Y New ports: A=3'000, B={ 2'00 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2496_Y [2:1] 7'0001011 }, Y=$flatten\Controller.\Uart.$procmux$2490_Y [2:0] New connections: $flatten\Controller.\Uart.$procmux$2490_Y [3] = 1'0 Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2585: Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$2579_Y, Y=$flatten\ResetBootSystem.$procmux$2585_Y New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$2579_Y [1], Y=$flatten\ResetBootSystem.$procmux$2585_Y [1] New connections: $flatten\ResetBootSystem.$procmux$2585_Y [0] = 1'0 Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_clint.$procmux$5934: Old ports: A=5'10100, B={ 1'0 $auto$wreduce.cc:461:run$7076 [3:0] }, Y={ $flatten\u_tinyriscv.\u_clint.$procmux$5934_Y [31] $flatten\u_tinyriscv.\u_clint.$procmux$5934_Y [3:0] } New ports: A=4'0100, B={ $auto$wreduce.cc:461:run$7076 [3] 2'01 $auto$wreduce.cc:461:run$7076 [0] }, Y=$flatten\u_tinyriscv.\u_clint.$procmux$5934_Y [3:0] New connections: $flatten\u_tinyriscv.\u_clint.$procmux$5934_Y [31] = $flatten\u_tinyriscv.\u_clint.$procmux$5934_Y [2] Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_clint.$procmux$6015: Old ports: A=$flatten\u_tinyriscv.\u_clint.$4\int_state[3:0], B={ 2'00 $auto$wreduce.cc:461:run$7074 [1:0] }, Y=$flatten\u_tinyriscv.\u_clint.$2\int_state[3:0] New ports: A={ $flatten\u_tinyriscv.\u_clint.$4\int_state[3:0] [3] 1'0 $flatten\u_tinyriscv.\u_clint.$4\int_state[3:0] [0] }, B={ 1'0 $auto$wreduce.cc:461:run$7074 [1:0] }, Y={ $flatten\u_tinyriscv.\u_clint.$2\int_state[3:0] [3] $flatten\u_tinyriscv.\u_clint.$2\int_state[3:0] [1:0] } New connections: $flatten\u_tinyriscv.\u_clint.$2\int_state[3:0] [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_id.$procmux$3202: Old ports: A=0, B=$flatten\u_tinyriscv.\u_id.$4\op2_jump_o[31:0], Y=$flatten\u_tinyriscv.\u_id.$3\op2_jump_o[31:0] New ports: A=1'0, B=$flatten\u_tinyriscv.\u_id.$4\op2_jump_o[31:0] [2], Y=$flatten\u_tinyriscv.\u_id.$3\op2_jump_o[31:0] [2] New connections: { $flatten\u_tinyriscv.\u_id.$3\op2_jump_o[31:0] [31:3] $flatten\u_tinyriscv.\u_id.$3\op2_jump_o[31:0] [1:0] } = 31'0000000000000000000000000000000 Optimizing cells in module \processorci_top. Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_clint.$procmux$6021: Old ports: A=4'0001, B=$flatten\u_tinyriscv.\u_clint.$2\int_state[3:0], Y=\u_tinyriscv.u_clint.int_state New ports: A=3'001, B={ $flatten\u_tinyriscv.\u_clint.$2\int_state[3:0] [3] $flatten\u_tinyriscv.\u_clint.$2\int_state[3:0] [1:0] }, Y={ \u_tinyriscv.u_clint.int_state [3] \u_tinyriscv.u_clint.int_state [1:0] } New connections: \u_tinyriscv.u_clint.int_state [2] = 1'0 Consolidated identical input bits for $mux cell $flatten\u_tinyriscv.\u_id.$procmux$3558: Old ports: A=$flatten\u_tinyriscv.\u_id.$3\op2_jump_o[31:0], B=0, Y=$flatten\u_tinyriscv.\u_id.$2\op2_jump_o[31:0] New ports: A=$flatten\u_tinyriscv.\u_id.$3\op2_jump_o[31:0] [2], B=1'0, Y=$flatten\u_tinyriscv.\u_id.$2\op2_jump_o[31:0] [2] New connections: { $flatten\u_tinyriscv.\u_id.$2\op2_jump_o[31:0] [31:3] $flatten\u_tinyriscv.\u_id.$2\op2_jump_o[31:0] [1:0] } = 31'0000000000000000000000000000000 Optimizing cells in module \processorci_top. Consolidated identical input bits for $pmux cell $flatten\u_tinyriscv.\u_id.$procmux$3744: Old ports: A=0, B={ $flatten\u_tinyriscv.\u_id.$2\op2_jump_o[31:0] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [19:12] \u_tinyriscv.u_if_id.inst_ff.qout_r [20] \u_tinyriscv.u_if_id.inst_ff.qout_r [30:21] 1'0 \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31:20] 32'00000000000000000000000000000100 }, Y=\u_tinyriscv.u_id_ex.op2_jump_ff.din New ports: A=21'000000000000000000000, B={ 18'000000000000000000 $flatten\u_tinyriscv.\u_id.$2\op2_jump_o[31:0] [2] 2'00 $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12] $flatten\u_tinyriscv.\u_id.$5\op2_jump_o[31:0] [12:1] 1'0 \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [19:12] \u_tinyriscv.u_if_id.inst_ff.qout_r [20] \u_tinyriscv.u_if_id.inst_ff.qout_r [30:21] 1'0 \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31] \u_tinyriscv.u_if_id.inst_ff.qout_r [31:20] 21'000000000000000000100 }, Y=\u_tinyriscv.u_id_ex.op2_jump_ff.din [20:0] New connections: \u_tinyriscv.u_id_ex.op2_jump_ff.din [31:21] = { \u_tinyriscv.u_id_ex.op2_jump_ff.din [20] \u_tinyriscv.u_id_ex.op2_jump_ff.din [20] \u_tinyriscv.u_id_ex.op2_jump_ff.din [20] \u_tinyriscv.u_id_ex.op2_jump_ff.din [20] \u_tinyriscv.u_id_ex.op2_jump_ff.din [20] \u_tinyriscv.u_id_ex.op2_jump_ff.din [20] \u_tinyriscv.u_id_ex.op2_jump_ff.din [20] \u_tinyriscv.u_id_ex.op2_jump_ff.din [20] \u_tinyriscv.u_id_ex.op2_jump_ff.din [20] \u_tinyriscv.u_id_ex.op2_jump_ff.din [20] \u_tinyriscv.u_id_ex.op2_jump_ff.din [20] } Optimizing cells in module \processorci_top. Performed a total of 57 changes. 24.30.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~12 debug messages> Removed a total of 4 cells. 24.30.6. Executing OPT_DFF pass (perform DFF optimizations). 24.30.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 1 unused cells and 5 unused wires. <suppressed ~2 debug messages> 24.30.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~7 debug messages> 24.30.9. Rerunning OPT passes. (Maybe there is more to do..) 24.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~112 debug messages> 24.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 24.30.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 24.30.13. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$6568 ($sdffe) from module processorci_top. Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$6727 ($sdffe) from module processorci_top. Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$6739 ($sdff) from module processorci_top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$6739 ($sdff) from module processorci_top. Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$6739 ($sdff) from module processorci_top. Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$6739 ($sdff) from module processorci_top. Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$6739 ($sdff) from module processorci_top. Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$6774 ($sdff) from module processorci_top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$6818 ($sdffe) from module processorci_top. Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$6846 ($sdffe) from module processorci_top. Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$6948 ($sdffe) from module processorci_top. Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$6948 ($sdffe) from module processorci_top. Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$6948 ($sdffe) from module processorci_top. Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$6975 ($dffe) from module processorci_top. Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$6975 ($dffe) from module processorci_top. Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$6975 ($dffe) from module processorci_top. Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$6975 ($dffe) from module processorci_top. Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$6975 ($dffe) from module processorci_top. Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$6975 ($dffe) from module processorci_top. Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$6975 ($dffe) from module processorci_top. Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$6975 ($dffe) from module processorci_top. 24.30.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 4 unused wires. <suppressed ~1 debug messages> 24.30.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~7 debug messages> 24.30.16. Rerunning OPT passes. (Maybe there is more to do..) 24.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~112 debug messages> 24.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1648: Old ports: A=8'00000100, B={ 3'000 \Controller.Interpreter.return_state [4:0] }, Y=$flatten\Controller.\Interpreter.$procmux$1648_Y New ports: A=5'00100, B=\Controller.Interpreter.return_state [4:0], Y=$flatten\Controller.\Interpreter.$procmux$1648_Y [4:0] New connections: $flatten\Controller.\Interpreter.$procmux$1648_Y [7:5] = 3'000 Optimizing cells in module \processorci_top. Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$1626: Old ports: A=8'00000000, B={ 7'0000000 $auto$wreduce.cc:461:run$7052 [0] 6'000000 $auto$wreduce.cc:461:run$7045 [1:0] 1'0 $auto$wreduce.cc:461:run$7050 [6:0] 14'00001101000011 $auto$wreduce.cc:461:run$7049 [1:0] 3'000 \Controller.Interpreter.return_state [4:0] 1'0 $auto$wreduce.cc:461:run$7048 [6] 1'0 $auto$wreduce.cc:461:run$7048 [6] 3'011 $auto$wreduce.cc:461:run$7048 [6] 7'0000011 \Controller.Uart.read_response 4'0000 $auto$wreduce.cc:461:run$7044 [3] 2'00 $auto$wreduce.cc:461:run$7044 [3] 6'000010 $auto$wreduce.cc:461:run$7045 [1:0] 20'00001000000010110000 $auto$wreduce.cc:461:run$7044 [3] $auto$wreduce.cc:461:run$7044 [3] 18'000000010100000100 $flatten\Controller.\Interpreter.$procmux$1648_Y 1'0 $auto$wreduce.cc:461:run$7043 [6] 3'010 $auto$wreduce.cc:461:run$7043 [2] $auto$wreduce.cc:461:run$7043 [6] $auto$wreduce.cc:461:run$7043 [2] 13'0001001100010 $auto$wreduce.cc:461:run$7042 [2:1] $auto$wreduce.cc:461:run$7042 [1] 31'0001011001010010000100000001000 $auto$wreduce.cc:461:run$7041 [0] 8'00000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1626_Y New ports: A=7'0000000, B={ 6'000000 $auto$wreduce.cc:461:run$7052 [0] 5'00000 $auto$wreduce.cc:461:run$7045 [1:0] $auto$wreduce.cc:461:run$7050 [6:0] 12'000110100011 $auto$wreduce.cc:461:run$7049 [1:0] 2'00 \Controller.Interpreter.return_state [4:0] $auto$wreduce.cc:461:run$7048 [6] 1'0 $auto$wreduce.cc:461:run$7048 [6] 3'011 $auto$wreduce.cc:461:run$7048 [6] 6'000011 \Controller.Uart.read_response 3'000 $auto$wreduce.cc:461:run$7044 [3] 2'00 $auto$wreduce.cc:461:run$7044 [3] 5'00010 $auto$wreduce.cc:461:run$7045 [1:0] 17'00010000001011000 $auto$wreduce.cc:461:run$7044 [3] $auto$wreduce.cc:461:run$7044 [3] 18'000000101000010000 $flatten\Controller.\Interpreter.$procmux$1648_Y [4:0] $auto$wreduce.cc:461:run$7043 [6] 3'010 $auto$wreduce.cc:461:run$7043 [2] $auto$wreduce.cc:461:run$7043 [6] $auto$wreduce.cc:461:run$7043 [2] 11'00100110010 $auto$wreduce.cc:461:run$7042 [2:1] $auto$wreduce.cc:461:run$7042 [1] 27'001011010100100010000001000 $auto$wreduce.cc:461:run$7041 [0] 7'0000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1626_Y [6:0] New connections: $flatten\Controller.\Interpreter.$procmux$1626_Y [7] = 1'0 Optimizing cells in module \processorci_top. Performed a total of 2 changes. 24.30.19. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~3 debug messages> Removed a total of 1 cells. 24.30.20. Executing OPT_DFF pass (perform DFF optimizations). 24.30.21. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 3 unused wires. <suppressed ~1 debug messages> 24.30.22. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 24.30.23. Rerunning OPT passes. (Maybe there is more to do..) 24.30.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~112 debug messages> 24.30.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 24.30.26. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 24.30.27. Executing OPT_DFF pass (perform DFF optimizations). Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$7012 ($sdff) from module processorci_top. 24.30.28. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 24.30.29. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~1 debug messages> 24.30.30. Rerunning OPT passes. (Maybe there is more to do..) 24.30.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. Evaluating internal representation of mux trees. Analyzing evaluation results. Removed 0 multiplexer ports. <suppressed ~112 debug messages> 24.30.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 24.30.33. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 24.30.34. Executing OPT_DFF pass (perform DFF optimizations). 24.30.35. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 24.30.36. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 24.30.37. Finished OPT passes. (There is nothing left to do.) 24.31. Executing TECHMAP pass (map to technology primitives). 24.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 24.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation. Generating RTLIL representation for module `\_80_ecp5_alu'. Successfully finished Verilog frontend. 24.31.3. Continuing TECHMAP pass. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $and. Using extmapper simplemap for cells of type $reduce_bool. Using extmapper simplemap for cells of type $eq. Using extmapper simplemap for cells of type $reduce_or. Using extmapper simplemap for cells of type $mux. Using template $paramod$constmap:a40e3cf6629147c9dca71662bcd34ce89a9f9989$paramod$feecc7a0dbd012970970f2858f15e786e251f677\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr. Using extmapper simplemap for cells of type $reduce_and. Using extmapper simplemap for cells of type $sdff. Using extmapper simplemap for cells of type $dff. Using extmapper simplemap for cells of type $ne. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $sdffe. Using extmapper simplemap for cells of type $xor. Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu. Analyzing pattern of constant bits for this cell: Creating constmapped module `$paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$feecc7a0dbd012970970f2858f15e786e251f677\_90_shift_ops_shr_shl_sshl_sshr'. 24.31.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$feecc7a0dbd012970970f2858f15e786e251f677\_90_shift_ops_shr_shl_sshl_sshr.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. <suppressed ~755 debug messages> 24.31.12. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$feecc7a0dbd012970970f2858f15e786e251f677\_90_shift_ops_shr_shl_sshl_sshr. <suppressed ~320 debug messages> Removed 0 unused cells and 14 unused wires. Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$feecc7a0dbd012970970f2858f15e786e251f677\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shr. Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ecp5_alu for cells of type $alu. Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ecp5_alu for cells of type $alu. Using template $paramod$039520c137afc9cd69dd56c3fb11a4e1fbe5f664\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $dffe. Using template $paramod$bdc78fe5225b43c64ccdf13e5eb67d9dcf228e8a\_80_ecp5_alu for cells of type $alu. Using template $paramod$ff467a932a72bec5a93c27dba04bf3daba067451\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $logic_not. Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu. Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu. Using template $paramod$79aa992f2eb7f354d4aaf651790713cf239111fa\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $logic_or. Using template $paramod$c9511eeb847f2aa95252b1013477609463f67ee0\_80_ecp5_alu for cells of type $alu. Using template $paramod$a7b312e4ba8fdc79d4c5e0789e4e6c41ea3896fb\_90_pmux for cells of type $pmux. Using template $paramod$7a385d5b7a2e603dbc5beef838648775b433f248\_90_pmux for cells of type $pmux. Using template $paramod$824a2ca00d29d886599434cf8ea60471635f2955\_90_demux for cells of type $demux. Using template $paramod$54a4503cc57b9df40b70c1899504d6aac2650719\_90_pmux for cells of type $pmux. Using template $paramod$59b03ae2620a41577de8da5f5c97b2919e82362b\_90_pmux for cells of type $pmux. Using template $paramod$24fb226dd75c9d3f6955ec2ad61d794776778cf6\_90_pmux for cells of type $pmux. Using template $paramod$cc1e387d9d5ac1d3f6e6bed180038d9c0ac48d0c\_90_pmux for cells of type $pmux. Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux. Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux. Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $logic_and. Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux. Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu. Using template $paramod$ac45afa5bcd8e16ca475cce13f9d19bb109f1516\_80_ecp5_alu for cells of type $alu. Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux. Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu. Using template $paramod$constmap:4621fcf06a436d1e2a4080e2ed9866a7d07a6e07$paramod$335cfd09f1afa8139c4aafcbbe5f361887b79c5e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $shl. Using extmapper simplemap for cells of type $lut. Using template $paramod$d7c91f8d4ce389beb1bd34b271e05fae2549a2a8\_80_ecp5_alu for cells of type $alu. Using template $paramod$c04af8dbf0e5d1d69bbccb2c7bd8a93fc9ef54dc\_80_ecp5_alu for cells of type $alu. Using template $paramod$eaeb96106163dbf82031649d189817109fe07c69\_90_demux for cells of type $demux. Using extmapper simplemap for cells of type $bmux. Using template $paramod$c6baa65225090ac0a120feab1b920965244aa496\_80_ecp5_alu for cells of type $alu. Using template $paramod$c5c783b17ab1d780abfad8cfe6563a0a7b47a3b0\_90_pmux for cells of type $pmux. Using template $paramod$cc80a4e89b0341cb117f5d28b0e7244620640141\_80_ecp5_alu for cells of type $alu. Using template $paramod$44a13d10af618e7fbe7b9aad2f6151ffcee1e2fa\_80_ecp5_alu for cells of type $alu. Using template $paramod$7e708ae28ab761f11d0fb59d3ffc72f6a4baf5d9\_90_alu for cells of type $alu. Using template $paramod$2653f68ddb8eab7b1907b4a20767b72a824a7a36\_80_ecp5_alu for cells of type $alu. Using template $paramod$c96def1cdcef2eee3c62e5dfb7ba2dd09c9f74dd\_90_pmux for cells of type $pmux. Using template $paramod$eaeb96106163dbf82031649d189817109fe07c69\_90_pmux for cells of type $pmux. Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux. Using template $paramod$fbf9cabb1106ebb19d2876bda35dcfbc3788d13d\_80_ecp5_alu for cells of type $alu. Using template $paramod$b098bc6f249c0ac91c4d6e19d54b23c285914115\_90_pmux for cells of type $pmux. Using template $paramod$49f1dc3dcd6d2c748486fe94c6744a34a19bbafe\_90_pmux for cells of type $pmux. Using template $paramod$fedb90247e1daaa8b0af86a595f377181f141d27\_90_pmux for cells of type $pmux. Using template $paramod$8e2cd9e836d46c40867c8d0d57053a4e1c3bcdbc\_90_pmux for cells of type $pmux. Using template $paramod$b3b6ac92d800c6f07aa48f510f923d86a674e5a7\_90_pmux for cells of type $pmux. Using template $paramod$c07880a582d15b9cc7030b06c09885efa6c47302\_90_pmux for cells of type $pmux. Using template $paramod$bf8e268f26361094a16ad6650df0ad1ca719658a\_90_pmux for cells of type $pmux. Using template $paramod$861f5302217787cd55fd1a501bc728125f176580\_80_ecp5_alu for cells of type $alu. Using template $paramod$c2e415ef15bc3ccd2723772353a6b450d3d76206\_90_pmux for cells of type $pmux. Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux. Using extmapper simplemap for cells of type $sdffce. Using template $paramod$610911f8769324f781128d641f7fe2120143c328\_80_ecp5_alu for cells of type $alu. Using extmapper simplemap for cells of type $pos. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu. Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux. Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu. Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux. No more expansions possible. <suppressed ~6597 debug messages> 24.32. Executing OPT pass (performing simple optimizations). 24.32.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~13323 debug messages> 24.32.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~5994 debug messages> Removed a total of 1998 cells. 24.32.3. Executing OPT_DFF pass (perform DFF optimizations). 24.32.4. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 2071 unused cells and 8501 unused wires. <suppressed ~2077 debug messages> 24.32.5. Finished fast OPT passes. 24.33. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 24.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target). 24.35. Executing TECHMAP pass (map to technology primitives). 24.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Successfully finished Verilog frontend. 24.35.2. Continuing TECHMAP pass. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_. Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_. Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_. Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_. Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_. Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_. Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_. Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_. No more expansions possible. <suppressed ~1745 debug messages> 24.36. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~167 debug messages> 24.37. Executing SIMPLEMAP pass (map simple cells to gate primitives). 24.38. Executing LATTICE_GSR pass (implement FF init values). Handling GSR in processorci_top. 24.39. Executing ATTRMVCP pass (move or copy attributes). 24.40. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 9035 unused wires. <suppressed ~1 debug messages> 24.41. Executing TECHMAP pass (map to technology primitives). 24.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation. Generating RTLIL representation for module `\$_DLATCH_N_'. Generating RTLIL representation for module `\$_DLATCH_P_'. Successfully finished Verilog frontend. 24.41.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~4 debug messages> 24.42. Executing ABC9 pass. 24.42.1. Executing ABC9_OPS pass (helper functions for ABC9). 24.42.2. Executing ABC9_OPS pass (helper functions for ABC9). 24.42.3. Executing PROC pass (convert processes to netlists). 24.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$54762'. Cleaned up 1 empty switch. 24.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$54763 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Removed a total of 0 dead cases. 24.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 22 assignments to connections. 24.42.3.4. Executing PROC_INIT pass (extract init attributes). 24.42.3.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.3.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. <suppressed ~1 debug messages> 24.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers). Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$54787'. Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$54763'. 1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$54761_EN[3:0]$54769 2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$54761_DATA[3:0]$54768 3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$54761_ADDR[3:0]$54767 Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$54762'. 24.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$54747_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$54748_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$54749_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$54753_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$54754_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$54755_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$54751_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$54759_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$54745_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$54760_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$54750_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$54756_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$54757_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$54758_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$54752_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$54746_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$54787'. created direct connection (no actual register cell created). Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$54761_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$54763'. created $dff cell `$procdff$54813' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$54761_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$54763'. created $dff cell `$procdff$54814' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$54761_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$54763'. created $dff cell `$procdff$54815' with positive edge clock. Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$54762'. created direct connection (no actual register cell created). 24.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$54787'. Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$54763'. Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$54762'. Cleaned up 1 empty switch. 24.42.3.12. Executing OPT_EXPR pass (perform const folding). 24.42.4. Executing SCC pass (detecting logic loops). Found an SCC: $auto$simplemap.cc:38:simplemap_not$21112 $auto$ff.cc:266:slice$22799 $auto$ff.cc:266:slice$22802 $auto$ff.cc:266:slice$22798 $auto$simplemap.cc:38:simplemap_not$37267 $auto$ff.cc:266:slice$22858 $auto$simplemap.cc:38:simplemap_not$36864 $auto$ff.cc:266:slice$22857 $auto$simplemap.cc:38:simplemap_not$29273 $auto$ff.cc:266:slice$22856 $auto$simplemap.cc:38:simplemap_not$36860 $auto$ff.cc:266:slice$22853 $auto$simplemap.cc:38:simplemap_not$29269 $auto$ff.cc:266:slice$22852 $auto$simplemap.cc:38:simplemap_not$29268 $auto$ff.cc:266:slice$22851 $auto$simplemap.cc:38:simplemap_not$29272 $auto$ff.cc:266:slice$22855 $auto$simplemap.cc:38:simplemap_not$29267 $auto$ff.cc:266:slice$22850 $auto$simplemap.cc:38:simplemap_not$29266 $auto$ff.cc:266:slice$22849 $auto$simplemap.cc:38:simplemap_not$36855 $auto$ff.cc:266:slice$22848 $auto$simplemap.cc:38:simplemap_not$36854 $auto$ff.cc:266:slice$22847 $auto$simplemap.cc:38:simplemap_not$37253 $auto$ff.cc:266:slice$22844 $auto$ff.cc:266:slice$22797 $auto$ff.cc:266:slice$22796 $auto$simplemap.cc:38:simplemap_not$29259 $auto$ff.cc:266:slice$22842 $auto$simplemap.cc:38:simplemap_not$29258 $auto$ff.cc:266:slice$22841 $auto$simplemap.cc:38:simplemap_not$29257 $auto$ff.cc:266:slice$22840 $auto$simplemap.cc:38:simplemap_not$37248 $auto$ff.cc:266:slice$22839 $auto$simplemap.cc:38:simplemap_not$29253 $auto$ff.cc:266:slice$22836 $auto$simplemap.cc:38:simplemap_not$29252 $auto$ff.cc:266:slice$22835 $auto$simplemap.cc:75:simplemap_bitop$29187 $auto$simplemap.cc:38:simplemap_not$29251 $auto$ff.cc:266:slice$22834 $auto$simplemap.cc:38:simplemap_not$29255 $auto$ff.cc:266:slice$22838 $auto$simplemap.cc:38:simplemap_not$29250 $auto$ff.cc:266:slice$22833 $auto$simplemap.cc:75:simplemap_bitop$29183 $auto$simplemap.cc:38:simplemap_not$29247 $auto$ff.cc:266:slice$22830 $auto$simplemap.cc:126:simplemap_reduce$10884 $auto$simplemap.cc:75:simplemap_bitop$29182 $auto$simplemap.cc:38:simplemap_not$29246 $auto$ff.cc:266:slice$22829 $auto$simplemap.cc:75:simplemap_bitop$29181 $auto$simplemap.cc:38:simplemap_not$36835 $auto$ff.cc:266:slice$22828 $auto$simplemap.cc:38:simplemap_not$29249 $auto$ff.cc:266:slice$22832 $auto$simplemap.cc:75:simplemap_bitop$37203 $auto$ff.cc:266:slice$22826 $auto$simplemap.cc:75:simplemap_bitop$29208 $auto$ff.cc:266:slice$22823 $auto$ff.cc:266:slice$22822 $auto$simplemap.cc:75:simplemap_bitop$29206 $auto$ff.cc:266:slice$22821 $auto$simplemap.cc:225:simplemap_logbin$37110 $auto$simplemap.cc:225:simplemap_logbin$37111 $auto$simplemap.cc:126:simplemap_reduce$10898 $auto$simplemap.cc:75:simplemap_bitop$29210 $auto$ff.cc:266:slice$22825 $auto$simplemap.cc:75:simplemap_bitop$29205 $auto$ff.cc:266:slice$22820 $auto$simplemap.cc:75:simplemap_bitop$29202 $auto$ff.cc:266:slice$22817 $auto$ff.cc:266:slice$22816 $auto$simplemap.cc:75:simplemap_bitop$37192 $auto$ff.cc:266:slice$22815 $auto$simplemap.cc:126:simplemap_reduce$10895 $auto$simplemap.cc:75:simplemap_bitop$29204 $auto$ff.cc:266:slice$22819 $auto$ff.cc:266:slice$22814 $auto$ff.cc:266:slice$22762 $auto$ff.cc:266:slice$22761 $auto$simplemap.cc:167:logic_reduce$20982 $auto$simplemap.cc:167:logic_reduce$20979 $auto$ff.cc:266:slice$22760 $auto$ff.cc:266:slice$22759 $auto$opt_expr.cc:617:replace_const_cells$50265 $auto$ff.cc:266:slice$22756 $auto$simplemap.cc:75:simplemap_bitop$37189 $auto$ff.cc:266:slice$22812 $auto$ff.cc:266:slice$22811 $auto$simplemap.cc:75:simplemap_bitop$29195 $auto$ff.cc:266:slice$22810 $auto$simplemap.cc:126:simplemap_reduce$20999 $auto$ff.cc:266:slice$22758 $auto$simplemap.cc:126:simplemap_reduce$10890 $auto$simplemap.cc:75:simplemap_bitop$29194 $auto$ff.cc:266:slice$22809 $auto$simplemap.cc:75:simplemap_bitop$29191 $auto$ff.cc:266:slice$22806 $auto$ff.cc:266:slice$22805 $auto$simplemap.cc:75:simplemap_bitop$29189 $auto$ff.cc:266:slice$22804 $auto$simplemap.cc:75:simplemap_bitop$29193 $auto$ff.cc:266:slice$22808 $auto$simplemap.cc:126:simplemap_reduce$10887 $auto$simplemap.cc:75:simplemap_bitop$29188 $auto$ff.cc:266:slice$22803 $auto$opt_expr.cc:617:replace_const_cells$50249 $auto$ff.cc:266:slice$22745 $auto$opt_expr.cc:617:replace_const_cells$50335 $auto$ff.cc:266:slice$22737 $auto$opt_expr.cc:617:replace_const_cells$50237 $auto$ff.cc:266:slice$22744 $auto$opt_expr.cc:617:replace_const_cells$51337 $auto$ff.cc:266:slice$22736 $auto$opt_expr.cc:617:replace_const_cells$51343 $auto$ff.cc:266:slice$22733 $auto$simplemap.cc:126:simplemap_reduce$22199 $auto$simplemap.cc:126:simplemap_reduce$22196 $auto$simplemap.cc:126:simplemap_reduce$22243 $auto$simplemap.cc:126:simplemap_reduce$22240 $auto$simplemap.cc:126:simplemap_reduce$22267 $auto$simplemap.cc:126:simplemap_reduce$22264 $auto$opt_expr.cc:617:replace_const_cells$51345 $auto$ff.cc:266:slice$22735 $auto$simplemap.cc:126:simplemap_reduce$22172 $auto$simplemap.cc:126:simplemap_reduce$22217 $auto$opt_expr.cc:617:replace_const_cells$50353 $auto$simplemap.cc:126:simplemap_reduce$22285 $auto$ff.cc:266:slice$22734 $auto$opt_expr.cc:617:replace_const_cells$51339 $auto$ff.cc:266:slice$22731 $auto$simplemap.cc:38:simplemap_not$29244 $auto$ff.cc:266:slice$22827 $auto$alumacc.cc:485:replace_alu$7326.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$7326.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$10900 $auto$simplemap.cc:126:simplemap_reduce$10883 $auto$simplemap.cc:75:simplemap_bitop$29180 $auto$alumacc.cc:485:replace_alu$7308.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[0].ccu2c_i $auto$ff.cc:266:slice$22795 $auto$simplemap.cc:196:simplemap_lognot$20553 $auto$simplemap.cc:126:simplemap_reduce$20551 $auto$simplemap.cc:196:simplemap_lognot$21552 $auto$simplemap.cc:126:simplemap_reduce$21550 $auto$simplemap.cc:126:simplemap_reduce$22175 $auto$simplemap.cc:196:simplemap_lognot$22203 $auto$simplemap.cc:126:simplemap_reduce$22201 $auto$simplemap.cc:126:simplemap_reduce$25635 $auto$simplemap.cc:196:simplemap_lognot$22225 $auto$simplemap.cc:126:simplemap_reduce$22223 $auto$simplemap.cc:126:simplemap_reduce$22220 $auto$simplemap.cc:126:simplemap_reduce$41068 $auto$simplemap.cc:126:simplemap_reduce$25637 $auto$simplemap.cc:196:simplemap_lognot$22247 $auto$simplemap.cc:126:simplemap_reduce$22245 $auto$simplemap.cc:126:simplemap_reduce$22288 $auto$simplemap.cc:126:simplemap_reduce$22284 $auto$opt_expr.cc:617:replace_const_cells$51341 $auto$ff.cc:266:slice$22732 $auto$simplemap.cc:196:simplemap_lognot$21398 $auto$simplemap.cc:126:simplemap_reduce$21396 $auto$simplemap.cc:126:simplemap_reduce$21433 $auto$simplemap.cc:126:simplemap_reduce$37749 $auto$simplemap.cc:196:simplemap_lognot$21353 $auto$simplemap.cc:126:simplemap_reduce$21351 $auto$simplemap.cc:126:simplemap_reduce$21420 $auto$simplemap.cc:196:simplemap_lognot$21411 $auto$simplemap.cc:126:simplemap_reduce$21409 $auto$simplemap.cc:75:simplemap_bitop$38253 $auto$simplemap.cc:196:simplemap_lognot$21450 $auto$simplemap.cc:126:simplemap_reduce$21448 $auto$simplemap.cc:126:simplemap_reduce$21446 $auto$opt_expr.cc:617:replace_const_cells$50239 $auto$simplemap.cc:126:simplemap_reduce$38241 $auto$simplemap.cc:126:simplemap_reduce$40379 $auto$simplemap.cc:196:simplemap_lognot$21525 $auto$simplemap.cc:126:simplemap_reduce$21523 $auto$simplemap.cc:126:simplemap_reduce$38243 $auto$simplemap.cc:126:simplemap_reduce$38262 $auto$simplemap.cc:196:simplemap_lognot$21530 $auto$simplemap.cc:167:logic_reduce$21529 $auto$simplemap.cc:167:logic_reduce$21527 $auto$ff.cc:266:slice$22743 $auto$opt_expr.cc:617:replace_const_cells$51095 $auto$simplemap.cc:267:simplemap_mux$20421 $auto$simplemap.cc:267:simplemap_mux$20454 $auto$simplemap.cc:267:simplemap_mux$20847 $auto$simplemap.cc:225:simplemap_logbin$20576 $auto$simplemap.cc:196:simplemap_lognot$20575 $auto$simplemap.cc:126:simplemap_reduce$20573 $auto$simplemap.cc:126:simplemap_reduce$20570 $auto$simplemap.cc:126:simplemap_reduce$20566 $auto$ff.cc:266:slice$22757 $auto$simplemap.cc:75:simplemap_bitop$29185 $auto$ff.cc:266:slice$22800 $auto$simplemap.cc:126:simplemap_reduce$10886 $auto$simplemap.cc:75:simplemap_bitop$29186 $auto$ff.cc:266:slice$22801 $auto$simplemap.cc:126:simplemap_reduce$10903 $auto$simplemap.cc:126:simplemap_reduce$10889 $auto$simplemap.cc:75:simplemap_bitop$29192 $auto$ff.cc:266:slice$22807 $auto$ff.cc:266:slice$22813 $auto$simplemap.cc:126:simplemap_reduce$10894 $auto$simplemap.cc:75:simplemap_bitop$29203 $auto$ff.cc:266:slice$22818 $auto$simplemap.cc:126:simplemap_reduce$10907 $auto$simplemap.cc:126:simplemap_reduce$10897 $auto$simplemap.cc:75:simplemap_bitop$29209 $auto$ff.cc:266:slice$22824 $auto$alumacc.cc:485:replace_alu$7326.slice[8].ccu2c_i $auto$alumacc.cc:485:replace_alu$7326.slice[6].ccu2c_i $auto$alumacc.cc:485:replace_alu$7326.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[8].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[6].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[4].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$10909 $auto$simplemap.cc:126:simplemap_reduce$10901 $auto$simplemap.cc:126:simplemap_reduce$10885 $auto$simplemap.cc:75:simplemap_bitop$29184 $auto$simplemap.cc:38:simplemap_not$29248 $auto$ff.cc:266:slice$22831 $auto$alumacc.cc:485:replace_alu$7326.slice[14].ccu2c_i $auto$alumacc.cc:485:replace_alu$7326.slice[12].ccu2c_i $auto$alumacc.cc:485:replace_alu$7326.slice[10].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[14].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[12].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[10].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$10914 $auto$simplemap.cc:126:simplemap_reduce$10910 $auto$simplemap.cc:126:simplemap_reduce$10902 $auto$simplemap.cc:126:simplemap_reduce$10888 $auto$simplemap.cc:75:simplemap_bitop$29190 $auto$simplemap.cc:38:simplemap_not$29254 $auto$ff.cc:266:slice$22837 $auto$alumacc.cc:485:replace_alu$7326.slice[16].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[16].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$10891 $auto$simplemap.cc:75:simplemap_bitop$29196 $auto$simplemap.cc:38:simplemap_not$29260 $auto$ff.cc:266:slice$22843 $auto$simplemap.cc:75:simplemap_bitop$29198 $auto$simplemap.cc:38:simplemap_not$37254 $auto$ff.cc:266:slice$22845 $auto$alumacc.cc:485:replace_alu$7326.slice[24].ccu2c_i $auto$alumacc.cc:485:replace_alu$7326.slice[22].ccu2c_i $auto$alumacc.cc:485:replace_alu$7326.slice[20].ccu2c_i $auto$alumacc.cc:485:replace_alu$7326.slice[18].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[24].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[22].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[20].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[18].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$10904 $auto$simplemap.cc:126:simplemap_reduce$10892 $auto$simplemap.cc:75:simplemap_bitop$37191 $auto$simplemap.cc:38:simplemap_not$37255 $auto$ff.cc:266:slice$22846 $auto$simplemap.cc:75:simplemap_bitop$38256 $auto$simplemap.cc:38:simplemap_not$20750 $auto$simplemap.cc:126:simplemap_reduce$38245 $auto$simplemap.cc:75:simplemap_bitop$38257 $auto$simplemap.cc:126:simplemap_reduce$10985 $auto$simplemap.cc:38:simplemap_not$10995 $auto$simplemap.cc:75:simplemap_bitop$10881 $auto$simplemap.cc:38:simplemap_not$10970 $auto$alumacc.cc:485:replace_alu$7326.slice[30].ccu2c_i $auto$alumacc.cc:485:replace_alu$7326.slice[28].ccu2c_i $auto$alumacc.cc:485:replace_alu$7326.slice[26].ccu2c_i $auto$simplemap.cc:225:simplemap_logbin$37108 $auto$simplemap.cc:225:simplemap_logbin$37109 $auto$simplemap.cc:75:simplemap_bitop$10805 $auto$simplemap.cc:75:simplemap_bitop$38254 $auto$simplemap.cc:38:simplemap_not$20744 $auto$simplemap.cc:126:simplemap_reduce$38249 $auto$simplemap.cc:126:simplemap_reduce$38246 $auto$simplemap.cc:75:simplemap_bitop$38255 $auto$simplemap.cc:126:simplemap_reduce$10983 $auto$simplemap.cc:38:simplemap_not$10880 $auto$simplemap.cc:75:simplemap_bitop$10859 $auto$simplemap.cc:75:simplemap_bitop$10806 $auto$alumacc.cc:485:replace_alu$7308.slice[30].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[28].ccu2c_i $auto$alumacc.cc:485:replace_alu$7308.slice[26].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$10912 $auto$simplemap.cc:126:simplemap_reduce$10906 $auto$simplemap.cc:126:simplemap_reduce$10896 $auto$simplemap.cc:75:simplemap_bitop$29207 $auto$simplemap.cc:38:simplemap_not$29271 $auto$ff.cc:266:slice$22854 $auto$simplemap.cc:75:simplemap_bitop$22730 $auto$simplemap.cc:341:simplemap_lut$19493 $auto$opt_expr.cc:617:replace_const_cells$50381 $auto$ff.cc:266:slice$14521 $auto$opt_expr.cc:617:replace_const_cells$50385 $auto$ff.cc:266:slice$10532 $auto$ff.cc:266:slice$10559 $auto$simplemap.cc:126:simplemap_reduce$27491 $auto$ff.cc:266:slice$10558 $auto$simplemap.cc:126:simplemap_reduce$27476 $auto$opt_expr.cc:617:replace_const_cells$50383 $auto$ff.cc:266:slice$10529 $auto$ff.cc:266:slice$10555 $auto$opt_expr.cc:617:replace_const_cells$50391 $auto$ff.cc:266:slice$10549 $auto$ff.cc:266:slice$10543 $auto$ff.cc:266:slice$10537 $auto$ff.cc:266:slice$10531 $auto$ff.cc:266:slice$10552 $auto$ff.cc:266:slice$10545 $auto$ff.cc:266:slice$10540 $auto$opt_expr.cc:617:replace_const_cells$50393 $auto$ff.cc:266:slice$10556 $auto$simplemap.cc:126:simplemap_reduce$27480 $auto$ff.cc:266:slice$10536 $auto$ff.cc:266:slice$10535 $auto$simplemap.cc:126:simplemap_reduce$27484 $auto$ff.cc:266:slice$10544 $auto$simplemap.cc:126:simplemap_reduce$27488 $auto$ff.cc:266:slice$10553 $auto$ff.cc:266:slice$10551 $auto$simplemap.cc:126:simplemap_reduce$27499 $auto$simplemap.cc:126:simplemap_reduce$27489 $auto$ff.cc:266:slice$10554 $auto$simplemap.cc:126:simplemap_reduce$27493 $auto$simplemap.cc:126:simplemap_reduce$27477 $auto$ff.cc:266:slice$10530 $auto$simplemap.cc:126:simplemap_reduce$27478 $auto$opt_expr.cc:617:replace_const_cells$50387 $auto$ff.cc:266:slice$10533 $auto$simplemap.cc:126:simplemap_reduce$27331 $auto$simplemap.cc:126:simplemap_reduce$27405 $auto$opt_expr.cc:617:replace_const_cells$50379 $auto$simplemap.cc:126:simplemap_reduce$27486 $auto$ff.cc:266:slice$10548 $auto$simplemap.cc:126:simplemap_reduce$27343 $auto$simplemap.cc:126:simplemap_reduce$27417 $auto$simplemap.cc:126:simplemap_reduce$27498 $auto$simplemap.cc:126:simplemap_reduce$27487 $auto$ff.cc:266:slice$10550 $auto$ff.cc:266:slice$10538 $auto$simplemap.cc:126:simplemap_reduce$27424 $auto$simplemap.cc:126:simplemap_reduce$27419 $auto$simplemap.cc:126:simplemap_reduce$27409 $auto$simplemap.cc:126:simplemap_reduce$27505 $auto$simplemap.cc:126:simplemap_reduce$27500 $auto$simplemap.cc:126:simplemap_reduce$27490 $auto$opt_expr.cc:617:replace_const_cells$50395 $auto$ff.cc:266:slice$10557 $auto$ff.cc:266:slice$10546 $auto$simplemap.cc:126:simplemap_reduce$27353 $auto$simplemap.cc:126:simplemap_reduce$27349 $auto$simplemap.cc:126:simplemap_reduce$27427 $auto$simplemap.cc:126:simplemap_reduce$27423 $auto$simplemap.cc:126:simplemap_reduce$27508 $auto$simplemap.cc:126:simplemap_reduce$27504 $auto$simplemap.cc:126:simplemap_reduce$27497 $auto$simplemap.cc:126:simplemap_reduce$27485 $auto$ff.cc:266:slice$10547 $auto$simplemap.cc:126:simplemap_reduce$27482 $auto$ff.cc:266:slice$10541 $auto$simplemap.cc:126:simplemap_reduce$27495 $auto$simplemap.cc:126:simplemap_reduce$27481 $auto$ff.cc:266:slice$10539 $auto$simplemap.cc:126:simplemap_reduce$27503 $auto$simplemap.cc:126:simplemap_reduce$27496 $auto$simplemap.cc:126:simplemap_reduce$27483 $auto$ff.cc:266:slice$10542 $auto$simplemap.cc:196:simplemap_lognot$27357 $auto$simplemap.cc:126:simplemap_reduce$27355 $auto$simplemap.cc:267:simplemap_mux$27805 $auto$simplemap.cc:267:simplemap_mux$27802 $auto$simplemap.cc:126:simplemap_reduce$47494 $auto$simplemap.cc:196:simplemap_lognot$27431 $auto$simplemap.cc:126:simplemap_reduce$27429 $auto$simplemap.cc:126:simplemap_reduce$27939 $auto$opt_expr.cc:617:replace_const_cells$50397 $auto$simplemap.cc:267:simplemap_mux$27804 $auto$simplemap.cc:267:simplemap_mux$27801 $auto$simplemap.cc:75:simplemap_bitop$27283 $auto$simplemap.cc:126:simplemap_reduce$27941 $auto$simplemap.cc:267:simplemap_mux$27806 $auto$simplemap.cc:267:simplemap_mux$27803 $auto$simplemap.cc:196:simplemap_lognot$27512 $auto$simplemap.cc:126:simplemap_reduce$27510 $auto$simplemap.cc:126:simplemap_reduce$27507 $auto$simplemap.cc:126:simplemap_reduce$27502 $auto$simplemap.cc:126:simplemap_reduce$27494 $auto$simplemap.cc:126:simplemap_reduce$27479 $auto$opt_expr.cc:617:replace_const_cells$50389 $auto$ff.cc:266:slice$10534 $auto$simplemap.cc:126:simplemap_reduce$19534 $auto$simplemap.cc:75:simplemap_bitop$26050 $auto$simplemap.cc:225:simplemap_logbin$27249 $auto$simplemap.cc:225:simplemap_logbin$27248 $auto$simplemap.cc:225:simplemap_logbin$20466 $auto$simplemap.cc:225:simplemap_logbin$20465 $auto$simplemap.cc:267:simplemap_mux$41105 $auto$simplemap.cc:126:simplemap_reduce$41102 $auto$simplemap.cc:75:simplemap_bitop$41103 $auto$simplemap.cc:267:simplemap_mux$38258 $auto$simplemap.cc:126:simplemap_reduce$38251 $auto$simplemap.cc:126:simplemap_reduce$38247 $auto$simplemap.cc:75:simplemap_bitop$38252 $auto$simplemap.cc:126:simplemap_reduce$10858 $auto$simplemap.cc:126:simplemap_reduce$10915 $auto$simplemap.cc:126:simplemap_reduce$10911 $auto$simplemap.cc:126:simplemap_reduce$10905 $auto$simplemap.cc:126:simplemap_reduce$10893 $auto$simplemap.cc:75:simplemap_bitop$37193 Found an SCC: $auto$opt_expr.cc:617:replace_const_cells$50687 $auto$ff.cc:266:slice$15193 $auto$opt_expr.cc:617:replace_const_cells$50659 $auto$ff.cc:266:slice$15196 $auto$simplemap.cc:126:simplemap_reduce$15309 $auto$simplemap.cc:126:simplemap_reduce$15294 $auto$ff.cc:266:slice$15194 $auto$simplemap.cc:75:simplemap_bitop$30363 $auto$simplemap.cc:196:simplemap_lognot$15314 $auto$simplemap.cc:126:simplemap_reduce$15312 $auto$simplemap.cc:126:simplemap_reduce$15310 $auto$opt_expr.cc:617:replace_const_cells$50679 $auto$simplemap.cc:267:simplemap_mux$30359 $auto$simplemap.cc:126:simplemap_reduce$30373 $auto$simplemap.cc:126:simplemap_reduce$30370 $auto$simplemap.cc:225:simplemap_logbin$15240 $auto$simplemap.cc:196:simplemap_lognot$15250 $auto$simplemap.cc:126:simplemap_reduce$15248 $auto$opt_expr.cc:617:replace_const_cells$50677 $auto$simplemap.cc:267:simplemap_mux$30360 $auto$simplemap.cc:126:simplemap_reduce$30378 $auto$simplemap.cc:126:simplemap_reduce$30375 $auto$simplemap.cc:75:simplemap_bitop$30361 $auto$simplemap.cc:267:simplemap_mux$15281 $auto$simplemap.cc:225:simplemap_logbin$15284 $auto$simplemap.cc:196:simplemap_lognot$15299 $auto$simplemap.cc:126:simplemap_reduce$15297 $auto$simplemap.cc:126:simplemap_reduce$15295 $auto$ff.cc:266:slice$15195 $auto$simplemap.cc:126:simplemap_reduce$16261 $auto$simplemap.cc:126:simplemap_reduce$16259 Found an SCC: $auto$simplemap.cc:126:simplemap_reduce$16365 $auto$simplemap.cc:126:simplemap_reduce$16326 $auto$simplemap.cc:126:simplemap_reduce$16368 $auto$simplemap.cc:126:simplemap_reduce$16366 $auto$simplemap.cc:38:simplemap_not$16648 $auto$simplemap.cc:38:simplemap_not$30329 $auto$ff.cc:266:slice$27989 $auto$ff.cc:479:convert_ce_over_srst$53027 $auto$simplemap.cc:126:simplemap_reduce$10999 $auto$ff.cc:266:slice$27988 $auto$ff.cc:479:convert_ce_over_srst$53025 $auto$simplemap.cc:38:simplemap_not$30327 $auto$ff.cc:266:slice$27987 $auto$ff.cc:479:convert_ce_over_srst$53023 $auto$simplemap.cc:126:simplemap_reduce$10998 $auto$ff.cc:266:slice$27986 $auto$ff.cc:479:convert_ce_over_srst$53021 $auto$simplemap.cc:38:simplemap_not$10822 $auto$alumacc.cc:485:replace_alu$7155.slice[4].ccu2c_i $auto$alumacc.cc:485:replace_alu$7155.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$7155.slice[0].ccu2c_i $auto$simplemap.cc:38:simplemap_not$30325 $auto$ff.cc:266:slice$27985 $auto$ff.cc:479:convert_ce_over_srst$53019 $auto$simplemap.cc:126:simplemap_reduce$26821 $auto$simplemap.cc:75:simplemap_bitop$16509 $auto$simplemap.cc:126:simplemap_reduce$11003 $auto$simplemap.cc:126:simplemap_reduce$11001 $auto$simplemap.cc:126:simplemap_reduce$10997 $auto$opt_expr.cc:617:replace_const_cells$50683 $auto$ff.cc:266:slice$27984 $auto$ff.cc:479:convert_ce_over_srst$53017 $auto$simplemap.cc:126:simplemap_reduce$16328 Found an SCC: $auto$opt_expr.cc:617:replace_const_cells$50685 $auto$ff.cc:266:slice$15059 $auto$simplemap.cc:126:simplemap_reduce$15175 $auto$simplemap.cc:126:simplemap_reduce$15148 $auto$ff.cc:266:slice$15060 $auto$simplemap.cc:38:simplemap_not$30381 $auto$ff.cc:266:slice$15061 $auto$simplemap.cc:126:simplemap_reduce$15180 $auto$simplemap.cc:126:simplemap_reduce$15176 $auto$simplemap.cc:126:simplemap_reduce$15153 $auto$simplemap.cc:126:simplemap_reduce$15149 $auto$simplemap.cc:38:simplemap_not$30382 $auto$ff.cc:266:slice$15062 $auto$ff.cc:266:slice$15063 $auto$simplemap.cc:126:simplemap_reduce$15150 $auto$simplemap.cc:38:simplemap_not$30384 $auto$ff.cc:266:slice$15064 $auto$simplemap.cc:38:simplemap_not$30385 $auto$ff.cc:266:slice$15065 $auto$simplemap.cc:126:simplemap_reduce$15156 $auto$simplemap.cc:126:simplemap_reduce$15154 $auto$simplemap.cc:126:simplemap_reduce$15151 $auto$simplemap.cc:126:simplemap_reduce$15178 $auto$simplemap.cc:38:simplemap_not$30386 $auto$ff.cc:266:slice$15066 $auto$simplemap.cc:225:simplemap_logbin$15133 $auto$simplemap.cc:196:simplemap_lognot$15160 $auto$simplemap.cc:126:simplemap_reduce$15158 $auto$ff.cc:266:slice$15067 $auto$simplemap.cc:167:logic_reduce$27793 $auto$simplemap.cc:225:simplemap_logbin$15132 $auto$simplemap.cc:196:simplemap_lognot$15187 $auto$simplemap.cc:126:simplemap_reduce$15185 $auto$simplemap.cc:126:simplemap_reduce$15183 $auto$simplemap.cc:126:simplemap_reduce$15181 $auto$simplemap.cc:126:simplemap_reduce$15177 $auto$simplemap.cc:38:simplemap_not$30383 Found an SCC: $auto$opt_expr.cc:617:replace_const_cells$50681 $auto$ff.cc:266:slice$15197 $auto$simplemap.cc:126:simplemap_reduce$15329 $auto$ff.cc:266:slice$15198 $auto$ff.cc:266:slice$15199 $auto$simplemap.cc:126:simplemap_reduce$15334 $auto$simplemap.cc:126:simplemap_reduce$15330 $auto$simplemap.cc:38:simplemap_not$30277 $auto$ff.cc:266:slice$15200 $auto$simplemap.cc:38:simplemap_not$30278 $auto$ff.cc:266:slice$15201 $auto$simplemap.cc:126:simplemap_reduce$15331 $auto$ff.cc:266:slice$15202 $auto$simplemap.cc:38:simplemap_not$30280 $auto$ff.cc:266:slice$15203 $auto$simplemap.cc:126:simplemap_reduce$15337 $auto$simplemap.cc:126:simplemap_reduce$15335 $auto$simplemap.cc:126:simplemap_reduce$15332 $auto$simplemap.cc:38:simplemap_not$30281 $auto$ff.cc:266:slice$15204 $auto$simplemap.cc:126:simplemap_reduce$15339 $auto$ff.cc:266:slice$15205 $auto$simplemap.cc:126:simplemap_reduce$16273 $auto$simplemap.cc:196:simplemap_lognot$15341 Found 5 SCCs in module processorci_top. Found 5 SCCs. 24.42.5. Executing ABC9_OPS pass (helper functions for ABC9). 24.42.6. Executing PROC pass (convert processes to netlists). 24.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 24.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees). Removed a total of 0 dead cases. 24.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes). Removed 0 redundant assignments. Promoted 0 assignments to connections. 24.42.6.4. Executing PROC_INIT pass (extract init attributes). 24.42.6.5. Executing PROC_ARST pass (detect async resets in processes). 24.42.6.6. Executing PROC_ROM pass (convert switches to ROMs). Converted 0 switches. 24.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers). 24.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches). 24.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs). 24.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells). 24.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees). Cleaned up 0 empty switches. 24.42.6.12. Executing OPT_EXPR pass (perform const folding). 24.42.7. Executing TECHMAP pass (map to technology primitives). 24.42.7.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 24.42.7.2. Continuing TECHMAP pass. No more expansions possible. <suppressed ~162 debug messages> 24.42.8. Executing OPT pass (performing simple optimizations). 24.42.8.1. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. 24.42.8.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Removed a total of 0 cells. 24.42.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 24.42.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Performed a total of 0 changes. 24.42.8.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'. Removed a total of 0 cells. 24.42.8.6. Executing OPT_DFF pass (perform DFF optimizations). 24.42.8.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.. 24.42.8.8. Executing OPT_EXPR pass (perform const folding). Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. 24.42.8.9. Finished OPT passes. (There is nothing left to do.) 24.42.9. Executing TECHMAP pass (map to technology primitives). 24.42.9.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation. Successfully finished Verilog frontend. 24.42.9.2. Continuing TECHMAP pass. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. No more expansions possible. <suppressed ~1063 debug messages> 24.42.10. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation. Generating RTLIL representation for module `$__ABC9_DELAY'. Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'. Generating RTLIL representation for module `$__DFF_N__$abc9_flop'. Generating RTLIL representation for module `$__DFF_P__$abc9_flop'. Successfully finished Verilog frontend. 24.42.11. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 24.42.12. Executing ABC9_OPS pass (helper functions for ABC9). 24.42.13. Executing ABC9_OPS pass (helper functions for ABC9). <suppressed ~2 debug messages> 24.42.14. Executing TECHMAP pass (map to technology primitives). 24.42.14.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation. Generating RTLIL representation for module `\_90_simplemap_bool_ops'. Generating RTLIL representation for module `\_90_simplemap_reduce_ops'. Generating RTLIL representation for module `\_90_simplemap_logic_ops'. Generating RTLIL representation for module `\_90_simplemap_compare_ops'. Generating RTLIL representation for module `\_90_simplemap_various'. Generating RTLIL representation for module `\_90_simplemap_registers'. Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'. Generating RTLIL representation for module `\_90_shift_shiftx'. Generating RTLIL representation for module `\_90_fa'. Generating RTLIL representation for module `\_90_lcu_brent_kung'. Generating RTLIL representation for module `\_90_alu'. Generating RTLIL representation for module `\_90_macc'. Generating RTLIL representation for module `\_90_alumacc'. Generating RTLIL representation for module `\$__div_mod_u'. Generating RTLIL representation for module `\$__div_mod_trunc'. Generating RTLIL representation for module `\_90_div'. Generating RTLIL representation for module `\_90_mod'. Generating RTLIL representation for module `\$__div_mod_floor'. Generating RTLIL representation for module `\_90_divfloor'. Generating RTLIL representation for module `\_90_modfloor'. Generating RTLIL representation for module `\_90_pow'. Generating RTLIL representation for module `\_90_pmux'. Generating RTLIL representation for module `\_90_demux'. Generating RTLIL representation for module `\_90_lut'. Successfully finished Verilog frontend. 24.42.14.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using extmapper simplemap for cells of type $and. Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4. Using extmapper simplemap for cells of type $or. Using extmapper simplemap for cells of type $xor. Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2. Using extmapper simplemap for cells of type $not. Using extmapper simplemap for cells of type $mux. No more expansions possible. <suppressed ~201 debug messages> 24.42.15. Executing OPT pass (performing simple optimizations). 24.42.15.1. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. <suppressed ~18 debug messages> 24.42.15.2. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. <suppressed ~6 debug messages> Removed a total of 2 cells. 24.42.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 24.42.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 24.42.15.5. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 24.42.15.6. Executing OPT_DFF pass (perform DFF optimizations). 24.42.15.7. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. Removed 0 unused cells and 55 unused wires. <suppressed ~1 debug messages> 24.42.15.8. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 24.42.15.9. Rerunning OPT passes. (Maybe there is more to do..) 24.42.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees). Running muxtree optimizer on module \processorci_top.. Creating internal representation of mux trees. No muxes found in this module. Removed 0 multiplexer ports. 24.42.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs). Optimizing cells in module \processorci_top. Performed a total of 0 changes. 24.42.15.12. Executing OPT_MERGE pass (detect identical cells). Finding identical cells in module `\processorci_top'. Removed a total of 0 cells. 24.42.15.13. Executing OPT_DFF pass (perform DFF optimizations). 24.42.15.14. Executing OPT_CLEAN pass (remove unused cells and wires). Finding unused cells or wires in module \processorci_top.. 24.42.15.15. Executing OPT_EXPR pass (perform const folding). Optimizing module processorci_top. 24.42.15.16. Finished OPT passes. (There is nothing left to do.) 24.42.16. Executing AIGMAP pass (map logic to AIG). Module processorci_top: replaced 18 cells with 120 new cells, skipped 39 cells. replaced 3 cell types: 2 $_OR_ 2 $_XOR_ 14 $_MUX_ not replaced 3 cell types: 31 $specify2 4 $_NOT_ 4 $_AND_ 24.42.17. Executing AIGMAP pass (map logic to AIG). Module processorci_top: replaced 11874 cells with 72675 new cells, skipped 8934 cells. replaced 3 cell types: 3481 $_OR_ 273 $_XOR_ 8120 $_MUX_ not replaced 9 cell types: 38 $scopeinfo 1285 $_NOT_ 3344 $_AND_ 1630 TRELLIS_FF 4 MULT18X18D 512 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C 1060 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp 1060 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 1 $__ABC9_SCC_BREAKER 24.42.17.1. Executing ABC9_OPS pass (helper functions for ABC9). 24.42.17.2. Executing ABC9_OPS pass (helper functions for ABC9). 24.42.17.3. Executing XAIGER backend. <suppressed ~11 debug messages> Extracted 32004 AND gates and 90654 wires from module `processorci_top' to a netlist network with 6010 inputs and 2471 outputs. 24.42.17.4. Executing ABC9_EXE pass (technology mapping using ABC9). 24.42.17.5. Executing ABC9. Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1 ABC: ABC command line: "source <abc-temp-dir>/abc.script". ABC: ABC: + read_lut <abc-temp-dir>/input.lut ABC: + read_box <abc-temp-dir>/input.box ABC: + &read <abc-temp-dir>/input.xaig ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 6010/ 2471 and = 27374 lev = 62 (3.59) mem = 0.73 MB box = 1572 bb = 1060 ABC: Warning: AIG with boxes has internal fanout in 0 complex flops and 1 carries. ABC: + &scorr ABC: Warning: The network is combinational. ABC: + &sweep ABC: + &dc2 ABC: + &dch -f ABC: + &ps ABC: <abc-temp-dir>/input : i/o = 6010/ 2471 and = 30396 lev = 65 (2.68) mem = 0.77 MB ch = 2825 box = 1571 bb = 1060 ABC: + &if -W 300 -v ABC: K = 7. Memory (bytes): Truth = 0. Cut = 64. Obj = 148. Set = 672. CutMin = no ABC: Node = 30396. Ch = 2102. Total mem = 9.03 MB. Peak cut mem = 0.32 MB. ABC: P: Del = 6679.00. Ar = 33884.0. Edge = 38570. Cut = 350112. T = 0.18 sec ABC: P: Del = 6679.00. Ar = 33532.0. Edge = 38293. Cut = 346521. T = 0.18 sec ABC: P: Del = 6679.00. Ar = 12021.0. Edge = 28746. Cut = 938056. T = 0.40 sec ABC: F: Del = 6678.00. Ar = 8895.0. Edge = 25599. Cut = 677096. T = 0.31 sec ABC: A: Del = 6678.00. Ar = 8334.0. Edge = 24304. Cut = 643267. T = 0.44 sec ABC: A: Del = 6678.00. Ar = 8295.0. Edge = 24245. Cut = 653006. T = 0.45 sec ABC: Total time = 1.96 sec ABC: + &write -n <abc-temp-dir>/output.aig ABC: + &mfs ABC: + &ps -l ABC: <abc-temp-dir>/input : i/o = 6010/ 2471 and = 19616 lev = 46 (2.60) mem = 0.64 MB box = 1556 bb = 1060 ABC: Mapping (K=7) : lut = 6208 edge = 23952 lev = 14 (1.14) Boxes are not in a topological order. Switching to level computation without boxes. ABC: levB = 46 mem = 0.32 MB ABC: LUT = 6208 : 2=683 11.0 % 3=892 14.4 % 4=3603 58.0 % 5=801 12.9 % 6=110 1.8 % 7=119 1.9 % Ave = 3.86 ABC: + &write -n <abc-temp-dir>/output.aig ABC: + time ABC: elapse: 16.00 seconds, total: 16.00 seconds 24.42.17.6. Executing AIGER frontend. <suppressed ~16990 debug messages> Removed 26419 unused cells and 58183 unused wires. 24.42.17.7. Executing ABC9_OPS pass (helper functions for ABC9). ABC RESULTS: $lut cells: 6351 ABC RESULTS: $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells: 496 ABC RESULTS: $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells: 1060 ABC RESULTS: input signals: 1170 ABC RESULTS: output signals: 896 Removing temp directory. 24.42.18. Executing TECHMAP pass (map to technology primitives). 24.42.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation. Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'. Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'. Successfully finished Verilog frontend. 24.42.18.2. Continuing TECHMAP pass. Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4. Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp. Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000000111 for cells of type $__ABC9_SCC_BREAKER. No more expansions possible. <suppressed ~2636 debug messages> Removed 742 unused cells and 108062 unused wires. 24.43. Executing TECHMAP pass (map to technology primitives). 24.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation. Generating RTLIL representation for module `\$_DFF_N_'. Generating RTLIL representation for module `\$_DFF_P_'. Generating RTLIL representation for module `\$_DFFE_NN_'. Generating RTLIL representation for module `\$_DFFE_PN_'. Generating RTLIL representation for module `\$_DFFE_NP_'. Generating RTLIL representation for module `\$_DFFE_PP_'. Generating RTLIL representation for module `\$_DFF_NP0_'. Generating RTLIL representation for module `\$_DFF_NP1_'. Generating RTLIL representation for module `\$_DFF_PP0_'. Generating RTLIL representation for module `\$_DFF_PP1_'. Generating RTLIL representation for module `\$_SDFF_NP0_'. Generating RTLIL representation for module `\$_SDFF_NP1_'. Generating RTLIL representation for module `\$_SDFF_PP0_'. Generating RTLIL representation for module `\$_SDFF_PP1_'. Generating RTLIL representation for module `\$_DFFE_NP0P_'. Generating RTLIL representation for module `\$_DFFE_NP1P_'. Generating RTLIL representation for module `\$_DFFE_PP0P_'. Generating RTLIL representation for module `\$_DFFE_PP1P_'. Generating RTLIL representation for module `\$_DFFE_NP0N_'. Generating RTLIL representation for module `\$_DFFE_NP1N_'. Generating RTLIL representation for module `\$_DFFE_PP0N_'. Generating RTLIL representation for module `\$_DFFE_PP1N_'. Generating RTLIL representation for module `\$_SDFFE_NP0P_'. Generating RTLIL representation for module `\$_SDFFE_NP1P_'. Generating RTLIL representation for module `\$_SDFFE_PP0P_'. Generating RTLIL representation for module `\$_SDFFE_PP1P_'. Generating RTLIL representation for module `\$_SDFFE_NP0N_'. Generating RTLIL representation for module `\$_SDFFE_NP1N_'. Generating RTLIL representation for module `\$_SDFFE_PP0N_'. Generating RTLIL representation for module `\$_SDFFE_PP1N_'. Generating RTLIL representation for module `\$_ALDFF_NP_'. Generating RTLIL representation for module `\$_ALDFF_PP_'. Generating RTLIL representation for module `\$_ALDFFE_NPN_'. Generating RTLIL representation for module `\$_ALDFFE_NPP_'. Generating RTLIL representation for module `\$_ALDFFE_PPN_'. Generating RTLIL representation for module `\$_ALDFFE_PPP_'. Generating RTLIL representation for module `\FD1P3AX'. Generating RTLIL representation for module `\FD1P3AY'. Generating RTLIL representation for module `\FD1P3BX'. Generating RTLIL representation for module `\FD1P3DX'. Generating RTLIL representation for module `\FD1P3IX'. Generating RTLIL representation for module `\FD1P3JX'. Generating RTLIL representation for module `\FD1S3AX'. Generating RTLIL representation for module `\FD1S3AY'. Generating RTLIL representation for module `\FD1S3BX'. Generating RTLIL representation for module `\FD1S3DX'. Generating RTLIL representation for module `\FD1S3IX'. Generating RTLIL representation for module `\FD1S3JX'. Generating RTLIL representation for module `\IFS1P3BX'. Generating RTLIL representation for module `\IFS1P3DX'. Generating RTLIL representation for module `\IFS1P3IX'. Generating RTLIL representation for module `\IFS1P3JX'. Generating RTLIL representation for module `\OFS1P3BX'. Generating RTLIL representation for module `\OFS1P3DX'. Generating RTLIL representation for module `\OFS1P3IX'. Generating RTLIL representation for module `\OFS1P3JX'. Generating RTLIL representation for module `\IB'. Generating RTLIL representation for module `\IBPU'. Generating RTLIL representation for module `\IBPD'. Generating RTLIL representation for module `\OB'. Generating RTLIL representation for module `\OBZ'. Generating RTLIL representation for module `\OBZPU'. Generating RTLIL representation for module `\OBZPD'. Generating RTLIL representation for module `\OBCO'. Generating RTLIL representation for module `\BB'. Generating RTLIL representation for module `\BBPU'. Generating RTLIL representation for module `\BBPD'. Generating RTLIL representation for module `\ILVDS'. Generating RTLIL representation for module `\OLVDS'. Generating RTLIL representation for module `\$lut'. Successfully finished Verilog frontend. 24.43.2. Continuing TECHMAP pass. Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut. Using template $paramod$d1e25f9b6f7e1f42eba061bba9180274c7493947\$lut for cells of type $lut. Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut. Using template $paramod$a75bc0aeb8db44f671a62d5e64b8218a0983966e\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut. Using template $paramod$a18739d02b0df88fd2140685d9b0f234ab194f49\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut. Using template $paramod$71d09d8354f5555fb54ab0bd4f3934a22c793990\$lut for cells of type $lut. Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut. Using template $paramod$9cf044275e70b6dc34d2f815a6f8ffc23f9694a0\$lut for cells of type $lut. Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut. Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut. Using template $paramod$ed309e84057dd9e3f2316a2c8571f692a9ac8cbc\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101100 for cells of type $lut. Using template $paramod$8b9bb8634a01dcf1ec7286f03a4e71b3580bcd8a\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut. Using template $paramod$277f0d9bdab7f45e246092781abc5cbfb7b01a64\$lut for cells of type $lut. Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut. Using template $paramod$841fab300658e8d1c572f70fee1fd7a0673ac8c0\$lut for cells of type $lut. Using template $paramod$fda9042e335e740ca895248884e94d2ec192e99f\$lut for cells of type $lut. Using template $paramod$1114d560ed98e9182fe073c9893577168d869f6b\$lut for cells of type $lut. Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut. Using template $paramod$78204da8196d468a927dfece17c9d1adec19023e\$lut for cells of type $lut. Using template $paramod$7c68a38461eada437758033cda986c95136e1369\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut. Using template $paramod$4d0b639853c5ac4fa17d68ec27d7cbc2fcdb05d4\$lut for cells of type $lut. Using template $paramod$4d5682dd6afedfd6df0816b3bca3365bbde91748\$lut for cells of type $lut. Using template $paramod$927bdb4eb8d02f9706a5d816b5ea39033d471fe3\$lut for cells of type $lut. Using template $paramod$e5b29079c1a88f3fc663c746ec8e3359690ef674\$lut for cells of type $lut. Using template $paramod$606f15653d571c851360b76e1498073cdb5dc46e\$lut for cells of type $lut. Using template $paramod$72e47c7695984d6b0736d1c3e4914c85e4307ab6\$lut for cells of type $lut. Using template $paramod$89d86ba03fb482b36c3f8c9f809090817a3f2174\$lut for cells of type $lut. Using template $paramod$116655be62007216c8cfda4964fcaab629eccb20\$lut for cells of type $lut. Using template $paramod$473796ff40549b824545fcee9a2685b2090a6db6\$lut for cells of type $lut. Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut. Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut. Using template $paramod$0c5a54c406cdb1ed108583f5d43071050a5e4d5c\$lut for cells of type $lut. Using template $paramod$037be5c00d8a02858cdb1ab049b58a0133287ff1\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut. Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut. Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut. Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut. Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100111 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110010 for cells of type $lut. Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut. Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut. Using template $paramod$6f9324703e8fcc3b6df2bc2bec54ec19a446ae96\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut. Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000110 for cells of type $lut. Using template $paramod$400df6440141fc1263a8f1610b7b43a8fa83f0fb\$lut for cells of type $lut. Using template $paramod$2e9afba29670cc6475874639e7c1b3979c8ebde3\$lut for cells of type $lut. Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut. Using template $paramod$b587e1dcd8f8a9800d395e4aeecac52c55d6f585\$lut for cells of type $lut. Using template $paramod$20235ca863361fbc253329cfc7eeea38c77404dc\$lut for cells of type $lut. Using template $paramod$5b569025ec6b29ee2678fd3f4c6e3d1c17700dad\$lut for cells of type $lut. Using template $paramod$d315acbf930db7c20b3f4ac2dad3b7982b1f437c\$lut for cells of type $lut. Using template $paramod$fdaf2f88d9dd529fbb478245c6472687251d2b58\$lut for cells of type $lut. Using template $paramod$b6f3a15b14a6c02e75265a58fb7b4713b7fcdd28\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101010 for cells of type $lut. Using template $paramod$d75de5fddc91c8230fc9706cca675434e3d479c9\$lut for cells of type $lut. Using template $paramod$619f95f3f59f39ad0b94d6639574d82b204ed4ba\$lut for cells of type $lut. Using template $paramod$7e9df0afb32b76fe5fce0691b8752aca650057fa\$lut for cells of type $lut. Using template $paramod$5e96c51e862795fcf5123ad90ed33b3bddf109cb\$lut for cells of type $lut. Using template $paramod$cccbb83646f94e4fa56b3fd179b85baf82888de5\$lut for cells of type $lut. Using template $paramod$c4bf216fba7e8e9f40a3f899e49a9c877538186a\$lut for cells of type $lut. Using template $paramod$153c6cdaaddbc43e6ef3facd06aa851de33910ae\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001010 for cells of type $lut. Using template $paramod$728be8621693cbe11cb14576e2994c948993fc85\$lut for cells of type $lut. Using template $paramod$19451f719aa4a75f15cb977ed4212a1c1a1550e9\$lut for cells of type $lut. Using template $paramod$3e5e578bf55a638641f56c44aa55e1cce8c8f38b\$lut for cells of type $lut. Using template $paramod$962aebbf5c4f0ae3198518fa9eeb30534f0de6e9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut. Using template $paramod$f1fef50632ad64a4db12adf3d0ebf2436a5fd8e5\$lut for cells of type $lut. Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut. Using template $paramod$c66e7b215e6f80c1915bda1df6f2ae95d0bda68c\$lut for cells of type $lut. Using template $paramod$446d5374f1a9a50c11eb107999155fc0219be593\$lut for cells of type $lut. Using template $paramod$a9fc6e1212e2c97f661279eebf7fa89d410eb14a\$lut for cells of type $lut. Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut. Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut. Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut. Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut. Using template $paramod$5ceaf4bd822242d40e5b68dbbe1fd10a5ca3bac7\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut. Using template $paramod$ca314c90332674badf3cc03eb037e8557fb293b1\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut. Using template $paramod$68fe50ee5a60a0bed36b1b1843c805d7bc807f41\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut. Using template $paramod$448496cb53eb7c1242b5786d67bd117d88f563fb\$lut for cells of type $lut. Using template $paramod$a197ef6f3b51d411ae3e5b42b5d77a606c4fb11a\$lut for cells of type $lut. Using template $paramod$e5e9da8fed769f971686eed8c5eea50e61f73aaa\$lut for cells of type $lut. Using template $paramod$068092ddede495d8462ffe530e6d91711913edbc\$lut for cells of type $lut. Using template $paramod$3331a91b4e24483a258fc0d47474cffbd93ab577\$lut for cells of type $lut. Using template $paramod$3ef319efded008eed5f930491a82ee1762b3c0df\$lut for cells of type $lut. Using template $paramod$712505941a295086314c22735153725461a87f4a\$lut for cells of type $lut. Using template $paramod$cf7f3a0cbef28573cfdd7218ef90ef5391ec0286\$lut for cells of type $lut. Using template $paramod$546c2397de4ca4f5182bdbc6c836249288f77ada\$lut for cells of type $lut. Using template $paramod$b2192df6f90569fea4015d0a6658bdc192199f95\$lut for cells of type $lut. Using template $paramod$655782bc30c333f93ae53797f6b67d2405425642\$lut for cells of type $lut. Using template $paramod$e46703b423a661cd7d311c41833ea655969702cc\$lut for cells of type $lut. Using template $paramod$2e11c0e004fab0373ef80005c65c968bc830b55a\$lut for cells of type $lut. Using template $paramod$1d9a837622683d39ce63612c7ebf6d008cdeaf88\$lut for cells of type $lut. Using template $paramod$9ce4a498e7038bb2a3d20426fbe6b5ad7361033c\$lut for cells of type $lut. Using template $paramod$6565e92242a21f5338d449de809baa175c228bcf\$lut for cells of type $lut. Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut. Using template $paramod$d4d4bb503ed128c19cb73d1e89ade7781d5378df\$lut for cells of type $lut. Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d\$lut for cells of type $lut. Using template $paramod$a47d3f6fd9a7aebdb1b556bc977da3380a17c8cf\$lut for cells of type $lut. Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut. Using template $paramod$2de23df76a24087ecc0fa38a78ecc970cd3f2492\$lut for cells of type $lut. Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut. Using template $paramod$20f82dd03802038bc013e5804609eaebb5d257db\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011111 for cells of type $lut. Using template $paramod$4cab3b31c601551ff65536bf4f533afa0b2094ee\$lut for cells of type $lut. Using template $paramod$4834046533425f54583d6bd31e49deb63455e1a5\$lut for cells of type $lut. Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut. Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut. Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut. Using template $paramod$992bdc10cff2c6edd722994f0e1044bc863f79f7\$lut for cells of type $lut. Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut. Using template $paramod$b9f1cc075fd5e1dc13f6aa9fc152bf79a0f71ef7\$lut for cells of type $lut. Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5\$lut for cells of type $lut. Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut. Using template $paramod$b86b68a00733dbecb31d58a14a13683475a2002a\$lut for cells of type $lut. Using template $paramod$2382b0dd4cb27fd4312681c40a6dd179c2a7a26a\$lut for cells of type $lut. Using template $paramod$8829675bb8c52553aed9f101ec0d5ef0c865e5c7\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut. Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut. Using template $paramod$b45308ffeb4031bc5d55ef31b149afd94d3d7565\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut. Using template $paramod$fa874836ac64420bb7d9c67e99a0912e16a50ef2\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut. Using template $paramod$59f2a3e232df3029c8bc36978b9bbe72a71dfb5a\$lut for cells of type $lut. Using template $paramod$8c24dc0cdd336b7fb88bbf7eed45cec5cbae862b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut. Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut. Using template $paramod$a76afe794e55ba422468b9db09d48da3f250b812\$lut for cells of type $lut. Using template $paramod$85c16b77ac5cbc03cd885233335d092a691531c5\$lut for cells of type $lut. Using template $paramod$f503ae6dd13af4ce255f26a38c5b2bb42d3444fc\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101000 for cells of type $lut. Using template $paramod$dc8f0be42379c903926eb5c45306997db4c0a27c\$lut for cells of type $lut. Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut. Using template $paramod$12879138d1e376f344e47ea40be66b776233be75\$lut for cells of type $lut. Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730\$lut for cells of type $lut. Using template $paramod$ffc80aea4aa44f0166b2d4713ba5912f56e92991\$lut for cells of type $lut. Using template $paramod$d909494d67d7075f17a422f7cb5526f6d6564ea6\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut. Using template $paramod$68f8a3050868da669d94d4e494c893d3dce59229\$lut for cells of type $lut. Using template $paramod$bb52033fa4a868a3e74e1b8840db1141cdc85231\$lut for cells of type $lut. Using template $paramod$dd7c1583fe0ade167c7826c594e5d16b758a72fe\$lut for cells of type $lut. Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut. Using template $paramod$c388bdf5bc34e848632d723db494e9a79bee28dd\$lut for cells of type $lut. Using template $paramod$1241d759e3df4cac11dc7c99c36b0d1b07f7a673\$lut for cells of type $lut. Using template $paramod$86d1a43c2f1d620ff2cef866448dd1258c868fad\$lut for cells of type $lut. Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut. Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut. Using template $paramod$954dbc3009cd610fe6e1d1f86d772f3b7586a345\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001011 for cells of type $lut. Using template $paramod$db08fd84fb3c4d6a41eaec6adfffe445fb7eb17f\$lut for cells of type $lut. Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut. Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut. Using template $paramod$e134ec2a47a2462a591072e65d34fb15b81c90e0\$lut for cells of type $lut. Using template $paramod$d76edc10344198fdbbc083cbc9765a888a1f48f2\$lut for cells of type $lut. Using template $paramod$dbdbcb07b9994e498bb1324e5c006c6aa08a7a37\$lut for cells of type $lut. Using template $paramod$5dccb93dc6c77781a2ce9b1f6222fb9989b34bfe\$lut for cells of type $lut. Using template $paramod$9b22a1c705c95b6d76d13b5d826906777087290e\$lut for cells of type $lut. Using template $paramod$adf6ead412ecb53ed0c96b90af15c42b9fe9e0f8\$lut for cells of type $lut. Using template $paramod$b8c58492c0c5a328af9d8bee395ae322f11fd1b8\$lut for cells of type $lut. Using template $paramod$9cd5bf5e74886a498c1de13a41595b1780f7a027\$lut for cells of type $lut. Using template $paramod$1718b78815c197f9cf63419425bee170c76e82fd\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut. Using template $paramod$3b43e9fbeacef60edfff2e6ed76202ebfac75384\$lut for cells of type $lut. Using template $paramod$c42ab8d3a0b4f503e2527a4e01b91570a4655ee8\$lut for cells of type $lut. Using template $paramod$8c11a155773d2e4aba9b1022fc059160b55313e8\$lut for cells of type $lut. Using template $paramod$e943b0894861e8179e80496d033f3cd541bb6ccc\$lut for cells of type $lut. Using template $paramod$c4f684a5ad94828302443d5c044fe053664a05a6\$lut for cells of type $lut. Using template $paramod$a778c0a17dd7f7ee20a881578cbbe6a72ebe3b3a\$lut for cells of type $lut. Using template $paramod$cb32832b462590ba6b4bda2fe4ab0e2da1abc198\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010101 for cells of type $lut. Using template $paramod$251994398653c4cf8de320f1e306e535d5d2d624\$lut for cells of type $lut. Using template $paramod$25696d6b21c8ac3da9913114964545779e21cfa5\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111001 for cells of type $lut. Using template $paramod$c347afbc85ad8703191dacbf5d3590fe54f2e1f8\$lut for cells of type $lut. Using template $paramod$72043e0aa7fa64cb454e3c2ca3dbe1636171896a\$lut for cells of type $lut. Using template $paramod$baa939b0bd5b3e0c8760492528669bd58f640542\$lut for cells of type $lut. Using template $paramod$03689da3fbbeab024e5566b38a26f33b669495fc\$lut for cells of type $lut. Using template $paramod$b26fbfdb68e98cf016d61a8611b449e9f4a30f3c\$lut for cells of type $lut. Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut. Using template $paramod$d3e8d5ab09bd6b90ac4faa541356d61263b24ae4\$lut for cells of type $lut. Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut. Using template $paramod$89de210e11c16138f89688ab911d555676147dc8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100011 for cells of type $lut. Using template $paramod$46f7e44fb5d42c7c6e4c2d1915650ac9397db4dd\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut. Using template $paramod$7ca4db46d3cd57dbe2541a389808e6d33af02319\$lut for cells of type $lut. Using template $paramod$47671b68495b53d6eea5a9dd67c114907e17980b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111010 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut. Using template $paramod$58bd588a49a6a3b9d057d75f907cb4932e1635f6\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001110 for cells of type $lut. Using template $paramod$f8978e3a0f6c6cf021e4a354a131759931786915\$lut for cells of type $lut. Using template $paramod$33e3c4fe14005c1001df0eafeba147d3d1923b4f\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100011 for cells of type $lut. Using template $paramod$beae4210b922fc9ba2fcc4008a7474b475e38c50\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut. Using template $paramod$4ebbf381cf64b08e3304ae8194da41d0cd1eaa92\$lut for cells of type $lut. Using template $paramod$afd7b4c177a33f5eb62789d24240afa93e05edd1\$lut for cells of type $lut. Using template $paramod$a4bbe892a28ec0471eac4c548ab7ee6abbaf1e36\$lut for cells of type $lut. Using template $paramod$5502a85110dbca29ac631107f0b0635e7fade476\$lut for cells of type $lut. Using template $paramod$509383819812d331dca6b49338d0f34aecd1e133\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110010 for cells of type $lut. Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut. Using template $paramod$d4c7ffbe09e2943cd35d415410454710e0893d02\$lut for cells of type $lut. Using template $paramod$3fb3f0de5b347667e45afe024bcf37620e184335\$lut for cells of type $lut. Using template $paramod$da0bf9959d41c330fce02de597edb21f8940225f\$lut for cells of type $lut. Using template $paramod$98c287044391051c508402a8bb26a3f11ae36342\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001100 for cells of type $lut. Using template $paramod$291097d1a8f3761115f354cdc029d613c6948554\$lut for cells of type $lut. Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5\$lut for cells of type $lut. Using template $paramod$734cd1512f671d92bc4f41153da0d9781801dd98\$lut for cells of type $lut. Using template $paramod$bbf8c65f00b09f2cf68e6ca5410fa9a0c7a5e2b9\$lut for cells of type $lut. Using template $paramod$c217e185eb8e6463ca272982ba8c5940fa90d81f\$lut for cells of type $lut. Using template $paramod$8ea003011c53653dd924e9e371b2673fd2b3f88e\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut. Using template $paramod$274ac0d53c4af76b67991d3f6159ec25a5f74c41\$lut for cells of type $lut. Using template $paramod$f53057b5d1c5b4cd253ac98aee0791215a3935dc\$lut for cells of type $lut. Using template $paramod$0f5c4dc6f92c3c6ee36482a209be300a0cac5e25\$lut for cells of type $lut. Using template $paramod$2474607ae544a71944626525d6ae11f1a2baa308\$lut for cells of type $lut. Using template $paramod$ececc55fe721b2d80098bfc00a6005f1af14b6e5\$lut for cells of type $lut. Using template $paramod$4b815e6c998e04ad0d0242e44b0c58a7a9d0b3b6\$lut for cells of type $lut. Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut. Using template $paramod$3d7168c8134c4765b84a7b86d5ef7e1e65bbf4a0\$lut for cells of type $lut. Using template $paramod$3f9a3800e34bd795630a4eaf44b2e1d4a7f48a74\$lut for cells of type $lut. Using template $paramod$de585cf88f5bba8c3844f2f85376b536b160ba2f\$lut for cells of type $lut. Using template $paramod$6b7c9c56fc2a32a479d463d5f3b0d3f4673b67f1\$lut for cells of type $lut. Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut. Using template $paramod$a6b2d4693fada6bebbe4480262641915d709d280\$lut for cells of type $lut. Using template $paramod$133d442dae750c43071369608380feab91f2bcef\$lut for cells of type $lut. Using template $paramod$7a0b348a7069d0c8f44afe945e212fcf3f3fd64c\$lut for cells of type $lut. Using template $paramod$c8d1ebad6975853f30e75644f1cda984ecf31f1e\$lut for cells of type $lut. Using template $paramod$c6a0421f5b5114b68e9782f0585d571421cf8f01\$lut for cells of type $lut. Using template $paramod$5dff0e85697c6be9804afdffa3a30bf4f4e392fe\$lut for cells of type $lut. Using template $paramod$2357431a20f3891da5d1d21801bc815b057e2dac\$lut for cells of type $lut. Using template $paramod$fa304133f7ef08f384201a0b35d6d183ddcd26f0\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut. Using template $paramod$d53578aacfd93124244778d88be0e90eb09c1b1b\$lut for cells of type $lut. Using template $paramod$620586420e818d3afa7e5b51fcf19f5c6ea83ad4\$lut for cells of type $lut. Using template $paramod$6375ab94b303a3f3c8d7ca6946328cb3c0b443a7\$lut for cells of type $lut. Using template $paramod$3f6d9d99ea7ef3b700f056470f3d63fc0240b099\$lut for cells of type $lut. Using template $paramod$035ec894c5c73208c50a836d319c53be4d37ecc4\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut. Using template $paramod$ead66ba22839f96e739c8f1b5a09bc1717b3be02\$lut for cells of type $lut. Using template $paramod$d76a082ac65b735f66c3b6bca13712f41180defa\$lut for cells of type $lut. Using template $paramod$a82a699dba54b8465366aeb90aba90d3d29adde0\$lut for cells of type $lut. Using template $paramod$1a441877fe507d6e3773ef1f291c342ba1351ff8\$lut for cells of type $lut. Using template $paramod$7ea2352f8f054781a715aeddf3e67f1db65f005a\$lut for cells of type $lut. Using template $paramod$d1ad07a4a7e5b1f5bffec30717e93ce9af39d517\$lut for cells of type $lut. Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut. Using template $paramod$adb84e058b0f32ce56f004e6ffa19883ace75fc0\$lut for cells of type $lut. Using template $paramod$7d5afe14dbe63bbcb001b9ac9ac12f8f5941dc33\$lut for cells of type $lut. Using template $paramod$5a905f214811b506416af2b7aaceec5e635b8fc3\$lut for cells of type $lut. Using template $paramod$5348912da867a611a8088b6b8b27a62d65f1de6e\$lut for cells of type $lut. Using template $paramod$b983a0727c7c357a3d638941d37a889b7d74b45b\$lut for cells of type $lut. Using template $paramod$84bef48419505c45080a829b4c4b6379a157eb8b\$lut for cells of type $lut. Using template $paramod$a9cc77ddc8c5b4f6a4d0854d18d68b74c5969526\$lut for cells of type $lut. Using template $paramod$c6c8aaf71df0998bf3ec6b2b78bcedc4ed24a6c4\$lut for cells of type $lut. Using template $paramod$3702268f692b8bf258e428f65d3bca4e1f76d98b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut. Using template $paramod$fb4ed309581bcd972f41afa8566ae8b9812c7f6c\$lut for cells of type $lut. Using template $paramod$e936d07f506a72542be1c55ed522fd99594fd535\$lut for cells of type $lut. Using template $paramod$430ff3cc137087db51245fe4f94d99755d044b30\$lut for cells of type $lut. Using template $paramod$aefdc08ea82ee57c767b4cec3efc09bfeef4c872\$lut for cells of type $lut. Using template $paramod$70a6f8b5e7c26d543ee5df54b2e21d28a007a4bc\$lut for cells of type $lut. Using template $paramod$f0740a6e324805120e00833ac51c0403ce0bac71\$lut for cells of type $lut. Using template $paramod$9851cb11f88bbbf4a516c0595f3b0113b1f100c4\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011101 for cells of type $lut. Using template $paramod$9012351afa37f8c21b210fcb3832dc6e8fd1ab09\$lut for cells of type $lut. Using template $paramod$889dc7b17c448030eaa05f5eb6c645a7ac00212c\$lut for cells of type $lut. Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d\$lut for cells of type $lut. Using template $paramod$f48b506ee4bc344bff5930bdbbabde68f446d1da\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut. Using template $paramod$8f2db6b8c04ce5ad1e643c3970f4071ac9f9c455\$lut for cells of type $lut. Using template $paramod$d3d2b6a5ec102f3c610e97414cb3f20b0198988a\$lut for cells of type $lut. Using template $paramod$2ec6422db00d358fc7469efce6208bffbc8521cd\$lut for cells of type $lut. Using template $paramod$baa9d2fb2d21010939721b85aa9f11effe0b53c4\$lut for cells of type $lut. Using template $paramod$8b5edd505331ea1322066a97b8d3ee73c26bc941\$lut for cells of type $lut. Using template $paramod$c92d19f87f844daa49aa248d8693c365cf26e240\$lut for cells of type $lut. Using template $paramod$9fcebe5f15037194cb85f4fa2b5484ef37b6afff\$lut for cells of type $lut. Using template $paramod$169e3ff199948acb6289d60ee69a6cbdb1d4057e\$lut for cells of type $lut. Using template $paramod$97313db2899ba1ac572634b88981bb6de3bd3637\$lut for cells of type $lut. Using template $paramod$72d04cda0ad63fcea17225ad4256bc664683b513\$lut for cells of type $lut. Using template $paramod$7c1f6afe503c0a9d86df3082e3bb8088dcf2d22b\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101111 for cells of type $lut. Using template $paramod$973818279bc95792902f3c09371fd2407d04a2a5\$lut for cells of type $lut. Using template $paramod$92c3899764cd8074859d6a5a5b733cffe8a391b3\$lut for cells of type $lut. Using template $paramod$c529e7295e75fa6a9822d7543170e25abf052dba\$lut for cells of type $lut. Using template $paramod$b502d26939da9d08e0c4b0645996a733a1477559\$lut for cells of type $lut. Using template $paramod$30ccc2d02d561628bd3e8ba21431cf11015685a5\$lut for cells of type $lut. Using template $paramod$2955ab75367a3dc9d6f50d3655eebcd4f615031f\$lut for cells of type $lut. Using template $paramod$d393adf941e844212705b5eb9e96656ac490af94\$lut for cells of type $lut. Using template $paramod$2646f79d883fe55c6115f3a5c1d9911a69497523\$lut for cells of type $lut. Using template $paramod$a648edd7290dbdc60b4277769ac1653dae6fd74c\$lut for cells of type $lut. Using template $paramod$00ffcc628ccb870304683cac36ad3a16cc41b6a4\$lut for cells of type $lut. Using template $paramod$e3d1f7a5be70c549b567cce08ebf28da10c48aca\$lut for cells of type $lut. Using template $paramod$c07d61aaf1d93e15249de987e8fd0ca391dbd52a\$lut for cells of type $lut. Using template $paramod$91d6743ceb0f093b57d242b538f7f23d2346d4c9\$lut for cells of type $lut. Using template $paramod$a5585a0d7d274785e9b965eebc7d3a8d39a0d415\$lut for cells of type $lut. Using template $paramod$66cfa457f3bf0a90e11a4f3cf9336b993db8c18a\$lut for cells of type $lut. Using template $paramod$ff80b97fda1a6dd143892567bf23cab4be1fbf18\$lut for cells of type $lut. Using template $paramod$7ea76a6234c0eb3d7fb4a8ed8a4aa074aef60e52\$lut for cells of type $lut. Using template $paramod$9a3e28b389c1f3cb6cf0807228c461506fb829f5\$lut for cells of type $lut. Using template $paramod$221832ea6a41a3208cd6f3411a952b5811695f4c\$lut for cells of type $lut. Using template $paramod$284267df938459b9413fa2429dd65c56f230d038\$lut for cells of type $lut. Using template $paramod$6e84d22ee7c2a4c38bea6ef32c294e3f7fa51831\$lut for cells of type $lut. Using template $paramod$1bc264c4d40efaf3fa6bc474a1efbb098b712f27\$lut for cells of type $lut. Using template $paramod$784a3d78e9b1482650167c12d5b9cf153552921d\$lut for cells of type $lut. Using template $paramod$af15d200e3605f2c4c42beab3430842bc93f1158\$lut for cells of type $lut. Using template $paramod$cf93df6a751c015d454aef52e32716809f254f3e\$lut for cells of type $lut. Using template $paramod$94cc9dc7ba20eb6ef27973e1d776ca04cbc15deb\$lut for cells of type $lut. Using template $paramod$9ae0f136c9ed34a2deb323e9b2a3a520eea61514\$lut for cells of type $lut. Using template $paramod$3d420c45fcaf200a454408122dcbe0a4f1f1628e\$lut for cells of type $lut. Using template $paramod$717f66aee89077840479c83a1f79be61fd139731\$lut for cells of type $lut. Using template $paramod$903905cca899aab473483ca27c3db12d7108e3a5\$lut for cells of type $lut. Using template $paramod$200337237619ba4c0bed9a492562f1d1b57fb569\$lut for cells of type $lut. Using template $paramod$3a5c30475a668f3c50e192d3f7fa6129244b3b14\$lut for cells of type $lut. Using template $paramod$b23dbea0c6904cf5ff05fb87166c6ae387137b81\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111110 for cells of type $lut. Using template $paramod$d11ba2bbca9997f916ceb644a17bb078c757e652\$lut for cells of type $lut. Using template $paramod$77710f7ae7b20f77f16b1eb4652da5735e1928d0\$lut for cells of type $lut. Using template $paramod$2752d3bb0dc29e165c12f44d581dc3e473837d50\$lut for cells of type $lut. Using template $paramod$ca6b8ebb9c3ff8df4ec2adf341caafd7015706cb\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11000100 for cells of type $lut. Using template $paramod$47efba32698f351a70e87bc22cc7fa72ab94acdd\$lut for cells of type $lut. Using template $paramod$99bea6b1a6bfc821c80186f7c0bda101c86a5f38\$lut for cells of type $lut. Using template $paramod$47d363ae7b1a0e81207e02fe31af85b6bf36a2ac\$lut for cells of type $lut. Using template $paramod$5c36a508e8885449eeca65fa0c02b7154f6a3130\$lut for cells of type $lut. Using template $paramod$578072231bd52651f4fc95d09f2d6ddb1b810767\$lut for cells of type $lut. Using template $paramod$933cafdfe76c82f6ca1bfd905cd49730a16db47f\$lut for cells of type $lut. Using template $paramod$93785b9c731eec5233cca020cc98b38141190c08\$lut for cells of type $lut. Using template $paramod$45caec2ccade20549f390eeb9db665d02d45400a\$lut for cells of type $lut. Using template $paramod$d6a246575d0ba3dcbbccd768ad41b602f82ff057\$lut for cells of type $lut. Using template $paramod$d334f7f249d55ed9e86623806bb0fab78f506854\$lut for cells of type $lut. Using template $paramod$f546bd96bcec6e3bf1b78bdea64b0f5bbbaff6df\$lut for cells of type $lut. Using template $paramod$734f58d941a9ce66b81babc958905baa6c8ab1ff\$lut for cells of type $lut. Using template $paramod$9c669e17239e630696f5bb85b60d7269d3597208\$lut for cells of type $lut. Using template $paramod$86a86bef334cd76b66a1658c5f306ef73f138871\$lut for cells of type $lut. Using template $paramod$6d05ee5be4fbc817e6482b590e1831ddde15ffbe\$lut for cells of type $lut. Using template $paramod$61e281d560727232efeff44f14d859a8af1bbaf4\$lut for cells of type $lut. Using template $paramod$23ba03b3f106a8b0f20f18bfebd862b419996ddc\$lut for cells of type $lut. Using template $paramod$1c4dba04c7b1b6f9ae2fbd2ebcdbd37f5c14a3e3\$lut for cells of type $lut. Using template $paramod$a238bb199d4b53d4c976c9e68dafcfe86b19f40f\$lut for cells of type $lut. Using template $paramod$8adf7e4b16cab60634c26f384b849e98b4a31be5\$lut for cells of type $lut. Using template $paramod$9888082d13c544afa98b0a3109ddbbdba5c4f025\$lut for cells of type $lut. Using template $paramod$7d813eb49700f971f2635a434700eafdfa816bc3\$lut for cells of type $lut. Using template $paramod$9e748083623c5149badfdfdc1ac81725ba5d6d94\$lut for cells of type $lut. Using template $paramod$533944ad09911275d2c1f759851a4f7f320b58a1\$lut for cells of type $lut. Using template $paramod$02bd3241881565cabee2401beb2950a85cec69ac\$lut for cells of type $lut. Using template $paramod$235e451b29422bd173a9721ba1df02da69532cb3\$lut for cells of type $lut. Using template $paramod$75da000637c65341bba0aeaae7f49cbd1f77f2bf\$lut for cells of type $lut. Using template $paramod$253532b742d151c01e8e51f153c24d934b8f6185\$lut for cells of type $lut. Using template $paramod$b9d3baa367e429670fdcc099dbbeb654f38fd2cd\$lut for cells of type $lut. Using template $paramod$cadf32ea2152c52540b06d281881252ca51643c1\$lut for cells of type $lut. Using template $paramod$ffd2daa816943d98d4befd944c0ade9f965da2a3\$lut for cells of type $lut. Using template $paramod$3ae9f1cda205b669870c653a21d45eee50078e98\$lut for cells of type $lut. Using template $paramod$5efe6695c4406baaf4ad74202e25338ae615a814\$lut for cells of type $lut. Using template $paramod$daac9b1e7bb2ac018f7132a3fbe0026ddd7b1a71\$lut for cells of type $lut. Using template $paramod$84abafac600770dbecbd08e858f90b0a8d019d50\$lut for cells of type $lut. Using template $paramod$2c9fdd9f81a9a0f20f195228573ae06ae3d35480\$lut for cells of type $lut. Using template $paramod$17a846ed18d725008603a1e21e7868d5c69c1348\$lut for cells of type $lut. Using template $paramod$4f9dd6dbe2c6f431e991684f6eb39518c2218a14\$lut for cells of type $lut. Using template $paramod$ce4dd68b75ef9027d892f268a239d9721291d336\$lut for cells of type $lut. Using template $paramod$e277a522d8a930c8c8c8cdb56d33d42914aefec4\$lut for cells of type $lut. Using template $paramod$d8119e7cf18bdd1d72e1822e569d9c40a2fc5848\$lut for cells of type $lut. Using template $paramod$bbd32bd467d62890b484fe941be0dc6df13618f5\$lut for cells of type $lut. Using template $paramod$3cfdeeb6715e4270e398da3c1b7dfb40fd25bd19\$lut for cells of type $lut. Using template $paramod$9b5120652ba1719e45b6419c2d500e377154042f\$lut for cells of type $lut. Using template $paramod$d3b4003a49cc631c440050b7c68facb2fd644569\$lut for cells of type $lut. Using template $paramod$f9cc9c25528a6db14532d780d3504218167c72fe\$lut for cells of type $lut. Using template $paramod$50d610799df931eff0fa306ae1ba282988122f97\$lut for cells of type $lut. Using template $paramod$e234b33fd72932ba3f0d727e277c697708f63208\$lut for cells of type $lut. Using template $paramod$6645601c2a001aeb5d06923298e9bc909649a395\$lut for cells of type $lut. Using template $paramod$adc0b354bb960519a616db7423a6274fc380540e\$lut for cells of type $lut. Using template $paramod$f13784ede300b12a5285177c86c7721a54cf9e12\$lut for cells of type $lut. Using template $paramod$19f568890ed784cb1efc3ce1b67eed20a6c54d9a\$lut for cells of type $lut. Using template $paramod$1a67f0bd6875448bc6b4f0936bc3f17942c2ab3d\$lut for cells of type $lut. Using template $paramod$becf4ae4f5301462ee316851950c81d66baf3e53\$lut for cells of type $lut. Using template $paramod$328b74448a63775b43b50cfbaf42dfa1ed574efb\$lut for cells of type $lut. Using template $paramod$3ac2c0f89fe9b6bdcccc07e049e36584de660216\$lut for cells of type $lut. Using template $paramod$2a06a9051ca08be1be91c0794c2191a859d51c63\$lut for cells of type $lut. Using template $paramod$eda60d6d8653bd5aaeb1a3951cffaca4bdd45837\$lut for cells of type $lut. Using template $paramod$de2b92d66e62d2468c774d4959d51c030800288f\$lut for cells of type $lut. Using template $paramod$fbace1c5af8b8efd1c625bd9d47d8b080aa709a4\$lut for cells of type $lut. Using template $paramod$c3da352931f1596c167573d1407e32cd83b2ee43\$lut for cells of type $lut. Using template $paramod$f62bf7b9bf368c5a044dd284e6192cdfb023ea0f\$lut for cells of type $lut. Using template $paramod$67e504b90f5462d63954ab32ea18c3e6f5ebce9c\$lut for cells of type $lut. Using template $paramod$a51481b878721d43d7952f9e8b72ec2ca5b9d883\$lut for cells of type $lut. Using template $paramod$3ab5694f71680621be084af28eddae217f158504\$lut for cells of type $lut. Using template $paramod$d95f3f3fee48f5ce153945c64ac9f66df0ed0f1e\$lut for cells of type $lut. Using template $paramod$87a42f7f6a1cb5d9708ead0b2ae7aa608a438aee\$lut for cells of type $lut. Using template $paramod$ebc96d54c58bc295ed1c25971281979887a5ca05\$lut for cells of type $lut. Using template $paramod$9e354de8d358bf081aa0c089488ea3bc5b7c2fd9\$lut for cells of type $lut. Using template $paramod$56e6d8a28a52006bb4e50e077743f0a2163235af\$lut for cells of type $lut. Using template $paramod$ad7268a3cffe5f4d67497e34873c5279a0964cb9\$lut for cells of type $lut. Using template $paramod$18d9a337a681d13f5f6ffd0b9a3872b8e2d3363b\$lut for cells of type $lut. Using template $paramod$30913fb18ecbbaa0f9eaee4ddf176fe554f044e8\$lut for cells of type $lut. Using template $paramod$6be53ab59e0a69757fc32adb071ddcb64e8c87b6\$lut for cells of type $lut. Using template $paramod$bea08a495d16293f8cc454a45845d26cde0762b6\$lut for cells of type $lut. Using template $paramod$4360249031867742b9f99766f191182f2c43af22\$lut for cells of type $lut. Using template $paramod$4b8324809148df6161610ef5b5bd73df0086e19e\$lut for cells of type $lut. Using template $paramod$767b7aceeb9937508bfd5f0a36223d5ce2e8af73\$lut for cells of type $lut. Using template $paramod$4b5390143765863dd4ad783d9a1665072f814613\$lut for cells of type $lut. Using template $paramod$d3b217881109947f5629b5e075c7e91690632ef0\$lut for cells of type $lut. Using template $paramod$6ed78fc9dce6a86ae2f7bdb90b3070ccd5808a40\$lut for cells of type $lut. Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut. Using template $paramod$4fca5f405a3ded126a54c23f508d7fea5abd1989\$lut for cells of type $lut. Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut. Using template $paramod$4d7f17f71543a1e7fc1835bd79c4827a43f2e844\$lut for cells of type $lut. Using template $paramod$10af25431369ba29ec0acc88709bd5c2241d1926\$lut for cells of type $lut. Using template $paramod$1685fea5ccb55e5af4aa43e078527523a9edd957\$lut for cells of type $lut. Using template $paramod$23e0ddd8ff31e0735d2a50460ab37f7284a9c6f0\$lut for cells of type $lut. Using template $paramod$4b9b235bc4444ff899bef0c648e4109b26737f1a\$lut for cells of type $lut. Using template $paramod$ba7f31f246a278c41fa0648a6e0512f63185dec0\$lut for cells of type $lut. Using template $paramod$bff309741b15faa8aef2ddaef831dc07fab2bcf1\$lut for cells of type $lut. Using template $paramod$4853050665c020c8d21fb1a749196950a09d9df8\$lut for cells of type $lut. Using template $paramod$e6412036fca6352e58cb43d19aca525c5b5ea9c1\$lut for cells of type $lut. Using template $paramod$bf00427ade60df6ecbee879d4a17f97643fe237b\$lut for cells of type $lut. Using template $paramod$c84d6981797c06fc503ef204d53f94644afab6a9\$lut for cells of type $lut. Using template $paramod$a18efd9245448b0a198b87f7e710a6a1c17ab9de\$lut for cells of type $lut. Using template $paramod$99aafa8478517601bb98e7dcf39065f9e1d7ac0d\$lut for cells of type $lut. Using template $paramod$b2ba40ab3e60600c6f3e7a0d5d42efdd08bc6022\$lut for cells of type $lut. Using template $paramod$f78f9da07d80b51167de648a6ad574eb84388849\$lut for cells of type $lut. Using template $paramod$36a85d4c7694b52a8c8b2a7b2d440c67106c9add\$lut for cells of type $lut. Using template $paramod$af2e7902d256fcfe5f420c8301f8be235d0387af\$lut for cells of type $lut. Using template $paramod$c7da182350c463dac9341b9202c767a484f2d529\$lut for cells of type $lut. Using template $paramod$ee5adfa1bcc7e4b8948c774483a7d19aaddb4759\$lut for cells of type $lut. Using template $paramod$95e3af1ce267c2242685f8bd2338d86a179ec7b0\$lut for cells of type $lut. Using template $paramod$8cc13fab11ed939f0e40808b82d4ee5fa0f31080\$lut for cells of type $lut. Using template $paramod$962a711d8da50020ec4f3a196d5fda6045749cb5\$lut for cells of type $lut. Using template $paramod$4d8b60a59246cee0925c5373897923a4f4a23c47\$lut for cells of type $lut. Using template $paramod$d3f9944e801238ce578b0adc781287f175f36821\$lut for cells of type $lut. Using template $paramod$e85b6eba0dacefc5f73f8748159b8b9599212afc\$lut for cells of type $lut. Using template $paramod$db001ada2391223fb31055797b66f3658a0f82c3\$lut for cells of type $lut. Using template $paramod$d497222f59d990d3f689ed9c6ac453ecc8a2f4b4\$lut for cells of type $lut. Using template $paramod$a770a58bbf55a5b518b4aab8868b6a99a50f3001\$lut for cells of type $lut. Using template $paramod$bef7fff73d7847e500891f20145b83b119b2bb41\$lut for cells of type $lut. Using template $paramod$2d4effcda09504a44b41d62137fca97840e3210c\$lut for cells of type $lut. Using template $paramod$d1dc785fc5b97e7bec2be30ee7302c8cf250ad22\$lut for cells of type $lut. Using template $paramod$25003f26a78bb2f583f23824f1e0b8cc16b88761\$lut for cells of type $lut. Using template $paramod$f8169086616a0eb4d0ea88125874a481b0bb2090\$lut for cells of type $lut. Using template $paramod$bbb10333e84a7e80f65e1494ebbfbf3f28568fcd\$lut for cells of type $lut. Using template $paramod$e3c5e4de270b555fd5b553e75491e305e290adfd\$lut for cells of type $lut. Using template $paramod$7f7120086b74d2ad6501bbaa30925c183268a1c2\$lut for cells of type $lut. Using template $paramod$0f1054d7a869eb1bffa14eab6537eeff64eb55da\$lut for cells of type $lut. Using template $paramod$0a9eb06856e79147b55c3d0c0349afae6651a745\$lut for cells of type $lut. Using template $paramod$b8a9d8ae3b3950088a96894de3fff6220fc9662e\$lut for cells of type $lut. Using template $paramod$09b813bb6c5a558fc67def49aea529f64a1997b9\$lut for cells of type $lut. Using template $paramod$c0cfc4c0f924b5e4a70961bc6a08a3b59cf72816\$lut for cells of type $lut. Using template $paramod$7febf92beabc81e16882a3f10047be87ba16913b\$lut for cells of type $lut. Using template $paramod$011a58a5aa41df7f13c8b832b7dc368743702325\$lut for cells of type $lut. Using template $paramod$52953750219effadf43093a566baf492fdd6b6c8\$lut for cells of type $lut. Using template $paramod$0d7ad76593d50ae78298d61c0138ea6f41e79e31\$lut for cells of type $lut. Using template $paramod$acbfd10ed3af1f799a8ca7a820470a646a2749e3\$lut for cells of type $lut. Using template $paramod$d96938b933811903763c8fc48238ba3a4fe3fe61\$lut for cells of type $lut. Using template $paramod$af3558b702f069846f44500ffe1a710a11b7c074\$lut for cells of type $lut. Using template $paramod$1ad9ca75a5e52e69f39f16c0b8ffb14773a0b7f2\$lut for cells of type $lut. Using template $paramod$c627e7fc36fd5f8fca16a74816d11be60e4b9470\$lut for cells of type $lut. Using template $paramod$40c0704488bfccd0953aa85a1fac93290c3e26ca\$lut for cells of type $lut. Using template $paramod$c5ded15be06e900632ca8fe083739cc25f30fa33\$lut for cells of type $lut. Using template $paramod$c8f16510db975553c8b0be1064e8f5234175f8a8\$lut for cells of type $lut. Using template $paramod$1ea513237b15940ef14fc0aa0b918a04c0414a4b\$lut for cells of type $lut. Using template $paramod$d5b95ef1c89d834e3e72966caf0c9ff97c5cfa95\$lut for cells of type $lut. Using template $paramod$fcff9a7b1687e357a40264efcefe8443c8b2971a\$lut for cells of type $lut. Using template $paramod$a42737e949e43313b0e8ebd7e66af7e6b04852ee\$lut for cells of type $lut. Using template $paramod$b4e9ea3921e02bce0d630933f106608ba1bed76e\$lut for cells of type $lut. Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut. Using template $paramod$e0286d7bdebdb6346cb367bb1962e01892ba2e32\$lut for cells of type $lut. Using template $paramod$786439ed757539cb2d3cb203aaa39706d1fbcbba\$lut for cells of type $lut. Using template $paramod$9d5048be4e9740fe3e1201704fdac42dd6b02a08\$lut for cells of type $lut. Using template $paramod$9dd298ae76fb41ac94779a83c068607fbc09ce4f\$lut for cells of type $lut. Using template $paramod$4fd3428c4b8b1accf8f8fb4bb88555a2b5fa688d\$lut for cells of type $lut. Using template $paramod$20935fa41751729f24d9e5054d788cd1d6170bd2\$lut for cells of type $lut. Using template $paramod$fa45f28daf300aaa781ee4b9baa5ce968b1d8c66\$lut for cells of type $lut. Using template $paramod$40e5a5bffee68d424d8b966d83c16c547cdeb8ab\$lut for cells of type $lut. Using template $paramod$cf9f8c485a0e1fdf92028a9b644f333d9756d793\$lut for cells of type $lut. Using template $paramod$9dd503014aa2dffd444d341a10442588e5a2f7f2\$lut for cells of type $lut. Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314\$lut for cells of type $lut. Using template $paramod$62e34d236b5cf9e50e7481784c0097067a15fba4\$lut for cells of type $lut. Using template $paramod$1ad72ddb1e399b5b822d7ca30d348b7d696d69eb\$lut for cells of type $lut. Using template $paramod$13caa797f9204188208579865e8a63f743d9eed1\$lut for cells of type $lut. Using template $paramod$6e64c13666511ae2ccc90ab6ddaf8be09bda5af2\$lut for cells of type $lut. Using template $paramod$e25009ededa6f42bbbb7dfa8b8d6d0e140dddb83\$lut for cells of type $lut. Using template $paramod$481167b39f8abb0a99a99d3d73f78c67f4c8fc07\$lut for cells of type $lut. Using template $paramod$9fe1b13423afde8c0340b342466aa1e66c78129d\$lut for cells of type $lut. Using template $paramod$dcd53277168363d86e52bd34c1e0ed29cac510d6\$lut for cells of type $lut. Using template $paramod$1bf62ab10e48d71d6497bccacf5c70420c470fe9\$lut for cells of type $lut. Using template $paramod$e8ed3122d39260aca8a6cf0a3f6bedd6d4a55c1c\$lut for cells of type $lut. Using template $paramod$1f40a9eae32a7201e2aa988939ab90fb73c6f51a\$lut for cells of type $lut. Using template $paramod$25da9d86af30ba2de7e4932c3cb954b5a63f67cd\$lut for cells of type $lut. Using template $paramod$9a55860b2276891136a73f7366001294a0bdcce9\$lut for cells of type $lut. Using template $paramod$72ce6fc0d1bafbc3a03d451d76dd2dac9cd11fe0\$lut for cells of type $lut. Using template $paramod$1632c1c0242796acfc963a05742c4acd2f475c4e\$lut for cells of type $lut. Using template $paramod$4d5fa0c21aaa9745a301eda7465c650b5896bed0\$lut for cells of type $lut. Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221\$lut for cells of type $lut. Using template $paramod$179bbca2dd7fa841ad12e8b0327ef61d6e9a7bc3\$lut for cells of type $lut. Using template $paramod$b89c522b7f70adaee1a35d80e932f38159b6a445\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110111 for cells of type $lut. Using template $paramod$176a6ceafa512d807921d7dfc76320dfbbfb5fe4\$lut for cells of type $lut. Using template $paramod$899a7d400185b4f778bea81a50f62c95a0b19d77\$lut for cells of type $lut. Using template $paramod$3ae3f75309f050b3bab755777ce88b11dc748157\$lut for cells of type $lut. Using template $paramod$034a69dd110db95ee917f313eafd6833fc6595f9\$lut for cells of type $lut. Using template $paramod$b4f15f202f50520dbc381cd0880ac94f830f05a8\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110100 for cells of type $lut. Using template $paramod$99d0ff9c2bade6603f504375b8acbb92213fb3a9\$lut for cells of type $lut. Using template $paramod$34f8a26453535646b9d6a3b77eb2dc80c3d31c62\$lut for cells of type $lut. Using template $paramod$42c7f7e0577b90a637faf761b61988640dc1e9f6\$lut for cells of type $lut. Using template $paramod$8cbea7472fe8ec8b0d9b301f17edad7f1c398048\$lut for cells of type $lut. Using template $paramod$044a0ce14c07f8137d92adda275c82e8782a2249\$lut for cells of type $lut. Using template $paramod$0d3ac82cf5b8a192d5ff4c23e3143360366ae882\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110010 for cells of type $lut. Using template $paramod$5b4b4ed558983d9f3ab4c896a7a011d129b0db9a\$lut for cells of type $lut. Using template $paramod$5dc745bb48e2cf535179547ba13f0fe5364d6d54\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110011 for cells of type $lut. Using template $paramod$bb4fff1cc3b827238aa40993cafede1c5beecbe3\$lut for cells of type $lut. Using template $paramod$cd3a53160bf1c20498f318053973a5579390d423\$lut for cells of type $lut. Using template $paramod$e4723c78131b859cdb296cc7099a965ce6bf28d9\$lut for cells of type $lut. Using template $paramod$359fe4e746656bf9c72aecaff84fc7bdea9f55a5\$lut for cells of type $lut. Using template $paramod$6fe34497620f8f4f756f16a037c2550db7a0a0b5\$lut for cells of type $lut. Using template $paramod$eac5ed09855cbfd5e73aad679d92627678c878a8\$lut for cells of type $lut. Using template $paramod$8be603794459732f9a374f76041b510fc63b115b\$lut for cells of type $lut. Using template $paramod$36a9fdea78660cfe315c27f5513f1b18d4a42960\$lut for cells of type $lut. Using template $paramod$71dfe9e789ababb1d1cb0a8b4c973cef67eeeec4\$lut for cells of type $lut. Using template $paramod$1dd08ae0c9c75c235d9038ee381888349f8b521a\$lut for cells of type $lut. Using template $paramod$861750984ac6db91b43268b1543d519f3e2b5c9f\$lut for cells of type $lut. Using template $paramod$1bbcbaf30677779d17245c2d62cb0b764a8171b2\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110011 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101110 for cells of type $lut. Using template $paramod$07e408f55ede597e07cdd5621f1308672fd3eb71\$lut for cells of type $lut. Using template $paramod$65f1ff7be04d4e6845f52e26be882f3e1d48a59a\$lut for cells of type $lut. Using template $paramod$bae397089b0689f402e0584dc417eb302546381e\$lut for cells of type $lut. Using template $paramod$17c27ffdda03355f95b2ba5edc73ca082237c935\$lut for cells of type $lut. Using template $paramod$e76779fd0aff146fdcbb917367fc19054812bcda\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111011 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110111 for cells of type $lut. Using template $paramod$ed89e5bafea5a44fb72d3e7d06b38b80c2d83edf\$lut for cells of type $lut. Using template $paramod$272990cb71745a7561b4e2dc3a26ca515ebfc277\$lut for cells of type $lut. Using template $paramod$a8ac3f2e43cfa128c2e8ae9cb6916fb4a877d056\$lut for cells of type $lut. Using template $paramod$46a3c0240e7a0e1ba60e351b8dd1863f2b554f8b\$lut for cells of type $lut. Using template $paramod$c4bf18335045bc5aba02d1004774c821a926f55f\$lut for cells of type $lut. Using template $paramod$f8a339f73677ba371413fc82c76e9f4e03977b78\$lut for cells of type $lut. Using template $paramod$ba1896d66a423e98734f1413876089b255b9a5bb\$lut for cells of type $lut. Using template $paramod$17c2f243a1da896c622c9087a9b7432bee6819fa\$lut for cells of type $lut. Using template $paramod$bf9d676dd5a15572d0e69198dcbc06929c8bebe6\$lut for cells of type $lut. Using template $paramod$8aff4745ca2a2cd3f579e51bfdbff4b32cd190ce\$lut for cells of type $lut. Using template $paramod$d10f9a84f94c1fdeb995fd3fe4295157e882ad0b\$lut for cells of type $lut. Using template $paramod$bb15606221c11e6e3631d8c40c9f07e2e0505b07\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut. Using template $paramod$ba039129d65dd249303a11d6e14b06e2506967c3\$lut for cells of type $lut. Using template $paramod$ba4467cb683b35a22e8871b38bcbc7c919f12359\$lut for cells of type $lut. Using template $paramod$923d6d0b98606d742c4e836383c21d150aee790b\$lut for cells of type $lut. Using template $paramod$fbaa1bfd23c97926136b324ed033510b12255dd4\$lut for cells of type $lut. Using template $paramod$0ea9f4e845e52bd7830962784cc82631df5269eb\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101100 for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut. Using template $paramod$e1ac894a2723e96ae103a1941dc871fbb0ccd216\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101111 for cells of type $lut. Using template $paramod$cd05f04889088c47a0a5abae8c2d644fd314805e\$lut for cells of type $lut. Using template $paramod$354f3ad2016291685024e599e50228612f67e554\$lut for cells of type $lut. Using template $paramod$468a70be730014d0c6e821be1fc5e5264e8b9a73\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001110 for cells of type $lut. Using template $paramod$f7e977e4ab769956ecac4448595a773db86c44e8\$lut for cells of type $lut. Using template $paramod$00dfa99b7aecc2e72490719b192118cbd6549a2c\$lut for cells of type $lut. Using template $paramod$9664b2f5fd61944d7798b30cde43b99ccda87303\$lut for cells of type $lut. Using template $paramod$7295da7c5b19f528a428229f2570e0a23ad372af\$lut for cells of type $lut. Using template $paramod$027b71830bd0fbfb04ad11206c5a0de76ed9d3f5\$lut for cells of type $lut. Using template $paramod$47b2f5a9f58cb4be072657772748a1ab82d6819a\$lut for cells of type $lut. Using template $paramod$c27bfee844081d0792e62d80b8db1170ed6df497\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut. Using template $paramod$02a84e953c934e9642efdb93d82c4cd5e0545198\$lut for cells of type $lut. Using template $paramod$432f26b811c14bf54c5e87c8670ec65cbcaf38ac\$lut for cells of type $lut. Using template $paramod$d50aaf7bc91b84437dde85e30486261cdbeeccac\$lut for cells of type $lut. Using template $paramod$bb91a41b6c6e90c9de123b408208c402cb3d3d4b\$lut for cells of type $lut. Using template $paramod$a1a52930161efb3548b305235290095b0bb0b543\$lut for cells of type $lut. Using template $paramod$43c617f6abf3506f31a0abb1a495aa57c34bbd13\$lut for cells of type $lut. Using template $paramod$ee82f1504b2c48e70160208feb4e1f2a1b612b8d\$lut for cells of type $lut. Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110001 for cells of type $lut. Using template $paramod$4789582d00084c3344b7a6dacf516efd46244876\$lut for cells of type $lut. Using template $paramod$6fc68b7e66a241641d7b1e06e3c55b5d94382873\$lut for cells of type $lut. Using template $paramod$6384a6dbebbe2905e798b075d02ab1c3e34618ff\$lut for cells of type $lut. Using template $paramod$0d44a3a6c6ee0cb4f7c04a7c9a640cffb0e5ac17\$lut for cells of type $lut. Using template $paramod$c5f3c57a6d466a2f42208bafb8985b96ce884440\$lut for cells of type $lut. Using template $paramod$7944ff32b1c2f3f3b05dfca0358698adebf48442\$lut for cells of type $lut. Using template $paramod$a59854b679c443f21a6748ea460109b8241cb007\$lut for cells of type $lut. Using template $paramod$da534c42d7c4da455a49d30923fb0b0a7ae4a63e\$lut for cells of type $lut. Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut. Using template $paramod$a707fff23748f6aa14ef55b3ae1f771b0f87b0eb\$lut for cells of type $lut. Using template $paramod$34536926332939882b8ff52380fffc08ed1f405f\$lut for cells of type $lut. No more expansions possible. <suppressed ~14445 debug messages> 24.44. Executing OPT_LUT_INS pass (discard unused LUT inputs). Optimizing LUTs in processorci_top. Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202241.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201696.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202067.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202067.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202332.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202078.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202256.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201851.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201798.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201912.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201983.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202192.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202192.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202216.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202379.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201950.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$30987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$30987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$30987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$30987.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$30952.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$30887.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$30629.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$30612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30594.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$30254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$29872.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29872.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29872.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$29872.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$29872.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$29856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$29837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$29837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$29837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$29522.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$29458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$29333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$29333.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$29299.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29293.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29238.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29238.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201807.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$28783.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28779.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28648.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$28523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$28516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$28516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$28499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$28234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28234.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$28061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28061.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28055.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$27998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201865.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$27637.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$27599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$27569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$27425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$27425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$27425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$27418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$27418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$27418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$27396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$27396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$27396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$27396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27026.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27021.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$26999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$26999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$26999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$26985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26985.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$26966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26950.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26950.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26596.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26596.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26596.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[18].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[18].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[18].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[18].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[18].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[18].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26120.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$26092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$26092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$26092.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$26081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$26081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$26075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$25817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$25817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$25817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$25801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$25801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25767.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$25725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$25725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$25725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$25725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$25725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$25713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$25508.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$25341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25341.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$25303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$25303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$25291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$25291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$25264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$25264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$25247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$25247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$25247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$25247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$25247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$25247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$25247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25143.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$24890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24890.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$24830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$24830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$24830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$24830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$24830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$24830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$24830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$24814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$24471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$24471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$24443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$24212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$23781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23298.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$23235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$22905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$22850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$22850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$22850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$22621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$21708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$21708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21701.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21697.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21669.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$21664.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21423.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21418.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21082.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21082.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21082.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$21082.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$21082.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$21082.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$20953.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$20654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$20654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$20356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$20356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$20356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$20356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$20356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$20347.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$20334.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$19646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$19646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$19186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$19186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$19186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$19186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$19177.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$18797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$18797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$18774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$18774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$18774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$18774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$18774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$18468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$18468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$18468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17933.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17929.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$17911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$17911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$17463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$17463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$17463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$17463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$17442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$17408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$17398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$16166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$16166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$16143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$15912.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$15733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$15733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$15733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$15256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$14411.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$14297.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13145.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$13140.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$13129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13108.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13108.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$11824.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$11781.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12902.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12959.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12093.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12154.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12943.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12943.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$11977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$12837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$11781.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$11787.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$11787.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$11794.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$11794.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$11808.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$11824.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$11830.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$11830.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$11837.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$11837.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$11848.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$11866.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$11884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$11940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$11957.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$11977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$11977.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12003.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12037.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12093.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12087.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12093.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12103.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12128.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12134.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12146.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12185.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12192.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12222.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12258.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12297.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12323.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12331.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12347.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12363.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12391.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12398.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12447.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12478.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12485.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12501.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12511.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12518.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12568.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12575.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12585.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12601.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12608.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12625.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12139.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12634.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12666.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12682.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12701.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12750.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12778.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12808.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12819.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12824.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12857.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12902.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12891.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12902.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12920.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12980.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12814.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$12985.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$13000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13000.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13086.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13108.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13108.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13120.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13129.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$13156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13167.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13178.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$13216.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$13239.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13268.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13296.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13324.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13354.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13429.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13499.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13555.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13619.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$13714.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13776.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13796.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$13965.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$14006.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$14096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$14233.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$14252.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$14257.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$14278.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$14284.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$14312.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$14340.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$14344.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$14389.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$14400.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$14426.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$14441.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$14501.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$14531.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$14545.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$14699.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$14715.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$14730.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$14745.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$auto$abc9_ops.cc:595:break_scc$55964.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$14811.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$auto$opt_dff.cc:219:make_patterns_logic$6750.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$14894.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$14997.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15013.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15023.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15097.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$15256.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$15267.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$15273.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$15289.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15298.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$15305.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15321.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15337.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15353.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15372.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15388.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15422.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15454.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15480.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15487.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15497.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15513.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15531.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15547.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15554.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15564.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15580.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15631.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15666.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15682.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15689.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15699.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15715.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15733.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15740.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15756.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15772.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15788.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15807.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15840.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$15856.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16071.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16085.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16094.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16106.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16157.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$16166.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$16173.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16189.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16239.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16290.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16308.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16324.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16331.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16341.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16357.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16408.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16424.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16437.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$16450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16466.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16476.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16483.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16517.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16550.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16566.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16579.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16587.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16603.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16619.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16635.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16687.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16703.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16716.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$16734.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16762.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16772.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16788.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16798.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16805.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16872.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$16966.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17099.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17130.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17140.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17147.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17243.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17316.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17332.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17351.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17398.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17408.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17413.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$17413.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$17424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17433.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17442.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17463.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$17475.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$17496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$17496.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$17503.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17519.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17529.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17536.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17552.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17559.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17608.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17618.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17631.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17674.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17690.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17793.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17809.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17844.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17860.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17867.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17911.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18179.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18195.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18229.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18245.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18261.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18280.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18314.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18337.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18380.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18396.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18431.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18460.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$18468.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18475.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18491.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18507.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18523.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18581.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18597.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18613.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18662.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18678.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18706.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18713.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18729.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$18747.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$18789.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$18804.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$18899.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18915.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18925.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$18999.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19045.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19186.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$19201.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$19211.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$19218.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19234.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19250.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19266.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19285.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19301.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19308.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19318.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19347.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$19366.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$19370.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$19377.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19403.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$19410.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19426.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19433.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19443.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19459.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19478.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19494.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19512.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19528.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19569.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$19579.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19612.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19628.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19646.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19653.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19679.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19686.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19753.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19769.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19782.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$19786.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19802.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$19820.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19836.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19846.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19853.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$19920.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20081.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20200.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20235.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20251.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20277.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20329.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$20356.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$20374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$20378.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$20385.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20401.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20417.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20433.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20468.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20484.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20500.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20513.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20520.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20536.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20552.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20568.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20654.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20710.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20726.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20755.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20762.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20778.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20831.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20847.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20891.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20898.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20914.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$20927.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$20947.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$20995.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21082.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21082.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$21109.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21125.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21135.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21142.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21208.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21224.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21237.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21254.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21287.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21294.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21304.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21343.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21368.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21373.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21389.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21428.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21432.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21447.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21455.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21471.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21496.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21512.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21517.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21531.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21554.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21570.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21595.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21605.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21621.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21654.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21669.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$21669.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$21679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$21679.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21708.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21730.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21746.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21813.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21831.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21847.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$21867.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$21982.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22031.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22047.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22057.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22064.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22131.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22185.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22218.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$22247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22371.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22471.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22487.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22497.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22504.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22571.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22621.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22642.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22661.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22677.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22683.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22691.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22691.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22711.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22757.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[9].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[9].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22850.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22864.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22898.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$22905.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$22910.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$23014.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23030.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23040.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23047.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23114.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$23235.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$23249.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23274.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23292.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$23305.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$23425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23523.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23539.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23558.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23574.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23623.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23639.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23649.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23656.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23723.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$23781.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$23830.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$23837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$23837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23886.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$24039.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24055.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24065.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24072.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24139.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24212.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$24235.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24253.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24265.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$24417.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$24424.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24443.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$24465.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24471.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24496.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$24554.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24570.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24580.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24587.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24654.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24807.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$24814.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24830.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$24853.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24882.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$24961.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25037.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25053.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25072.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25088.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25247.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$25264.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$25291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25291.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$25303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$25303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$25311.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25329.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$25374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25400.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25407.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25474.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25643.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$25713.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$25725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$25725.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$25736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25771.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$25801.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25806.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$25817.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25908.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25943.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25959.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26040.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26075.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26081.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26085.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$26110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26138.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26164.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26171.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26238.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26347.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26493.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26509.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26528.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26570.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26579.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26596.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26600.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$26613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$26633.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26709.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26807.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26823.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26833.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26840.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26907.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26966.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$27015.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27203.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27219.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27229.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27236.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27303.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27396.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27418.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$27425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27425.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$27471.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27533.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27569.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27599.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$27604.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$27622.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$27658.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27681.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27697.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27707.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27714.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27781.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$27998.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$28028.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$28048.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$28085.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28101.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28111.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28118.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28185.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28201.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28295.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28386.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28402.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28421.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28437.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28509.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28516.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28523.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$28564.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$28570.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28723.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28761.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$28827.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28853.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28934.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28969.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$28985.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29153.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29204.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29253.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29286.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$29304.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$29458.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$29481.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$29493.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29507.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29595.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29605.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29621.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29631.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29638.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29705.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[27].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$29837.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29856.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$29872.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29872.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29897.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29968.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29984.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29994.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30001.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30134.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30182.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30206.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$30213.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30254.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30357.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30373.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30392.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30408.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30511.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30598.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30612.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30629.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$30643.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$30649.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30712.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30728.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30738.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30745.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30812.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30894.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30899.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$30932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$30952.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$30957.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$30957.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$31058.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$31096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$31112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$31122.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$31129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$31196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$31212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23219.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$auto$opt_dff.cc:219:make_patterns_logic$6829.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$14777.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$23955.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$24784.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$25587.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$auto$fsm_map.cc:170:map_fsm$6365[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$flatten\u_tinyriscv.\u_clint.$procmux$5959_Y[0].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$23336.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$26674.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27456.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$20004.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[14].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28692.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$29421.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$27167.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202361.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$15891.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$22434.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut\Controller.memory_read_data[23].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut\Controller.memory_read_data[31].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[18].genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg1_rdata_i[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$flatten\u_tinyriscv.\u_div.$procmux$5478_Y[0].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$23385.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$24317.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[16].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[18].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$26714.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[20].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$28239.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[24].genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201754.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17089.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $abc$201690$lut$aiger201689$17938.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut$aiger201689$20958.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[10].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $abc$201690$lut\u_tinyriscv.u_id.reg2_rdata_i[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$18797.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$18083.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201695.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201697.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201702.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201703.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201707.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201727.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201739.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201740.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201752.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201763.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201766.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201769.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201866.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202145.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202134.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201835.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202159.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201844.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201851.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201866.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201871.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201873.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202093.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201875.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201797.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201803.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201892.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201892.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202003.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201818.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201912.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201930.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201937.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201937.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201975.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201981.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201983.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201991.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202003.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201850.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202013.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202017.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202021.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202021.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$24722.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202040.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202040.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202042.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202047.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202051.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202065.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202067.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202069.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202071.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202079.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202164.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201844.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202094.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202099.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202100.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202280.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201846.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202113.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202114.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202116.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201853.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202071.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202127.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202128.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201897.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201903.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202160.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202133.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202134.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202124.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202143.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202145.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202147.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202153.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202156.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202164.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202174.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202179.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202092.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202182.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202183.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202187.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202187.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202192.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202199.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202214.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202216.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202219.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202220.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202221.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202225.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202227.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202322.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202178.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202239.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202244.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202252.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202255.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202259.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202279.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202271.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202275.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202240.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202282.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202285.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202291.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$201746.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202297.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202302.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202303.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202272.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202322.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202077.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202099.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202336.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202379.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202359.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202361.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202364.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202368.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202371.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202379.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202387.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$12976.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12933.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $abc$201690$lut$aiger201689$12949.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2) Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$202227.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3) Optimizing lut $abc$201690$lut$aiger201689$22311.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0) Removed 0 unused cells and 17892 unused wires. 24.45. Executing AUTONAME pass. Renamed 820503 objects in module processorci_top (333 iterations). <suppressed ~21849 debug messages> 24.46. Executing HIERARCHY pass (managing design hierarchy). 24.46.1. Analyzing design hierarchy.. Top module: \processorci_top 24.46.2. Analyzing design hierarchy.. Top module: \processorci_top Removed 0 unused modules. 24.47. Printing statistics. === processorci_top === Number of wires: 9982 Number of wire bits: 33409 Number of public wires: 9982 Number of public wire bits: 33409 Number of ports: 10 Number of port bits: 10 Number of memories: 0 Number of memory bits: 0 Number of processes: 0 Number of cells: 13508 $scopeinfo 38 CCU2C 496 L6MUX21 467 LUT4 8316 MULT18X18D 4 PFUMX 1497 TRELLIS_DPR16X4 1060 TRELLIS_FF 1630 24.48. Executing CHECK pass (checking for obvious problems). Checking module processorci_top... Found and reported 0 problems. 24.49. Executing JSON backend. Warnings: 3 unique messages, 3 total End of script. Logfile hash: ad670c8827, CPU: user 41.71s system 0.34s, MEM: 385.61 MB peak Yosys 0.45+139 (git sha1 4d581a97d, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3) Time spent: 27% 1x abc9_exe (16 sec), 14% 1x autoname (8 sec), ... /eda/oss-cad-suite/bin/nextpnr-ecp5 --json colorlight_i9.json --write colorlight_i9_pnr.json --45k \ --lpf /eda/processor_ci/constraints/colorlight_i9.lpf --textcfg colorlight_i9.config --package CABGA381 \ --speed 6 --lpf-allow-unconstrained --ignore-loops /eda/oss-cad-suite/bin/ecppack --compress --input colorlight_i9.config --bit colorlight_i9.bit [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash colorlight_i9) [Pipeline] dir Running in /var/jenkins_home/workspace/tinyriscv/tinyriscv [Pipeline] { [Pipeline] echo Flashing FPGA colorlight_i9. [Pipeline] sh + python3 /eda/processor_ci/main.py -c /eda/processor_ci/config.json -p tinyriscv -b colorlight_i9 -l Final configuration file generated at /var/jenkins_home/workspace/tinyriscv/tinyriscv/build_colorlight_i9.tcl Makefile executed successfully. Makefile output: /eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 colorlight_i9.bit empty Found 1 compatible device: 0x0d28 0x0204 0x3 (null) Open file: DONE b3bdffff Parse file: DONE Enable configuration: DONE SRAM erase: DONE Loading: [==== ] 7.23% Loading: [======== ] 14.45% Loading: [=========== ] 21.68% Loading: [=============== ] 28.90% Loading: [=================== ] 36.13% Loading: [====================== ] 43.35% Loading: [========================== ] 50.58% Loading: [============================= ] 57.81% Loading: [================================= ] 65.03% Loading: [===================================== ] 72.26% Loading: [======================================== ] 79.48% Loading: [============================================ ] 86.71% Loading: [=============================================== ] 93.93% Loading: [==================================================] 100.00% Done Disable configuration: DONE [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Test colorlight_i9) [Pipeline] echo Testing FPGA colorlight_i9. [Pipeline] dir Running in /var/jenkins_home/workspace/tinyriscv/tinyriscv [Pipeline] { [Pipeline] sh + echo Test for FPGA in /dev/ttyACM0 Test for FPGA in /dev/ttyACM0 [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: colorlight_i9] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Declarative: Post Actions) [Pipeline] junit Recording test results No test report files were found. Configuration error? Error when executing always post condition: Also: org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: 2f3070e0-a3a0-4ee9-a1f4-a22a2d36e015 hudson.AbortException: No test report files were found. Configuration error? at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253) at hudson.FilePath.act(FilePath.java:1234) at hudson.FilePath.act(FilePath.java:1217) at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27) at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:47) at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source) at java.base/java.util.concurrent.FutureTask.run(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source) at java.base/java.lang.Thread.run(Unknown Source) [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline ERROR: script returned exit code 1 Finished: FAILURE