Console Output

Started by timer
[Pipeline] Start of Pipeline
[Pipeline] node
Running on Jenkins in /var/lib/jenkins/workspace/tinyriscv
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Git Clone)
[Pipeline] sh
+ rm -rf tinyriscv
[Pipeline] sh
+ git clone --recursive https://github.com/liangkangnan/tinyriscv tinyriscv
Cloning into 'tinyriscv'...
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Simulation)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/tinyriscv/tinyriscv
[Pipeline] {
[Pipeline] sh
+ iverilog -o simulation.out -g2005 -s tinyriscv -I rtl/core/ rtl/core/clint.v rtl/core/csr_reg.v rtl/core/ctrl.v rtl/core/div.v rtl/core/ex.v rtl/core/id.v rtl/core/id_ex.v rtl/core/if_id.v rtl/core/pc_reg.v rtl/core/regs.v rtl/core/rib.v rtl/core/tinyriscv.v rtl/utils/gen_dff.v
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (FPGA Build Pipeline)
[Pipeline] parallel
[Pipeline] { (Branch: colorlight_i9)
[Pipeline] { (Branch: digilent_nexys4_ddr)
[Pipeline] stage
[Pipeline] { (colorlight_i9)
[Pipeline] stage
[Pipeline] { (digilent_nexys4_ddr)
[Pipeline] lock
Trying to acquire lock on [Resource: colorlight_i9]
The resource [colorlight_i9] is locked by build AUK-V-Aethia #35 #35 since Oct 22, 2024, 2:40 AM.
[Resource: colorlight_i9] is not free, waiting for execution ...
[Required resources: [colorlight_i9]] added into queue at position 0
[Pipeline] lock
Trying to acquire lock on [Resource: digilent_nexys4_ddr]
The resource [digilent_nexys4_ddr] is locked by build AUK-V-Aethia #35 #35 since Oct 22, 2024, 2:40 AM.
[Resource: digilent_nexys4_ddr] is not free, waiting for execution ...
[Required resources: [digilent_nexys4_ddr]] added into queue at position 1
Lock acquired on [Resource: colorlight_i9]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/tinyriscv/tinyriscv
[Pipeline] {
[Pipeline] echo
Iniciando síntese para FPGA colorlight_i9.
[Pipeline] sh
+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p tinyriscv -b colorlight_i9
Lock acquired on [Resource: digilent_nexys4_ddr]
[Pipeline] {
[Pipeline] stage
[Pipeline] { (Síntese e PnR)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/tinyriscv/tinyriscv
[Pipeline] {
[Pipeline] echo
Iniciando síntese para FPGA digilent_nexys4_ddr.
[Pipeline] sh
+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p tinyriscv -b digilent_nexys4_ddr
Arquivo de configura����o final gerado em /var/lib/jenkins/workspace/tinyriscv/tinyriscv/build_colorlight_i9.tcl
Makefile executado com sucesso.
Sa��da do Makefile:
/eda/oss-cad-suite/bin/yosys -c /var/lib/jenkins/workspace/tinyriscv/tinyriscv/build_colorlight_i9.tcl -DID=0x6a6a6a6a -DCLOCK_FREQ=25000000 -DMEMORY_SIZE=4096

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.45+139 (git sha1 4d581a97d, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3)

-- Running command `read -define ID=0x6a6a6a6a CLOCK_FREQ=25000000 MEMORY_SIZE=4096' --

1. Executing Verilog-2005 frontend: /eda/processor-ci/rtl/tinyriscv.v
Parsing Verilog input from `/eda/processor-ci/rtl/tinyriscv.v' to AST representation.
Generating RTLIL representation for module `\processorci_top'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v
Parsing Verilog input from `/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v' to AST representation.
Generating RTLIL representation for module `\clint'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v
Parsing Verilog input from `/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v' to AST representation.
Generating RTLIL representation for module `\csr_reg'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v
Parsing Verilog input from `/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v' to AST representation.
Generating RTLIL representation for module `\ctrl'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/div.v
Parsing Verilog input from `/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/div.v' to AST representation.
Generating RTLIL representation for module `\div'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v
Parsing Verilog input from `/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v' to AST representation.
Generating RTLIL representation for module `\ex'.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v
Parsing Verilog input from `/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v' to AST representation.
Generating RTLIL representation for module `\id'.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id_ex.v
Parsing Verilog input from `/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id_ex.v' to AST representation.
Generating RTLIL representation for module `\id_ex'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/if_id.v
Parsing Verilog input from `/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/if_id.v' to AST representation.
Generating RTLIL representation for module `\if_id'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v
Parsing Verilog input from `/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v' to AST representation.
Generating RTLIL representation for module `\pc_reg'.
Successfully finished Verilog frontend.

11. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v
Parsing Verilog input from `/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v' to AST representation.
Generating RTLIL representation for module `\regs'.
Successfully finished Verilog frontend.

12. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/rib.v
Parsing Verilog input from `/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/rib.v' to AST representation.
Generating RTLIL representation for module `\rib'.
Successfully finished Verilog frontend.

13. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/tinyriscv.v
Parsing Verilog input from `/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/tinyriscv.v' to AST representation.
Generating RTLIL representation for module `\tinyriscv'.
Successfully finished Verilog frontend.

14. Executing Verilog-2005 frontend: /var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v
Parsing Verilog input from `/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v' to AST representation.
Generating RTLIL representation for module `\gen_pipe_dff'.
Generating RTLIL representation for module `\gen_rst_0_dff'.
Generating RTLIL representation for module `\gen_rst_1_dff'.
Generating RTLIL representation for module `\gen_rst_def_dff'.
Generating RTLIL representation for module `\gen_en_dff'.
Successfully finished Verilog frontend.

15. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/uart.v
Parsing Verilog input from `/eda/processor-ci-controller/modules/uart.v' to AST representation.
Generating RTLIL representation for module `\UART'.
Successfully finished Verilog frontend.

16. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v' to AST representation.
Generating RTLIL representation for module `\uart_rx'.
Successfully finished Verilog frontend.

17. Executing Verilog-2005 frontend: /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v
Parsing Verilog input from `/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v' to AST representation.
Generating RTLIL representation for module `\uart_tx'.
Successfully finished Verilog frontend.

18. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/fifo.v
Parsing Verilog input from `/eda/processor-ci-controller/src/fifo.v' to AST representation.
Generating RTLIL representation for module `\FIFO'.
Successfully finished Verilog frontend.

19. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/reset.v
Parsing Verilog input from `/eda/processor-ci-controller/src/reset.v' to AST representation.
Generating RTLIL representation for module `\ResetBootSystem'.
Successfully finished Verilog frontend.

20. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/clk_divider.v
Parsing Verilog input from `/eda/processor-ci-controller/src/clk_divider.v' to AST representation.
Generating RTLIL representation for module `\ClkDivider'.
Successfully finished Verilog frontend.

21. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/memory.v
Parsing Verilog input from `/eda/processor-ci-controller/src/memory.v' to AST representation.
Generating RTLIL representation for module `\Memory'.
Successfully finished Verilog frontend.

22. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/interpreter.v
Parsing Verilog input from `/eda/processor-ci-controller/src/interpreter.v' to AST representation.
Generating RTLIL representation for module `\Interpreter'.
Successfully finished Verilog frontend.

23. Executing Verilog-2005 frontend: /eda/processor-ci-controller/src/controller.v
Parsing Verilog input from `/eda/processor-ci-controller/src/controller.v' to AST representation.
Generating RTLIL representation for module `\Controller'.
Successfully finished Verilog frontend.

24. Executing SYNTH_ECP5 pass.

24.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\LUT4'.
Generating RTLIL representation for module `\$__ABC9_LUT5'.
Generating RTLIL representation for module `\$__ABC9_LUT6'.
Generating RTLIL representation for module `\$__ABC9_LUT7'.
Generating RTLIL representation for module `\L6MUX21'.
Generating RTLIL representation for module `\CCU2C'.
Generating RTLIL representation for module `\TRELLIS_RAM16X2'.
Generating RTLIL representation for module `\PFUMX'.
Generating RTLIL representation for module `\TRELLIS_DPR16X4'.
Generating RTLIL representation for module `\DPR16X4C'.
Generating RTLIL representation for module `\LUT2'.
Generating RTLIL representation for module `\TRELLIS_FF'.
Generating RTLIL representation for module `\TRELLIS_IO'.
Generating RTLIL representation for module `\INV'.
Generating RTLIL representation for module `\TRELLIS_COMB'.
Generating RTLIL representation for module `\DP16KD'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

24.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_bb.v' to AST representation.
Generating RTLIL representation for module `\MULT18X18D'.
Generating RTLIL representation for module `\ALU54B'.
Generating RTLIL representation for module `\EHXPLLL'.
Generating RTLIL representation for module `\DTR'.
Generating RTLIL representation for module `\OSCG'.
Generating RTLIL representation for module `\USRMCLK'.
Generating RTLIL representation for module `\JTAGG'.
Generating RTLIL representation for module `\DELAYF'.
Generating RTLIL representation for module `\DELAYG'.
Generating RTLIL representation for module `\IDDRX1F'.
Generating RTLIL representation for module `\IDDRX2F'.
Generating RTLIL representation for module `\IDDR71B'.
Generating RTLIL representation for module `\IDDRX2DQA'.
Generating RTLIL representation for module `\ODDRX1F'.
Generating RTLIL representation for module `\ODDRX2F'.
Generating RTLIL representation for module `\ODDR71B'.
Generating RTLIL representation for module `\OSHX2A'.
Generating RTLIL representation for module `\ODDRX2DQA'.
Generating RTLIL representation for module `\ODDRX2DQSB'.
Generating RTLIL representation for module `\TSHX2DQA'.
Generating RTLIL representation for module `\TSHX2DQSA'.
Generating RTLIL representation for module `\DQSBUFM'.
Generating RTLIL representation for module `\DDRDLLA'.
Generating RTLIL representation for module `\DLLDELD'.
Generating RTLIL representation for module `\CLKDIVF'.
Generating RTLIL representation for module `\ECLKSYNCB'.
Generating RTLIL representation for module `\ECLKBRIDGECS'.
Generating RTLIL representation for module `\DCCA'.
Generating RTLIL representation for module `\DCSC'.
Generating RTLIL representation for module `\DCUA'.
Generating RTLIL representation for module `\EXTREFB'.
Generating RTLIL representation for module `\PCSCLKDIV'.
Generating RTLIL representation for module `\PUR'.
Generating RTLIL representation for module `\GSR'.
Generating RTLIL representation for module `\SGSR'.
Generating RTLIL representation for module `\PDPW16KD'.
Successfully finished Verilog frontend.

24.3. Executing HIERARCHY pass (managing design hierarchy).

24.3.1. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     \ResetBootSystem
Used module:     \tinyriscv
Used module:         \clint
Used module:         \div
Used module:         \ex
Used module:         \id_ex
Used module:             \gen_pipe_dff
Used module:         \id
Used module:         \if_id
Used module:         \csr_reg
Used module:         \regs
Used module:         \ctrl
Used module:         \pc_reg
Used module:     \Controller
Used module:         \Memory
Used module:         \UART
Used module:             \uart_tx
Used module:             \uart_rx
Used module:             \FIFO
Used module:         \Interpreter
Used module:         \ClkDivider
Parameter \CYCLES = 20

24.3.2. Executing AST frontend in derive mode using pre-parsed AST for module `\ResetBootSystem'.
Parameter \CYCLES = 20
Generating RTLIL representation for module `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \WORD_SIZE_BY = 4
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

24.3.3. Executing AST frontend in derive mode using pre-parsed AST for module `\Controller'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \WORD_SIZE_BY = 4
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096

24.3.4. Executing AST frontend in derive mode using pre-parsed AST for module `\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Generating RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4

24.3.5. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 9600
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4
Generating RTLIL representation for module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 12
Parameter \BUS_WIDTH = 32
Parameter \ID = 1
Parameter \RESET_CLK_CYCLES = 20

24.3.6. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 12
Parameter \BUS_WIDTH = 32
Parameter \ID = 1
Parameter \RESET_CLK_CYCLES = 20
Generating RTLIL representation for module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 12

24.3.7. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 12
Generating RTLIL representation for module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'.
Parameter 1 (\DW) = 32

24.3.8. Executing AST frontend in derive mode using pre-parsed AST for module `\gen_pipe_dff'.
Parameter 1 (\DW) = 32
Generating RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'.
Parameter 1 (\DW) = 32
Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'.
Parameter 1 (\DW) = 32
Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'.
Parameter 1 (\DW) = 32
Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'.
Parameter 1 (\DW) = 32
Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'.
Parameter 1 (\DW) = 32
Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'.
Parameter 1 (\DW) = 1

24.3.9. Executing AST frontend in derive mode using pre-parsed AST for module `\gen_pipe_dff'.
Parameter 1 (\DW) = 1
Generating RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001'.
Parameter 1 (\DW) = 32
Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'.
Parameter 1 (\DW) = 32
Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'.
Parameter 1 (\DW) = 5

24.3.10. Executing AST frontend in derive mode using pre-parsed AST for module `\gen_pipe_dff'.
Parameter 1 (\DW) = 5
Generating RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101'.
Parameter 1 (\DW) = 1
Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001'.
Parameter 1 (\DW) = 32
Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'.
Parameter 1 (\DW) = 32
Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'.
Parameter 1 (\DW) = 8

24.3.11. Executing AST frontend in derive mode using pre-parsed AST for module `\gen_pipe_dff'.
Parameter 1 (\DW) = 8
Generating RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000'.
Parameter 1 (\DW) = 32
Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'.
Parameter 1 (\DW) = 32
Found cached RTLIL representation for module `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

24.3.12. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

24.3.13. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'.
Parameter \BIT_RATE = 9600
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8

24.3.14. Executing AST frontend in derive mode using pre-parsed AST for module `\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Generating RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

24.3.15. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     \tinyriscv
Used module:         \clint
Used module:         \div
Used module:         \ex
Used module:         \id_ex
Used module:             $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000
Used module:             $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001
Used module:             $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101
Used module:         \id
Used module:         \if_id
Used module:             $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000
Used module:         \csr_reg
Used module:         \regs
Used module:         \ctrl
Used module:         \pc_reg
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         \Memory
Used module:         \UART
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx
Used module:             $paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         \Interpreter
Used module:         \ClkDivider
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \MEMORY_FILE = { }
Parameter \MEMORY_SIZE = 4096
Found cached RTLIL representation for module `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4

24.3.16. Executing AST frontend in derive mode using pre-parsed AST for module `\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \BIT_RATE = 115200
Parameter \PAYLOAD_BITS = 8
Parameter \BUFFER_SIZE = 8
Parameter \WORD_SIZE_BY = 4
Generating RTLIL representation for module `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20

24.3.17. Executing AST frontend in derive mode using pre-parsed AST for module `\Interpreter'.
Parameter \CLK_FREQ = 25000000
Parameter \PULSE_CONTROL_BITS = 32
Parameter \BUS_WIDTH = 32
Parameter \ID = 0
Parameter \RESET_CLK_CYCLES = 20
Generating RTLIL representation for module `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 32

24.3.18. Executing AST frontend in derive mode using pre-parsed AST for module `\ClkDivider'.
Parameter \COUNTER_BITS = 32
Parameter \PULSE_CONTROL_BITS = 32
Generating RTLIL representation for module `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider'.

24.3.19. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     \tinyriscv
Used module:         \clint
Used module:         \div
Used module:         \ex
Used module:         \id_ex
Used module:             $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000
Used module:             $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001
Used module:             $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101
Used module:         \id
Used module:         \if_id
Used module:             $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000
Used module:         \csr_reg
Used module:         \regs
Used module:         \ctrl
Used module:         \pc_reg
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory
Used module:         $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART
Used module:             \uart_tx
Used module:             \uart_rx
Used module:             \FIFO
Used module:         $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter
Used module:         $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

24.3.20. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8

24.3.21. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'.
Parameter \BIT_RATE = 115200
Parameter \CLK_HZ = 25000000
Parameter \PAYLOAD_BITS = 8
Generating RTLIL representation for module `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.
Parameter \DEPTH = 8
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO'.

24.3.22. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     \tinyriscv
Used module:         \clint
Used module:         \div
Used module:         \ex
Used module:         \id_ex
Used module:             $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000
Used module:             $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001
Used module:             $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101
Used module:         \id
Used module:         \if_id
Used module:             $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000
Used module:         \csr_reg
Used module:         \regs
Used module:         \ctrl
Used module:         \pc_reg
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory
Used module:         $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter
Used module:         $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider

24.3.23. Analyzing design hierarchy..
Top module:  \processorci_top
Used module:     $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100
Used module:     \tinyriscv
Used module:         \clint
Used module:         \div
Used module:         \ex
Used module:         \id_ex
Used module:             $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000
Used module:             $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001
Used module:             $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101
Used module:         \id
Used module:         \if_id
Used module:             $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000
Used module:         \csr_reg
Used module:         \regs
Used module:         \ctrl
Used module:         \pc_reg
Used module:     $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller
Used module:         $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory
Used module:         $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx
Used module:             $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx
Used module:             $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO
Used module:         $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter
Used module:         $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_rx'.
Removing unused module `$paramod$47e501d01bc2413462576fdae8a5a8e558677547\uart_tx'.
Removing unused module `$paramod$d236a3555e5fe48231d3a0bdd0f1031eebbe67d5\ClkDivider'.
Removing unused module `$paramod$6cc68bce6e5ef8358e4f854f8e1607a73728e8ac\Interpreter'.
Removing unused module `$paramod$0ebcb351531b968e3a65ee57624639e797f21099\UART'.
Removing unused module `\Controller'.
Removing unused module `\Interpreter'.
Removing unused module `\Memory'.
Removing unused module `\ClkDivider'.
Removing unused module `\ResetBootSystem'.
Removing unused module `\FIFO'.
Removing unused module `\uart_tx'.
Removing unused module `\uart_rx'.
Removing unused module `\UART'.
Removing unused module `\gen_en_dff'.
Removing unused module `\gen_rst_def_dff'.
Removing unused module `\gen_rst_1_dff'.
Removing unused module `\gen_rst_0_dff'.
Removing unused module `\gen_pipe_dff'.
Removing unused module `\rib'.
Removed 20 unused modules.
Mapping positional arguments of cell if_id.int_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000).
Mapping positional arguments of cell if_id.inst_addr_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000).
Mapping positional arguments of cell if_id.inst_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000).
Mapping positional arguments of cell id_ex.op2_jump_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000).
Mapping positional arguments of cell id_ex.op1_jump_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000).
Mapping positional arguments of cell id_ex.op2_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000).
Mapping positional arguments of cell id_ex.op1_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000).
Mapping positional arguments of cell id_ex.csr_rdata_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000).
Mapping positional arguments of cell id_ex.csr_waddr_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000).
Mapping positional arguments of cell id_ex.csr_we_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001).
Mapping positional arguments of cell id_ex.reg2_rdata_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000).
Mapping positional arguments of cell id_ex.reg1_rdata_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000).
Mapping positional arguments of cell id_ex.reg_waddr_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101).
Mapping positional arguments of cell id_ex.reg_we_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001).
Mapping positional arguments of cell id_ex.inst_addr_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000).
Mapping positional arguments of cell id_ex.inst_ff ($paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000).
Warning: Resizing cell port processorci_top.u_tinyriscv.int_i from 1 bits to 8 bits.
Warning: Resizing cell port processorci_top.u_tinyriscv.jtag_reg_data_o from 1 bits to 32 bits.
Warning: Resizing cell port processorci_top.u_tinyriscv.jtag_reg_data_i from 1 bits to 32 bits.
Warning: Resizing cell port processorci_top.u_tinyriscv.jtag_reg_addr_i from 1 bits to 5 bits.

24.4. Executing PROC pass (convert processes to netlists).

24.4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$678'.
Found and cleaned up 1 empty switch in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$860'.
Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:0$860'.
Cleaned up 2 empty switches.

24.4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$785 in module TRELLIS_FF.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$737 in module DPR16X4C.
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$679 in module TRELLIS_DPR16X4.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:36$1052 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/fifo.v:25$1044 in module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1245 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1243 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1235 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1232 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1226 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1221 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1216 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1207 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1194 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1192 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1184 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1170 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1164 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1159 in module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Marked 1 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$945 in module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000.
Marked 1 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$942 in module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101.
Marked 1 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$939 in module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001.
Marked 1 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$936 in module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:57$1146 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
Marked 3 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/clk_divider.v:36$1137 in module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
Marked 15 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/interpreter.v:116$1101 in module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.
Removed 1 dead cases from process $proc$/eda/processor-ci-controller/modules/uart.v:203$1093 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:203$1093 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:187$1088 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:132$1083 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 4 switch rules as full_case in process $proc$/eda/processor-ci-controller/modules/uart.v:74$1078 in module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Marked 1 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/memory.v:36$849 in module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.
Marked 2 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/controller.v:113$838 in module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.
Marked 5 switch rules as full_case in process $proc$/eda/processor-ci-controller/src/reset.v:25$788 in module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Marked 1 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:91$262 in module regs.
Marked 2 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:79$256 in module regs.
Marked 2 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:67$250 in module regs.
Marked 3 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$221 in module regs.
Marked 3 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:35$212 in module pc_reg.
Removed 3 dead cases from process $proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205 in module id.
Marked 10 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205 in module id.
Removed 2 dead cases from process $proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142 in module ex.
Marked 21 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142 in module ex.
Marked 4 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136 in module ex.
Marked 2 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:172$126 in module ex.
Marked 15 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64 in module div.
Marked 3 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v:48$46 in module ctrl.
Marked 2 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:179$42 in module csr_reg.
Marked 2 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:141$38 in module csr_reg.
Marked 2 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$34 in module csr_reg.
Marked 1 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:66$31 in module csr_reg.
Marked 2 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:218$27 in module clint.
Marked 2 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:177$25 in module clint.
Marked 8 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:111$15 in module clint.
Marked 5 switch rules as full_case in process $proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:89$5 in module clint.
Removed a total of 6 dead cases.

24.4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 15 redundant assignments.
Promoted 140 assignments to connections.

24.4.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$786'.
  Set init value: \Q = 1'0
Found init rule in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1077'.
  Set init value: \read_ptr = 6'000000
  Set init value: \write_ptr = 6'000000
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1247'.
  Set init value: \i = 0
Found init rule in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1200'.
  Set init value: \i = 0
Found init rule in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1152'.
  Set init value: \clk_o_auto = 1'0
  Set init value: \clk_counter = 0
  Set init value: \pulse_counter = 0
Found init rule in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1130'.
  Set init value: \state = 8'00000000
  Set init value: \counter = 8'00000000
  Set init value: \read_buffer = 0
  Set init value: \timeout = 0
  Set init value: \accumulator = 64'0000000000000000000000000000000000000000000000000000000000000000
Found init rule in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1100'.
  Set init value: \read_response = 1'0
  Set init value: \write_response = 1'0
  Set init value: \read_data = 0
  Set init value: \uart_tx_en = 1'0
  Set init value: \tx_fifo_read = 1'0
  Set init value: \tx_fifo_write = 1'0
  Set init value: \rx_fifo_read = 1'0
  Set init value: \rx_fifo_write = 1'0
  Set init value: \uart_tx_data = 8'00000000
  Set init value: \tx_fifo_write_data = 8'00000000
  Set init value: \rx_fifo_write_data = 8'00000000
  Set init value: \counter_write = 3'000
  Set init value: \counter_read = 3'000
  Set init value: \state_read = 4'0000
  Set init value: \state_write = 4'0000
Found init rule in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$795'.
  Set init value: \reset_o = 1'0
  Set init value: \state = 2'01
  Set init value: \counter = 6'000000

24.4.5. Executing PROC_ARST pass (detect async resets in processes).

24.4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~193 debug messages>

24.4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$786'.
Creating decoders for process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$785'.
     1/1: $0\Q[0:0]
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
Creating decoders for process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$737'.
     1/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$736_EN[3:0]$743
     2/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$736_DATA[3:0]$742
     3/3: $1$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$736_ADDR[3:0]$741
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$703'.
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$679'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$677_EN[3:0]$685
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$677_DATA[3:0]$684
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$677_ADDR[3:0]$683
Creating decoders for process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$678'.
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1077'.
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1052'.
     1/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_EN[7:0]$1064
     2/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_DATA[7:0]$1063
     3/7: $2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_ADDR[5:0]$1062
     4/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_EN[7:0]$1058
     5/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_DATA[7:0]$1057
     6/7: $1$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_ADDR[5:0]$1056
     7/7: $0\write_ptr[5:0]
Creating decoders for process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1044'.
     1/2: $0\read_ptr[5:0]
     2/2: $0\read_data[7:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1247'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1245'.
     1/2: $0\rxd_reg_0[0:0]
     2/2: $0\rxd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1243'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1235'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1232'.
     1/1: $0\bit_sample[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1226'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1221'.
     1/11: $3\i[31:0]
     2/11: $0\recieved_data[7:0] [1]
     3/11: $0\recieved_data[7:0] [0]
     4/11: $0\recieved_data[7:0] [2]
     5/11: $0\recieved_data[7:0] [3]
     6/11: $0\recieved_data[7:0] [4]
     7/11: $0\recieved_data[7:0] [5]
     8/11: $0\recieved_data[7:0] [6]
     9/11: $0\recieved_data[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1216'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1207'.
     1/1: $0\uart_rx_data[7:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1200'.
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1194'.
     1/1: $0\txd_reg[0:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1192'.
     1/1: $0\fsm_state[2:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1184'.
     1/1: $0\cycle_counter[8:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1170'.
     1/1: $0\bit_counter[3:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1164'.
     1/11: $3\i[31:0]
     2/11: $0\data_to_send[7:0] [1]
     3/11: $0\data_to_send[7:0] [0]
     4/11: $0\data_to_send[7:0] [2]
     5/11: $0\data_to_send[7:0] [3]
     6/11: $0\data_to_send[7:0] [4]
     7/11: $0\data_to_send[7:0] [5]
     8/11: $0\data_to_send[7:0] [6]
     9/11: $0\data_to_send[7:0] [7]
    10/11: $1\i[31:0]
    11/11: $2\i[31:0]
Creating decoders for process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1159'.
     1/1: $1\n_fsm_state[2:0]
Creating decoders for process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$945'.
     1/1: $0\qout_r[7:0]
Creating decoders for process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$942'.
     1/1: $0\qout_r[4:0]
Creating decoders for process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$939'.
     1/1: $0\qout_r[0:0]
Creating decoders for process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$936'.
     1/1: $0\qout_r[31:0]
Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1152'.
Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1146'.
     1/1: $0\pulse_counter[31:0]
Creating decoders for process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1137'.
     1/2: $0\clk_counter[31:0]
     2/2: $0\clk_o_auto[0:0]
Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1130'.
Creating decoders for process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
     1/28: $0\state[7:0]
     2/28: $0\reset_bus[0:0]
     3/28: $0\memory_write[0:0]
     4/28: $0\memory_read[0:0]
     5/28: $0\write_pulse[0:0]
     6/28: $0\core_reset[0:0]
     7/28: $0\communication_write[0:0]
     8/28: $0\communication_read[0:0]
     9/28: $0\temp_buffer[63:0]
    10/28: $0\accumulator[63:0]
    11/28: $0\timeout_counter[31:0]
    12/28: $0\timeout[31:0]
    13/28: $0\read_buffer[31:0]
    14/28: $0\communication_buffer[31:0]
    15/28: $0\num_of_positions[23:0]
    16/28: $0\num_of_pages[23:0]
    17/28: $0\return_state[7:0]
    18/28: $0\memory_page_number[23:0]
    19/28: $0\memory_mux_selector[0:0]
    20/28: $0\end_position[31:0]
    21/28: $0\memory_page_size[23:0]
    22/28: $0\bus_mode[0:0]
    23/28: $0\num_of_cycles_to_pulse[31:0]
    24/28: $0\core_clk_enable[0:0]
    25/28: $0\communication_write_data[31:0]
    26/28: $0\counter[7:0]
    27/28: $0\write_data[31:0]
    28/28: $0\address[31:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1100'.
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1093'.
     1/4: $0\tx_fifo_read[0:0]
     2/4: $0\uart_tx_en[0:0]
     3/4: $0\tx_fifo_read_state[1:0]
     4/4: $0\uart_tx_data[7:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1088'.
     1/2: $0\rx_fifo_write[0:0]
     2/2: $0\rx_fifo_write_data[7:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1083'.
     1/6: $0\tx_fifo_write[0:0]
     2/6: $0\write_response[0:0]
     3/6: $0\state_write[3:0]
     4/6: $0\counter_write[2:0]
     5/6: $0\write_data_buffer[31:0]
     6/6: $0\tx_fifo_write_data[7:0]
Creating decoders for process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1078'.
     1/5: $0\read_response[0:0]
     2/5: $0\rx_fifo_read[0:0]
     3/5: $0\state_read[3:0]
     4/5: $0\counter_read[2:0]
     5/5: $0\read_data[31:0]
Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$859'.
Creating decoders for process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$849'.
     1/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$858
     2/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_DATA[31:0]$857
     3/4: $1$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_ADDR[31:0]$856
     4/4: $0\read_sync[31:0]
Creating decoders for process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$838'.
     1/1: $0\finish_execution[0:0]
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$795'.
Creating decoders for process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$788'.
     1/3: $0\counter[5:0]
     2/3: $0\state[1:0]
     3/3: $0\reset_o[0:0]
Creating decoders for process `\regs.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:91$262'.
     1/1: $1\jtag_data_o[31:0]
Creating decoders for process `\regs.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:79$256'.
     1/2: $2\rdata2_o[31:0]
     2/2: $1\rdata2_o[31:0]
Creating decoders for process `\regs.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:67$250'.
     1/2: $2\rdata1_o[31:0]
     2/2: $1\rdata1_o[31:0]
Creating decoders for process `\regs.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$221'.
     1/15: $3$memwr$\regs$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_EN[31:0]$249
     2/15: $3$memwr$\regs$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_DATA[31:0]$248
     3/15: $3$memwr$\regs$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_ADDR[4:0]$247
     4/15: $2$memwr$\regs$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$240
     5/15: $2$memwr$\regs$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_DATA[31:0]$239
     6/15: $2$memwr$\regs$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_ADDR[4:0]$238
     7/15: $2$memwr$\regs$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_EN[31:0]$243
     8/15: $2$memwr$\regs$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_DATA[31:0]$242
     9/15: $2$memwr$\regs$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_ADDR[4:0]$241
    10/15: $1$memwr$\regs$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_EN[31:0]$234
    11/15: $1$memwr$\regs$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_DATA[31:0]$233
    12/15: $1$memwr$\regs$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_ADDR[4:0]$232
    13/15: $1$memwr$\regs$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN[31:0]$231
    14/15: $1$memwr$\regs$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_DATA[31:0]$230
    15/15: $1$memwr$\regs$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_ADDR[4:0]$229
Creating decoders for process `\pc_reg.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:35$212'.
     1/1: $0\pc_o[31:0]
Creating decoders for process `\id.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'.
     1/72: $2\csr_we_o[0:0]
     2/72: $10\reg_waddr_o[4:0]
     3/72: $10\reg_we_o[0:0]
     4/72: $10\reg2_raddr_o[4:0]
     5/72: $10\reg1_raddr_o[4:0]
     6/72: $5\op2_jump_o[31:0]
     7/72: $5\op1_jump_o[31:0]
     8/72: $9\op2_o[31:0]
     9/72: $9\op1_o[31:0]
    10/72: $9\reg_waddr_o[4:0]
    11/72: $9\reg_we_o[0:0]
    12/72: $9\reg2_raddr_o[4:0]
    13/72: $9\reg1_raddr_o[4:0]
    14/72: $8\op2_o[31:0]
    15/72: $8\op1_o[31:0]
    16/72: $8\reg_waddr_o[4:0]
    17/72: $8\reg_we_o[0:0]
    18/72: $8\reg2_raddr_o[4:0]
    19/72: $8\reg1_raddr_o[4:0]
    20/72: $7\op2_o[31:0]
    21/72: $7\op1_o[31:0]
    22/72: $7\reg_waddr_o[4:0]
    23/72: $7\reg_we_o[0:0]
    24/72: $7\reg2_raddr_o[4:0]
    25/72: $7\reg1_raddr_o[4:0]
    26/72: $6\op2_o[31:0]
    27/72: $6\op1_o[31:0]
    28/72: $6\reg2_raddr_o[4:0]
    29/72: $6\reg1_raddr_o[4:0]
    30/72: $6\reg_waddr_o[4:0]
    31/72: $6\reg_we_o[0:0]
    32/72: $4\op2_jump_o[31:0]
    33/72: $4\op1_jump_o[31:0]
    34/72: $3\op2_jump_o[31:0]
    35/72: $3\op1_jump_o[31:0]
    36/72: $5\op2_o[31:0]
    37/72: $5\op1_o[31:0]
    38/72: $5\reg2_raddr_o[4:0]
    39/72: $5\reg1_raddr_o[4:0]
    40/72: $5\reg_we_o[0:0]
    41/72: $5\reg_waddr_o[4:0]
    42/72: $4\op2_o[31:0]
    43/72: $4\op1_o[31:0]
    44/72: $4\reg2_raddr_o[4:0]
    45/72: $4\reg1_raddr_o[4:0]
    46/72: $4\reg_waddr_o[4:0]
    47/72: $4\reg_we_o[0:0]
    48/72: $3\op2_o[31:0]
    49/72: $3\op1_o[31:0]
    50/72: $3\reg2_raddr_o[4:0]
    51/72: $3\reg1_raddr_o[4:0]
    52/72: $3\reg_we_o[0:0]
    53/72: $3\reg_waddr_o[4:0]
    54/72: $2\op2_jump_o[31:0]
    55/72: $2\op1_jump_o[31:0]
    56/72: $2\op2_o[31:0]
    57/72: $2\op1_o[31:0]
    58/72: $2\reg2_raddr_o[4:0]
    59/72: $2\reg1_raddr_o[4:0]
    60/72: $2\reg_waddr_o[4:0]
    61/72: $2\reg_we_o[0:0]
    62/72: $1\op2_o[31:0]
    63/72: $1\op1_o[31:0]
    64/72: $1\reg2_raddr_o[4:0]
    65/72: $1\reg1_raddr_o[4:0]
    66/72: $1\reg_we_o[0:0]
    67/72: $1\reg_waddr_o[4:0]
    68/72: $1\op2_jump_o[31:0]
    69/72: $1\op1_jump_o[31:0]
    70/72: $1\csr_raddr_o[31:0]
    71/72: $1\csr_waddr_o[31:0]
    72/72: $1\csr_we_o[0:0]
Creating decoders for process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'.
     1/96: $19\reg_wdata[31:0]
     2/96: $2\csr_wdata_o[31:0]
     3/96: $10\mem_we[0:0]
     4/96: $10\jump_addr[31:0]
     5/96: $10\jump_flag[0:0]
     6/96: $10\hold_flag[0:0]
     7/96: $10\mem_waddr_o[31:0]
     8/96: $10\mem_raddr_o[31:0]
     9/96: $12\mem_wdata_o[31:0]
    10/96: $9\jump_addr[31:0]
    11/96: $9\jump_flag[0:0]
    12/96: $18\reg_wdata[31:0]
    13/96: $9\mem_we[0:0]
    14/96: $9\mem_waddr_o[31:0]
    15/96: $9\mem_raddr_o[31:0]
    16/96: $11\mem_wdata_o[31:0]
    17/96: $9\hold_flag[0:0]
    18/96: $10\mem_wdata_o[31:0]
    19/96: $9\mem_wdata_o[31:0]
    20/96: $8\mem_wdata_o[31:0]
    21/96: $8\mem_raddr_o[31:0]
    22/96: $8\mem_waddr_o[31:0]
    23/96: $3\mem_req[0:0]
    24/96: $8\mem_we[0:0]
    25/96: $17\reg_wdata[31:0]
    26/96: $8\jump_addr[31:0]
    27/96: $8\hold_flag[0:0]
    28/96: $8\jump_flag[0:0]
    29/96: $16\reg_wdata[31:0]
    30/96: $15\reg_wdata[31:0]
    31/96: $14\reg_wdata[31:0]
    32/96: $13\reg_wdata[31:0]
    33/96: $12\reg_wdata[31:0]
    34/96: $7\mem_raddr_o[31:0]
    35/96: $2\mem_req[0:0]
    36/96: $7\mem_we[0:0]
    37/96: $7\mem_waddr_o[31:0]
    38/96: $7\mem_wdata_o[31:0]
    39/96: $7\jump_addr[31:0]
    40/96: $7\hold_flag[0:0]
    41/96: $7\jump_flag[0:0]
    42/96: $11\reg_wdata[31:0]
    43/96: $10\reg_wdata[31:0]
    44/96: $9\reg_wdata[31:0]
    45/96: $6\mem_we[0:0]
    46/96: $6\mem_waddr_o[31:0]
    47/96: $6\mem_raddr_o[31:0]
    48/96: $6\mem_wdata_o[31:0]
    49/96: $6\jump_addr[31:0]
    50/96: $6\hold_flag[0:0]
    51/96: $6\jump_flag[0:0]
    52/96: $5\mem_we[0:0]
    53/96: $5\jump_addr[31:0]
    54/96: $5\jump_flag[0:0]
    55/96: $5\hold_flag[0:0]
    56/96: $8\reg_wdata[31:0]
    57/96: $5\mem_waddr_o[31:0]
    58/96: $5\mem_raddr_o[31:0]
    59/96: $5\mem_wdata_o[31:0]
    60/96: $7\reg_wdata[31:0]
    61/96: $6\reg_wdata[31:0]
    62/96: $5\reg_wdata[31:0]
    63/96: $4\mem_we[0:0]
    64/96: $4\mem_waddr_o[31:0]
    65/96: $4\mem_raddr_o[31:0]
    66/96: $4\mem_wdata_o[31:0]
    67/96: $4\jump_addr[31:0]
    68/96: $4\hold_flag[0:0]
    69/96: $4\jump_flag[0:0]
    70/96: $3\mem_we[0:0]
    71/96: $3\jump_addr[31:0]
    72/96: $3\jump_flag[0:0]
    73/96: $3\hold_flag[0:0]
    74/96: $4\reg_wdata[31:0]
    75/96: $3\mem_waddr_o[31:0]
    76/96: $3\mem_raddr_o[31:0]
    77/96: $3\mem_wdata_o[31:0]
    78/96: $3\reg_wdata[31:0]
    79/96: $2\reg_wdata[31:0]
    80/96: $2\mem_we[0:0]
    81/96: $2\mem_waddr_o[31:0]
    82/96: $2\mem_raddr_o[31:0]
    83/96: $2\mem_wdata_o[31:0]
    84/96: $2\jump_addr[31:0]
    85/96: $2\hold_flag[0:0]
    86/96: $2\jump_flag[0:0]
    87/96: $1\mem_we[0:0]
    88/96: $1\jump_addr[31:0]
    89/96: $1\jump_flag[0:0]
    90/96: $1\hold_flag[0:0]
    91/96: $1\reg_wdata[31:0]
    92/96: $1\mem_waddr_o[31:0]
    93/96: $1\mem_raddr_o[31:0]
    94/96: $1\mem_wdata_o[31:0]
    95/96: $1\mem_req[0:0]
    96/96: $1\csr_wdata_o[31:0]
Creating decoders for process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'.
     1/19: $3\div_we[0:0]
     2/19: $3\div_waddr[4:0]
     3/19: $3\div_wdata[31:0]
     4/19: $3\div_hold_flag[0:0]
     5/19: $2\div_waddr[4:0]
     6/19: $2\div_wdata[31:0]
     7/19: $2\div_we[0:0]
     8/19: $3\div_start[0:0]
     9/19: $2\div_jump_addr[31:0]
    10/19: $2\div_hold_flag[0:0]
    11/19: $2\div_jump_flag[0:0]
    12/19: $2\div_start[0:0]
    13/19: $1\div_start[0:0]
    14/19: $1\div_jump_addr[31:0]
    15/19: $1\div_jump_flag[0:0]
    16/19: $1\div_hold_flag[0:0]
    17/19: $1\div_waddr[4:0]
    18/19: $1\div_wdata[31:0]
    19/19: $1\div_we[0:0]
Creating decoders for process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:172$126'.
     1/4: $2\mul_op2[31:0]
     2/4: $2\mul_op1[31:0]
     3/4: $1\mul_op2[31:0]
     4/4: $1\mul_op1[31:0]
Creating decoders for process `\div.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'.
     1/13: $0\invert_result[0:0]
     2/13: $0\minuend[31:0]
     3/13: $0\div_remain[31:0]
     4/13: $0\div_result[31:0]
     5/13: $0\count[31:0]
     6/13: $0\state[3:0]
     7/13: $0\op_r[2:0]
     8/13: $0\divisor_r[31:0]
     9/13: $0\dividend_r[31:0]
    10/13: $0\reg_waddr_o[4:0]
    11/13: $0\busy_o[0:0]
    12/13: $0\ready_o[0:0]
    13/13: $0\result_o[31:0]
Creating decoders for process `\ctrl.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v:48$46'.
     1/3: $3\hold_flag_o[2:0]
     2/3: $2\hold_flag_o[2:0]
     3/3: $1\hold_flag_o[2:0]
Creating decoders for process `\csr_reg.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:179$42'.
     1/2: $2\clint_data_o[31:0]
     2/2: $1\clint_data_o[31:0]
Creating decoders for process `\csr_reg.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:141$38'.
     1/2: $2\data_o[31:0]
     2/2: $1\data_o[31:0]
Creating decoders for process `\csr_reg.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$34'.
     1/6: $0\mscratch[31:0]
     2/6: $0\mstatus[31:0]
     3/6: $0\mie[31:0]
     4/6: $0\mepc[31:0]
     5/6: $0\mcause[31:0]
     6/6: $0\mtvec[31:0]
Creating decoders for process `\csr_reg.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:66$31'.
     1/1: $0\cycle[63:0]
Creating decoders for process `\clint.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:218$27'.
     1/2: $0\int_addr_o[31:0]
     2/2: $0\int_assert_o[0:0]
Creating decoders for process `\clint.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:177$25'.
     1/3: $0\data_o[31:0]
     2/3: $0\waddr_o[31:0]
     3/3: $0\we_o[0:0]
Creating decoders for process `\clint.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:111$15'.
     1/3: $0\cause[31:0]
     2/3: $0\inst_addr[31:0]
     3/3: $0\csr_state[4:0]
Creating decoders for process `\clint.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:89$5'.
     1/5: $5\int_state[3:0]
     2/5: $4\int_state[3:0]
     3/5: $3\int_state[3:0]
     4/5: $2\int_state[3:0]
     5/5: $1\int_state[3:0]

24.4.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1216'.
No latch inferred for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\n_fsm_state' from process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1159'.
No latch inferred for signal `\regs.\jtag_data_o' from process `\regs.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:91$262'.
No latch inferred for signal `\regs.\rdata2_o' from process `\regs.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:79$256'.
No latch inferred for signal `\regs.\rdata1_o' from process `\regs.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:67$250'.
No latch inferred for signal `\id.\reg_waddr_o' from process `\id.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'.
No latch inferred for signal `\id.\reg_we_o' from process `\id.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'.
No latch inferred for signal `\id.\csr_we_o' from process `\id.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'.
No latch inferred for signal `\id.\csr_waddr_o' from process `\id.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'.
No latch inferred for signal `\id.\reg1_raddr_o' from process `\id.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'.
No latch inferred for signal `\id.\reg2_raddr_o' from process `\id.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'.
No latch inferred for signal `\id.\csr_raddr_o' from process `\id.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'.
No latch inferred for signal `\id.\op1_o' from process `\id.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'.
No latch inferred for signal `\id.\op2_o' from process `\id.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'.
No latch inferred for signal `\id.\op1_jump_o' from process `\id.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'.
No latch inferred for signal `\id.\op2_jump_o' from process `\id.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'.
No latch inferred for signal `\id.\inst_o' from process `\id.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'.
No latch inferred for signal `\id.\inst_addr_o' from process `\id.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'.
No latch inferred for signal `\id.\reg1_rdata_o' from process `\id.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'.
No latch inferred for signal `\id.\reg2_rdata_o' from process `\id.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'.
No latch inferred for signal `\id.\csr_rdata_o' from process `\id.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'.
No latch inferred for signal `\ex.\mem_wdata_o' from process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'.
No latch inferred for signal `\ex.\mem_raddr_o' from process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'.
No latch inferred for signal `\ex.\mem_waddr_o' from process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'.
No latch inferred for signal `\ex.\csr_wdata_o' from process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'.
No latch inferred for signal `\ex.\reg_wdata' from process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'.
No latch inferred for signal `\ex.\reg_we' from process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'.
No latch inferred for signal `\ex.\reg_waddr' from process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'.
No latch inferred for signal `\ex.\hold_flag' from process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'.
No latch inferred for signal `\ex.\jump_flag' from process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'.
No latch inferred for signal `\ex.\jump_addr' from process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'.
No latch inferred for signal `\ex.\mem_we' from process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'.
No latch inferred for signal `\ex.\mem_req' from process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'.
No latch inferred for signal `\ex.\div_dividend_o' from process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'.
No latch inferred for signal `\ex.\div_divisor_o' from process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'.
No latch inferred for signal `\ex.\div_op_o' from process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'.
No latch inferred for signal `\ex.\div_reg_waddr_o' from process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'.
No latch inferred for signal `\ex.\div_wdata' from process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'.
No latch inferred for signal `\ex.\div_we' from process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'.
No latch inferred for signal `\ex.\div_waddr' from process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'.
No latch inferred for signal `\ex.\div_hold_flag' from process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'.
No latch inferred for signal `\ex.\div_jump_flag' from process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'.
No latch inferred for signal `\ex.\div_jump_addr' from process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'.
No latch inferred for signal `\ex.\div_start' from process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'.
No latch inferred for signal `\ex.\mul_op1' from process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:172$126'.
No latch inferred for signal `\ex.\mul_op2' from process `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:172$126'.
No latch inferred for signal `\ctrl.\hold_flag_o' from process `\ctrl.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v:48$46'.
No latch inferred for signal `\ctrl.\jump_flag_o' from process `\ctrl.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v:48$46'.
No latch inferred for signal `\ctrl.\jump_addr_o' from process `\ctrl.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v:48$46'.
No latch inferred for signal `\csr_reg.\clint_data_o' from process `\csr_reg.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:179$42'.
No latch inferred for signal `\csr_reg.\data_o' from process `\csr_reg.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:141$38'.
No latch inferred for signal `\clint.\int_state' from process `\clint.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:89$5'.

24.4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\TRELLIS_FF.\Q' using process `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$785'.
  created $dff cell `$procdff$6021' with positive edge clock.
Creating register for signal `\DPR16X4C.\i' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$721_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$722_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$723_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$724_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$725_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$726_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$727_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$728_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$729_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$730_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$731_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$732_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$733_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$734_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:281$735_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
  created direct connection (no actual register cell created).
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$736_ADDR' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$737'.
  created $dff cell `$procdff$6022' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$736_DATA' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$737'.
  created $dff cell `$procdff$6023' with positive edge clock.
Creating register for signal `\DPR16X4C.$memwr$\ram$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:287$736_EN' using process `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$737'.
  created $dff cell `$procdff$6024' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\i' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$703'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$661_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$703'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$662_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$703'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$663_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$703'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$664_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$703'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$665_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$703'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$666_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$703'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$667_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$703'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$668_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$703'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$669_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$703'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$670_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$703'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$671_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$703'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$672_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$703'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$673_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$703'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$674_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$703'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$675_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$703'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$676_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$703'.
  created direct connection (no actual register cell created).
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$677_ADDR' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$679'.
  created $dff cell `$procdff$6025' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$677_DATA' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$679'.
  created $dff cell `$procdff$6026' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$677_EN' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$679'.
  created $dff cell `$procdff$6027' with positive edge clock.
Creating register for signal `\TRELLIS_DPR16X4.\muxwre' using process `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$678'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\write_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1052'.
  created $dff cell `$procdff$6028' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_ADDR' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1052'.
  created $dff cell `$procdff$6029' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_DATA' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1052'.
  created $dff cell `$procdff$6030' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_EN' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1052'.
  created $dff cell `$procdff$6031' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_data' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1044'.
  created $dff cell `$procdff$6032' with positive edge clock.
Creating register for signal `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.\read_ptr' using process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1044'.
  created $dff cell `$procdff$6033' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1245'.
  created $dff cell `$procdff$6034' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\rxd_reg_0' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1245'.
  created $dff cell `$procdff$6035' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1243'.
  created $dff cell `$procdff$6036' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1235'.
  created $dff cell `$procdff$6037' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_sample' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1232'.
  created $dff cell `$procdff$6038' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1226'.
  created $dff cell `$procdff$6039' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\recieved_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1221'.
  created $dff cell `$procdff$6040' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1221'.
  created $dff cell `$procdff$6041' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.\uart_rx_data' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1207'.
  created $dff cell `$procdff$6042' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\txd_reg' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1194'.
  created $dff cell `$procdff$6043' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\fsm_state' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1192'.
  created $dff cell `$procdff$6044' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\cycle_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1184'.
  created $dff cell `$procdff$6045' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\bit_counter' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1170'.
  created $dff cell `$procdff$6046' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\i' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1164'.
  created $dff cell `$procdff$6047' with positive edge clock.
Creating register for signal `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.\data_to_send' using process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1164'.
  created $dff cell `$procdff$6048' with positive edge clock.
Creating register for signal `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000.\qout_r' using process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$945'.
  created $dff cell `$procdff$6049' with positive edge clock.
Creating register for signal `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101.\qout_r' using process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$942'.
  created $dff cell `$procdff$6050' with positive edge clock.
Creating register for signal `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001.\qout_r' using process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$939'.
  created $dff cell `$procdff$6051' with positive edge clock.
Creating register for signal `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000.\qout_r' using process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$936'.
  created $dff cell `$procdff$6052' with positive edge clock.
Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\pulse_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1146'.
  created $dff cell `$procdff$6053' with positive edge clock.
Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_o_auto' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1137'.
  created $dff cell `$procdff$6054' with positive edge clock.
Creating register for signal `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.\clk_counter' using process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1137'.
  created $dff cell `$procdff$6055' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6056' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6057' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\address' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6058' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6059' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6060' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6061' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\write_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6062' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_read' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6063' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6064' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_write_data' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6065' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_clk_enable' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6066' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\core_reset' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6067' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_cycles_to_pulse' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6068' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\reset_bus' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6069' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\bus_mode' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6070' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_size' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6071' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\end_position' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6072' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_mux_selector' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6073' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\memory_page_number' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6074' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\return_state' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6075' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_pages' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6076' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\num_of_positions' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6077' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\communication_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6078' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\read_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6079' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6080' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\timeout_counter' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6081' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\accumulator' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6082' with positive edge clock.
Creating register for signal `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.\temp_buffer' using process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
  created $dff cell `$procdff$6083' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_en' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1093'.
  created $dff cell `$procdff$6084' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1093'.
  created $dff cell `$procdff$6085' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\uart_tx_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1093'.
  created $dff cell `$procdff$6086' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_read_state' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1093'.
  created $dff cell `$procdff$6087' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1088'.
  created $dff cell `$procdff$6088' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1088'.
  created $dff cell `$procdff$6089' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1083'.
  created $dff cell `$procdff$6090' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1083'.
  created $dff cell `$procdff$6091' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\tx_fifo_write_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1083'.
  created $dff cell `$procdff$6092' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\write_data_buffer' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1083'.
  created $dff cell `$procdff$6093' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1083'.
  created $dff cell `$procdff$6094' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_write' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1083'.
  created $dff cell `$procdff$6095' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_response' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1078'.
  created $dff cell `$procdff$6096' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\read_data' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1078'.
  created $dff cell `$procdff$6097' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\rx_fifo_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1078'.
  created $dff cell `$procdff$6098' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\counter_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1078'.
  created $dff cell `$procdff$6099' with positive edge clock.
Creating register for signal `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.\state_read' using process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1078'.
  created $dff cell `$procdff$6100' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_write_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$859'.
  created $dff cell `$procdff$6101' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\sync_read_response' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$859'.
  created $dff cell `$procdff$6102' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.\read_sync' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$849'.
  created $dff cell `$procdff$6103' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_ADDR' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$849'.
  created $dff cell `$procdff$6104' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_DATA' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$849'.
  created $dff cell `$procdff$6105' with positive edge clock.
Creating register for signal `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN' using process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$849'.
  created $dff cell `$procdff$6106' with positive edge clock.
Creating register for signal `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.\finish_execution' using process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$838'.
  created $dff cell `$procdff$6107' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\reset_o' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$788'.
  created $dff cell `$procdff$6108' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\state' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$788'.
  created $dff cell `$procdff$6109' with positive edge clock.
Creating register for signal `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.\counter' using process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$788'.
  created $dff cell `$procdff$6110' with positive edge clock.
Creating register for signal `\regs.$memwr$\regs$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_ADDR' using process `\regs.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$221'.
  created $dff cell `$procdff$6111' with positive edge clock.
Creating register for signal `\regs.$memwr$\regs$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_DATA' using process `\regs.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$221'.
  created $dff cell `$procdff$6112' with positive edge clock.
Creating register for signal `\regs.$memwr$\regs$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:59$219_EN' using process `\regs.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$221'.
  created $dff cell `$procdff$6113' with positive edge clock.
Creating register for signal `\regs.$memwr$\regs$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_ADDR' using process `\regs.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$221'.
  created $dff cell `$procdff$6114' with positive edge clock.
Creating register for signal `\regs.$memwr$\regs$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_DATA' using process `\regs.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$221'.
  created $dff cell `$procdff$6115' with positive edge clock.
Creating register for signal `\regs.$memwr$\regs$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:61$220_EN' using process `\regs.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$221'.
  created $dff cell `$procdff$6116' with positive edge clock.
Creating register for signal `\pc_reg.\pc_o' using process `\pc_reg.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:35$212'.
  created $dff cell `$procdff$6117' with positive edge clock.
Creating register for signal `\div.\result_o' using process `\div.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'.
  created $dff cell `$procdff$6118' with positive edge clock.
Creating register for signal `\div.\ready_o' using process `\div.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'.
  created $dff cell `$procdff$6119' with positive edge clock.
Creating register for signal `\div.\busy_o' using process `\div.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'.
  created $dff cell `$procdff$6120' with positive edge clock.
Creating register for signal `\div.\reg_waddr_o' using process `\div.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'.
  created $dff cell `$procdff$6121' with positive edge clock.
Creating register for signal `\div.\dividend_r' using process `\div.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'.
  created $dff cell `$procdff$6122' with positive edge clock.
Creating register for signal `\div.\divisor_r' using process `\div.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'.
  created $dff cell `$procdff$6123' with positive edge clock.
Creating register for signal `\div.\op_r' using process `\div.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'.
  created $dff cell `$procdff$6124' with positive edge clock.
Creating register for signal `\div.\state' using process `\div.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'.
  created $dff cell `$procdff$6125' with positive edge clock.
Creating register for signal `\div.\count' using process `\div.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'.
  created $dff cell `$procdff$6126' with positive edge clock.
Creating register for signal `\div.\div_result' using process `\div.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'.
  created $dff cell `$procdff$6127' with positive edge clock.
Creating register for signal `\div.\div_remain' using process `\div.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'.
  created $dff cell `$procdff$6128' with positive edge clock.
Creating register for signal `\div.\minuend' using process `\div.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'.
  created $dff cell `$procdff$6129' with positive edge clock.
Creating register for signal `\div.\invert_result' using process `\div.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'.
  created $dff cell `$procdff$6130' with positive edge clock.
Creating register for signal `\csr_reg.\mtvec' using process `\csr_reg.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$34'.
  created $dff cell `$procdff$6131' with positive edge clock.
Creating register for signal `\csr_reg.\mcause' using process `\csr_reg.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$34'.
  created $dff cell `$procdff$6132' with positive edge clock.
Creating register for signal `\csr_reg.\mepc' using process `\csr_reg.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$34'.
  created $dff cell `$procdff$6133' with positive edge clock.
Creating register for signal `\csr_reg.\mie' using process `\csr_reg.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$34'.
  created $dff cell `$procdff$6134' with positive edge clock.
Creating register for signal `\csr_reg.\mstatus' using process `\csr_reg.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$34'.
  created $dff cell `$procdff$6135' with positive edge clock.
Creating register for signal `\csr_reg.\mscratch' using process `\csr_reg.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$34'.
  created $dff cell `$procdff$6136' with positive edge clock.
Creating register for signal `\csr_reg.\cycle' using process `\csr_reg.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:66$31'.
  created $dff cell `$procdff$6137' with positive edge clock.
Creating register for signal `\clint.\int_addr_o' using process `\clint.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:218$27'.
  created $dff cell `$procdff$6138' with positive edge clock.
Creating register for signal `\clint.\int_assert_o' using process `\clint.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:218$27'.
  created $dff cell `$procdff$6139' with positive edge clock.
Creating register for signal `\clint.\we_o' using process `\clint.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:177$25'.
  created $dff cell `$procdff$6140' with positive edge clock.
Creating register for signal `\clint.\waddr_o' using process `\clint.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:177$25'.
  created $dff cell `$procdff$6141' with positive edge clock.
Creating register for signal `\clint.\data_o' using process `\clint.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:177$25'.
  created $dff cell `$procdff$6142' with positive edge clock.
Creating register for signal `\clint.\csr_state' using process `\clint.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:111$15'.
  created $dff cell `$procdff$6143' with positive edge clock.
Creating register for signal `\clint.\inst_addr' using process `\clint.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:111$15'.
  created $dff cell `$procdff$6144' with positive edge clock.
Creating register for signal `\clint.\cause' using process `\clint.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:111$15'.
  created $dff cell `$procdff$6145' with positive edge clock.

24.4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

24.4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$786'.
Found and cleaned up 2 empty switches in `\TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$785'.
Removing empty process `TRELLIS_FF.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:350$785'.
Removing empty process `DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$760'.
Found and cleaned up 1 empty switch in `\DPR16X4C.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:285$737'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$703'.
Found and cleaned up 1 empty switch in `\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$679'.
Removing empty process `TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$678'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:0$1077'.
Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1052'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:36$1052'.
Found and cleaned up 2 empty switches in `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1044'.
Removing empty process `$paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.$proc$/eda/processor-ci-controller/src/fifo.v:25$1044'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:131$1247'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1245'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:196$1245'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1243'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:185$1243'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1235'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:170$1235'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1232'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:159$1232'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1226'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:147$1226'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1221'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:132$1221'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1216'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:115$1216'.
Found and cleaned up 2 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1207'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:96$1207'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:114$1200'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1194'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:173$1194'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1192'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:162$1192'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1184'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:147$1184'.
Found and cleaned up 5 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1170'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:130$1170'.
Found and cleaned up 3 empty switches in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1164'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:115$1164'.
Found and cleaned up 1 empty switch in `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1159'.
Removing empty process `$paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.$proc$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:98$1159'.
Found and cleaned up 1 empty switch in `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$945'.
Removing empty process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$945'.
Found and cleaned up 1 empty switch in `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$942'.
Removing empty process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$942'.
Found and cleaned up 1 empty switch in `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$939'.
Removing empty process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$939'.
Found and cleaned up 1 empty switch in `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$936'.
Removing empty process `$paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:33$936'.
Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:0$1152'.
Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1146'.
Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:57$1146'.
Found and cleaned up 4 empty switches in `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1137'.
Removing empty process `$paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.$proc$/eda/processor-ci-controller/src/clk_divider.v:36$1137'.
Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:0$1130'.
Found and cleaned up 15 empty switches in `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
Removing empty process `$paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.$proc$/eda/processor-ci-controller/src/interpreter.v:116$1101'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:0$1100'.
Found and cleaned up 3 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1093'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:203$1093'.
Found and cleaned up 2 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1088'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:187$1088'.
Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1083'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:132$1083'.
Found and cleaned up 5 empty switches in `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1078'.
Removing empty process `$paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.$proc$/eda/processor-ci-controller/modules/uart.v:74$1078'.
Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:45$859'.
Found and cleaned up 2 empty switches in `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$849'.
Removing empty process `$paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.$proc$/eda/processor-ci-controller/src/memory.v:36$849'.
Found and cleaned up 4 empty switches in `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$838'.
Removing empty process `$paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.$proc$/eda/processor-ci-controller/src/controller.v:113$838'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:0$795'.
Found and cleaned up 6 empty switches in `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$788'.
Removing empty process `$paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.$proc$/eda/processor-ci-controller/src/reset.v:25$788'.
Found and cleaned up 1 empty switch in `\regs.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:91$262'.
Removing empty process `regs.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:91$262'.
Found and cleaned up 2 empty switches in `\regs.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:79$256'.
Removing empty process `regs.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:79$256'.
Found and cleaned up 2 empty switches in `\regs.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:67$250'.
Removing empty process `regs.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:67$250'.
Found and cleaned up 3 empty switches in `\regs.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$221'.
Removing empty process `regs.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:55$221'.
Found and cleaned up 3 empty switches in `\pc_reg.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:35$212'.
Removing empty process `pc_reg.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:35$212'.
Found and cleaned up 10 empty switches in `\id.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'.
Removing empty process `id.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v:71$205'.
Found and cleaned up 21 empty switches in `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'.
Removing empty process `ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:248$142'.
Found and cleaned up 4 empty switches in `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'.
Removing empty process `ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:199$136'.
Found and cleaned up 2 empty switches in `\ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:172$126'.
Removing empty process `ex.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:172$126'.
Found and cleaned up 17 empty switches in `\div.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'.
Removing empty process `div.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/div.v:71$64'.
Found and cleaned up 3 empty switches in `\ctrl.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v:48$46'.
Removing empty process `ctrl.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v:48$46'.
Found and cleaned up 2 empty switches in `\csr_reg.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:179$42'.
Removing empty process `csr_reg.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:179$42'.
Found and cleaned up 2 empty switches in `\csr_reg.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:141$38'.
Removing empty process `csr_reg.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:141$38'.
Found and cleaned up 5 empty switches in `\csr_reg.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$34'.
Removing empty process `csr_reg.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:76$34'.
Found and cleaned up 1 empty switch in `\csr_reg.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:66$31'.
Removing empty process `csr_reg.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:66$31'.
Found and cleaned up 2 empty switches in `\clint.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:218$27'.
Removing empty process `clint.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:218$27'.
Found and cleaned up 2 empty switches in `\clint.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:177$25'.
Removing empty process `clint.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:177$25'.
Found and cleaned up 9 empty switches in `\clint.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:111$15'.
Removing empty process `clint.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:111$15'.
Found and cleaned up 5 empty switches in `\clint.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:89$5'.
Removing empty process `clint.$proc$/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:89$5'.
Cleaned up 193 empty switches.

24.4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
<suppressed ~5 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
<suppressed ~21 debug messages>
Optimizing module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
<suppressed ~19 debug messages>
Optimizing module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000.
Optimizing module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101.
Optimizing module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001.
Optimizing module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000.
Optimizing module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
<suppressed ~9 debug messages>
Optimizing module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.
<suppressed ~15 debug messages>
Optimizing module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
<suppressed ~24 debug messages>
Optimizing module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.
<suppressed ~3 debug messages>
Optimizing module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.
<suppressed ~26 debug messages>
Optimizing module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
<suppressed ~8 debug messages>
Optimizing module tinyriscv.
<suppressed ~1 debug messages>
Optimizing module regs.
<suppressed ~10 debug messages>
Optimizing module pc_reg.
<suppressed ~3 debug messages>
Optimizing module if_id.
Optimizing module id_ex.
Optimizing module id.
<suppressed ~36 debug messages>
Optimizing module ex.
<suppressed ~67 debug messages>
Optimizing module div.
<suppressed ~23 debug messages>
Optimizing module ctrl.
<suppressed ~5 debug messages>
Optimizing module csr_reg.
<suppressed ~14 debug messages>
Optimizing module clint.
<suppressed ~24 debug messages>
Optimizing module processorci_top.

24.5. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod$fb00a4f1e01b6404091dd91fbb53b046994f1d61\FIFO.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_rx.
Deleting now unused module $paramod$e9b10436db29f470fcafaa59abb2778c152f6035\uart_tx.
Deleting now unused module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000001000.
Deleting now unused module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000101.
Deleting now unused module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000000001.
Deleting now unused module $paramod\gen_pipe_dff\DW=s32'00000000000000000000000000100000.
Deleting now unused module $paramod$1849aaf56e55fcd2c7df624bf67aa48a75c68e43\ClkDivider.
Deleting now unused module $paramod$6225aedda1f3667cdd5e9335cb7334668cb837ba\Interpreter.
Deleting now unused module $paramod$6159f48792d90307d66afb7435ba8117dc5f9228\UART.
Deleting now unused module $paramod$860abc9b363840d7b46a2d1e00ea80d20a30d2ee\Memory.
Deleting now unused module $paramod$be568a6683087bc1c783fd234d0a3f16819ced17\Controller.
Deleting now unused module $paramod\ResetBootSystem\CYCLES=s32'00000000000000000000000000010100.
Deleting now unused module tinyriscv.
Deleting now unused module regs.
Deleting now unused module pc_reg.
Deleting now unused module if_id.
Deleting now unused module id_ex.
Deleting now unused module id.
Deleting now unused module ex.
Deleting now unused module div.
Deleting now unused module ctrl.
Deleting now unused module csr_reg.
Deleting now unused module clint.
<suppressed ~38 debug messages>

24.6. Executing TRIBUF pass.

24.7. Executing DEMINOUT pass (demote inout ports to input or output).

24.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~70 debug messages>

24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 1864 unused cells and 3072 unused wires.
<suppressed ~2143 debug messages>

24.10. Executing CHECK pass (checking for obvious problems).
Checking module processorci_top...
Warning: Wire processorci_top.\miso is used but has no driver.
Warning: Wire processorci_top.\intr is used but has no driver.
Warning: Wire processorci_top.\ResetBootSystem.start is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [31] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [30] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [29] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [28] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [27] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [26] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [25] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [24] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [23] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [22] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [21] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [20] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [19] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [18] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [17] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [16] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [15] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [14] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [13] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [12] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [11] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [10] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [9] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [8] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [7] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [6] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [5] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [4] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [3] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [2] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [1] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_data_memory_data [0] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_write_memory_data is used but has no driver.
Warning: Wire processorci_top.\Controller.core_read_memory_data is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [31] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [30] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [29] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [28] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [27] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [26] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [25] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [24] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [23] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [22] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [21] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [20] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [19] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [18] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [17] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [16] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [15] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [14] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [13] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [12] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [11] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [10] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [9] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [8] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [7] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [6] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [5] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [4] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [3] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [2] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [1] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory_data [0] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [31] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [30] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [29] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [28] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [27] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [26] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [25] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [24] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [23] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [22] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [21] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [20] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [19] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [18] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [17] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [16] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [15] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [14] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [13] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [12] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [11] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [10] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [9] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [8] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [7] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [6] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [5] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [4] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [3] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [2] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [1] is used but has no driver.
Warning: Wire processorci_top.\Controller.core_address_memory [0] is used but has no driver.
Found and reported 101 problems.

24.11. Executing OPT pass (performing simple optimizations).

24.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

24.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~387 debug messages>
Removed a total of 129 cells.

24.11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1276.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1282.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\RX_FIFO.$procmux$1288.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1276.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1282.
    dead port 1/2 on $mux $flatten\Controller.\Uart.\TX_FIFO.$procmux$1288.
Removed 6 multiplexer ports.
<suppressed ~102 debug messages>

24.11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1724: $auto$opt_reduce.cc:134:opt_pmux$6189
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1748: $auto$opt_reduce.cc:134:opt_pmux$6191
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1770: $auto$opt_reduce.cc:134:opt_pmux$6193
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1871: $auto$opt_reduce.cc:134:opt_pmux$6195
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1896: { $flatten\Controller.\Interpreter.$procmux$1664_CMP $auto$opt_reduce.cc:134:opt_pmux$6197 $flatten\Controller.\Interpreter.$procmux$1654_CMP }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1949: { $auto$opt_reduce.cc:134:opt_pmux$6201 $auto$opt_reduce.cc:134:opt_pmux$6199 }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Data_Memory.$procmux$2534:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0]
      New connections: $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [31:1] = { $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2018: $auto$opt_reduce.cc:134:opt_pmux$6203
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2043: { $flatten\Controller.\Interpreter.$procmux$1664_CMP $auto$opt_reduce.cc:134:opt_pmux$6205 $flatten\Controller.\Interpreter.$procmux$1654_CMP }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2071: { $flatten\Controller.\Interpreter.$procmux$1650_CMP $flatten\Controller.\Interpreter.$procmux$1643_CMP $flatten\Controller.\Interpreter.$procmux$1632_CMP $flatten\Controller.\Interpreter.$procmux$1626_CMP $auto$opt_reduce.cc:134:opt_pmux$6207 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2103: { $auto$opt_reduce.cc:134:opt_pmux$6211 $auto$opt_reduce.cc:134:opt_pmux$6209 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2185: { $flatten\Controller.\Interpreter.$procmux$1644_CMP $auto$opt_reduce.cc:134:opt_pmux$6213 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2282: { $auto$opt_reduce.cc:134:opt_pmux$6215 $flatten\Controller.\Interpreter.$procmux$1683_CMP }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2306: { $flatten\Controller.\Interpreter.$procmux$1751_CMP $flatten\Controller.\Interpreter.$procmux$1750_CMP $auto$opt_reduce.cc:134:opt_pmux$6217 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1624: { $flatten\Controller.\Interpreter.$procmux$1718_CMP $flatten\Controller.\Interpreter.$procmux$1714_CMP $flatten\Controller.\Interpreter.$procmux$1710_CMP $flatten\Controller.\Interpreter.$procmux$1684_CMP $flatten\Controller.\Interpreter.$procmux$1683_CMP $flatten\Controller.\Interpreter.$procmux$1679_CMP $flatten\Controller.\Interpreter.$procmux$1678_CMP $flatten\Controller.\Interpreter.$procmux$1674_CMP $flatten\Controller.\Interpreter.$procmux$1664_CMP $flatten\Controller.\Interpreter.$procmux$1660_CMP $auto$opt_reduce.cc:134:opt_pmux$6225 $flatten\Controller.\Interpreter.$procmux$1655_CMP $flatten\Controller.\Interpreter.$procmux$1654_CMP $auto$opt_reduce.cc:134:opt_pmux$6223 $flatten\Controller.\Interpreter.$procmux$1649_CMP $flatten\Controller.\Interpreter.$procmux$1648_CMP $flatten\Controller.\Interpreter.$procmux$1643_CMP $flatten\Controller.\Interpreter.$procmux$1639_CMP $flatten\Controller.\Interpreter.$procmux$1638_CMP $auto$opt_reduce.cc:134:opt_pmux$6221 $flatten\Controller.\Interpreter.$procmux$1632_CMP $flatten\Controller.\Interpreter.$procmux$1631_CMP $flatten\Controller.\Interpreter.$procmux$1630_CMP $auto$opt_reduce.cc:134:opt_pmux$6219 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2332: { $auto$opt_reduce.cc:134:opt_pmux$6227 $flatten\Controller.\Interpreter.$procmux$1750_CMP $flatten\Controller.\Interpreter.$procmux$1669_CMP $flatten\Controller.\Interpreter.$procmux$1664_CMP $flatten\Controller.\Interpreter.$procmux$1654_CMP }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Memory.$procmux$2534:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0]
      New connections: $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [31:1] = { $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] $flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_EN[31:0]$852 [0] }
    New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2402: $auto$opt_reduce.cc:134:opt_pmux$6229
    New ctrl vector for $pmux cell $flatten\Controller.\Uart.$procmux$2466: $auto$opt_reduce.cc:134:opt_pmux$6231
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1273:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1273_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1273_Y [0]
      New connections: $flatten\Controller.\Uart.\RX_FIFO.$procmux$1273_Y [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$procmux$1273_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1273_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1273_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1273_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1273_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1273_Y [0] $flatten\Controller.\Uart.\RX_FIFO.$procmux$1273_Y [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1273:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1273_Y
      New ports: A=1'0, B=1'1, Y=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1273_Y [0]
      New connections: $flatten\Controller.\Uart.\TX_FIFO.$procmux$1273_Y [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$procmux$1273_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1273_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1273_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1273_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1273_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1273_Y [0] $flatten\Controller.\Uart.\TX_FIFO.$procmux$1273_Y [0] }
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\RX_FIFO.$procmux$1291:
      Old ports: A=$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_EN[7:0]$1064, B=8'00000000, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_EN[7:0]$1055
      New ports: A=$flatten\Controller.\Uart.\RX_FIFO.$procmux$1273_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_EN[7:0]$1055 [0]
      New connections: $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_EN[7:0]$1055 [7:1] = { $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_EN[7:0]$1055 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_EN[7:0]$1055 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_EN[7:0]$1055 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_EN[7:0]$1055 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_EN[7:0]$1055 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_EN[7:0]$1055 [0] $flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_EN[7:0]$1055 [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\TX_FIFO.$procmux$1291:
      Old ports: A=$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_EN[7:0]$1064, B=8'00000000, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_EN[7:0]$1055
      New ports: A=$flatten\Controller.\Uart.\TX_FIFO.$procmux$1273_Y [0], B=1'0, Y=$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_EN[7:0]$1055 [0]
      New connections: $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_EN[7:0]$1055 [7:1] = { $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_EN[7:0]$1055 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_EN[7:0]$1055 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_EN[7:0]$1055 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_EN[7:0]$1055 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_EN[7:0]$1055 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_EN[7:0]$1055 [0] $flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_EN[7:0]$1055 [0] }
  Optimizing cells in module \processorci_top.
Performed a total of 23 changes.

24.11.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~18 debug messages>
Removed a total of 6 cells.

24.11.6. Executing OPT_DFF pass (perform DFF optimizations).

24.11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 365 unused wires.
<suppressed ~225 debug messages>

24.11.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

24.11.9. Rerunning OPT passes. (Maybe there is more to do..)

24.11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~102 debug messages>

24.11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$1896: { $auto$opt_reduce.cc:134:opt_pmux$6197 $auto$opt_reduce.cc:134:opt_pmux$6233 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2043: { $auto$opt_reduce.cc:134:opt_pmux$6197 $auto$opt_reduce.cc:134:opt_pmux$6235 }
    New ctrl vector for $pmux cell $flatten\Controller.\Interpreter.$procmux$2332: { $auto$opt_reduce.cc:134:opt_pmux$6227 $flatten\Controller.\Interpreter.$procmux$1750_CMP $flatten\Controller.\Interpreter.$procmux$1669_CMP $auto$opt_reduce.cc:134:opt_pmux$6237 }
  Optimizing cells in module \processorci_top.
Performed a total of 3 changes.

24.11.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

24.11.13. Executing OPT_DFF pass (perform DFF optimizations).

24.11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 2 unused wires.
<suppressed ~1 debug messages>

24.11.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

24.11.16. Rerunning OPT passes. (Maybe there is more to do..)

24.11.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~102 debug messages>

24.11.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

24.11.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

24.11.20. Executing OPT_DFF pass (perform DFF optimizations).

24.11.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

24.11.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

24.11.23. Finished OPT passes. (There is nothing left to do.)

24.12. Executing FSM pass (extract and optimize FSM).

24.12.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking processorci_top.Controller.Interpreter.return_state as FSM state register:
    Users of register don't seem to benefit from recoding.
Found FSM state register processorci_top.Controller.Uart.i_uart_rx.fsm_state.
Not marking processorci_top.Controller.Uart.i_uart_tx.fsm_state as FSM state register:
    Users of register don't seem to benefit from recoding.
Not marking processorci_top.Controller.Uart.state_read as FSM state register:
    Register has an initialization value.
Not marking processorci_top.Controller.Uart.state_write as FSM state register:
    Register has an initialization value.
Found FSM state register processorci_top.Controller.Uart.tx_fifo_read_state.
Not marking processorci_top.ResetBootSystem.state as FSM state register:
    Register has an initialization value.
    Circuit seems to be self-resetting.

24.12.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\Controller.Uart.i_uart_rx.fsm_state' from module `\processorci_top'.
  found $dff cell for state register: $flatten\Controller.\Uart.\i_uart_rx.$procdff$6036
  root of input selection tree: $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1211_Y
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1224_Y
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1237_Y
  found ctrl input: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1223_Y
  found state code: 3'000
  found ctrl input: \Controller.Uart.i_uart_rx.next_bit
  found state code: 3'011
  found ctrl input: \Controller.Uart.i_uart_rx.payload_done
  found state code: 3'010
  found state code: 3'001
  found ctrl input: \Controller.Uart.i_uart_rx.rxd_reg
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1237_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1228_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1224_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1223_Y
  found ctrl output: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1211_Y
  ctrl inputs: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.rxd_reg \Controller.Uart.i_uart_rx.next_bit \Controller.Uart.i_uart_rx.payload_done }
  ctrl outputs: { $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1211_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1223_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1224_Y $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1228_Y $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1237_Y $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] }
  transition:      3'000 4'00-- ->      3'001 8'01010001
  transition:      3'000 4'01-- ->      3'000 8'01010000
  transition:      3'000 4'1--- ->      3'000 8'01010000
  transition:      3'010 4'0--0 ->      3'010 8'00100010
  transition:      3'010 4'0--1 ->      3'011 8'00100011
  transition:      3'010 4'1--- ->      3'000 8'00100000
  transition:      3'001 4'0-0- ->      3'001 8'00011001
  transition:      3'001 4'0-1- ->      3'010 8'00011010
  transition:      3'001 4'1--- ->      3'000 8'00011000
  transition:      3'011 4'0-0- ->      3'011 8'10010011
  transition:      3'011 4'0-1- ->      3'000 8'10010000
  transition:      3'011 4'1--- ->      3'000 8'10010000
Extracting FSM `\Controller.Uart.tx_fifo_read_state' from module `\processorci_top'.
  found $dff cell for state register: $flatten\Controller.\Uart.$procdff$6087
  root of input selection tree: $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0]
  found reset state: 2'00 (guessed from mux tree)
  found ctrl input: \ResetBootSystem.reset_o
  found ctrl input: $flatten\Controller.\Uart.$procmux$2363_CMP
  found ctrl input: $flatten\Controller.\Uart.$procmux$2358_CMP
  found ctrl input: $flatten\Controller.\Uart.$procmux$2365_CMP
  found ctrl input: $flatten\Controller.\Uart.$procmux$2352_CMP
  found state code: 2'00
  found state code: 2'11
  found state code: 2'10
  found ctrl input: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1097_Y
  found state code: 2'01
  found ctrl output: $flatten\Controller.\Uart.$procmux$2352_CMP
  found ctrl output: $flatten\Controller.\Uart.$procmux$2358_CMP
  found ctrl output: $flatten\Controller.\Uart.$procmux$2363_CMP
  found ctrl output: $flatten\Controller.\Uart.$procmux$2365_CMP
  ctrl inputs: { \ResetBootSystem.reset_o $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1097_Y }
  ctrl outputs: { $flatten\Controller.\Uart.$procmux$2365_CMP $flatten\Controller.\Uart.$procmux$2363_CMP $flatten\Controller.\Uart.$procmux$2358_CMP $flatten\Controller.\Uart.$procmux$2352_CMP $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] }
  transition:       2'00 2'00 ->       2'00 6'000100
  transition:       2'00 2'01 ->       2'01 6'000101
  transition:       2'00 2'1- ->       2'00 6'000100
  transition:       2'10 2'0- ->       2'11 6'001011
  transition:       2'10 2'1- ->       2'00 6'001000
  transition:       2'01 2'0- ->       2'10 6'100010
  transition:       2'01 2'1- ->       2'00 6'100000
  transition:       2'11 2'0- ->       2'00 6'010000
  transition:       2'11 2'1- ->       2'00 6'010000

24.12.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$6245' from module `\processorci_top'.
  Merging pattern 2'0- and 2'1- from group (3 0 6'010000).
  Merging pattern 2'1- and 2'0- from group (3 0 6'010000).
Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$6238' from module `\processorci_top'.

24.12.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 15 unused cells and 15 unused wires.
<suppressed ~16 debug messages>

24.12.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$6238' from module `\processorci_top'.
  Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [0].
  Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [1].
  Removing unused output signal $flatten\Controller.\Uart.\i_uart_rx.$0\fsm_state[2:0] [2].
Optimizing FSM `$fsm$\Controller.Uart.tx_fifo_read_state$6245' from module `\processorci_top'.
  Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [0].
  Removing unused output signal $flatten\Controller.\Uart.$0\tx_fifo_read_state[1:0] [1].
  Removing unused output signal $flatten\Controller.\Uart.$procmux$2363_CMP.
  Removing unused output signal $flatten\Controller.\Uart.$procmux$2365_CMP.

24.12.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$6238' from module `\processorci_top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ---1
  010 -> --1-
  001 -> -1--
  011 -> 1---
Recoding FSM `$fsm$\Controller.Uart.tx_fifo_read_state$6245' from module `\processorci_top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  00 -> ---1
  10 -> --1-
  01 -> -1--
  11 -> 1---

24.12.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$6238' from module `processorci_top':
-------------------------------------

  Information on FSM $fsm$\Controller.Uart.i_uart_rx.fsm_state$6238 (\Controller.Uart.i_uart_rx.fsm_state):

  Number of input signals:    4
  Number of output signals:   5
  Number of state bits:       4

  Input signals:
    0: \Controller.Uart.i_uart_rx.payload_done
    1: \Controller.Uart.i_uart_rx.next_bit
    2: \Controller.Uart.i_uart_rx.rxd_reg
    3: \ResetBootSystem.reset_o

  Output signals:
    0: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:175$1237_Y
    1: $flatten\Controller.\Uart.\i_uart_rx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:150$1228_Y
    2: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:137$1224_Y
    3: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:135$1223_Y
    4: $flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:109$1211_Y

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 4'01--   ->     0 5'01010
      1:     0 4'1---   ->     0 5'01010
      2:     0 4'00--   ->     2 5'01010
      3:     1 4'1---   ->     0 5'00100
      4:     1 4'0--0   ->     1 5'00100
      5:     1 4'0--1   ->     3 5'00100
      6:     2 4'1---   ->     0 5'00011
      7:     2 4'0-1-   ->     1 5'00011
      8:     2 4'0-0-   ->     2 5'00011
      9:     3 4'0-1-   ->     0 5'10010
     10:     3 4'1---   ->     0 5'10010
     11:     3 4'0-0-   ->     3 5'10010

-------------------------------------

FSM `$fsm$\Controller.Uart.tx_fifo_read_state$6245' from module `processorci_top':
-------------------------------------

  Information on FSM $fsm$\Controller.Uart.tx_fifo_read_state$6245 (\Controller.Uart.tx_fifo_read_state):

  Number of input signals:    2
  Number of output signals:   2
  Number of state bits:       4

  Input signals:
    0: $flatten\Controller.\Uart.$logic_and$/eda/processor-ci-controller/modules/uart.v:215$1097_Y
    1: \ResetBootSystem.reset_o

  Output signals:
    0: $flatten\Controller.\Uart.$procmux$2352_CMP
    1: $flatten\Controller.\Uart.$procmux$2358_CMP

  State encoding:
    0:     4'---1  <RESET STATE>
    1:     4'--1-
    2:     4'-1--
    3:     4'1---

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 2'00   ->     0 2'01
      1:     0 2'1-   ->     0 2'01
      2:     0 2'01   ->     2 2'01
      3:     1 2'1-   ->     0 2'10
      4:     1 2'0-   ->     3 2'10
      5:     2 2'1-   ->     0 2'00
      6:     2 2'0-   ->     1 2'00
      7:     3 2'--   ->     0 2'00

-------------------------------------

24.12.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\Controller.Uart.i_uart_rx.fsm_state$6238' from module `\processorci_top'.
Mapping FSM `$fsm$\Controller.Uart.tx_fifo_read_state$6245' from module `\processorci_top'.

24.13. Executing OPT pass (performing simple optimizations).

24.13.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~9 debug messages>

24.13.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~9 debug messages>
Removed a total of 3 cells.

24.13.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~100 debug messages>

24.13.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

24.13.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

24.13.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $flatten\ResetBootSystem.$procdff$6110 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\counter[5:0], Q = \ResetBootSystem.counter).
Adding EN signal on $flatten\ResetBootSystem.$procdff$6108 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\reset_o[0:0], Q = \ResetBootSystem.reset_o).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$6048 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1562_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1556_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1547_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1538_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1529_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1520_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1502_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1511_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$6333 ($sdff) from module processorci_top (D = \Controller.Uart.uart_tx_data [7], Q = \Controller.Uart.i_uart_tx.data_to_send [7]).
Adding EN signal on $auto$ff.cc:266:slice$6333 ($sdff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_tx.$procmux$1556_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1547_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1538_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1529_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1520_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1502_Y $flatten\Controller.\Uart.\i_uart_tx.$procmux$1511_Y }, Q = \Controller.Uart.i_uart_tx.data_to_send [6:0]).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$6046 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1478_Y, Q = \Controller.Uart.i_uart_tx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$6338 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1478_Y, Q = \Controller.Uart.i_uart_tx.bit_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$6045 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1467_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$6344 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1191_Y, Q = \Controller.Uart.i_uart_tx.cycle_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$6044 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_tx.n_fsm_state, Q = \Controller.Uart.i_uart_tx.fsm_state, rval = 3'000).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_tx.$procdff$6043 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1456_Y, Q = \Controller.Uart.i_uart_tx.txd_reg, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$6349 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_tx.$procmux$1456_Y, Q = \Controller.Uart.i_uart_tx.txd_reg).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$6042 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1445_Y, Q = \Controller.Uart.i_uart_rx.uart_rx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$6355 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.recieved_data, Q = \Controller.Uart.i_uart_rx.uart_rx_data).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$6040 ($dff) from module processorci_top (D = { $flatten\Controller.\Uart.\i_uart_rx.$procmux$1422_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1413_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1404_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1395_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1386_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1377_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1359_Y $flatten\Controller.\Uart.\i_uart_rx.$procmux$1368_Y }, Q = \Controller.Uart.i_uart_rx.recieved_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$6357 ($sdff) from module processorci_top (D = { \Controller.Uart.i_uart_rx.bit_sample \Controller.Uart.i_uart_rx.recieved_data [7:1] }, Q = \Controller.Uart.i_uart_rx.recieved_data).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$6039 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1341_Y, Q = \Controller.Uart.i_uart_rx.bit_counter, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$6361 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1231_Y, Q = \Controller.Uart.i_uart_rx.bit_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$6038 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1336_Y, Q = \Controller.Uart.i_uart_rx.bit_sample, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$6365 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg, Q = \Controller.Uart.i_uart_rx.bit_sample).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$6037 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$procmux$1328_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter, rval = 9'000000000).
Adding EN signal on $auto$ff.cc:266:slice$6367 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1242_Y, Q = \Controller.Uart.i_uart_rx.cycle_counter).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$6035 ($dff) from module processorci_top (D = \rx, Q = \Controller.Uart.i_uart_rx.rxd_reg_0, rval = 1'1).
Adding SRST signal on $flatten\Controller.\Uart.\i_uart_rx.$procdff$6034 ($dff) from module processorci_top (D = \Controller.Uart.i_uart_rx.rxd_reg_0, Q = \Controller.Uart.i_uart_rx.rxd_reg, rval = 1'1).
Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$6033 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1305_Y, Q = \Controller.Uart.TX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$6373 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1051_Y [5:0], Q = \Controller.Uart.TX_FIFO.read_ptr).
Adding EN signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$6032 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1048_DATA, Q = \Controller.Uart.TX_FIFO.read_data).
Adding SRST signal on $flatten\Controller.\Uart.\TX_FIFO.$procdff$6028 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$procmux$1300_Y, Q = \Controller.Uart.TX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$6380 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1067_Y [5:0], Q = \Controller.Uart.TX_FIFO.write_ptr).
Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$6033 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1305_Y, Q = \Controller.Uart.RX_FIFO.read_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$6382 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1051_Y [5:0], Q = \Controller.Uart.RX_FIFO.read_ptr).
Adding EN signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$6032 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1048_DATA, Q = \Controller.Uart.RX_FIFO.read_data).
Adding SRST signal on $flatten\Controller.\Uart.\RX_FIFO.$procdff$6028 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$procmux$1300_Y, Q = \Controller.Uart.RX_FIFO.write_ptr, rval = 6'000000).
Adding EN signal on $auto$ff.cc:266:slice$6389 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1067_Y [5:0], Q = \Controller.Uart.RX_FIFO.write_ptr).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$6100 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2488_Y, Q = \Controller.Uart.state_read, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$6391 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2488_Y, Q = \Controller.Uart.state_read).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$6099 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2513_Y, Q = \Controller.Uart.counter_read, rval = 3'000).
Adding EN signal on $auto$ff.cc:266:slice$6395 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2513_Y, Q = \Controller.Uart.counter_read).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$6098 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2477_Y, Q = \Controller.Uart.rx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$6097 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2528_Y, Q = \Controller.Uart.read_data, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6412 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2526_Y, Q = \Controller.Uart.read_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$6096 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2466_Y, Q = \Controller.Uart.read_response, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$6095 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2410_Y, Q = \Controller.Uart.state_write, rval = 4'0000).
Adding EN signal on $auto$ff.cc:266:slice$6419 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2410_Y, Q = \Controller.Uart.state_write).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$6094 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2432_Y, Q = \Controller.Uart.counter_write, rval = 3'000).
Adding EN signal on $auto$ff.cc:266:slice$6423 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2432_Y, Q = \Controller.Uart.counter_write).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$6093 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2446_Y, Q = \Controller.Uart.write_data_buffer, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6433 ($sdff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2446_Y, Q = \Controller.Uart.write_data_buffer).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$6092 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2460_Y, Q = \Controller.Uart.tx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$6443 ($sdff) from module processorci_top (D = \Controller.Uart.write_data_buffer [31:24], Q = \Controller.Uart.tx_fifo_write_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$6091 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2392_Y, Q = \Controller.Uart.tx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$6090 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2402_Y, Q = \Controller.Uart.write_response, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$6089 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2383_Y, Q = \Controller.Uart.rx_fifo_write_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$6457 ($sdff) from module processorci_top (D = \Controller.Uart.i_uart_rx.uart_rx_data, Q = \Controller.Uart.rx_fifo_write_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$6088 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2378_Y, Q = \Controller.Uart.rx_fifo_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$6086 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2373_Y, Q = \Controller.Uart.uart_tx_data, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$6460 ($sdff) from module processorci_top (D = \Controller.Uart.TX_FIFO.read_data, Q = \Controller.Uart.uart_tx_data).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$6085 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2349_Y, Q = \Controller.Uart.tx_fifo_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Uart.$procdff$6084 ($dff) from module processorci_top (D = $flatten\Controller.\Uart.$procmux$2357_Y, Q = \Controller.Uart.uart_tx_en, rval = 1'0).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$6083 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1896_Y, Q = \Controller.Interpreter.temp_buffer).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6082 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1939_Y, Q = \Controller.Interpreter.accumulator, rval = 64'0000000000000000000000000000000000000000000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$6477 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1939_Y [63:8], Q = \Controller.Interpreter.accumulator [63:8]).
Adding EN signal on $auto$ff.cc:266:slice$6477 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1939_Y [7:0], Q = \Controller.Interpreter.accumulator [7:0]).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6081 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1949_Y, Q = \Controller.Interpreter.timeout_counter, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6492 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1949_Y, Q = \Controller.Interpreter.timeout_counter).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$6080 ($dff) from module processorci_top (D = { 8'00000000 \Controller.Interpreter.communication_buffer [31:8] }, Q = \Controller.Interpreter.timeout).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$6079 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1990_Y, Q = \Controller.Interpreter.read_buffer).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6078 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2018_Y, Q = \Controller.Interpreter.communication_buffer, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6508 ($sdff) from module processorci_top (D = \Controller.Uart.read_data, Q = \Controller.Interpreter.communication_buffer).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$6077 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2043_Y, Q = \Controller.Interpreter.num_of_positions).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6076 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2065_Y, Q = \Controller.Interpreter.num_of_pages, rval = 24'000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$6519 ($sdff) from module processorci_top (D = \Controller.Interpreter.communication_buffer [31:8], Q = \Controller.Interpreter.num_of_pages).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6075 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2071_Y, Q = \Controller.Interpreter.return_state, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$6521 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2071_Y, Q = \Controller.Interpreter.return_state).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$6074 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2095_Y, Q = \Controller.Interpreter.memory_page_number).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6073 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2103_Y, Q = \Controller.Interpreter.memory_mux_selector, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$6536 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2103_Y, Q = \Controller.Interpreter.memory_mux_selector).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6072 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2143_Y, Q = \Controller.Interpreter.end_position, rval = 0).
Adding EN signal on $auto$ff.cc:266:slice$6540 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2143_Y, Q = \Controller.Interpreter.end_position).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6070 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2185_Y, Q = \Controller.Interpreter.bus_mode, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$6544 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2185_Y, Q = \Controller.Interpreter.bus_mode).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6069 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1724_Y, Q = \Controller.Interpreter.reset_bus, rval = 1'1).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$6065 ($dff) from module processorci_top (D = \Controller.Interpreter.read_buffer, Q = \Controller.Interpreter.communication_write_data).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6064 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1848_Y, Q = \Controller.Interpreter.communication_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6063 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1871_Y, Q = \Controller.Interpreter.communication_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6061 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2282_Y, Q = \Controller.Interpreter.counter, rval = 8'00000000).
Adding EN signal on $auto$ff.cc:266:slice$6556 ($sdff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2282_Y, Q = \Controller.Interpreter.counter).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$6060 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2306_Y, Q = \Controller.Interpreter.write_data).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6059 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1624_Y, Q = \Controller.Interpreter.state, rval = 8'00000000).
Adding EN signal on $flatten\Controller.\Interpreter.$procdff$6058 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2332_Y, Q = \Controller.Interpreter.address).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6057 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1748_Y, Q = \Controller.Interpreter.memory_write, rval = 1'0).
Adding SRST signal on $flatten\Controller.\Interpreter.$procdff$6056 ($dff) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1770_Y, Q = \Controller.Interpreter.memory_read, rval = 1'0).
Adding SRST signal on $flatten\Controller.$procdff$6107 ($dff) from module processorci_top (D = $flatten\Controller.$procmux$2549_Y, Q = \Controller.finish_execution, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$6579 ($sdff) from module processorci_top (D = $flatten\Controller.$procmux$2549_Y, Q = \Controller.finish_execution).
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$6496 ($dffe) from module processorci_top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$6496 ($dffe) from module processorci_top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$6496 ($dffe) from module processorci_top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$6496 ($dffe) from module processorci_top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$6496 ($dffe) from module processorci_top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$6496 ($dffe) from module processorci_top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$6496 ($dffe) from module processorci_top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$6496 ($dffe) from module processorci_top.

24.13.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 121 unused cells and 126 unused wires.
<suppressed ~122 debug messages>

24.13.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~25 debug messages>

24.13.9. Rerunning OPT passes. (Maybe there is more to do..)

24.13.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~74 debug messages>

24.13.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New input vector for $reduce_or cell $auto$opt_dff.cc:254:combine_resets$6363: { \ResetBootSystem.reset_o \Controller.Uart.i_uart_rx.fsm_state [3:2] \Controller.Uart.i_uart_rx.fsm_state [0] }
  Optimizing cells in module \processorci_top.
Performed a total of 1 changes.

24.13.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~57 debug messages>
Removed a total of 19 cells.

24.13.13. Executing OPT_DFF pass (perform DFF optimizations).

24.13.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 1 unused cells and 20 unused wires.
<suppressed ~2 debug messages>

24.13.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

24.13.16. Rerunning OPT passes. (Maybe there is more to do..)

24.13.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~74 debug messages>

24.13.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

24.13.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

24.13.20. Executing OPT_DFF pass (perform DFF optimizations).

24.13.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

24.13.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

24.13.23. Finished OPT passes. (There is nothing left to do.)

24.14. Executing WREDUCE pass (reducing word size of cells).
Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Data_Memory.$auto$proc_memwr.cc:45:proc_memwr$6147 (Controller.Data_Memory.memory).
Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$846 (Controller.Data_Memory.memory).
Removed top 22 address bits (of 32) from memory init port processorci_top.$flatten\Controller.\Memory.$auto$proc_memwr.cc:45:proc_memwr$6147 (Controller.Memory.memory).
Removed top 22 address bits (of 32) from memory read port processorci_top.$flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$846 (Controller.Memory.memory).
Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$6146 (Controller.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1048 (Controller.Uart.RX_FIFO.memory).
Removed top 3 address bits (of 6) from memory init port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$auto$proc_memwr.cc:45:proc_memwr$6146 (Controller.Uart.TX_FIFO.memory).
Removed top 3 address bits (of 6) from memory read port processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$memrd$\memory$/eda/processor-ci-controller/src/fifo.v:30$1048 (Controller.Uart.TX_FIFO.memory).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6584 ($ne).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$6260 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$6285 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:219$1106 ($eq).
Removed top 6 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1110 ($add).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1113 ($add).
Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1122 ($lt).
Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1127 ($eq).
Removed top 8 bits (of 32) from port A of cell processorci_top.$flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1129 ($ge).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1625_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1626_CMP0 ($eq).
Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1628 ($mux).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1630_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1631_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1632_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1633_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1634_CMP0 ($eq).
Removed top 5 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1636 ($mux).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1638_CMP0 ($eq).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1639_CMP0 ($eq).
Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1641 ($mux).
Removed top 3 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1643_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1644_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1648_CMP0 ($eq).
Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1649_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1650_CMP0 ($eq).
Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1652 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1654_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1655_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1656_CMP0 ($eq).
Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1658 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1660_CMP0 ($eq).
Removed top 4 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1662 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1664_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1665_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1666_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1667_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1668_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1669_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1670_CMP0 ($eq).
Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1672 ($mux).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1674_CMP0 ($eq).
Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1676 ($mux).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1678_CMP0 ($eq).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1679_CMP0 ($eq).
Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1681 ($mux).
Removed top 4 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1683_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1684_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1687_CMP0 ($eq).
Removed top 1 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1686 ($pmux).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1688_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1689_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1690_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1691_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1692_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1693_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1694_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1695_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1696_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1697_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1698_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1699_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1700_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1701_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1702_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1703_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1704_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1705_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1706_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1707_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1708_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1709_CMP0 ($eq).
Removed top 6 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1710_CMP0 ($eq).
Removed top 6 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1712 ($mux).
Removed top 7 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1714_CMP0 ($eq).
Removed top 7 bits (of 8) from mux cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1716 ($mux).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1750_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1751_CMP0 ($eq).
Removed top 5 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1752_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1940_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1941_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1942_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$1985_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2111_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2144_CMP0 ($eq).
Removed top 1 bits (of 8) from port B of cell processorci_top.$flatten\Controller.\Interpreter.$procmux$2145_CMP0 ($eq).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:95$1080 ($lt).
Removed top 29 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.$lt$/eda/processor-ci-controller/modules/uart.v:159$1085 ($lt).
Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2397_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2403_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2404_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2416_CMP0 ($eq).
Removed top 1 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2418 ($mux).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2467_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2468_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2482_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.$procmux$2490_CMP0 ($eq).
Removed top 3 bits (of 4) from mux cell processorci_top.$flatten\Controller.\Uart.$procmux$2498 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1297 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$procmux$1285 ($mux).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1068 ($sub).
Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1068 ($sub).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1067 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1066 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$1065 ($eq).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1051 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1050 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$1049 ($eq).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1297 ($mux).
Removed top 3 bits (of 6) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$procmux$1285 ($mux).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1068 ($sub).
Removed top 25 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1068 ($sub).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1067 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1066 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:42$1065 ($eq).
Removed top 26 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1051 ($mux).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1050 ($add).
Removed top 3 bits (of 6) from port B of cell processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$eq$/eda/processor-ci-controller/src/fifo.v:31$1049 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$6271 ($eq).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1220 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:119$1219 ($mux).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1218 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1217 ($mux).
Removed top 2 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:110$1212 ($eq).
Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_rx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:108$1210 ($eq).
Removed top 2 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:152$1186 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:137$1178 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:135$1176 ($eq).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1173 ($ne).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ne$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:133$1172 ($ne).
Removed top 1 bits (of 3) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:120$1168 ($eq).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1163 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1162 ($mux).
Removed top 30 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1161 ($mux).
Removed top 31 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1160 ($mux).
Removed top 3 bits (of 4) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:94$1156 ($eq).
Removed top 1 bits (of 9) from port B of cell processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$eq$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:92$1154 ($eq).
Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Memory.$procmux$2540 ($mux).
Removed top 22 bits (of 32) from mux cell processorci_top.$flatten\Controller.\Data_Memory.$procmux$2540 ($mux).
Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:96$823 ($mux).
Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$807 ($mux).
Removed top 20 bits (of 32) from mux cell processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$806 ($mux).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$opt_dff.cc:195:make_patterns_logic$6323 ($ne).
Removed top 1 bits (of 2) from port B of cell processorci_top.$auto$fsm_map.cc:77:implement_pattern_cache$6310 ($eq).
Removed top 1 bits (of 2) from port B of cell processorci_top.$flatten\ResetBootSystem.$procmux$2566_CMP0 ($eq).
Removed top 1 bits (of 6) from port B of cell processorci_top.$flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$793 ($eq).
Removed top 31 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$792 ($add).
Removed top 26 bits (of 32) from port Y of cell processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$792 ($add).
Removed top 27 bits (of 32) from port B of cell processorci_top.$flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$791 ($lt).
Removed top 20 bits (of 32) from wire processorci_top.$flatten\Controller.$ternary$/eda/processor-ci-controller/src/controller.v:84$806_Y.
Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Data_Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_ADDR[31:0]$850.
Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1628_Y.
Removed top 5 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1636_Y.
Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1641_Y.
Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1652_Y.
Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1658_Y.
Removed top 4 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1662_Y.
Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1672_Y.
Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1676_Y.
Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1681_Y.
Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1686_Y.
Removed top 6 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1712_Y.
Removed top 7 bits (of 8) from wire processorci_top.$flatten\Controller.\Interpreter.$procmux$1716_Y.
Removed top 22 bits (of 32) from wire processorci_top.$flatten\Controller.\Memory.$0$memwr$\memory$/eda/processor-ci-controller/src/memory.v:41$844_ADDR[31:0]$850.
Removed top 1 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2418_Y.
Removed top 3 bits (of 4) from wire processorci_top.$flatten\Controller.\Uart.$procmux$2498_Y.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_ADDR[5:0]$1053.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_ADDR[5:0]$1062.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1050_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1066_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:31$1051_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\RX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1067_Y.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$0$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_ADDR[5:0]$1053.
Removed top 3 bits (of 6) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_ADDR[5:0]$1062.
Removed top 1 bits (of 8) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$2$memwr$\memory$/eda/processor-ci-controller/src/fifo.v:41$1043_DATA[7:0]$1063.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1050_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1066_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\TX_FIFO.$ternary$/eda/processor-ci-controller/src/fifo.v:42$1067_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:100$1160_Y.
Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:101$1161_Y.
Removed top 31 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:102$1162_Y.
Removed top 30 bits (of 32) from wire processorci_top.$flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1163_Y.
Removed top 26 bits (of 32) from wire processorci_top.$flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$792_Y.

24.15. Executing PEEPOPT pass (run peephole optimizers).

24.16. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 34 unused wires.
<suppressed ~1 debug messages>

24.17. Executing SHARE pass (SAT-based resource sharing).
Found 2 cells in module processorci_top that may be considered for resource sharing.
  Analyzing resource sharing options for $flatten\Controller.\Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$846 ($memrd):
    Found 1 activation_patterns using ctrl signal { \Controller.Memory.memory_read $flatten\Controller.\Interpreter.$procmux$1668_CMP \Controller.Interpreter.address [31] \Controller.Interpreter.memory_mux_selector }.
    No candidates found.
  Analyzing resource sharing options for $flatten\Controller.\Data_Memory.$memrd$\memory$/eda/processor-ci-controller/src/memory.v:21$846 ($memrd):
    Found 1 activation_patterns using ctrl signal { \Controller.Data_Memory.memory_read $flatten\Controller.\Interpreter.$procmux$1668_CMP \Controller.Interpreter.address [31] \Controller.Interpreter.memory_mux_selector }.
    No candidates found.

24.18. Executing TECHMAP pass (map to technology primitives).

24.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

24.18.2. Continuing TECHMAP pass.
Using template $paramod$141b0f41d8ab4b936f42c52ead39f1f9a7c93200\_90_lut_cmp_ for cells of type $lt.
No more expansions possible.
<suppressed ~119 debug messages>

24.19. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

24.20. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 6 unused wires.
<suppressed ~1 debug messages>

24.21. Executing TECHMAP pass (map to technology primitives).

24.21.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.

24.21.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/dsp_map.v' to AST representation.
Generating RTLIL representation for module `\$__MUL18X18'.
Successfully finished Verilog frontend.

24.21.3. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~5 debug messages>

24.22. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module processorci_top:
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1105 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1109 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1110 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1113 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1120 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1124 ($add).
  creating $macc model for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1112 ($sub).
  creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1087 ($add).
  creating $macc model for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1082 ($add).
  creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1050 ($add).
  creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1066 ($add).
  creating $macc model for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1068 ($sub).
  creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1050 ($add).
  creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1066 ($add).
  creating $macc model for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1068 ($sub).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1231 ($add).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1242 ($add).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1180 ($add).
  creating $macc model for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1191 ($add).
  creating $macc model for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$792 ($add).
  creating $alu model for $macc $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$792.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1191.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1180.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1242.
  creating $alu model for $macc $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1231.
  creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1068.
  creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1066.
  creating $alu model for $macc $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1050.
  creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1068.
  creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1066.
  creating $alu model for $macc $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1050.
  creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1082.
  creating $alu model for $macc $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1087.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1112.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1124.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1120.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1113.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1110.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1109.
  creating $alu model for $macc $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1105.
  creating $alu model for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1129 ($ge): new $alu
  creating $alu model for $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1122 ($lt): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1129.
  creating $alu model for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$791 ($lt): new $alu
  creating $alu model for $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1127 ($eq): merged with $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1129.
  creating $alu model for $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$793 ($eq): merged with $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$791.
  creating $alu cell for $flatten\ResetBootSystem.$lt$/eda/processor-ci-controller/src/reset.v:41$791, $flatten\ResetBootSystem.$eq$/eda/processor-ci-controller/src/reset.v:43$793: $auto$alumacc.cc:485:replace_alu$6628
  creating $alu cell for $flatten\Controller.\Interpreter.$ge$/eda/processor-ci-controller/src/interpreter.v:511$1129, $flatten\Controller.\Interpreter.$lt$/eda/processor-ci-controller/src/interpreter.v:455$1122, $flatten\Controller.\Interpreter.$eq$/eda/processor-ci-controller/src/interpreter.v:494$1127: $auto$alumacc.cc:485:replace_alu$6639
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:218$1105: $auto$alumacc.cc:485:replace_alu$6652
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:280$1109: $auto$alumacc.cc:485:replace_alu$6655
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:302$1110: $auto$alumacc.cc:485:replace_alu$6658
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:364$1113: $auto$alumacc.cc:485:replace_alu$6661
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:454$1120: $auto$alumacc.cc:485:replace_alu$6664
  creating $alu cell for $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1124: $auto$alumacc.cc:485:replace_alu$6667
  creating $alu cell for $flatten\Controller.\Interpreter.$sub$/eda/processor-ci-controller/src/interpreter.v:361$1112: $auto$alumacc.cc:485:replace_alu$6670
  creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:163$1087: $auto$alumacc.cc:485:replace_alu$6673
  creating $alu cell for $flatten\Controller.\Uart.$add$/eda/processor-ci-controller/modules/uart.v:98$1082: $auto$alumacc.cc:485:replace_alu$6676
  creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1050: $auto$alumacc.cc:485:replace_alu$6679
  creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1066: $auto$alumacc.cc:485:replace_alu$6682
  creating $alu cell for $flatten\Controller.\Uart.\RX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1068: $auto$alumacc.cc:485:replace_alu$6685
  creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:31$1050: $auto$alumacc.cc:485:replace_alu$6688
  creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$add$/eda/processor-ci-controller/src/fifo.v:42$1066: $auto$alumacc.cc:485:replace_alu$6691
  creating $alu cell for $flatten\Controller.\Uart.\TX_FIFO.$sub$/eda/processor-ci-controller/src/fifo.v:47$1068: $auto$alumacc.cc:485:replace_alu$6694
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:153$1231: $auto$alumacc.cc:485:replace_alu$6697
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_rx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:178$1242: $auto$alumacc.cc:485:replace_alu$6700
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:138$1180: $auto$alumacc.cc:485:replace_alu$6703
  creating $alu cell for $flatten\Controller.\Uart.\i_uart_tx.$add$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:155$1191: $auto$alumacc.cc:485:replace_alu$6706
  creating $alu cell for $flatten\ResetBootSystem.$add$/eda/processor-ci-controller/src/reset.v:42$792: $auto$alumacc.cc:485:replace_alu$6709
  created 22 $alu and 0 $macc cells.

24.23. Executing OPT pass (performing simple optimizations).

24.23.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~2 debug messages>

24.23.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

24.23.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~74 debug messages>

24.23.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

24.23.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

24.23.6. Executing OPT_DFF pass (perform DFF optimizations).

24.23.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 7 unused wires.
<suppressed ~1 debug messages>

24.23.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

24.23.9. Rerunning OPT passes. (Maybe there is more to do..)

24.23.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~74 debug messages>

24.23.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

24.23.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

24.23.13. Executing OPT_DFF pass (perform DFF optimizations).

24.23.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

24.23.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

24.23.16. Finished OPT passes. (There is nothing left to do.)

24.24. Executing MEMORY pass.

24.24.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

24.24.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

24.24.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing processorci_top.Controller.Data_Memory.memory write port 0.
  Analyzing processorci_top.Controller.Memory.memory write port 0.
  Analyzing processorci_top.Controller.Uart.RX_FIFO.memory write port 0.
  Analyzing processorci_top.Controller.Uart.TX_FIFO.memory write port 0.

24.24.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

24.24.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no output FF found.
Checking read port `\Controller.Memory.memory'[0] in module `\processorci_top': no output FF found.
Checking read port `\Controller.Uart.RX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\Controller.Uart.TX_FIFO.memory'[0] in module `\processorci_top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port address `\Controller.Data_Memory.memory'[0] in module `\processorci_top': no address FF found.
Checking read port address `\Controller.Memory.memory'[0] in module `\processorci_top': no address FF found.

24.24.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 2 unused cells and 18 unused wires.
<suppressed ~3 debug messages>

24.24.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

24.24.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

24.24.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

24.24.10. Executing MEMORY_COLLECT pass (generating $mem cells).

24.25. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

24.26. Executing MEMORY_LIBMAP pass (mapping memories to cells).
mapping memory processorci_top.Controller.Data_Memory.memory via $__TRELLIS_DPR16X4_
mapping memory processorci_top.Controller.Memory.memory via $__TRELLIS_DPR16X4_
mapping memory processorci_top.Controller.Uart.RX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of processorci_top.Controller.Uart.RX_FIFO.memory: $\Controller.Uart.RX_FIFO.memory$rdreg[0]
mapping memory processorci_top.Controller.Uart.TX_FIFO.memory via $__TRELLIS_DPR16X4_
Extracted data FF from read port 0 of processorci_top.Controller.Uart.TX_FIFO.memory: $\Controller.Uart.TX_FIFO.memory$rdreg[0]
<suppressed ~1098 debug messages>

24.27. Executing TECHMAP pass (map to technology primitives).

24.27.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/lutrams_map.v' to AST representation.
Generating RTLIL representation for module `\$__TRELLIS_DPR16X4_'.
Successfully finished Verilog frontend.

24.27.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ECP5_DP16KD_'.
Generating RTLIL representation for module `\$__ECP5_PDPW16KD_'.
Successfully finished Verilog frontend.

24.27.3. Continuing TECHMAP pass.
Using template $paramod$04778961cc1285a5efea28f98f28381eb2862208\$__TRELLIS_DPR16X4_ for cells of type $__TRELLIS_DPR16X4_.
No more expansions possible.
<suppressed ~1046 debug messages>

24.28. Executing OPT pass (performing simple optimizations).

24.28.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~195 debug messages>

24.28.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

24.28.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $flatten\ResetBootSystem.$procdff$6109 ($dff) from module processorci_top (D = $flatten\ResetBootSystem.$0\state[1:0], Q = \ResetBootSystem.state).
Adding SRST signal on $auto$ff.cc:266:slice$6529 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$add$/eda/processor-ci-controller/src/interpreter.v:464$1124_Y, Q = \Controller.Interpreter.memory_page_number, rval = 24'000000000000000000000000).
Adding EN signal on $auto$ff.cc:266:slice$6468 ($dffe) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1896_Y [1:0], Q = \Controller.Interpreter.temp_buffer [1:0]).
Adding SRST signal on $auto$ff.cc:266:slice$6317 ($dffe) from module processorci_top (D = $flatten\ResetBootSystem.$procmux$2563_Y, Q = \ResetBootSystem.counter, rval = 6'000000).

24.28.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 2 unused cells and 7266 unused wires.
<suppressed ~3 debug messages>

24.28.5. Rerunning OPT passes. (Removed registers in this run.)

24.28.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~9 debug messages>

24.28.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

24.28.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$9068 ($sdffce) from module processorci_top (D = $auto$wreduce.cc:461:run$6621 [5:0], Q = \ResetBootSystem.counter, rval = 6'000000).

24.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 1 unused cells and 7 unused wires.
<suppressed ~2 debug messages>

24.28.10. Rerunning OPT passes. (Removed registers in this run.)

24.28.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

24.28.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

24.28.13. Executing OPT_DFF pass (perform DFF optimizations).

24.28.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

24.28.15. Finished fast OPT passes.

24.29. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

24.30. Executing OPT pass (performing simple optimizations).

24.30.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

24.30.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

24.30.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~44 debug messages>

24.30.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$9066: { $auto$fsm_map.cc:74:implement_pattern_cache$6305 $auto$opt_dff.cc:194:make_patterns_logic$6469 $auto$opt_dff.cc:194:make_patterns_logic$6471 $auto$opt_dff.cc:194:make_patterns_logic$9063 }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1636:
      Old ports: A=3'011, B=3'100, Y=$auto$wreduce.cc:461:run$6591 [2:0]
      New ports: A=2'01, B=2'10, Y={ $auto$wreduce.cc:461:run$6591 [2] $auto$wreduce.cc:461:run$6591 [0] }
      New connections: $auto$wreduce.cc:461:run$6591 [1] = $auto$wreduce.cc:461:run$6591 [0]
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1641:
      Old ports: A=7'1010010, B=7'0010101, Y=$auto$wreduce.cc:461:run$6592 [6:0]
      New ports: A=2'10, B=2'01, Y=$auto$wreduce.cc:461:run$6592 [1:0]
      New connections: $auto$wreduce.cc:461:run$6592 [6:2] = { $auto$wreduce.cc:461:run$6592 [1] 3'010 $auto$wreduce.cc:461:run$6592 [0] }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1652:
      Old ports: A=4'1100, B=4'0000, Y=$auto$wreduce.cc:461:run$6593 [3:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$6593 [2]
      New connections: { $auto$wreduce.cc:461:run$6593 [3] $auto$wreduce.cc:461:run$6593 [1:0] } = { $auto$wreduce.cc:461:run$6593 [2] 2'00 }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1662:
      Old ports: A=4'1001, B=4'0000, Y=$auto$wreduce.cc:461:run$6595 [3:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$6595 [0]
      New connections: $auto$wreduce.cc:461:run$6595 [3:1] = { $auto$wreduce.cc:461:run$6595 [0] 2'00 }
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1676:
      Old ports: A=7'0000110, B=7'1010111, Y=$auto$wreduce.cc:461:run$6597 [6:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$6597 [0]
      New connections: $auto$wreduce.cc:461:run$6597 [6:1] = { $auto$wreduce.cc:461:run$6597 [0] 1'0 $auto$wreduce.cc:461:run$6597 [0] 3'011 }
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$2071:
      Old ports: A=8'00001011, B=302978816, Y=$flatten\Controller.\Interpreter.$procmux$2071_Y
      New ports: A=5'01011, B=20'10010011111011100000, Y=$flatten\Controller.\Interpreter.$procmux$2071_Y [4:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$2071_Y [7:5] = 3'000
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2410:
      Old ports: A=4'0000, B={ 1'0 $auto$wreduce.cc:461:run$6603 [2:0] 12'000100100011 }, Y=$flatten\Controller.\Uart.$procmux$2410_Y
      New ports: A=3'000, B={ $auto$wreduce.cc:461:run$6603 [2:0] 9'001010011 }, Y=$flatten\Controller.\Uart.$procmux$2410_Y [2:0]
      New connections: $flatten\Controller.\Uart.$procmux$2410_Y [3] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2418:
      Old ports: A=3'000, B=3'100, Y=$auto$wreduce.cc:461:run$6603 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$6603 [2]
      New connections: $auto$wreduce.cc:461:run$6603 [1:0] = 2'00
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.$procmux$2494:
      Old ports: A=4'0010, B=4'0100, Y=$flatten\Controller.\Uart.$procmux$2494_Y
      New ports: A=2'01, B=2'10, Y=$flatten\Controller.\Uart.$procmux$2494_Y [2:1]
      New connections: { $flatten\Controller.\Uart.$procmux$2494_Y [3] $flatten\Controller.\Uart.$procmux$2494_Y [0] } = 2'00
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_rx.$procmux$1440:
      Old ports: A=3'000, B={ 2'00 $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1217_Y [0] 1'0 $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1218_Y [1:0] 2'01 \Controller.Uart.i_uart_rx.payload_done 1'0 $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1220_Y [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state
      New ports: A=2'00, B={ 1'0 $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:117$1217_Y [0] $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:118$1218_Y [1:0] 1'1 \Controller.Uart.i_uart_rx.payload_done $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1220_Y [1:0] }, Y=\Controller.Uart.i_uart_rx.n_fsm_state [1:0]
      New connections: \Controller.Uart.i_uart_rx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1220:
      Old ports: A=2'11, B=2'00, Y=$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1220_Y [1:0]
      New ports: A=1'1, B=1'0, Y=$flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1220_Y [0]
      New connections: $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1220_Y [1] = $flatten\Controller.\Uart.\i_uart_rx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:120$1220_Y [0]
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.\i_uart_tx.$procmux$1577:
      Old ports: A=3'000, B={ 2'00 \Controller.Uart.uart_tx_en 1'0 $auto$wreduce.cc:461:run$6618 [1:0] 2'01 \Controller.Uart.i_uart_tx.payload_done 1'0 $auto$wreduce.cc:461:run$6620 [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state
      New ports: A=2'00, B={ 1'0 \Controller.Uart.uart_tx_en $auto$wreduce.cc:461:run$6618 [1:0] 1'1 \Controller.Uart.i_uart_tx.payload_done $auto$wreduce.cc:461:run$6620 [1:0] }, Y=\Controller.Uart.i_uart_tx.n_fsm_state [1:0]
      New connections: \Controller.Uart.i_uart_tx.n_fsm_state [2] = 1'0
    Consolidated identical input bits for $mux cell $flatten\Controller.\Uart.\i_uart_tx.$ternary$/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:103$1163:
      Old ports: A=2'11, B=2'00, Y=$auto$wreduce.cc:461:run$6620 [1:0]
      New ports: A=1'1, B=1'0, Y=$auto$wreduce.cc:461:run$6620 [0]
      New connections: $auto$wreduce.cc:461:run$6620 [1] = $auto$wreduce.cc:461:run$6620 [0]
    New ctrl vector for $pmux cell $flatten\ResetBootSystem.$procmux$2574: { $flatten\ResetBootSystem.$procmux$2567_CMP $flatten\ResetBootSystem.$procmux$2566_CMP }
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2577:
      Old ports: A=2'00, B=2'10, Y=$flatten\ResetBootSystem.$procmux$2577_Y
      New ports: A=1'0, B=1'1, Y=$flatten\ResetBootSystem.$procmux$2577_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2577_Y [0] = 1'0
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Uart.$procmux$2488:
      Old ports: A=4'0000, B={ 3'000 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2494_Y 8'00010011 }, Y=$flatten\Controller.\Uart.$procmux$2488_Y
      New ports: A=3'000, B={ 2'00 \Controller.Interpreter.communication_read $flatten\Controller.\Uart.$procmux$2494_Y [2:1] 7'0001011 }, Y=$flatten\Controller.\Uart.$procmux$2488_Y [2:0]
      New connections: $flatten\Controller.\Uart.$procmux$2488_Y [3] = 1'0
    Consolidated identical input bits for $mux cell $flatten\ResetBootSystem.$procmux$2583:
      Old ports: A=2'00, B=$flatten\ResetBootSystem.$procmux$2577_Y, Y=$flatten\ResetBootSystem.$procmux$2583_Y
      New ports: A=1'0, B=$flatten\ResetBootSystem.$procmux$2577_Y [1], Y=$flatten\ResetBootSystem.$procmux$2583_Y [1]
      New connections: $flatten\ResetBootSystem.$procmux$2583_Y [0] = 1'0
  Optimizing cells in module \processorci_top.
Performed a total of 18 changes.

24.30.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

24.30.6. Executing OPT_DFF pass (perform DFF optimizations).

24.30.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

24.30.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~1 debug messages>

24.30.9. Rerunning OPT passes. (Maybe there is more to do..)

24.30.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~44 debug messages>

24.30.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

24.30.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

24.30.13. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$6348 ($sdff) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$6392 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$6420 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$6522 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$6522 ($sdffe) from module processorci_top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$6522 ($sdffe) from module processorci_top.

24.30.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

24.30.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~4 debug messages>

24.30.16. Rerunning OPT passes. (Maybe there is more to do..)

24.30.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~44 debug messages>

24.30.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $mux cell $flatten\Controller.\Interpreter.$procmux$1646:
      Old ports: A=8'00000100, B={ 3'000 \Controller.Interpreter.return_state [4:0] }, Y=$flatten\Controller.\Interpreter.$procmux$1646_Y
      New ports: A=5'00100, B=\Controller.Interpreter.return_state [4:0], Y=$flatten\Controller.\Interpreter.$procmux$1646_Y [4:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$1646_Y [7:5] = 3'000
  Optimizing cells in module \processorci_top.
    Consolidated identical input bits for $pmux cell $flatten\Controller.\Interpreter.$procmux$1624:
      Old ports: A=8'00000000, B={ 7'0000000 $auto$wreduce.cc:461:run$6601 [0] 6'000000 $auto$wreduce.cc:461:run$6594 [1:0] 1'0 $auto$wreduce.cc:461:run$6599 [6:0] 14'00001101000011 $auto$wreduce.cc:461:run$6598 [1:0] 3'000 \Controller.Interpreter.return_state [4:0] 1'0 $auto$wreduce.cc:461:run$6597 [6] 1'0 $auto$wreduce.cc:461:run$6597 [6] 3'011 $auto$wreduce.cc:461:run$6597 [6] 7'0000011 \Controller.Uart.read_response 4'0000 $auto$wreduce.cc:461:run$6593 [3] 2'00 $auto$wreduce.cc:461:run$6593 [3] 6'000010 $auto$wreduce.cc:461:run$6594 [1:0] 20'00001000000010110000 $auto$wreduce.cc:461:run$6593 [3] $auto$wreduce.cc:461:run$6593 [3] 18'000000010100000100 $flatten\Controller.\Interpreter.$procmux$1646_Y 1'0 $auto$wreduce.cc:461:run$6592 [6] 3'010 $auto$wreduce.cc:461:run$6592 [2] $auto$wreduce.cc:461:run$6592 [6] $auto$wreduce.cc:461:run$6592 [2] 13'0001001100010 $auto$wreduce.cc:461:run$6591 [2:1] $auto$wreduce.cc:461:run$6591 [1] 31'0001011001010010000100000001000 $auto$wreduce.cc:461:run$6590 [0] 8'00000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1624_Y
      New ports: A=7'0000000, B={ 6'000000 $auto$wreduce.cc:461:run$6601 [0] 5'00000 $auto$wreduce.cc:461:run$6594 [1:0] $auto$wreduce.cc:461:run$6599 [6:0] 12'000110100011 $auto$wreduce.cc:461:run$6598 [1:0] 2'00 \Controller.Interpreter.return_state [4:0] $auto$wreduce.cc:461:run$6597 [6] 1'0 $auto$wreduce.cc:461:run$6597 [6] 3'011 $auto$wreduce.cc:461:run$6597 [6] 6'000011 \Controller.Uart.read_response 3'000 $auto$wreduce.cc:461:run$6593 [3] 2'00 $auto$wreduce.cc:461:run$6593 [3] 5'00010 $auto$wreduce.cc:461:run$6594 [1:0] 17'00010000001011000 $auto$wreduce.cc:461:run$6593 [3] $auto$wreduce.cc:461:run$6593 [3] 18'000000101000010000 $flatten\Controller.\Interpreter.$procmux$1646_Y [4:0] $auto$wreduce.cc:461:run$6592 [6] 3'010 $auto$wreduce.cc:461:run$6592 [2] $auto$wreduce.cc:461:run$6592 [6] $auto$wreduce.cc:461:run$6592 [2] 11'00100110010 $auto$wreduce.cc:461:run$6591 [2:1] $auto$wreduce.cc:461:run$6591 [1] 27'001011010100100010000001000 $auto$wreduce.cc:461:run$6590 [0] 7'0000011 }, Y=$flatten\Controller.\Interpreter.$procmux$1624_Y [6:0]
      New connections: $flatten\Controller.\Interpreter.$procmux$1624_Y [7] = 1'0
  Optimizing cells in module \processorci_top.
Performed a total of 2 changes.

24.30.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

24.30.20. Executing OPT_DFF pass (perform DFF optimizations).

24.30.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

24.30.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

24.30.23. Rerunning OPT passes. (Maybe there is more to do..)

24.30.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~44 debug messages>

24.30.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

24.30.26. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

24.30.27. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$6567 ($sdff) from module processorci_top.

24.30.28. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

24.30.29. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~1 debug messages>

24.30.30. Rerunning OPT passes. (Maybe there is more to do..)

24.30.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~44 debug messages>

24.30.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

24.30.33. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

24.30.34. Executing OPT_DFF pass (perform DFF optimizations).

24.30.35. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

24.30.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

24.30.37. Finished OPT passes. (There is nothing left to do.)

24.31. Executing TECHMAP pass (map to technology primitives).

24.31.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

24.31.2. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ecp5_alu'.
Successfully finished Verilog frontend.

24.31.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $reduce_and.
Using template $paramod$e04283ca12514baf3d204c6994bec8f178dd89f8\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $ne.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $lut.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $sdffe.
Using template $paramod$039520c137afc9cd69dd56c3fb11a4e1fbe5f664\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $dffe.
Using template $paramod$bdc78fe5225b43c64ccdf13e5eb67d9dcf228e8a\_80_ecp5_alu for cells of type $alu.
Using template $paramod$ff467a932a72bec5a93c27dba04bf3daba067451\_80_ecp5_alu for cells of type $alu.
Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_90_alu for cells of type $alu.
Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ecp5_alu for cells of type $alu.
Using template $paramod$79aa992f2eb7f354d4aaf651790713cf239111fa\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_or.
Using template $paramod$c9511eeb847f2aa95252b1013477609463f67ee0\_80_ecp5_alu for cells of type $alu.
Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ecp5_alu for cells of type $alu.
Using template $paramod$a7b312e4ba8fdc79d4c5e0789e4e6c41ea3896fb\_90_pmux for cells of type $pmux.
Using template $paramod$7a385d5b7a2e603dbc5beef838648775b433f248\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $mux.
Using template $paramod$54a4503cc57b9df40b70c1899504d6aac2650719\_90_pmux for cells of type $pmux.
Using template $paramod$59b03ae2620a41577de8da5f5c97b2919e82362b\_90_pmux for cells of type $pmux.
Using template $paramod$24fb226dd75c9d3f6955ec2ad61d794776778cf6\_90_pmux for cells of type $pmux.
Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux.
Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $sdff.
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod$d31bf4d7d72e59528d18fbd4f322e9d608532043\_90_pmux for cells of type $pmux.
Using template $paramod$32a7b7b86c07519b7537abc18e96f0331f97914d\_90_alu for cells of type $alu.
Using template $paramod$ac45afa5bcd8e16ca475cce13f9d19bb109f1516\_80_ecp5_alu for cells of type $alu.
Using template $paramod$068ad458e7761d78e5eed8238508872e7b0aef95\_90_pmux for cells of type $pmux.
Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $bmux.
Using template $paramod$eaeb96106163dbf82031649d189817109fe07c69\_90_demux for cells of type $demux.
Using extmapper simplemap for cells of type $sdffce.
Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux.
Using template $paramod$610911f8769324f781128d641f7fe2120143c328\_80_ecp5_alu for cells of type $alu.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000011 for cells of type $lcu.
Using template $paramod$46c272b461898a6a76adeeeedb0917ce1a81b478\_90_demux for cells of type $demux.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000100 for cells of type $lcu.
Using template $paramod$5d1d2614b24accd0f9d06c4779fd9ef771faf494\_90_demux for cells of type $demux.
Using template $paramod$63301a5e78ceb1f2c17a4ac1894f292ed5701c1f\_90_demux for cells of type $demux.
No more expansions possible.
<suppressed ~2956 debug messages>

24.32. Executing OPT pass (performing simple optimizations).

24.32.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~9083 debug messages>

24.32.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~2208 debug messages>
Removed a total of 736 cells.

24.32.3. Executing OPT_DFF pass (perform DFF optimizations).
Removing always-active EN on $auto$ff.cc:266:slice$13593 ($_SDFFE_PP0P_) from module processorci_top.

24.32.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 1034 unused cells and 3339 unused wires.
<suppressed ~1044 debug messages>

24.32.5. Rerunning OPT passes. (Removed registers in this run.)

24.32.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

24.32.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

24.32.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$13537 ($_DFFE_PP_) from module processorci_top (D = $flatten\ResetBootSystem.$procmux$2574.B_AND_S [1], Q = \ResetBootSystem.state [1], rval = 1'0).
Adding SRST signal on $auto$ff.cc:266:slice$13536 ($_DFFE_PP_) from module processorci_top (D = $flatten\ResetBootSystem.$procmux$2574.B_AND_S [2], Q = \ResetBootSystem.state [0], rval = 1'0).
Adding SRST signal on $auto$ff.cc:266:slice$12243 ($_SDFF_PP0_) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1624.Y_B [6], Q = \Controller.Interpreter.state [6], rval = 1'0).
Adding SRST signal on $auto$ff.cc:266:slice$12242 ($_SDFF_PP0_) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1624.B_AND_S [152], Q = \Controller.Interpreter.state [5], rval = 1'0).
Adding SRST signal on $auto$ff.cc:266:slice$12241 ($_SDFF_PP0_) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1624.Y_B [4], Q = \Controller.Interpreter.state [4], rval = 1'0).
Adding SRST signal on $auto$ff.cc:266:slice$12240 ($_SDFF_PP0_) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1624.Y_B [3], Q = \Controller.Interpreter.state [3], rval = 1'0).
Adding SRST signal on $auto$ff.cc:266:slice$12239 ($_SDFF_PP0_) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1624.Y_B [2], Q = \Controller.Interpreter.state [2], rval = 1'0).
Adding SRST signal on $auto$ff.cc:266:slice$12238 ($_SDFF_PP0_) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1624.Y_B [1], Q = \Controller.Interpreter.state [1], rval = 1'0).
Adding SRST signal on $auto$ff.cc:266:slice$12237 ($_SDFF_PP0_) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$1624.Y_B [0], Q = \Controller.Interpreter.state [0], rval = 1'0).
Adding SRST signal on $auto$ff.cc:266:slice$12127 ($_DFFE_PP_) from module processorci_top (D = $flatten\Controller.\Interpreter.$procmux$2332.Y_B [31], Q = \Controller.Interpreter.address [31], rval = 1'0).

24.32.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 10 unused cells and 9 unused wires.
<suppressed ~11 debug messages>

24.32.10. Rerunning OPT passes. (Removed registers in this run.)

24.32.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

24.32.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~36 debug messages>
Removed a total of 12 cells.

24.32.13. Executing OPT_DFF pass (perform DFF optimizations).

24.32.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 12 unused wires.
<suppressed ~1 debug messages>

24.32.15. Finished fast OPT passes.

24.33. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

24.34. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

24.35. Executing TECHMAP pass (map to technology primitives).

24.35.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Successfully finished Verilog frontend.

24.35.2. Continuing TECHMAP pass.
Using template $paramod\$_DFF_P_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFF_P_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'0 for cells of type $_DFFE_PP_.
Using template \$_SDFFE_PP0P_ for cells of type $_SDFFE_PP0P_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'x for cells of type $_DFFE_PP_.
Using template $paramod\$_DFFE_PP_\_TECHMAP_WIREINIT_Q_=1'1 for cells of type $_DFFE_PP_.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template \$_SDFFE_PP0N_ for cells of type $_SDFFE_PP0N_.
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
Using template \$_SDFFE_PP1P_ for cells of type $_SDFFE_PP1P_.
No more expansions possible.
<suppressed ~691 debug messages>

24.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~100 debug messages>

24.37. Executing SIMPLEMAP pass (map simple cells to gate primitives).

24.38. Executing LATTICE_GSR pass (implement FF init values).
Handling GSR in processorci_top.

24.39. Executing ATTRMVCP pass (move or copy attributes).

24.40. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 3215 unused wires.
<suppressed ~1 debug messages>

24.41. Executing TECHMAP pass (map to technology primitives).

24.41.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

24.41.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>

24.42. Executing ABC9 pass.

24.42.1. Executing ABC9_OPS pass (helper functions for ABC9).

24.42.2. Executing ABC9_OPS pass (helper functions for ABC9).

24.42.3. Executing PROC pass (convert processes to netlists).

24.42.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30361'.
Cleaned up 1 empty switch.

24.42.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30362 in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Removed a total of 0 dead cases.

24.42.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 22 assignments to connections.

24.42.3.4. Executing PROC_INIT pass (extract init attributes).

24.42.3.5. Executing PROC_ARST pass (detect async resets in processes).

24.42.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

24.42.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30386'.
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30362'.
     1/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30360_EN[3:0]$30368
     2/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30360_DATA[3:0]$30366
     3/3: $1$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30360_ADDR[3:0]$30367
Creating decoders for process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30361'.

24.42.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

24.42.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\i' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30386'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30356_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30386'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30348_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30386'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30352_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30386'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30357_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30386'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30351_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30386'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30346_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30386'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30358_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30386'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30350_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30386'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30345_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30386'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30347_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30386'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30353_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30386'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30344_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30386'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30354_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30386'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30355_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30386'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30349_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30386'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:207$30359_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30386'.
  created direct connection (no actual register cell created).
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30360_DATA' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30362'.
  created $dff cell `$procdff$30412' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30360_ADDR' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30362'.
  created $dff cell `$procdff$30413' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$memwr$\mem$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:223$30360_EN' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30362'.
  created $dff cell `$procdff$30414' with positive edge clock.
Creating register for signal `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.\muxwre' using process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30361'.
  created direct connection (no actual register cell created).

24.42.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

24.42.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:0$30386'.
Found and cleaned up 1 empty switch in `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:221$30362'.
Removing empty process `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.$proc$/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_sim.v:213$30361'.
Cleaned up 1 empty switch.

24.42.3.12. Executing OPT_EXPR pass (perform const folding).

24.42.4. Executing SCC pass (detecting logic loops).
Found an SCC: $auto$opt_expr.cc:617:replace_const_cells$29066 $auto$simplemap.cc:267:simplemap_mux$24214 $auto$simplemap.cc:126:simplemap_reduce$24115 $auto$simplemap.cc:126:simplemap_reduce$24112 $auto$opt_expr.cc:617:replace_const_cells$29044 $auto$ff.cc:266:slice$13059 $auto$simplemap.cc:126:simplemap_reduce$13212 $auto$simplemap.cc:126:simplemap_reduce$13197 $auto$ff.cc:266:slice$13058 $auto$ff.cc:266:slice$13057 $auto$simplemap.cc:75:simplemap_bitop$24786 $auto$simplemap.cc:196:simplemap_lognot$13216 $auto$simplemap.cc:126:simplemap_reduce$13214 $auto$simplemap.cc:126:simplemap_reduce$13211 $auto$simplemap.cc:267:simplemap_mux$13181 $auto$simplemap.cc:225:simplemap_logbin$13184 $auto$simplemap.cc:196:simplemap_lognot$13201 $auto$simplemap.cc:126:simplemap_reduce$13199 $auto$simplemap.cc:126:simplemap_reduce$13196 $auto$opt_expr.cc:617:replace_const_cells$29530 $auto$ff.cc:266:slice$13056 $auto$simplemap.cc:126:simplemap_reduce$16021 $auto$simplemap.cc:126:simplemap_reduce$16019 $auto$simplemap.cc:225:simplemap_logbin$13140 $auto$simplemap.cc:196:simplemap_lognot$13150 $auto$simplemap.cc:126:simplemap_reduce$13148 $auto$opt_expr.cc:617:replace_const_cells$29068 $auto$simplemap.cc:267:simplemap_mux$24213 $auto$simplemap.cc:126:simplemap_reduce$24120 $auto$simplemap.cc:126:simplemap_reduce$24117 $auto$simplemap.cc:75:simplemap_bitop$24789
Found an SCC: $auto$simplemap.cc:196:simplemap_lognot$18159 $auto$simplemap.cc:167:logic_reduce$18158 $auto$simplemap.cc:126:simplemap_reduce$13654 $auto$simplemap.cc:126:simplemap_reduce$16041 $auto$simplemap.cc:126:simplemap_reduce$12333 $auto$simplemap.cc:196:simplemap_lognot$18169 $auto$simplemap.cc:126:simplemap_reduce$18179 $auto$simplemap.cc:38:simplemap_not$24812 $auto$ff.cc:266:slice$18151 $auto$ff.cc:479:convert_ce_over_srst$29660 $auto$ff.cc:266:slice$18153 $auto$ff.cc:479:convert_ce_over_srst$29664 $auto$simplemap.cc:38:simplemap_not$24817 $auto$ff.cc:266:slice$18156 $auto$ff.cc:479:convert_ce_over_srst$29670 $auto$alumacc.cc:485:replace_alu$6628.slice[2].ccu2c_i $auto$alumacc.cc:485:replace_alu$6628.slice[0].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$9260 $auto$simplemap.cc:38:simplemap_not$19087 $auto$simplemap.cc:126:simplemap_reduce$18181 $auto$ff.cc:266:slice$18152 $auto$ff.cc:479:convert_ce_over_srst$29662 $auto$simplemap.cc:126:simplemap_reduce$9262 $auto$simplemap.cc:38:simplemap_not$9268 $auto$alumacc.cc:485:replace_alu$6628.slice[4].ccu2c_i $auto$simplemap.cc:126:simplemap_reduce$18183 $auto$ff.cc:266:slice$18155 $auto$ff.cc:479:convert_ce_over_srst$29668 $auto$simplemap.cc:126:simplemap_reduce$18177 $auto$simplemap.cc:126:simplemap_reduce$18167 $auto$simplemap.cc:126:simplemap_reduce$18148 $auto$opt_expr.cc:617:replace_const_cells$29026 $auto$ff.cc:266:slice$29560 $auto$dfflegalize.cc:941:flip_pol$29674 $auto$ff.cc:485:convert_ce_over_srst$29672 $auto$simplemap.cc:126:simplemap_reduce$13588 $auto$simplemap.cc:126:simplemap_reduce$18131 $auto$simplemap.cc:126:simplemap_reduce$18187 $auto$simplemap.cc:126:simplemap_reduce$18185 $auto$simplemap.cc:126:simplemap_reduce$18182 $auto$ff.cc:266:slice$18154 $auto$ff.cc:479:convert_ce_over_srst$29666 $auto$simplemap.cc:126:simplemap_reduce$16046 $auto$simplemap.cc:126:simplemap_reduce$16044 $auto$simplemap.cc:126:simplemap_reduce$13657 $auto$simplemap.cc:126:simplemap_reduce$13655 $auto$simplemap.cc:38:simplemap_not$9279 $auto$simplemap.cc:75:simplemap_bitop$9175 $auto$simplemap.cc:126:simplemap_reduce$9266 $auto$simplemap.cc:126:simplemap_reduce$9264 $auto$simplemap.cc:126:simplemap_reduce$9261 $auto$simplemap.cc:38:simplemap_not$24815
Found an SCC: $auto$simplemap.cc:38:simplemap_not$25800 $auto$ff.cc:266:slice$12893 $auto$simplemap.cc:126:simplemap_reduce$13031 $auto$simplemap.cc:126:simplemap_reduce$13000 $auto$simplemap.cc:38:simplemap_not$25801 $auto$ff.cc:266:slice$12894 $auto$opt_expr.cc:617:replace_const_cells$29034 $auto$ff.cc:266:slice$12895 $auto$simplemap.cc:126:simplemap_reduce$13032 $auto$simplemap.cc:126:simplemap_reduce$13001 $auto$simplemap.cc:38:simplemap_not$25803 $auto$ff.cc:266:slice$12896 $auto$opt_expr.cc:617:replace_const_cells$29038 $auto$ff.cc:266:slice$12897 $auto$simplemap.cc:126:simplemap_reduce$13036 $auto$simplemap.cc:126:simplemap_reduce$13033 $auto$opt_expr.cc:617:replace_const_cells$29036 $auto$simplemap.cc:126:simplemap_reduce$13005 $auto$simplemap.cc:126:simplemap_reduce$13002 $auto$ff.cc:266:slice$12898 $auto$ff.cc:266:slice$12899 $auto$opt_expr.cc:617:replace_const_cells$29042 $auto$ff.cc:266:slice$12891 $auto$simplemap.cc:196:simplemap_lognot$13042 $auto$simplemap.cc:126:simplemap_reduce$13040 $auto$simplemap.cc:126:simplemap_reduce$13038 $auto$simplemap.cc:126:simplemap_reduce$13035 $auto$simplemap.cc:126:simplemap_reduce$13030 $auto$simplemap.cc:225:simplemap_logbin$12984 $auto$simplemap.cc:196:simplemap_lognot$13011 $auto$simplemap.cc:126:simplemap_reduce$13009 $auto$simplemap.cc:126:simplemap_reduce$13007 $auto$simplemap.cc:126:simplemap_reduce$13004 $auto$simplemap.cc:126:simplemap_reduce$12999 $auto$ff.cc:266:slice$12892 $auto$simplemap.cc:167:logic_reduce$9167 $auto$simplemap.cc:225:simplemap_logbin$12983
Found an SCC: $auto$opt_expr.cc:617:replace_const_cells$29290 $auto$ff.cc:266:slice$29583 $auto$opt_expr.cc:617:replace_const_cells$29054 $auto$ff.cc:266:slice$29562 $auto$opt_expr.cc:617:replace_const_cells$29142 $auto$ff.cc:266:slice$29576 $auto$opt_expr.cc:617:replace_const_cells$29288 $auto$ff.cc:266:slice$29604 $auto$simplemap.cc:126:simplemap_reduce$11903 $auto$simplemap.cc:126:simplemap_reduce$11979 $auto$opt_expr.cc:617:replace_const_cells$29056 $auto$simplemap.cc:126:simplemap_reduce$10636 $auto$simplemap.cc:126:simplemap_reduce$11640 $auto$ff.cc:266:slice$29590 $auto$simplemap.cc:126:simplemap_reduce$11810 $auto$simplemap.cc:126:simplemap_reduce$10434 $auto$simplemap.cc:126:simplemap_reduce$11807 $auto$simplemap.cc:126:simplemap_reduce$11929 $auto$simplemap.cc:126:simplemap_reduce$11926 $auto$simplemap.cc:126:simplemap_reduce$11536 $auto$simplemap.cc:126:simplemap_reduce$11533 $auto$opt_expr.cc:617:replace_const_cells$29052 $auto$simplemap.cc:126:simplemap_reduce$11983 $auto$simplemap.cc:126:simplemap_reduce$11558 $auto$simplemap.cc:126:simplemap_reduce$11980 $auto$ff.cc:266:slice$29569 $auto$simplemap.cc:196:simplemap_lognot$10324 $auto$simplemap.cc:126:simplemap_reduce$10322 $auto$simplemap.cc:196:simplemap_lognot$10346 $auto$simplemap.cc:126:simplemap_reduce$10344 $auto$simplemap.cc:196:simplemap_lognot$10460 $auto$simplemap.cc:126:simplemap_reduce$10458 $auto$simplemap.cc:196:simplemap_lognot$10666 $auto$simplemap.cc:126:simplemap_reduce$10664 $auto$simplemap.cc:126:simplemap_reduce$10730 $auto$simplemap.cc:126:simplemap_reduce$11755 $auto$simplemap.cc:196:simplemap_lognot$10576 $auto$simplemap.cc:126:simplemap_reduce$10574 $auto$simplemap.cc:196:simplemap_lognot$10867 $auto$simplemap.cc:126:simplemap_reduce$10865 $auto$simplemap.cc:126:simplemap_reduce$10862 $auto$simplemap.cc:196:simplemap_lognot$10622 $auto$simplemap.cc:126:simplemap_reduce$10620 $auto$simplemap.cc:126:simplemap_reduce$10617 $auto$simplemap.cc:196:simplemap_lognot$10258 $auto$simplemap.cc:126:simplemap_reduce$10256 $auto$simplemap.cc:126:simplemap_reduce$15990 $auto$simplemap.cc:196:simplemap_lognot$10688 $auto$simplemap.cc:126:simplemap_reduce$10686 $auto$simplemap.cc:196:simplemap_lognot$11485 $auto$simplemap.cc:126:simplemap_reduce$11483 $auto$simplemap.cc:126:simplemap_reduce$11643 $auto$simplemap.cc:126:simplemap_reduce$11751 $auto$simplemap.cc:126:simplemap_reduce$26195 $auto$simplemap.cc:196:simplemap_lognot$10302 $auto$simplemap.cc:126:simplemap_reduce$10300 $auto$simplemap.cc:126:simplemap_reduce$11906 $auto$simplemap.cc:196:simplemap_lognot$10554 $auto$simplemap.cc:126:simplemap_reduce$10552 $auto$simplemap.cc:126:simplemap_reduce$10549 $auto$simplemap.cc:196:simplemap_lognot$10392 $auto$simplemap.cc:126:simplemap_reduce$10390 $auto$simplemap.cc:196:simplemap_lognot$10509 $auto$simplemap.cc:126:simplemap_reduce$10507 $auto$simplemap.cc:126:simplemap_reduce$11513 $auto$simplemap.cc:126:simplemap_reduce$15993 $auto$simplemap.cc:126:simplemap_reduce$15989 $auto$simplemap.cc:196:simplemap_lognot$10171 $auto$simplemap.cc:126:simplemap_reduce$10169 $auto$simplemap.cc:196:simplemap_lognot$10754 $auto$simplemap.cc:126:simplemap_reduce$10752 $auto$simplemap.cc:196:simplemap_lognot$10821 $auto$simplemap.cc:126:simplemap_reduce$10819 $auto$simplemap.cc:126:simplemap_reduce$11557 $auto$simplemap.cc:126:simplemap_reduce$11902 $auto$simplemap.cc:126:simplemap_reduce$25439 $auto$simplemap.cc:126:simplemap_reduce$13098 $auto$simplemap.cc:196:simplemap_lognot$10598 $auto$simplemap.cc:126:simplemap_reduce$10596 $auto$simplemap.cc:126:simplemap_reduce$10593 $auto$simplemap.cc:196:simplemap_lognot$10438 $auto$simplemap.cc:126:simplemap_reduce$10436 $auto$simplemap.cc:126:simplemap_reduce$26265 $auto$simplemap.cc:196:simplemap_lognot$10798 $auto$simplemap.cc:126:simplemap_reduce$10796 $auto$simplemap.cc:126:simplemap_reduce$10793 $auto$simplemap.cc:126:simplemap_reduce$26442 $auto$simplemap.cc:126:simplemap_reduce$26434 $auto$simplemap.cc:196:simplemap_lognot$10843 $auto$simplemap.cc:126:simplemap_reduce$10841 $auto$simplemap.cc:126:simplemap_reduce$10838 $auto$simplemap.cc:126:simplemap_reduce$26197 $auto$simplemap.cc:196:simplemap_lognot$10414 $auto$simplemap.cc:126:simplemap_reduce$10412 $auto$simplemap.cc:196:simplemap_lognot$10889 $auto$simplemap.cc:126:simplemap_reduce$10887 $auto$simplemap.cc:126:simplemap_reduce$26435 $auto$simplemap.cc:196:simplemap_lognot$11463 $auto$simplemap.cc:126:simplemap_reduce$11461 $auto$simplemap.cc:126:simplemap_reduce$11458 $auto$simplemap.cc:126:simplemap_reduce$11454 $auto$opt_expr.cc:617:replace_const_cells$29286 $auto$simplemap.cc:126:simplemap_reduce$12929 $auto$simplemap.cc:196:simplemap_lognot$10531 $auto$simplemap.cc:126:simplemap_reduce$10529 $auto$simplemap.cc:126:simplemap_reduce$26430 $auto$simplemap.cc:126:simplemap_reduce$12931 $auto$simplemap.cc:196:simplemap_lognot$10776 $auto$simplemap.cc:126:simplemap_reduce$10774 $auto$simplemap.cc:126:simplemap_reduce$11733 $auto$simplemap.cc:126:simplemap_reduce$26439 $auto$simplemap.cc:126:simplemap_reduce$26196 $auto$simplemap.cc:126:simplemap_reduce$16034 $auto$simplemap.cc:196:simplemap_lognot$10368 $auto$simplemap.cc:126:simplemap_reduce$10366 $auto$simplemap.cc:126:simplemap_reduce$26440 $auto$simplemap.cc:126:simplemap_reduce$26429 $auto$simplemap.cc:196:simplemap_lognot$10487 $auto$simplemap.cc:126:simplemap_reduce$10485 $auto$simplemap.cc:126:simplemap_reduce$11982 $auto$simplemap.cc:196:simplemap_lognot$10280 $auto$simplemap.cc:126:simplemap_reduce$10278 $auto$simplemap.cc:196:simplemap_lognot$10710 $auto$simplemap.cc:126:simplemap_reduce$10708 $auto$simplemap.cc:126:simplemap_reduce$26447 $auto$simplemap.cc:126:simplemap_reduce$26443 $auto$simplemap.cc:126:simplemap_reduce$26436 $auto$simplemap.cc:196:simplemap_lognot$11496 $auto$simplemap.cc:167:logic_reduce$11495 $auto$simplemap.cc:167:logic_reduce$11492 $auto$simplemap.cc:126:simplemap_reduce$26446 $auto$simplemap.cc:126:simplemap_reduce$26441 $auto$simplemap.cc:126:simplemap_reduce$26432 $auto$simplemap.cc:196:simplemap_lognot$10644 $auto$simplemap.cc:126:simplemap_reduce$10642 $auto$simplemap.cc:126:simplemap_reduce$10639 $auto$simplemap.cc:126:simplemap_reduce$11978 $auto$ff.cc:266:slice$29597 $auto$simplemap.cc:126:simplemap_reduce$29568 $auto$opt_dff.cc:248:combine_resets$29563 $auto$simplemap.cc:126:simplemap_reduce$26451 $auto$simplemap.cc:126:simplemap_reduce$26449 $auto$simplemap.cc:126:simplemap_reduce$26445 $auto$simplemap.cc:126:simplemap_reduce$26438 $auto$simplemap.cc:126:simplemap_reduce$26425 $auto$simplemap.cc:126:simplemap_reduce$15995 $auto$simplemap.cc:126:simplemap_reduce$15991 $auto$simplemap.cc:196:simplemap_lognot$10732
Found an SCC: $auto$ff.cc:266:slice$13068 $auto$ff.cc:266:slice$13065 $auto$simplemap.cc:126:simplemap_reduce$13233 $auto$simplemap.cc:38:simplemap_not$18583 $auto$ff.cc:266:slice$13064 $auto$simplemap.cc:38:simplemap_not$18582 $auto$ff.cc:266:slice$13063 $auto$simplemap.cc:126:simplemap_reduce$13232 $auto$ff.cc:266:slice$13062 $auto$ff.cc:266:slice$13061 $auto$simplemap.cc:38:simplemap_not$18585 $auto$ff.cc:266:slice$13066 $auto$simplemap.cc:126:simplemap_reduce$13237 $auto$simplemap.cc:126:simplemap_reduce$13234 $auto$simplemap.cc:38:simplemap_not$18586 $auto$ff.cc:266:slice$13067 $auto$simplemap.cc:126:simplemap_reduce$13241 $auto$simplemap.cc:126:simplemap_reduce$13239 $auto$simplemap.cc:126:simplemap_reduce$13236 $auto$simplemap.cc:126:simplemap_reduce$13231 $auto$simplemap.cc:38:simplemap_not$18579 $auto$ff.cc:266:slice$13060 $auto$simplemap.cc:126:simplemap_reduce$9321 $auto$simplemap.cc:196:simplemap_lognot$13243
Found 5 SCCs in module processorci_top.
Found 5 SCCs.

24.42.5. Executing ABC9_OPS pass (helper functions for ABC9).

24.42.6. Executing PROC pass (convert processes to netlists).

24.42.6.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

24.42.6.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

24.42.6.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

24.42.6.4. Executing PROC_INIT pass (extract init attributes).

24.42.6.5. Executing PROC_ARST pass (detect async resets in processes).

24.42.6.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

24.42.6.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

24.42.6.8. Executing PROC_DLATCH pass (convert process syncs to latches).

24.42.6.9. Executing PROC_DFF pass (convert process syncs to FFs).

24.42.6.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

24.42.6.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

24.42.6.12. Executing OPT_EXPR pass (perform const folding).

24.42.7. Executing TECHMAP pass (map to technology primitives).

24.42.7.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

24.42.7.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~162 debug messages>

24.42.8. Executing OPT pass (performing simple optimizations).

24.42.8.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.

24.42.8.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

24.42.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

24.42.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Performed a total of 0 changes.

24.42.8.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `$paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4'.
Removed a total of 0 cells.

24.42.8.6. Executing OPT_DFF pass (perform DFF optimizations).

24.42.8.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4..

24.42.8.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.

24.42.8.9. Finished OPT passes. (There is nothing left to do.)

24.42.9. Executing TECHMAP pass (map to technology primitives).

24.42.9.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.

24.42.9.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
No more expansions possible.
<suppressed ~1031 debug messages>

24.42.10. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_model.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.

24.42.11. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

24.42.12. Executing ABC9_OPS pass (helper functions for ABC9).

24.42.13. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

24.42.14. Executing TECHMAP pass (map to technology primitives).

24.42.14.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/techmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

24.42.14.2. Continuing TECHMAP pass.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod\LUT4\INIT=16'1001011010101010 for cells of type LUT4.
Using template $paramod\LUT2\INIT=4'1010 for cells of type LUT2.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~201 debug messages>

24.42.15. Executing OPT pass (performing simple optimizations).

24.42.15.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.
<suppressed ~18 debug messages>

24.42.15.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

24.42.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

24.42.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

24.42.15.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

24.42.15.6. Executing OPT_DFF pass (perform DFF optimizations).

24.42.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..
Removed 0 unused cells and 55 unused wires.
<suppressed ~1 debug messages>

24.42.15.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

24.42.15.9. Rerunning OPT passes. (Maybe there is more to do..)

24.42.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \processorci_top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

24.42.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \processorci_top.
Performed a total of 0 changes.

24.42.15.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\processorci_top'.
Removed a total of 0 cells.

24.42.15.13. Executing OPT_DFF pass (perform DFF optimizations).

24.42.15.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \processorci_top..

24.42.15.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module processorci_top.

24.42.15.16. Finished OPT passes. (There is nothing left to do.)

24.42.16. Executing AIGMAP pass (map logic to AIG).
Module processorci_top: replaced 18 cells with 120 new cells, skipped 39 cells.
  replaced 3 cell types:
       2 $_OR_
       2 $_XOR_
      14 $_MUX_
  not replaced 3 cell types:
      31 $specify2
       4 $_NOT_
       4 $_AND_

24.42.17. Executing AIGMAP pass (map logic to AIG).
Module processorci_top: replaced 5417 cells with 35790 new cells, skipped 3591 cells.
  replaced 4 cell types:
     707 $_OR_
      82 $_XOR_
       2 $_ORNOT_
    4626 $_MUX_
  not replaced 8 cell types:
      38 $scopeinfo
     234 $_NOT_
     544 $_AND_
     576 TRELLIS_FF
    1028 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp
     142 $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C
    1028 $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4
       1 $__ABC9_SCC_BREAKER

24.42.17.1. Executing ABC9_OPS pass (helper functions for ABC9).

24.42.17.2. Executing ABC9_OPS pass (helper functions for ABC9).

24.42.17.3. Executing XAIGER backend.
<suppressed ~11 debug messages>
Extracted 15377 AND gates and 46420 wires from module `processorci_top' to a netlist network with 4700 inputs and 838 outputs.

24.42.17.4. Executing ABC9_EXE pass (technology mapping using ABC9).

24.42.17.5. Executing ABC9.
Running ABC command: "<yosys-exe-dir>/yosys-abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_lut <abc-temp-dir>/input.lut 
ABC: + read_box <abc-temp-dir>/input.box 
ABC: + &read <abc-temp-dir>/input.xaig 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   4700/    838  and =   14593  lev =   20 (0.34)  mem = 0.47 MB  box = 1170  bb = 1028
ABC: + &scorr 
ABC: Warning: The network is combinational.
ABC: + &sweep 
ABC: + &dc2 
ABC: + &dch -f 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   4700/    838  and =   17737  lev =   17 (0.31)  mem = 0.50 MB  ch = 1488  box = 1170  bb = 1028
ABC: + &if -W 300 -v 
ABC: K = 7. Memory (bytes): Truth =    0. Cut =   64. Obj =  148. Set =  672. CutMin = no
ABC: Node =   17737.  Ch =   879.  Total mem =    5.84 MB. Peak cut mem =    0.11 MB.
ABC: P:  Del = 4099.00.  Ar =   12579.0.  Edge =    15893.  Cut =   201388.  T =     0.09 sec
ABC: P:  Del = 4099.00.  Ar =   12527.0.  Edge =    15846.  Cut =   198864.  T =     0.09 sec
ABC: P:  Del = 4099.00.  Ar =    6451.0.  Edge =    14733.  Cut =   501549.  T =     0.21 sec
ABC: F:  Del = 4094.00.  Ar =    5616.0.  Edge =    14414.  Cut =   280148.  T =     0.12 sec
ABC: A:  Del = 4065.00.  Ar =    5171.0.  Edge =    14286.  Cut =   276245.  T =     0.18 sec
ABC: A:  Del = 4065.00.  Ar =    4486.0.  Edge =    14279.  Cut =   279834.  T =     0.19 sec
ABC: Total time =     0.89 sec
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + &mfs 
ABC: + &ps -l 
ABC: <abc-temp-dir>/input : i/o =   4700/    838  and =   10998  lev =   18 (0.33)  mem = 0.43 MB  box = 1170  bb = 1028
ABC: Mapping (K=7)  :  lut =   3646  edge =   14253  lev =    8 (0.20)  Boxes are not in a topological order. Switching to level computation without boxes.
ABC: levB =   18  mem = 0.20 MB
ABC: LUT = 3646 : 2=346 9.5 %  3=307 8.4 %  4=2427 66.6 %  5=497 13.6 %  6=36 1.0 %  7=33 0.9 %  Ave = 3.91
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + time 
ABC: elapse: 5.58 seconds, total: 5.58 seconds

24.42.17.6. Executing AIGER frontend.
<suppressed ~11088 debug messages>
Removed 13888 unused cells and 37947 unused wires.

24.42.17.7. Executing ABC9_OPS pass (helper functions for ABC9).
ABC RESULTS:              $lut cells:     3658
ABC RESULTS:   $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp cells:     1028
ABC RESULTS:   $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C cells:      142
ABC RESULTS:           input signals:     1084
ABC RESULTS:          output signals:      177
Removing temp directory.

24.42.18. Executing TECHMAP pass (map to technology primitives).

24.42.18.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.

24.42.18.2. Continuing TECHMAP pass.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4 for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4.
Using template $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp for cells of type $paramod$2074b3813575c9ede27f9a04ee0bf291c9c7bf2f\TRELLIS_DPR16X4_$abc9_byp.
Using template $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C for cells of type $paramod$838872d5a4bab89607f53482b205c0fd50d8b82e\CCU2C.
Using template $paramod\$__ABC9_SCC_BREAKER\WIDTH=32'00000000000000000000000000000111 for cells of type $__ABC9_SCC_BREAKER.
No more expansions possible.
<suppressed ~2218 debug messages>
Removed 208 unused cells and 61145 unused wires.

24.43. Executing TECHMAP pass (map to technology primitives).

24.43.1. Executing Verilog-2005 frontend: /eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v
Parsing Verilog input from `/eda/oss-cad-suite/lib/../share/yosys/ecp5/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_DFFE_NP0N_'.
Generating RTLIL representation for module `\$_DFFE_NP1N_'.
Generating RTLIL representation for module `\$_DFFE_PP0N_'.
Generating RTLIL representation for module `\$_DFFE_PP1N_'.
Generating RTLIL representation for module `\$_SDFFE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFFE_NP0N_'.
Generating RTLIL representation for module `\$_SDFFE_NP1N_'.
Generating RTLIL representation for module `\$_SDFFE_PP0N_'.
Generating RTLIL representation for module `\$_SDFFE_PP1N_'.
Generating RTLIL representation for module `\$_ALDFF_NP_'.
Generating RTLIL representation for module `\$_ALDFF_PP_'.
Generating RTLIL representation for module `\$_ALDFFE_NPN_'.
Generating RTLIL representation for module `\$_ALDFFE_NPP_'.
Generating RTLIL representation for module `\$_ALDFFE_PPN_'.
Generating RTLIL representation for module `\$_ALDFFE_PPP_'.
Generating RTLIL representation for module `\FD1P3AX'.
Generating RTLIL representation for module `\FD1P3AY'.
Generating RTLIL representation for module `\FD1P3BX'.
Generating RTLIL representation for module `\FD1P3DX'.
Generating RTLIL representation for module `\FD1P3IX'.
Generating RTLIL representation for module `\FD1P3JX'.
Generating RTLIL representation for module `\FD1S3AX'.
Generating RTLIL representation for module `\FD1S3AY'.
Generating RTLIL representation for module `\FD1S3BX'.
Generating RTLIL representation for module `\FD1S3DX'.
Generating RTLIL representation for module `\FD1S3IX'.
Generating RTLIL representation for module `\FD1S3JX'.
Generating RTLIL representation for module `\IFS1P3BX'.
Generating RTLIL representation for module `\IFS1P3DX'.
Generating RTLIL representation for module `\IFS1P3IX'.
Generating RTLIL representation for module `\IFS1P3JX'.
Generating RTLIL representation for module `\OFS1P3BX'.
Generating RTLIL representation for module `\OFS1P3DX'.
Generating RTLIL representation for module `\OFS1P3IX'.
Generating RTLIL representation for module `\OFS1P3JX'.
Generating RTLIL representation for module `\IB'.
Generating RTLIL representation for module `\IBPU'.
Generating RTLIL representation for module `\IBPD'.
Generating RTLIL representation for module `\OB'.
Generating RTLIL representation for module `\OBZ'.
Generating RTLIL representation for module `\OBZPU'.
Generating RTLIL representation for module `\OBZPD'.
Generating RTLIL representation for module `\OBCO'.
Generating RTLIL representation for module `\BB'.
Generating RTLIL representation for module `\BBPU'.
Generating RTLIL representation for module `\BBPD'.
Generating RTLIL representation for module `\ILVDS'.
Generating RTLIL representation for module `\OLVDS'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

24.43.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
Using template $paramod$11ec7271d8e6e5aeaace08c13e4c601f10e31038\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod$f3ada871809f362efd8eb0c4fb952bb5c98f0750\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut.
Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut.
Using template $paramod$373d637619c29cb9150902df9528107e5f3b8288\$lut for cells of type $lut.
Using template $paramod$ddace04fba544e6adc4cdda6a50048ddd7c111af\$lut for cells of type $lut.
Using template $paramod$037be5c00d8a02858cdb1ab049b58a0133287ff1\$lut for cells of type $lut.
Using template $paramod$2e9afba29670cc6475874639e7c1b3979c8ebde3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod$3bb7e0f38c95bb34c4c0d65ba82f8853a7dad6b0\$lut for cells of type $lut.
Using template $paramod$390100c100be946e71458bb0f6cff8e1f65a2e18\$lut for cells of type $lut.
Using template $paramod$362575889e8038ccd753f0aeb8a3205dfee54d00\$lut for cells of type $lut.
Using template $paramod$d21d214a5aa271f2d9da3f90f22432c0ecee130f\$lut for cells of type $lut.
Using template $paramod$c9cacea93e48dbdafc5454c7b716dc15fe7e5a4d\$lut for cells of type $lut.
Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut.
Using template $paramod$c9660a7363470828a36400d8a897c50467f9447e\$lut for cells of type $lut.
Using template $paramod$56aad51fb7b279620a0eb687a16eaf1fb92f4a75\$lut for cells of type $lut.
Using template $paramod$8a0b4883c15a2ecc4461cc484e6fafca1b78f9a5\$lut for cells of type $lut.
Using template $paramod$5c194b50cebc34e0a5050f2a2ccf9cc7ee0b13c9\$lut for cells of type $lut.
Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut.
Using template $paramod$b089060a61c5d29ddce66d73edb5ee493ec9de27\$lut for cells of type $lut.
Using template $paramod$b93d1ea7a612a32c185108f67a153d44ffb9aac2\$lut for cells of type $lut.
Using template $paramod$00ffcc628ccb870304683cac36ad3a16cc41b6a4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut.
Using template $paramod$000fa2164e1f538c16460571efee2b6209a086cc\$lut for cells of type $lut.
Using template $paramod$bb16063c3ae8ecbd88336b4a464f5bc660922ed6\$lut for cells of type $lut.
Using template $paramod$9851cb11f88bbbf4a516c0595f3b0113b1f100c4\$lut for cells of type $lut.
Using template $paramod$d79e8c7f0cb3bd049a34d82ec5fe688d444e5a52\$lut for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut.
Using template $paramod$219b71aec9a19e7a27754ed85a7d6cdad9e5ec96\$lut for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
Using template $paramod$eba7de026ff587370e320127e266317dae097a89\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
Using template $paramod$983adbc56c7400f95b406f02e82bd0da8b98fd00\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod$2d07c1a6c53c7b878509360922c4fa5ebedc3011\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut.
Using template $paramod$b40ed8783cd24943f4c31bddb9063d9895eb569a\$lut for cells of type $lut.
Using template $paramod$992bdc10cff2c6edd722994f0e1044bc863f79f7\$lut for cells of type $lut.
Using template $paramod$b86b68a00733dbecb31d58a14a13683475a2002a\$lut for cells of type $lut.
Using template $paramod$43779580bfffd5d5a9f321249a174febf1dac288\$lut for cells of type $lut.
Using template $paramod$65d5d5c1e01bf41ee659754efba932f3d99198e5\$lut for cells of type $lut.
Using template $paramod$f45429e380905f064bb0bad3a8bdb941708e63a7\$lut for cells of type $lut.
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut.
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut.
Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut.
Using template $paramod$cf652acbfbf67d2248e3045cd0f09c58ca55886c\$lut for cells of type $lut.
Using template $paramod$8c24dc0cdd336b7fb88bbf7eed45cec5cbae862b\$lut for cells of type $lut.
Using template $paramod$338ce46cf7ff44b9974887dd2adee6c4e0530bed\$lut for cells of type $lut.
Using template $paramod$82b4a585d1edcb5c6e755dc9bd3392228a1c1304\$lut for cells of type $lut.
Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut.
Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001100 for cells of type $lut.
Using template $paramod$2382b0dd4cb27fd4312681c40a6dd179c2a7a26a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
Using template $paramod$d76edc10344198fdbbc083cbc9765a888a1f48f2\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00111010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
Using template $paramod$f5f41ee5d60dede31a2b59f58ec46b167939d713\$lut for cells of type $lut.
Using template $paramod$9cc51547ab44a72dd506ee5bb84a864365a103da\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001010 for cells of type $lut.
Using template $paramod$12e9049d8709286a770fe60b59ec4d94c39ce3c9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010100 for cells of type $lut.
Using template $paramod$9beb8ded65337efae33440136749662bd930ae79\$lut for cells of type $lut.
Using template $paramod$a471f8e9abec0fbc54d503744e2fc526d857a6b7\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut.
Using template $paramod$eb0b7b796486150424969057dee3cec0b7ea7771\$lut for cells of type $lut.
Using template $paramod$d7ec878ecfa8f5f7604d3e91692b5d4c2ee758ad\$lut for cells of type $lut.
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod$fe9a0158d0352193457c4f5b6282ac86d35fb3ee\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
Using template $paramod$23764ef6208c0eba4ffe4afe904943e1ed80e8a4\$lut for cells of type $lut.
Using template $paramod$3d7168c8134c4765b84a7b86d5ef7e1e65bbf4a0\$lut for cells of type $lut.
Using template $paramod$e0933dc5829c51c34f6c673ccf5dc18c4bc56f7c\$lut for cells of type $lut.
Using template $paramod$2fd3c42461376c704c07117e7368b2ed8179d1e0\$lut for cells of type $lut.
Using template $paramod$c2dc8bc4808cd817aa875891b1f3a4dbb8b3c4df\$lut for cells of type $lut.
Using template $paramod$0e3a63073d9266614119b800b7973fa7b8c05e77\$lut for cells of type $lut.
Using template $paramod$0e7ce19e5da99c6675c7a5220f7cc55270b24ac0\$lut for cells of type $lut.
Using template $paramod$e5759512db67494ff77fbdfc66dff4006376568f\$lut for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
Using template $paramod$d546db88fc169832512e499a9cdf9a41b89ab74e\$lut for cells of type $lut.
Using template $paramod$92c3899764cd8074859d6a5a5b733cffe8a391b3\$lut for cells of type $lut.
Using template $paramod$f3e1547c4b47e64c590e75cf09078b2507c8cc75\$lut for cells of type $lut.
Using template $paramod$5321e04f7ce32c091123c3570ab562efb1c81402\$lut for cells of type $lut.
Using template $paramod$58ed37e0047dc9021b2681b3fa25560406a456c6\$lut for cells of type $lut.
Using template $paramod$8af1d7de486caf60eeec1cdcefc1d5b70c13b855\$lut for cells of type $lut.
Using template $paramod$46969734f619307bdfb8ca4ad5af273b11115f8d\$lut for cells of type $lut.
Using template $paramod$dbdbcb07b9994e498bb1324e5c006c6aa08a7a37\$lut for cells of type $lut.
Using template $paramod$7e3de18263fb7d0a2e12a4401120994e66bde6a4\$lut for cells of type $lut.
Using template $paramod$bde0f4b82f0bb2e27f01f1b9f1880ce2bb4a21a4\$lut for cells of type $lut.
Using template $paramod$f564d09aba1072e2a15c033602471ae2a7d995dc\$lut for cells of type $lut.
Using template $paramod$3b8882b0d6bc600370b248ab21711bf777487dcc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
Using template $paramod$f610396a8c1614f373f4d73e3d1e988bc93e396c\$lut for cells of type $lut.
Using template $paramod$58425b7a5048b0a76d60e8b663c630822fa29499\$lut for cells of type $lut.
Using template $paramod$25f4c29da5c7377f61ba4ef7ba6db95053b6905e\$lut for cells of type $lut.
Using template $paramod$81d8a60fd95b1a9f9ef71c12a774ae6988cb9fd5\$lut for cells of type $lut.
Using template $paramod$92264ff2e4ad0c75c9a56a08258e8f32f527121c\$lut for cells of type $lut.
Using template $paramod$77f79ca54e9cde8e0a4a3851773ec0a8bfa9d620\$lut for cells of type $lut.
Using template $paramod$a462117541566384a2f7b7f7d9d41b1139721862\$lut for cells of type $lut.
Using template $paramod$a564887bbf2c017c6e8cdcc3ce6ce49e00810266\$lut for cells of type $lut.
Using template $paramod$84a8f8f5c4fc3ca4ab76818073b00098bddce155\$lut for cells of type $lut.
Using template $paramod$3258fabf91107b4a007ae89b2246a16c31e8ae28\$lut for cells of type $lut.
Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut.
Using template $paramod$a47d3f6fd9a7aebdb1b556bc977da3380a17c8cf\$lut for cells of type $lut.
Using template $paramod$edc5a73130589b9210f4bdf92e14bdcacac8945d\$lut for cells of type $lut.
Using template $paramod$2de23df76a24087ecc0fa38a78ecc970cd3f2492\$lut for cells of type $lut.
Using template $paramod$b587e1dcd8f8a9800d395e4aeecac52c55d6f585\$lut for cells of type $lut.
Using template $paramod$a4640096cbef09c4ef8613155a589c40164ac034\$lut for cells of type $lut.
Using template $paramod$620586420e818d3afa7e5b51fcf19f5c6ea83ad4\$lut for cells of type $lut.
Using template $paramod$df929792afd0bebf101a124ee890c12e0fed6a8d\$lut for cells of type $lut.
Using template $paramod$adce9c89515a4e83641fc3471eb3c01ec7b082ff\$lut for cells of type $lut.
Using template $paramod$f85f1073c412d406200a6a72283f918c8b751314\$lut for cells of type $lut.
Using template $paramod$8ae5e24171bca0b8d12d43741a6723f274290f92\$lut for cells of type $lut.
Using template $paramod$1078665aa144cf7ff525a892db61e5cee078ce7c\$lut for cells of type $lut.
Using template $paramod$9eaabafe459be125f48a5e46558dd0084a2c0d60\$lut for cells of type $lut.
Using template $paramod$ac13e0f6643fb784ba2e8a0549a3c9d0434040e6\$lut for cells of type $lut.
Using template $paramod$44c0fe996e6f3f4ba8bae2e194245aa82c30fa47\$lut for cells of type $lut.
Using template $paramod$c16f370ae7798b1bdf00bba0fa0d15e5edfce48d\$lut for cells of type $lut.
Using template $paramod$f1634144306d0b04d719faae32942eb36eb1c43c\$lut for cells of type $lut.
Using template $paramod$e01a027fedb28671a20c130493a89c7afd4e87d3\$lut for cells of type $lut.
Using template $paramod$d52cb446bc89fafcaa49f2b908e540f513a4d760\$lut for cells of type $lut.
Using template $paramod$2b08ce1d04340c1a7f05668c045c7104684c4784\$lut for cells of type $lut.
Using template $paramod$6786213342169f46cbca44284df298da11653c08\$lut for cells of type $lut.
Using template $paramod$672e798a02b8bcc43378b3bcf167b71b5747401f\$lut for cells of type $lut.
Using template $paramod$48681ef49f982ba7a640c193dcd827aee097b947\$lut for cells of type $lut.
Using template $paramod$ea79e410ad0f4fc3326666c891e1f3992816d636\$lut for cells of type $lut.
Using template $paramod$0588a56d956de2ef39b1ca190e1d8667770312f4\$lut for cells of type $lut.
Using template $paramod$9bdc414229f06e785dc8fd97a243faa9336e164a\$lut for cells of type $lut.
Using template $paramod$ffc2ea81a65101fbef8a332deddf112494d27163\$lut for cells of type $lut.
Using template $paramod$244955618a510e4a80414dbc0f64e83b0827188c\$lut for cells of type $lut.
Using template $paramod$b2e8d279775d333b39e310bd45fd5952acdde290\$lut for cells of type $lut.
Using template $paramod$55f18de0c05c50db7bd7f85e669763b2bc3543dc\$lut for cells of type $lut.
Using template $paramod$6f9324703e8fcc3b6df2bc2bec54ec19a446ae96\$lut for cells of type $lut.
Using template $paramod$9c7a967a5dd69d8b7070c7493295b0c7b420660f\$lut for cells of type $lut.
Using template $paramod$6b62468353a716e43972563d3074fa328b3ddcae\$lut for cells of type $lut.
Using template $paramod$aa117dc02d4f218ed5974b258634c3f38264f15f\$lut for cells of type $lut.
Using template $paramod$059968be1ef12c596bb5d360a749040b6777bf4a\$lut for cells of type $lut.
Using template $paramod$3f8bddb26a8905ea147acf4247acf6d000ca20f7\$lut for cells of type $lut.
Using template $paramod$5c6d01824df27a97c3776b3694e8814e23c197cd\$lut for cells of type $lut.
Using template $paramod$e134ec2a47a2462a591072e65d34fb15b81c90e0\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101111 for cells of type $lut.
Using template $paramod$f5cf7d48a1d000717a8f14a770131cc7d416cfe6\$lut for cells of type $lut.
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
Using template $paramod$58bd588a49a6a3b9d057d75f907cb4932e1635f6\$lut for cells of type $lut.
Using template $paramod$7ca4db46d3cd57dbe2541a389808e6d33af02319\$lut for cells of type $lut.
Using template $paramod$8c14e6d85060218e346675600ae1194fdf5a803e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111001 for cells of type $lut.
Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut.
Using template $paramod$5348912da867a611a8088b6b8b27a62d65f1de6e\$lut for cells of type $lut.
Using template $paramod$db08fd84fb3c4d6a41eaec6adfffe445fb7eb17f\$lut for cells of type $lut.
Using template $paramod$8829675bb8c52553aed9f101ec0d5ef0c865e5c7\$lut for cells of type $lut.
Using template $paramod$3c5eb16fa418cfbbe1710d24d17e7d0b5448c3c1\$lut for cells of type $lut.
Using template $paramod$e54349d9a634ecff5f53629ed023a0262d334efb\$lut for cells of type $lut.
Using template $paramod$8abe21ee38ced38064203ce27d377b5c4dcd9cc2\$lut for cells of type $lut.
Using template $paramod$5dc745bb48e2cf535179547ba13f0fe5364d6d54\$lut for cells of type $lut.
Using template $paramod$8c13ad014d500c3a349fa680995aa7f6f9eaaf87\$lut for cells of type $lut.
Using template $paramod$a781a45d07c31599ddba9f9ea6ab12ba1ad09a10\$lut for cells of type $lut.
Using template $paramod$e4723c78131b859cdb296cc7099a965ce6bf28d9\$lut for cells of type $lut.
Using template $paramod$ff4dd96a8adc011bb838ebb9d645764e57a15653\$lut for cells of type $lut.
Using template $paramod$01d6171b877f7655dc0d32e32900a6a207a75b44\$lut for cells of type $lut.
Using template $paramod$0d3ac82cf5b8a192d5ff4c23e3143360366ae882\$lut for cells of type $lut.
Using template $paramod$1e9d7896e1dd3d2af9633eefc9c29afb478cef41\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut.
Using template $paramod$a988852add2bdce7c1dfac786401ba7c7bc832c1\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
Using template $paramod$ab4188c7524eec831e9177bc675d62b21a3ccd8b\$lut for cells of type $lut.
Using template $paramod$9664b2f5fd61944d7798b30cde43b99ccda87303\$lut for cells of type $lut.
Using template $paramod$3c712553f2f5a448e8c696903ee0800251a0a2fe\$lut for cells of type $lut.
Using template $paramod$47b2f5a9f58cb4be072657772748a1ab82d6819a\$lut for cells of type $lut.
Using template $paramod$50222e4d0527635d5cf211ed95d1ccfc839e99e8\$lut for cells of type $lut.
Using template $paramod$7295da7c5b19f528a428229f2570e0a23ad372af\$lut for cells of type $lut.
Using template $paramod$899a7d400185b4f778bea81a50f62c95a0b19d77\$lut for cells of type $lut.
Using template $paramod$4972722c284f07fee673f7cb99e6a36ce4a244f0\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
Using template $paramod$0277567e04bf6ce483bb2bcb077e44dbc2f633d1\$lut for cells of type $lut.
Using template $paramod$f9b715fbf1040e81e900b2461c2390d17ed5e988\$lut for cells of type $lut.
Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut.
Using template $paramod$359fe4e746656bf9c72aecaff84fc7bdea9f55a5\$lut for cells of type $lut.
Using template $paramod$d35161d1d7976dcc02e7c7d51172431be85143b4\$lut for cells of type $lut.
Using template $paramod$ead66ba22839f96e739c8f1b5a09bc1717b3be02\$lut for cells of type $lut.
Using template $paramod$02b63907fb626de3e5f6572173cbabd407ece191\$lut for cells of type $lut.
No more expansions possible.
<suppressed ~6526 debug messages>

24.44. Executing OPT_LUT_INS pass (discard unused LUT inputs).
Optimizing LUTs in processorci_top.
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103551.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103557.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103597.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103598.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103585.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103630.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103632.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103610.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103638.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103645.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103676.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103680.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103660.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103692.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103537.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103581.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103592.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103670.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103618.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103624.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103626.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$19930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$19921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$19921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$18736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$18736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$16635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$16635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$103487$lut$aiger103486$16635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$16320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$16320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$103487$lut$aiger103486$16320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$16017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$16017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$15726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$103487$lut$aiger103486$15726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$103487$lut$aiger103486$15499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$103487$lut$aiger103486$15499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$15383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14787.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$14778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$14778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$103487$lut$aiger103486$14778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$13243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$13243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$12638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$12638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$12479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$12479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$12444.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$12444.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$12436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$12436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$12436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$12422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$103487$lut$aiger103486$12422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$12413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$12413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$12413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$12304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$12304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$11958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$103487$lut$aiger103486$11958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $abc$103487$lut$aiger103486$11509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$103487$lut$aiger103486$11499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11382.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11382.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11382.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11382.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11382.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11382.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11382.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$11330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$103487$lut$aiger103486$11330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$10908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$10908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$10688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$10688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$10592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$10592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 2)
  Optimizing lut $abc$103487$lut$aiger103486$9992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$9992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$9992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$10026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$10026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$10026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$10026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$10026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$9982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$9982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$9982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$10019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$10019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$10019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$10019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$10009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$10009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$10009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$9970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$9970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$9970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$9970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut2 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$9999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut3 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$9999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut4 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut5 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut6 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut7 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$10009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$10019.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$10026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$10070.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10119.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$10156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$10232.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10301.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10502.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$10535.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$10568.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$10592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$10592.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$103487$lut$aiger103486$10601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$10601.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$10608.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10615.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10622.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$10629.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10645.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10661.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$10688.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$10701.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10709.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10734.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10750.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10766.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$103487$lut$auto$fsm_map.cc:170:map_fsm$6251[1].genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$10818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$10851.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$10884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$10908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$10908.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$103487$lut$aiger103486$10917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$10917.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$10924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10931.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10938.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$10945.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10978.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11012.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11033.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11038.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$11045.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11061.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$11113.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11273.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11306.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11330.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$11339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11339.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11346.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11353.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11360.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11382.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11387.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11407.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11441.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11484.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11509.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$103487$lut$aiger103486$11520.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11593.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11710.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11726.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11761.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11777.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11784.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11794.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11817.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11868.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11901.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11934.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11958.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$11967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11967.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11974.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11981.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$11988.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$11995.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12045.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12061.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12078.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12094.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12128.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12214.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$12247.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$12280.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$12304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$12304.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$103487$lut$aiger103486$12313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$12313.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$12320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12327.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$12374.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12413.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$12422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12422.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$12436.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12444.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$103487$lut$aiger103486$12444.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12456.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12479.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$12484.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12494.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12548.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$12581.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$12614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$12638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$12638.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$103487$lut$aiger103486$12647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$12647.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$12654.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12661.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$12675.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12691.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12716.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12723.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12758.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12783.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12844.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12860.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12867.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12877.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12893.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12911.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12927.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12937.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$12973.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$13013.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13056.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$13089.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$13111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13153.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$13186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$13219.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$13243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$13243.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$103487$lut$aiger103486$13252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$13252.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$13259.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13266.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13273.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$13330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13339.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$13356.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13371.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13378.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13389.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$13396.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13412.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13488.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13531.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$13564.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$13589.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13605.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13621.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13637.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13656.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13672.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13679.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13689.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13709.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13722.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$13795.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13802.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13811.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13828.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13844.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13855.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13862.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13878.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13885.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13895.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13911.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13918.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$13964.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14007.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$14040.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$14062.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$14080.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14112.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14128.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14147.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14173.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$14180.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14196.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14203.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14249.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14292.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$14325.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$14399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14415.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14431.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14438.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14442.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14449.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14465.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14475.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14482.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14528.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$14568.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14611.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$14644.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$14666.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14688.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$14721.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$14754.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$14778.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$14787.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$14787.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$14794.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14801.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14808.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$14823.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14839.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14846.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14865.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14881.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14898.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$14939.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14943.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$14947.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15001.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15017.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15024.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15034.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15050.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15068.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15084.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15091.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15213.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15246.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15293.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15326.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15359.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$15383.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$103487$lut$aiger103486$15392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15392.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15406.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15413.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15453.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15461.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15468.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15489.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15499.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$103487$lut$aiger103486$15503.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15521.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15525.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15562.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15572.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15636.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15669.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15702.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15726.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$15735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15735.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15742.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15749.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15756.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15774.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15784.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15794.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15801.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15810.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15825.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15835.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15868.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15877.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15884.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$15900.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$15927.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$15993.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$16017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$16017.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$103487$lut$aiger103486$16026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$16026.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$16033.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16040.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16047.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$16054.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16059.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16080.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$16087.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16096.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$16111.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16129.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16147.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$16154.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16170.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16186.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16230.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$16263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$16296.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$16320.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$16329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$16329.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$16336.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16343.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$16357.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16407.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16428.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16433.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$16440.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16456.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16473.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$16545.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$16578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$16611.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$16635.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$16644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$16644.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$16651.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16658.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16665.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$16672.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16688.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16704.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16732.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16739.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16752.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16780.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16787.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16800.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16863.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16897.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16910.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16923.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$103487$lut$aiger103486$16930.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16956.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$16999.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17042.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$17075.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$17097.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17140.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17156.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17172.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17188.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17207.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17240.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17256.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17309.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17352.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$17385.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$17407.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17440.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17456.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17463.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17473.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17489.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17507.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17520.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17533.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 2)
  Optimizing lut $abc$103487$lut$aiger103486$17540.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17556.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17563.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17609.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17652.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$17685.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$17775.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17818.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$17851.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$17876.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17909.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17925.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17932.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17942.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17958.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$17965.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18005.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$18009.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$18043.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18076.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18092.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18110.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18126.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18136.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18143.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18159.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18166.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9975.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10009.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$9982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$9992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$18212.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18255.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$18288.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$18310.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$18334.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18350.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18357.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18367.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18383.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18390.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18394.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18401.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18450.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18463.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$18503.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18546.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$18579.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$18601.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18646.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$18679.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$18712.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$18736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$18736.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$103487$lut$aiger103486$18745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$18745.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$18752.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18759.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18766.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$18773.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18789.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18814.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18821.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18832.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$18847.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18862.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18872.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18888.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18901.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18924.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18940.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18947.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18990.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19006.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19025.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19041.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19093.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19136.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$19169.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$19263.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19279.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19297.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19313.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19320.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19330.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19346.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19359.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$19399.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19442.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$19475.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$19497.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19520.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19536.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19543.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19553.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19569.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19587.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19603.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19689.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19732.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$19765.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$19787.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19831.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$19864.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$19897.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$19921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$19921.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $abc$103487$lut$aiger103486$19930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$19930.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$19937.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19944.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19951.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$19966.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19973.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$19984.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$20016.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$20023.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$20039.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$20058.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$20074.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$10183.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9311.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9349.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9396.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9537.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9544.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9719.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9793.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9808.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9834.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9872.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9890.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9908.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9915.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9925.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9943.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9950.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$9960.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 1)
  Optimizing lut $abc$103487$lut$aiger103486$9999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$9970.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$9982.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$9992.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$9999.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$16804.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$103487$lut$auto$opt_dff.cc:219:make_patterns_logic$6403.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $abc$103487$lut$auto$opt_dff.cc:219:make_patterns_logic$6324.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $abc$103487$lut$aiger103486$9780.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $abc$103487$lut$aiger103486$18905.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103521.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103528.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103530.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103535.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103559.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103543.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103546.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103556.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103557.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103570.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103559.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103560.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103565.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103565.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103566.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103569.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103570.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103573.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103573.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103576.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103578.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103578.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103584.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103585.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103588.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103588.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103594.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103597.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103598.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103602.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103603.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103606.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103606.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103610.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103611.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103613.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103614.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103644.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103640.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103618.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103620.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103620.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103621.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103626.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103629.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103632.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103634.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103635.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103638.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103641.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103644.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103647.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103650.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103653.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103659.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 0)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103661.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103663.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103663.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103665.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103668.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103670.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103650.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103676.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103655.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103683.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 2)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103690.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103682.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 1)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103690.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103694.genblk1.genblk1.genblk1.genblk1.genblk1.lut1 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103694.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
  Optimizing lut $auto$abc9_ops.cc:1550:reintegrate$103697.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.lut0 (4 -> 3)
Removed 0 unused cells and 11571 unused wires.

24.45. Executing AUTONAME pass.
Renamed 127974 objects in module processorci_top (84 iterations).
<suppressed ~11183 debug messages>

24.46. Executing HIERARCHY pass (managing design hierarchy).

24.46.1. Analyzing design hierarchy..
Top module:  \processorci_top

24.46.2. Analyzing design hierarchy..
Top module:  \processorci_top
Removed 0 unused modules.

24.47. Printing statistics.

=== processorci_top ===

   Number of wires:               5333
   Number of wire bits:          17481
   Number of public wires:        5333
   Number of public wire bits:   17481
   Number of ports:                 10
   Number of port bits:             10
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               7115
     $scopeinfo                     38
     CCU2C                         142
     L6MUX21                       135
     LUT4                         4495
     PFUMX                         701
     TRELLIS_DPR16X4              1028
     TRELLIS_FF                    576

24.48. Executing CHECK pass (checking for obvious problems).
Checking module processorci_top...
Found and reported 0 problems.

24.49. Executing JSON backend.

Warnings: 105 unique messages, 105 total
End of script. Logfile hash: ac0bc3f162, CPU: user 16.87s system 0.14s, MEM: 155.68 MB peak
Yosys 0.45+139 (git sha1 4d581a97d, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3)
Time spent: 24% 1x abc9_exe (5 sec), 14% 11x techmap (3 sec), ...
/eda/oss-cad-suite/bin/nextpnr-ecp5 --json colorlight_i9.json --write colorlight_i9_pnr.json --45k \
	--lpf /eda/processor-ci/constraints/colorlight_i9.lpf --textcfg colorlight_i9.config --package CABGA381 \
	--speed 6 --lpf-allow-unconstrained --report report_timing.json \
	--detailed-timing-report  --ignore-loops
/eda/oss-cad-suite/bin/ecppack --compress --input colorlight_i9.config  --bit colorlight_i9.bit

[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash colorlight_i9)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/tinyriscv/tinyriscv
[Pipeline] {
[Pipeline] echo
FPGA colorlight_i9 bloqueada para flash.
[Pipeline] sh
+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p tinyriscv -b colorlight_i9 -l
Arquivo de configura����o final gerado em /var/lib/jenkins/workspace/tinyriscv/tinyriscv/build_colorlight_i9.tcl
Makefile executado com sucesso.
Sa��da do Makefile:
/eda/oss-cad-suite/bin/openFPGALoader -b colorlight-i9 colorlight_i9.bit
empty
Found 1 compatible device:
	0x0d28 0x0204 0x3 DAPLink CMSIS-DAP
Open file: DONE
b3bdffff
Parse file: DONE
Enable configuration: DONE
SRAM erase: DONE

Loading: [=====                                             ] 8.40%
Loading: [=========                                         ] 17.12%
Loading: [=============                                     ] 25.84%
Loading: [==================                                ] 34.56%
Loading: [======================                            ] 43.28%
Loading: [===========================                       ] 52.00%
Loading: [===============================                   ] 60.72%
Loading: [===================================               ] 69.44%
Loading: [========================================          ] 78.16%
Loading: [============================================      ] 86.56%
Loading: [================================================  ] 95.28%
Loading: [==================================================] 100.00%
Done
Disable configuration: DONE

[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Teste colorlight_i9)
[Pipeline] echo
Testando FPGA colorlight_i9.
[Pipeline] dir
Running in /var/lib/jenkins/workspace/tinyriscv/tinyriscv
[Pipeline] {
[Pipeline] sh
+ PYTHONPATH=/eda/processor-ci-communication PORT=/dev/ttyACM0 python /eda/processor-ci-communication/run_tests.py

Running tests...
----------------------------------------------------------------------
FFFFFFFFFF.FFFF
======================================================================
ERROR [0.105s]: test_addi (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_00.py", line 21, in test_addi
    self.assertEqual(int.from_bytes(retorno, "big"), 5)
AssertionError: 0 != 5

======================================================================
ERROR [0.106s]: test_andi (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_00.py", line 28, in test_andi
    self.assertEqual(int.from_bytes(retorno, "big"), 1)
AssertionError: 0 != 1

======================================================================
ERROR [0.105s]: test_jalr (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_00.py", line 112, in test_jalr
    self.assertEqual(int.from_bytes(retorno, "big"), 7)
AssertionError: 0 != 7

======================================================================
ERROR [0.106s]: test_jalr_2 (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_00.py", line 119, in test_jalr_2
    self.assertEqual(int.from_bytes(retorno, "big"), 7)
AssertionError: 0 != 7

======================================================================
ERROR [0.105s]: test_lb (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_00.py", line 105, in test_lb
    self.assertEqual(int.from_bytes(retorno, "big"), 0xFF)
AssertionError: 0 != 255

======================================================================
ERROR [0.105s]: test_lh (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_00.py", line 98, in test_lh
    self.assertEqual(int.from_bytes(retorno, "big"), 0xFFC0)
AssertionError: 0 != 65472

======================================================================
ERROR [0.105s]: test_lw (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_00.py", line 91, in test_lw
    self.assertEqual(int.from_bytes(retorno, "big"), 0x809)
AssertionError: 0 != 2057

======================================================================
ERROR [0.105s]: test_ori (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_00.py", line 35, in test_ori
    self.assertEqual(int.from_bytes(retorno, "big"), 7)
AssertionError: 0 != 7

======================================================================
ERROR [0.105s]: test_slli (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_00.py", line 70, in test_slli
    self.assertEqual(int.from_bytes(retorno, "big"), 8)
AssertionError: 0 != 8

======================================================================
ERROR [0.105s]: test_slli_2 (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_00.py", line 77, in test_slli_2
    self.assertEqual(int.from_bytes(retorno, "big"), 0x10)
AssertionError: 0 != 16

======================================================================
ERROR [0.105s]: test_slti_2 (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_00.py", line 56, in test_slti_2
    self.assertEqual(int.from_bytes(retorno, "big"), 1)
AssertionError: 0 != 1

======================================================================
ERROR [0.106s]: test_sltiu (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_00.py", line 63, in test_sltiu
    self.assertEqual(int.from_bytes(retorno, "big"), 1)
AssertionError: 0 != 1

======================================================================
ERROR [0.105s]: test_srli (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_00.py", line 84, in test_srli
    self.assertEqual(int.from_bytes(retorno, "big"), 2)
AssertionError: 0 != 2

======================================================================
ERROR [0.105s]: test_xori (test_00.TestTypeIBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_00.py", line 42, in test_xori
    self.assertEqual(int.from_bytes(retorno, "big"), 6)
AssertionError: 0 != 6

----------------------------------------------------------------------
Ran 15 tests in 1.578s

FAILED (errors=14)

Generating XML reports...

Running tests...
----------------------------------------------------------------------
FFFF..FFFF
======================================================================
ERROR [0.105s]: test_add (test_01.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_01.py", line 21, in test_add
    self.assertEqual(int.from_bytes(retorno, "big"), 10)
AssertionError: 0 != 10

======================================================================
ERROR [0.105s]: test_and (test_01.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_01.py", line 35, in test_and
    self.assertEqual(int.from_bytes(retorno, "big"), 1)
AssertionError: 0 != 1

======================================================================
ERROR [0.105s]: test_or (test_01.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_01.py", line 42, in test_or
    self.assertEqual(int.from_bytes(retorno, "big"), 7)
AssertionError: 0 != 7

======================================================================
ERROR [0.105s]: test_sll (test_01.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_01.py", line 70, in test_sll
    self.assertEqual(int.from_bytes(retorno, "big"), 8)
AssertionError: 0 != 8

======================================================================
ERROR [0.105s]: test_sra (test_01.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_01.py", line 84, in test_sra
    self.assertEqual(int.from_bytes(retorno, "big"), 2)
AssertionError: 0 != 2

======================================================================
ERROR [0.107s]: test_srl (test_01.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_01.py", line 77, in test_srl
    self.assertEqual(int.from_bytes(retorno, "big"), 2)
AssertionError: 0 != 2

======================================================================
ERROR [0.105s]: test_sub (test_01.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_01.py", line 28, in test_sub
    self.assertEqual(int.from_bytes(retorno, "big"), 10)
AssertionError: 0 != 10

======================================================================
ERROR [0.105s]: test_xor (test_01.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_01.py", line 49, in test_xor
    self.assertEqual(int.from_bytes(retorno, "big"), 6)
AssertionError: 0 != 6

----------------------------------------------------------------------
Ran 10 tests in 1.052s

FAILED (errors=8)

Generating XML reports...

Running tests...
----------------------------------------------------------------------
FFF
======================================================================
ERROR [0.106s]: test_sb (test_02.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_02.py", line 35, in test_sb
    self.assertEqual(int.from_bytes(retorno, "big"), 0xFE)
AssertionError: 0 != 254

======================================================================
ERROR [0.105s]: test_sh (test_02.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_02.py", line 28, in test_sh
    self.assertEqual(int.from_bytes(retorno, "big"), 0xFFC0)
AssertionError: 0 != 65472

======================================================================
ERROR [0.105s]: test_sw (test_02.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_02.py", line 21, in test_sw
    self.assertEqual(int.from_bytes(retorno, "big"), 0x1E)
AssertionError: 0 != 30

----------------------------------------------------------------------
Ran 3 tests in 0.315s

FAILED (errors=3)

Generating XML reports...

Running tests...
----------------------------------------------------------------------
FFFFFFFFFFFF
======================================================================
ERROR [0.106s]: test_beq (test_03.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_03.py", line 21, in test_beq
    self.assertEqual(int.from_bytes(retorno, "big"), 0x11)
AssertionError: 0 != 17

======================================================================
ERROR [0.105s]: test_beq_2 (test_03.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_03.py", line 28, in test_beq_2
    self.assertEqual(int.from_bytes(retorno, "big"), 10)
AssertionError: 0 != 10

======================================================================
ERROR [0.105s]: test_bge (test_03.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_03.py", line 63, in test_bge
    self.assertEqual(int.from_bytes(retorno, "big"), 0x11)
AssertionError: 0 != 17

======================================================================
ERROR [0.109s]: test_bge_2 (test_03.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_03.py", line 70, in test_bge_2
    self.assertEqual(int.from_bytes(retorno, "big"), 10)
AssertionError: 0 != 10

======================================================================
ERROR [0.135s]: test_bgeu (test_03.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_03.py", line 91, in test_bgeu
    self.assertEqual(int.from_bytes(retorno, "big"), 0x11)
AssertionError: 0 != 17

======================================================================
ERROR [0.120s]: test_bgeu_2 (test_03.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_03.py", line 98, in test_bgeu_2
    self.assertEqual(int.from_bytes(retorno, "big"), 10)
AssertionError: 0 != 10

======================================================================
ERROR [0.105s]: test_blt (test_03.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_03.py", line 49, in test_blt
    self.assertEqual(int.from_bytes(retorno, "big"), 0x11)
AssertionError: 0 != 17

======================================================================
ERROR [0.105s]: test_blt_2 (test_03.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_03.py", line 56, in test_blt_2
    self.assertEqual(int.from_bytes(retorno, "big"), 10)
AssertionError: 0 != 10

======================================================================
ERROR [0.105s]: test_bltu (test_03.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_03.py", line 77, in test_bltu
    self.assertEqual(int.from_bytes(retorno, "big"), 0x11)
AssertionError: 0 != 17

======================================================================
ERROR [0.105s]: test_bltu_2 (test_03.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_03.py", line 84, in test_bltu_2
    self.assertEqual(int.from_bytes(retorno, "big"), 10)
AssertionError: 0 != 10

======================================================================
ERROR [0.105s]: test_bne (test_03.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_03.py", line 35, in test_bne
    self.assertEqual(int.from_bytes(retorno, "big"), 0x11)
AssertionError: 0 != 17

======================================================================
ERROR [0.105s]: test_bne_2 (test_03.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_03.py", line 42, in test_bne_2
    self.assertEqual(int.from_bytes(retorno, "big"), 10)
AssertionError: 0 != 10

----------------------------------------------------------------------
Ran 12 tests in 1.311s

FAILED (errors=12)

Generating XML reports...

Running tests...
----------------------------------------------------------------------
FF
======================================================================
ERROR [0.105s]: test_auipc (test_04.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_04.py", line 21, in test_auipc
    self.assertEqual(int.from_bytes(retorno, "big"), 0x000DA004)
AssertionError: 0 != 892932

======================================================================
ERROR [0.106s]: test_lui (test_04.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_04.py", line 28, in test_lui
    self.assertEqual(int.from_bytes(retorno, "big"), 0x0006D000)
AssertionError: 0 != 446464

----------------------------------------------------------------------
Ran 2 tests in 0.211s

FAILED (errors=2)

Generating XML reports...

Running tests...
----------------------------------------------------------------------
FF
======================================================================
ERROR [0.106s]: test_jal (test_05.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_05.py", line 21, in test_jal
    self.assertEqual(int.from_bytes(retorno, "big"), 0xA)
AssertionError: 0 != 10

======================================================================
ERROR [0.107s]: test_jal_2 (test_05.TestTypeRBasic)
----------------------------------------------------------------------
Traceback (most recent call last):
  File "/eda/processor-ci-communication/tests/test_05.py", line 28, in test_jal_2
    self.assertEqual(int.from_bytes(retorno, "big"), 0xF)
AssertionError: 0 != 15

----------------------------------------------------------------------
Ran 2 tests in 0.213s

FAILED (errors=2)

Generating XML reports...
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: colorlight_i9]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Arquivo de configura����o final gerado em /var/lib/jenkins/workspace/tinyriscv/tinyriscv/build_digilent_nexys4_ddr.tcl
Makefile executado com sucesso.
Sa��da do Makefile:
Building the Design...
/eda/vivado/Vivado/2023.2/bin/vivado -mode batch -nolog -nojournal -source /var/lib/jenkins/workspace/tinyriscv/tinyriscv/build_digilent_nexys4_ddr.tcl -tclargs "ID=0x6a6a6a6a" "CLOCK_FREQ=50000000" "MEMORY_SIZE=4096"

****** Vivado v2023.2 (64-bit)
  **** SW Build 4029153 on Fri Oct 13 20:13:54 MDT 2023
  **** IP Build 4028589 on Sat Oct 14 00:45:43 MDT 2023
  **** SharedData Build 4025554 on Tue Oct 10 17:18:54 MDT 2023
    ** Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
    ** Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.

source /var/lib/jenkins/workspace/tinyriscv/tinyriscv/build_digilent_nexys4_ddr.tcl
# read_verilog /eda/processor-ci/rtl/tinyriscv.v
read_verilog: Time (s): cpu = 00:00:15 ; elapsed = 00:00:17 . Memory (MB): peak = 1274.766 ; gain = 25.836 ; free physical = 1902 ; free virtual = 26586
# read_verilog /var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v
# read_verilog /var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v
# read_verilog /var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v
# read_verilog /var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/div.v
# read_verilog /var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v
# read_verilog /var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v
# read_verilog /var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id_ex.v
# read_verilog /var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/if_id.v
# read_verilog /var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v
# read_verilog /var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v
# read_verilog /var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/rib.v
# read_verilog /var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/tinyriscv.v
# read_verilog /var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v
# set ID 0x6a6a6a6a
# set CLOCK_FREQ 50000000
# read_verilog /eda/processor-ci-controller/modules/uart.v
# read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_rx.v
# read_verilog /eda/processor-ci-controller/modules/UART/rtl/uart_tx.v
# read_verilog /eda/processor-ci-controller/src/fifo.v
# read_verilog /eda/processor-ci-controller/src/reset.v
# read_verilog /eda/processor-ci-controller/src/clk_divider.v
# read_verilog /eda/processor-ci-controller/src/memory.v
# read_verilog /eda/processor-ci-controller/src/interpreter.v
# read_verilog /eda/processor-ci-controller/src/controller.v
# set ID [lindex $argv 0]
# set CLOCK_FREQ [lindex $argv 1]
# set MEMORY_SIZE [lindex $argv 2]
# read_xdc "/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc"
# set_property PROCESSING_ORDER EARLY [get_files /eda/processor-ci/constraints/digilent_nexys4_ddr.xdc]
# synth_design -top "processorci_top" -part "xc7a100tcsg324-1" -verilog_define $ID -verilog_define $CLOCK_FREQ -verilog_define $MEMORY_SIZE
Command: synth_design -top processorci_top -part xc7a100tcsg324-1 -verilog_define ID=0x6a6a6a6a -verilog_define CLOCK_FREQ=50000000 -verilog_define MEMORY_SIZE=4096
Starting synth_design
Attempting to get a license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7a100t'
INFO: [Device 21-403] Loading part xc7a100tcsg324-1
INFO: [Synth 8-7079] Multithreading enabled for synth_design using a maximum of 4 processes.
INFO: [Synth 8-7078] Launching helper process for spawning children vivado processes
INFO: [Synth 8-7075] Helper process launched with PID 2442770
---------------------------------------------------------------------------------
Starting RTL Elaboration : Time (s): cpu = 00:00:11 ; elapsed = 00:00:16 . Memory (MB): peak = 2028.457 ; gain = 404.715 ; free physical = 769 ; free virtual = 25452
---------------------------------------------------------------------------------
INFO: [Synth 8-11241] undeclared symbol 'reset_o', assumed default net type 'wire' [/eda/processor-ci/rtl/tinyriscv.v:68]
WARNING: [Synth 8-8895] 'reset_o' is already implicitly declared on line 68 [/eda/processor-ci/rtl/tinyriscv.v:164]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:16]
WARNING: [Synth 8-6901] identifier 'PAYLOAD_BITS' is used before its declaration [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:16]
WARNING: [Synth 8-11065] parameter 'INIT' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:15]
WARNING: [Synth 8-11065] parameter 'RESET_COUNTER' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:16]
WARNING: [Synth 8-11065] parameter 'IDLE' becomes localparam in 'ResetBootSystem' with formal parameter declaration list [/eda/processor-ci-controller/src/reset.v:17]
WARNING: [Synth 8-6901] identifier 'bus_mode' is used before its declaration [/eda/processor-ci-controller/src/controller.v:84]
WARNING: [Synth 8-6901] identifier 'memory_page_number' is used before its declaration [/eda/processor-ci-controller/src/controller.v:85]
INFO: [Synth 8-6157] synthesizing module 'processorci_top' [/eda/processor-ci/rtl/tinyriscv.v:1]
INFO: [Synth 8-6157] synthesizing module 'Controller' [/eda/processor-ci-controller/src/controller.v:1]
	Parameter CLK_FREQ bound to: 50000000 - type: integer 
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
	Parameter BUFFER_SIZE bound to: 8 - type: integer 
	Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer 
	Parameter BUS_WIDTH bound to: 32 - type: integer 
	Parameter WORD_SIZE_BY bound to: 4 - type: integer 
	Parameter ID bound to: 0 - type: integer 
	Parameter RESET_CLK_CYCLES bound to: 20 - type: integer 
	Parameter MEMORY_FILE bound to: (null) - type: string 
	Parameter MEMORY_SIZE bound to: 4096 - type: integer 
INFO: [Synth 8-6157] synthesizing module 'ClkDivider' [/eda/processor-ci-controller/src/clk_divider.v:1]
	Parameter COUNTER_BITS bound to: 32 - type: integer 
	Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'ClkDivider' (0#1) [/eda/processor-ci-controller/src/clk_divider.v:1]
INFO: [Synth 8-6157] synthesizing module 'Interpreter' [/eda/processor-ci-controller/src/interpreter.v:1]
	Parameter CLK_FREQ bound to: 50000000 - type: integer 
	Parameter PULSE_CONTROL_BITS bound to: 32 - type: integer 
	Parameter BUS_WIDTH bound to: 32 - type: integer 
	Parameter ID bound to: 0 - type: integer 
	Parameter RESET_CLK_CYCLES bound to: 20 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'Interpreter' (0#1) [/eda/processor-ci-controller/src/interpreter.v:1]
INFO: [Synth 8-6157] synthesizing module 'UART' [/eda/processor-ci-controller/modules/uart.v:1]
	Parameter CLK_FREQ bound to: 50000000 - type: integer 
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
	Parameter BUFFER_SIZE bound to: 8 - type: integer 
	Parameter WORD_SIZE_BY bound to: 4 - type: integer 
INFO: [Synth 8-226] default block is never used [/eda/processor-ci-controller/modules/uart.v:213]
INFO: [Synth 8-6157] synthesizing module 'FIFO' [/eda/processor-ci-controller/src/fifo.v:1]
	Parameter DEPTH bound to: 8 - type: integer 
	Parameter WIDTH bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'FIFO' (0#1) [/eda/processor-ci-controller/src/fifo.v:1]
INFO: [Synth 8-6157] synthesizing module 'uart_rx' [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9]
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter CLK_HZ bound to: 50000000 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'uart_rx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_rx.v:9]
INFO: [Synth 8-6157] synthesizing module 'uart_tx' [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10]
	Parameter BIT_RATE bound to: 115200 - type: integer 
	Parameter CLK_HZ bound to: 50000000 - type: integer 
	Parameter PAYLOAD_BITS bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'uart_tx' (0#1) [/eda/processor-ci-controller/modules/UART/rtl/uart_tx.v:10]
INFO: [Synth 8-6155] done synthesizing module 'UART' (0#1) [/eda/processor-ci-controller/modules/uart.v:1]
INFO: [Synth 8-6157] synthesizing module 'Memory' [/eda/processor-ci-controller/src/memory.v:1]
	Parameter MEMORY_FILE bound to: (null) - type: string 
	Parameter MEMORY_SIZE bound to: 4096 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'Memory' (0#1) [/eda/processor-ci-controller/src/memory.v:1]
WARNING: [Synth 8-7071] port 'read_sync' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268]
WARNING: [Synth 8-7071] port 'sync_write_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268]
WARNING: [Synth 8-7071] port 'sync_read_response' of module 'Memory' is unconnected for instance 'Data_Memory' [/eda/processor-ci-controller/src/controller.v:268]
WARNING: [Synth 8-7023] instance 'Data_Memory' of module 'Memory' has 11 connections declared, but only 8 given [/eda/processor-ci-controller/src/controller.v:268]
INFO: [Synth 8-6155] done synthesizing module 'Controller' (0#1) [/eda/processor-ci-controller/src/controller.v:1]
INFO: [Synth 8-6157] synthesizing module 'tinyriscv' [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/tinyriscv.v:20]
INFO: [Synth 8-6157] synthesizing module 'pc_reg' [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:20]
INFO: [Synth 8-6155] done synthesizing module 'pc_reg' (0#1) [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/pc_reg.v:20]
INFO: [Synth 8-6157] synthesizing module 'ctrl' [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v:21]
INFO: [Synth 8-6155] done synthesizing module 'ctrl' (0#1) [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ctrl.v:21]
INFO: [Synth 8-6157] synthesizing module 'regs' [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:20]
INFO: [Synth 8-6155] done synthesizing module 'regs' (0#1) [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/regs.v:20]
INFO: [Synth 8-6157] synthesizing module 'csr_reg' [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:20]
INFO: [Synth 8-6155] done synthesizing module 'csr_reg' (0#1) [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/csr_reg.v:20]
INFO: [Synth 8-6157] synthesizing module 'if_id' [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/if_id.v:20]
INFO: [Synth 8-6157] synthesizing module 'gen_pipe_dff' [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:18]
	Parameter DW bound to: 32 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'gen_pipe_dff' (0#1) [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:18]
INFO: [Synth 8-6157] synthesizing module 'gen_pipe_dff__parameterized0' [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:18]
	Parameter DW bound to: 8 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'gen_pipe_dff__parameterized0' (0#1) [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:18]
INFO: [Synth 8-6155] done synthesizing module 'if_id' (0#1) [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/if_id.v:20]
INFO: [Synth 8-6157] synthesizing module 'id' [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v:21]
INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v:87]
INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v:106]
INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v:123]
INFO: [Synth 8-6155] done synthesizing module 'id' (0#1) [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id.v:21]
INFO: [Synth 8-6157] synthesizing module 'id_ex' [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id_ex.v:20]
INFO: [Synth 8-6157] synthesizing module 'gen_pipe_dff__parameterized1' [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:18]
	Parameter DW bound to: 1 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'gen_pipe_dff__parameterized1' (0#1) [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:18]
INFO: [Synth 8-6157] synthesizing module 'gen_pipe_dff__parameterized2' [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:18]
	Parameter DW bound to: 5 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'gen_pipe_dff__parameterized2' (0#1) [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/utils/gen_dff.v:18]
INFO: [Synth 8-6155] done synthesizing module 'id_ex' (0#1) [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/id_ex.v:20]
INFO: [Synth 8-6157] synthesizing module 'ex' [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:21]
INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:256]
INFO: [Synth 8-226] default block is never used [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:355]
INFO: [Synth 8-6155] done synthesizing module 'ex' (0#1) [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/ex.v:21]
INFO: [Synth 8-6157] synthesizing module 'div' [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/div.v:22]
INFO: [Synth 8-155] case statement is not full and has no default [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/div.v:87]
INFO: [Synth 8-6155] done synthesizing module 'div' (0#1) [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/div.v:22]
INFO: [Synth 8-6157] synthesizing module 'clint' [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:22]
INFO: [Synth 8-6155] done synthesizing module 'clint' (0#1) [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:22]
INFO: [Synth 8-6155] done synthesizing module 'tinyriscv' (0#1) [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/tinyriscv.v:20]
WARNING: [Synth 8-689] width (1) of port connection 'jtag_reg_data_o' does not match port width (32) of module 'tinyriscv' [/eda/processor-ci/rtl/tinyriscv.v:120]
INFO: [Synth 8-6157] synthesizing module 'ResetBootSystem' [/eda/processor-ci-controller/src/reset.v:1]
	Parameter CYCLES bound to: 20 - type: integer 
INFO: [Synth 8-6155] done synthesizing module 'ResetBootSystem' (0#1) [/eda/processor-ci-controller/src/reset.v:1]
WARNING: [Synth 8-7071] port 'start' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor-ci/rtl/tinyriscv.v:168]
WARNING: [Synth 8-7071] port 'resetn_o' of module 'ResetBootSystem' is unconnected for instance 'ResetBootSystem' [/eda/processor-ci/rtl/tinyriscv.v:168]
WARNING: [Synth 8-7023] instance 'ResetBootSystem' of module 'ResetBootSystem' has 4 connections declared, but only 2 given [/eda/processor-ci/rtl/tinyriscv.v:168]
INFO: [Synth 8-6155] done synthesizing module 'processorci_top' (0#1) [/eda/processor-ci/rtl/tinyriscv.v:1]
WARNING: [Synth 8-3848] Net intr in module/entity Controller does not have driver. [/eda/processor-ci-controller/src/controller.v:25]
WARNING: [Synth 8-3848] Net raddr_o in module/entity clint does not have driver. [/var/lib/jenkins/workspace/tinyriscv/tinyriscv/rtl/core/clint.v:56]
WARNING: [Synth 8-3848] Net miso in module/entity processorci_top does not have driver. [/eda/processor-ci/rtl/tinyriscv.v:21]
WARNING: [Synth 8-3848] Net address in module/entity processorci_top does not have driver. [/eda/processor-ci/rtl/tinyriscv.v:32]
WARNING: [Synth 8-3848] Net memory_read in module/entity processorci_top does not have driver. [/eda/processor-ci/rtl/tinyriscv.v:30]
WARNING: [Synth 8-3848] Net memory_write in module/entity processorci_top does not have driver. [/eda/processor-ci/rtl/tinyriscv.v:30]
WARNING: [Synth 8-3848] Net data_address in module/entity processorci_top does not have driver. [/eda/processor-ci/rtl/tinyriscv.v:33]
WARNING: [Synth 8-3848] Net data_write in module/entity processorci_top does not have driver. [/eda/processor-ci/rtl/tinyriscv.v:33]
WARNING: [Synth 8-3848] Net m0_data_o in module/entity processorci_top does not have driver. [/eda/processor-ci/rtl/tinyriscv.v:36]
WARNING: [Synth 8-3848] Net m1_data_o in module/entity processorci_top does not have driver. [/eda/processor-ci/rtl/tinyriscv.v:38]
WARNING: [Synth 8-3848] Net rib_hold_flag_o in module/entity processorci_top does not have driver. [/eda/processor-ci/rtl/tinyriscv.v:39]
WARNING: [Synth 8-7129] Port raddr_o[31] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[30] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[29] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[28] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[27] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[26] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[25] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[24] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[23] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[22] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[21] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[20] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[19] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[18] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[17] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[16] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[15] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[14] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[13] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[12] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[11] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[10] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[9] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[8] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[7] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[6] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[5] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[4] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[3] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[2] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[1] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port raddr_o[0] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port hold_flag_i[2] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port hold_flag_i[1] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port hold_flag_i[0] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[31] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[30] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[29] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[28] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[27] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[26] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[25] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[24] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[23] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[22] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[21] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[20] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[19] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[18] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[17] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[16] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[15] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[14] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[13] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[12] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[11] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[10] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[9] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[8] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[7] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[6] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[5] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[4] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[3] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[2] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[1] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port data_i[0] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port csr_mstatus[3] in module clint is either unconnected or has no load
WARNING: [Synth 8-7129] Port rst in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_i[11] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_i[10] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_i[9] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[31] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[30] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[29] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[28] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[27] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[26] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[25] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[24] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[23] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[22] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[21] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[20] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[19] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[18] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[17] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[16] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[15] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[14] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[13] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[12] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[11] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[10] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[9] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[8] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[7] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[6] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[5] in module ex is either unconnected or has no load
WARNING: [Synth 8-7129] Port inst_addr_i[4] in module ex is either unconnected or has no load
INFO: [Common 17-14] Message 'Synth 8-7129' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 2126.395 ; gain = 502.652 ; free physical = 842 ; free virtual = 25616
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 2144.207 ; gain = 520.465 ; free physical = 841 ; free virtual = 25616
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:16 ; elapsed = 00:00:22 . Memory (MB): peak = 2144.207 ; gain = 520.465 ; free physical = 841 ; free virtual = 25616
---------------------------------------------------------------------------------
Netlist sorting complete. Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2144.207 ; gain = 0.000 ; free physical = 827 ; free virtual = 25609
INFO: [Project 1-570] Preparing netlist for logic optimization

Processing XDC Constraints
Initializing timing engine
Parsing XDC File [/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc]
INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/processorci_top_propImpl.xdc].
Resolution: To avoid this warning, move constraints listed in [.Xil/processorci_top_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis.
Completed Processing XDC Constraints

Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2287.957 ; gain = 0.000 ; free physical = 747 ; free virtual = 25559
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

Constraint Validation Runtime : Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2287.992 ; gain = 0.000 ; free physical = 745 ; free virtual = 25559
---------------------------------------------------------------------------------
Finished Constraint Validation : Time (s): cpu = 00:00:35 ; elapsed = 00:00:43 . Memory (MB): peak = 2287.992 ; gain = 664.250 ; free physical = 576 ; free virtual = 25492
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Loading Part and Timing Information
---------------------------------------------------------------------------------
Loading part: xc7a100tcsg324-1
---------------------------------------------------------------------------------
Finished Loading Part and Timing Information : Time (s): cpu = 00:00:35 ; elapsed = 00:00:43 . Memory (MB): peak = 2287.992 ; gain = 664.250 ; free physical = 573 ; free virtual = 25489
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying 'set_property' XDC Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:35 ; elapsed = 00:00:43 . Memory (MB): peak = 2287.992 ; gain = 664.250 ; free physical = 570 ; free virtual = 25486
---------------------------------------------------------------------------------
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_rx'
INFO: [Synth 8-802] inferred FSM for state register 'fsm_state_reg' in module 'uart_tx'
INFO: [Synth 8-802] inferred FSM for state register 'state_read_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'state_write_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'tx_fifo_read_state_reg' in module 'UART'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'div'
INFO: [Synth 8-802] inferred FSM for state register 'csr_state_reg' in module 'clint'
INFO: [Synth 8-802] inferred FSM for state register 'state_reg' in module 'ResetBootSystem'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                FSM_IDLE |                               00 |                              000
               FSM_START |                               11 |                              001
                FSM_RECV |                               10 |                              010
                FSM_STOP |                               01 |                              011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_rx'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                FSM_IDLE |                               00 |                              000
               FSM_START |                               11 |                              001
                FSM_SEND |                               10 |                              010
                FSM_STOP |                               01 |                              011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'fsm_state_reg' using encoding 'sequential' in module 'uart_tx'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                              000 |                             0000
                    READ |                              001 |                             0001
        COPY_READ_BUFFER |                              010 |                             0100
                      WB |                              011 |                             0010
                  FINISH |                              100 |                             0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_read_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                    IDLE |                              000 |                             0000
       COPY_WRITE_BUFFER |                              001 |                             0100
                   WRITE |                              010 |                             0001
                      WB |                              011 |                             0010
                  FINISH |                              100 |                             0011
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_write_reg' using encoding 'sequential' in module 'UART'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
                  iSTATE |                             0001 |                               00
                 iSTATE0 |                             0010 |                               01
                 iSTATE1 |                             0100 |                               10
                 iSTATE2 |                             1000 |                               11
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'tx_fifo_read_state_reg' using encoding 'one-hot' in module 'UART'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
*
              STATE_IDLE |                             0001 |                             0001
             STATE_START |                             0010 |                             0010
              STATE_CALC |                             0100 |                             0100
               STATE_END |                             1000 |                             1000
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3898] No Re-encoding of one hot register 'state_reg' in module 'div'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
*
              S_CSR_IDLE |                            00001 |                            00001
              S_CSR_MEPC |                            00100 |                            00100
           S_CSR_MSTATUS |                            00010 |                            00010
            S_CSR_MCAUSE |                            10000 |                            10000
      S_CSR_MSTATUS_MRET |                            01000 |                            01000
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3898] No Re-encoding of one hot register 'csr_state_reg' in module 'clint'
---------------------------------------------------------------------------------------------------
                   State |                     New Encoding |                Previous Encoding 
---------------------------------------------------------------------------------------------------
           RESET_COUNTER |                               00 |                               01
                    IDLE |                               01 |                               10
                    INIT |                               10 |                               00
---------------------------------------------------------------------------------------------------
INFO: [Synth 8-3354] encoded FSM with state register 'state_reg' using encoding 'sequential' in module 'ResetBootSystem'
---------------------------------------------------------------------------------
Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:41 ; elapsed = 00:00:51 . Memory (MB): peak = 2287.992 ; gain = 664.250 ; free physical = 641 ; free virtual = 25568
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start RTL Component Statistics 
---------------------------------------------------------------------------------
Detailed RTL Component Info : 
+---Adders : 
	   2 Input   64 Bit       Adders := 3     
	   2 Input   32 Bit       Adders := 17    
	   3 Input   32 Bit       Adders := 2     
	   2 Input   24 Bit       Adders := 2     
	   2 Input   10 Bit       Adders := 2     
	   2 Input    8 Bit       Adders := 1     
	   2 Input    6 Bit       Adders := 4     
	   2 Input    5 Bit       Adders := 1     
	   2 Input    4 Bit       Adders := 2     
	   2 Input    3 Bit       Adders := 2     
	   2 Input    2 Bit       Adders := 2     
+---XORs : 
	   2 Input     32 Bit         XORs := 1     
	   2 Input      1 Bit         XORs := 1     
+---Registers : 
	               64 Bit    Registers := 2     
	               32 Bit    Registers := 44    
	               24 Bit    Registers := 5     
	               10 Bit    Registers := 2     
	                8 Bit    Registers := 12    
	                6 Bit    Registers := 1     
	                5 Bit    Registers := 2     
	                4 Bit    Registers := 2     
	                3 Bit    Registers := 3     
	                1 Bit    Registers := 35    
+---RAMs : 
	              32K Bit	(1024 X 32 bit)          RAMs := 2     
	               64 Bit	(8 X 8 bit)          RAMs := 2     
+---Muxes : 
	   4 Input   64 Bit        Muxes := 1     
	   2 Input   64 Bit        Muxes := 1     
	  48 Input   64 Bit        Muxes := 2     
	   2 Input   32 Bit        Muxes := 90    
	   5 Input   32 Bit        Muxes := 9     
	   9 Input   32 Bit        Muxes := 2     
	   8 Input   32 Bit        Muxes := 2     
	  13 Input   32 Bit        Muxes := 1     
	   6 Input   32 Bit        Muxes := 3     
	   4 Input   32 Bit        Muxes := 8     
	  11 Input   32 Bit        Muxes := 5     
	   7 Input   32 Bit        Muxes := 1     
	   3 Input   32 Bit        Muxes := 1     
	   2 Input   31 Bit        Muxes := 1     
	  48 Input   24 Bit        Muxes := 1     
	   2 Input   16 Bit        Muxes := 1     
	  13 Input   12 Bit        Muxes := 1     
	   5 Input   10 Bit        Muxes := 1     
	  48 Input    8 Bit        Muxes := 2     
	   2 Input    8 Bit        Muxes := 5     
	   4 Input    8 Bit        Muxes := 1     
	  24 Input    7 Bit        Muxes := 1     
	   2 Input    7 Bit        Muxes := 2     
	   2 Input    6 Bit        Muxes := 4     
	   3 Input    6 Bit        Muxes := 1     
	   2 Input    5 Bit        Muxes := 22    
	   3 Input    5 Bit        Muxes := 2     
	  13 Input    5 Bit        Muxes := 1     
	   6 Input    5 Bit        Muxes := 1     
	   2 Input    4 Bit        Muxes := 7     
	   9 Input    4 Bit        Muxes := 2     
	   5 Input    4 Bit        Muxes := 1     
	   4 Input    4 Bit        Muxes := 1     
	   3 Input    4 Bit        Muxes := 2     
	   5 Input    3 Bit        Muxes := 4     
	   2 Input    3 Bit        Muxes := 8     
	  13 Input    3 Bit        Muxes := 3     
	  11 Input    3 Bit        Muxes := 1     
	   2 Input    2 Bit        Muxes := 19    
	  48 Input    2 Bit        Muxes := 1     
	   4 Input    2 Bit        Muxes := 4     
	   3 Input    2 Bit        Muxes := 2     
	   2 Input    1 Bit        Muxes := 78    
	  48 Input    1 Bit        Muxes := 22    
	   3 Input    1 Bit        Muxes := 8     
	   4 Input    1 Bit        Muxes := 5     
	   5 Input    1 Bit        Muxes := 25    
	   7 Input    1 Bit        Muxes := 6     
	   8 Input    1 Bit        Muxes := 6     
	  13 Input    1 Bit        Muxes := 2     
	  11 Input    1 Bit        Muxes := 3     
	   6 Input    1 Bit        Muxes := 3     
---------------------------------------------------------------------------------
Finished RTL Component Statistics 
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 240 (col length:80)
BRAMs: 270 (col length: RAMB18 80 RAMB36 40)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Cross Boundary and Area Optimization
---------------------------------------------------------------------------------
WARNING: [Synth 8-7080] Parallel synthesis criteria is not met
DSP Report: Generating DSP mul_temp, operation Mode is: A*B.
DSP Report: operator mul_temp is absorbed into DSP mul_temp.
DSP Report: operator mul_temp is absorbed into DSP mul_temp.
DSP Report: Generating DSP mul_temp, operation Mode is: (PCIN>>17)+A*B.
DSP Report: operator mul_temp is absorbed into DSP mul_temp.
DSP Report: operator mul_temp is absorbed into DSP mul_temp.
DSP Report: Generating DSP mul_temp, operation Mode is: A*B.
DSP Report: operator mul_temp is absorbed into DSP mul_temp.
DSP Report: operator mul_temp is absorbed into DSP mul_temp.
DSP Report: Generating DSP mul_temp, operation Mode is: (PCIN>>17)+A*B.
DSP Report: operator mul_temp is absorbed into DSP mul_temp.
DSP Report: operator mul_temp is absorbed into DSP mul_temp.
---------------------------------------------------------------------------------
Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:57 ; elapsed = 00:01:08 . Memory (MB): peak = 2287.992 ; gain = 664.250 ; free physical = 564 ; free virtual = 25567
---------------------------------------------------------------------------------
 Sort Area is  mul_temp_0 : 0 0 : 2701 5044 : Used 1 time 0
 Sort Area is  mul_temp_0 : 0 1 : 2343 5044 : Used 1 time 0
 Sort Area is  mul_temp_3 : 0 0 : 2339 4365 : Used 1 time 0
 Sort Area is  mul_temp_3 : 0 1 : 2026 4365 : Used 1 time 0
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

ROM: Preliminary Mapping Report
+------------+---------------------+---------------+----------------+
|Module Name | RTL Object          | Depth x Width | Implemented As | 
+------------+---------------------+---------------+----------------+
|Interpreter | memory_mux_selector | 256x1         | LUT            | 
|Interpreter | memory_mux_selector | 256x1         | LUT            | 
+------------+---------------------+---------------+----------------+


Distributed RAM: Preliminary Mapping Report (see note below)
+------------+-------------------------+-----------+----------------------+------------------+
|Module Name | RTL Object              | Inference | Size (Depth x Width) | Primitives       | 
+------------+-------------------------+-----------+----------------------+------------------+
|Controller  | Uart/TX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2       | 
|Controller  | Uart/RX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2       | 
|Controller  | Memory/memory_reg       | Implied   | 1 K x 32             | RAM256X1S x 128  | 
|Controller  | Data_Memory/memory_reg  | Implied   | 1 K x 32             | RAM256X1S x 128  | 
+------------+-------------------------+-----------+----------------------+------------------+

Note: The table above is a preliminary report that shows the Distributed RAMs at the current stage of the synthesis flow. Some Distributed RAMs may be reimplemented as non Distributed RAM primitives later in the synthesis flow. Multiple instantiated RAMs are reported only once.

DSP: Preliminary Mapping Report (see note below. The ' indicates corresponding REG is set)
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|Module Name | DSP Mapping    | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG | 
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+
|ex          | A*B            | 18     | 16     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|ex          | (PCIN>>17)+A*B | 16     | 16     | -      | -      | 30     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|ex          | A*B            | 18     | 18     | -      | -      | 48     | 0    | 0    | -    | -    | -     | 0    | 0    | 
|ex          | (PCIN>>17)+A*B | 18     | 16     | -      | -      | 47     | 0    | 0    | -    | -    | -     | 0    | 0    | 
+------------+----------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+

Note: The table above is a preliminary report that shows the DSPs inferred at the current stage of the synthesis flow. Some DSP may be reimplemented as non DSP primitives later in the synthesis flow. Multiple instantiated DSPs are reported only once.
---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Applying XDC Timing Constraints
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Applying XDC Timing Constraints : Time (s): cpu = 00:01:08 ; elapsed = 00:01:18 . Memory (MB): peak = 2287.992 ; gain = 664.250 ; free physical = 625 ; free virtual = 25566
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Timing Optimization
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Timing Optimization : Time (s): cpu = 00:01:16 ; elapsed = 00:01:26 . Memory (MB): peak = 2287.992 ; gain = 664.250 ; free physical = 1010 ; free virtual = 25990
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------

Distributed RAM: Final Mapping Report
+------------+-------------------------+-----------+----------------------+------------------+
|Module Name | RTL Object              | Inference | Size (Depth x Width) | Primitives       | 
+------------+-------------------------+-----------+----------------------+------------------+
|Controller  | Uart/TX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2       | 
|Controller  | Uart/RX_FIFO/memory_reg | Implied   | 8 x 8                | RAM32M x 2       | 
|Controller  | Memory/memory_reg       | Implied   | 1 K x 32             | RAM256X1S x 128  | 
|Controller  | Data_Memory/memory_reg  | Implied   | 1 K x 32             | RAM256X1S x 128  | 
+------------+-------------------------+-----------+----------------------+------------------+

---------------------------------------------------------------------------------
Finished ROM, RAM, DSP, Shift Register and Retiming Reporting
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Technology Mapping
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Technology Mapping : Time (s): cpu = 00:01:18 ; elapsed = 00:01:28 . Memory (MB): peak = 2287.992 ; gain = 664.250 ; free physical = 1008 ; free virtual = 25988
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Flattening Before IO Insertion
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Final Netlist Cleanup
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished IO Insertion : Time (s): cpu = 00:01:26 ; elapsed = 00:01:37 . Memory (MB): peak = 2287.992 ; gain = 664.250 ; free physical = 1007 ; free virtual = 25988
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Instances
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Instances : Time (s): cpu = 00:01:26 ; elapsed = 00:01:37 . Memory (MB): peak = 2287.992 ; gain = 664.250 ; free physical = 1006 ; free virtual = 25987
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Rebuilding User Hierarchy
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Rebuilding User Hierarchy : Time (s): cpu = 00:01:27 ; elapsed = 00:01:38 . Memory (MB): peak = 2287.992 ; gain = 664.250 ; free physical = 1009 ; free virtual = 25990
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Ports
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Ports : Time (s): cpu = 00:01:27 ; elapsed = 00:01:38 . Memory (MB): peak = 2287.992 ; gain = 664.250 ; free physical = 1009 ; free virtual = 25990
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Handling Custom Attributes
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Handling Custom Attributes : Time (s): cpu = 00:01:27 ; elapsed = 00:01:38 . Memory (MB): peak = 2287.992 ; gain = 664.250 ; free physical = 1009 ; free virtual = 25990
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Renaming Generated Nets
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Finished Renaming Generated Nets : Time (s): cpu = 00:01:27 ; elapsed = 00:01:38 . Memory (MB): peak = 2287.992 ; gain = 664.250 ; free physical = 1009 ; free virtual = 25990
---------------------------------------------------------------------------------
---------------------------------------------------------------------------------
Start Writing Synthesis Report
---------------------------------------------------------------------------------

Report BlackBoxes: 
+-+--------------+----------+
| |BlackBox name |Instances |
+-+--------------+----------+
+-+--------------+----------+

Report Cell Usage: 
+------+----------+------+
|      |Cell      |Count |
+------+----------+------+
|1     |BUFG      |     1|
|2     |CARRY4    |    65|
|3     |LUT1      |    34|
|4     |LUT2      |   191|
|5     |LUT3      |   232|
|6     |LUT4      |    93|
|7     |LUT5      |   110|
|8     |LUT6      |   274|
|9     |MUXF7     |     2|
|10    |RAM256X1S |   256|
|11    |RAM32M    |     2|
|12    |RAM32X1D  |     4|
|13    |FDRE      |   606|
|14    |FDSE      |     5|
|15    |IBUF      |     2|
|16    |OBUF      |     1|
|17    |OBUFT     |     2|
+------+----------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:01:27 ; elapsed = 00:01:38 . Memory (MB): peak = 2287.992 ; gain = 664.250 ; free physical = 1009 ; free virtual = 25990
---------------------------------------------------------------------------------
Synthesis finished with 0 errors, 0 critical warnings and 219 warnings.
Synthesis Optimization Runtime : Time (s): cpu = 00:01:21 ; elapsed = 00:01:32 . Memory (MB): peak = 2287.992 ; gain = 520.465 ; free physical = 1008 ; free virtual = 25989
Synthesis Optimization Complete : Time (s): cpu = 00:01:27 ; elapsed = 00:01:38 . Memory (MB): peak = 2287.992 ; gain = 664.250 ; free physical = 1008 ; free virtual = 25989
INFO: [Project 1-571] Translating synthesized netlist
Netlist sorting complete. Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2287.992 ; gain = 0.000 ; free physical = 1325 ; free virtual = 26306
INFO: [Netlist 29-17] Analyzing 329 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc]
Finished Parsing XDC File [/eda/processor-ci/constraints/digilent_nexys4_ddr.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2351.988 ; gain = 0.000 ; free physical = 1315 ; free virtual = 26296
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 262 instances were transformed.
  RAM256X1S => RAM256X1S (MUXF7(x2), MUXF8, RAMS64E(x4)): 256 instances
  RAM32M => RAM32M (RAMD32(x6), RAMS32(x2)): 2 instances
  RAM32X1D => RAM32X1D (RAMD32(x2)): 4 instances

Synth Design complete | Checksum: 915b59d3
INFO: [Common 17-83] Releasing license: Synthesis
90 Infos, 128 Warnings, 0 Critical Warnings and 0 Errors encountered.
synth_design completed successfully
synth_design: Time (s): cpu = 00:01:44 ; elapsed = 00:01:52 . Memory (MB): peak = 2352.023 ; gain = 1077.258 ; free physical = 1321 ; free virtual = 26302
INFO: [Common 17-2834] synth_design peak Physical Memory [PSS] (MB): overall = 2086.889; main = 1761.587; forked = 469.676
INFO: [Common 17-2834] synth_design peak Virtual Memory [VSS] (MB): overall = 3258.723; main = 2351.992; forked = 1002.777
# opt_design
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2416.020 ; gain = 63.996 ; free physical = 1321 ; free virtual = 26302

Starting Cache Timing Information Task
INFO: [Timing 38-35] Done setting XDC timing constraints.
Ending Cache Timing Information Task | Checksum: 1e7fb49da

Time (s): cpu = 00:00:05 ; elapsed = 00:00:05 . Memory (MB): peak = 2520.832 ; gain = 104.812 ; free physical = 1272 ; free virtual = 26253

Starting Logic Optimization Task

Phase 1 Initialization

Phase 1.1 Core Generation And Design Setup
Phase 1.1 Core Generation And Design Setup | Checksum: 1e7fb49da

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2765.770 ; gain = 0.000 ; free physical = 1007 ; free virtual = 25989

Phase 1.2 Setup Constraints And Sort Netlist
Phase 1.2 Setup Constraints And Sort Netlist | Checksum: 1e7fb49da

Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2765.770 ; gain = 0.000 ; free physical = 1006 ; free virtual = 25988
Phase 1 Initialization | Checksum: 1e7fb49da

Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2765.770 ; gain = 0.000 ; free physical = 1006 ; free virtual = 25988

Phase 2 Timer Update And Timing Data Collection

Phase 2.1 Timer Update
Phase 2.1 Timer Update | Checksum: 1e7fb49da

Time (s): cpu = 00:00:00.55 ; elapsed = 00:00:00.25 . Memory (MB): peak = 2765.770 ; gain = 0.000 ; free physical = 1000 ; free virtual = 25981

Phase 2.2 Timing Data Collection
Phase 2.2 Timing Data Collection | Checksum: 1e7fb49da

Time (s): cpu = 00:00:00.56 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2765.770 ; gain = 0.000 ; free physical = 1003 ; free virtual = 25984
Phase 2 Timer Update And Timing Data Collection | Checksum: 1e7fb49da

Time (s): cpu = 00:00:00.57 ; elapsed = 00:00:00.26 . Memory (MB): peak = 2765.770 ; gain = 0.000 ; free physical = 1003 ; free virtual = 25984

Phase 3 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 3 Retarget | Checksum: 1e7fb49da

Time (s): cpu = 00:00:00.64 ; elapsed = 00:00:00.35 . Memory (MB): peak = 2765.770 ; gain = 0.000 ; free physical = 1003 ; free virtual = 25984
Retarget | Checksum: 1e7fb49da
INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells

Phase 4 Constant propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
Phase 4 Constant propagation | Checksum: 23d3fc9f6

Time (s): cpu = 00:00:00.69 ; elapsed = 00:00:00.4 . Memory (MB): peak = 2765.770 ; gain = 0.000 ; free physical = 1001 ; free virtual = 25983
Constant propagation | Checksum: 23d3fc9f6
INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells

Phase 5 Sweep
Phase 5 Sweep | Checksum: 1d5abd6c1

Time (s): cpu = 00:00:00.76 ; elapsed = 00:00:00.47 . Memory (MB): peak = 2765.770 ; gain = 0.000 ; free physical = 1003 ; free virtual = 25984
Sweep | Checksum: 1d5abd6c1
INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 0 cells

Phase 6 BUFG optimization
Phase 6 BUFG optimization | Checksum: 1d5abd6c1

Time (s): cpu = 00:00:00.96 ; elapsed = 00:00:00.57 . Memory (MB): peak = 2797.785 ; gain = 32.016 ; free physical = 1003 ; free virtual = 25985
BUFG optimization | Checksum: 1d5abd6c1
INFO: [Opt 31-662] Phase BUFG optimization created 0 cells of which 0 are BUFGs and removed 0 cells.

Phase 7 Shift Register Optimization
INFO: [Opt 31-1064] SRL Remap converted 0 SRLs to 0 registers and converted 0 registers of register chains to 0 SRLs
Phase 7 Shift Register Optimization | Checksum: 1d5abd6c1

Time (s): cpu = 00:00:00.97 ; elapsed = 00:00:00.58 . Memory (MB): peak = 2797.785 ; gain = 32.016 ; free physical = 1003 ; free virtual = 25985
Shift Register Optimization | Checksum: 1d5abd6c1
INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells

Phase 8 Post Processing Netlist
Phase 8 Post Processing Netlist | Checksum: 1d5abd6c1

Time (s): cpu = 00:00:00.99 ; elapsed = 00:00:00.6 . Memory (MB): peak = 2797.785 ; gain = 32.016 ; free physical = 1003 ; free virtual = 25985
Post Processing Netlist | Checksum: 1d5abd6c1
INFO: [Opt 31-389] Phase Post Processing Netlist created 0 cells and removed 0 cells

Phase 9 Finalization

Phase 9.1 Finalizing Design Cores and Updating Shapes
Phase 9.1 Finalizing Design Cores and Updating Shapes | Checksum: 14cdbd9d0

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.68 . Memory (MB): peak = 2797.785 ; gain = 32.016 ; free physical = 1003 ; free virtual = 25984

Phase 9.2 Verifying Netlist Connectivity

Starting Connectivity Check Task

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2797.785 ; gain = 0.000 ; free physical = 1002 ; free virtual = 25984
Phase 9.2 Verifying Netlist Connectivity | Checksum: 14cdbd9d0

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.69 . Memory (MB): peak = 2797.785 ; gain = 32.016 ; free physical = 1002 ; free virtual = 25983
Phase 9 Finalization | Checksum: 14cdbd9d0

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.69 . Memory (MB): peak = 2797.785 ; gain = 32.016 ; free physical = 1002 ; free virtual = 25983
Opt_design Change Summary
=========================


-------------------------------------------------------------------------------------------------------------------------
|  Phase                        |  #Cells created  |  #Cells Removed  |  #Constrained objects preventing optimizations  |
-------------------------------------------------------------------------------------------------------------------------
|  Retarget                     |               0  |               0  |                                              0  |
|  Constant propagation         |               0  |               0  |                                              0  |
|  Sweep                        |               0  |               0  |                                              0  |
|  BUFG optimization            |               0  |               0  |                                              0  |
|  Shift Register Optimization  |               0  |               0  |                                              0  |
|  Post Processing Netlist      |               0  |               0  |                                              0  |
-------------------------------------------------------------------------------------------------------------------------


Ending Logic Optimization Task | Checksum: 14cdbd9d0

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.7 . Memory (MB): peak = 2797.785 ; gain = 32.016 ; free physical = 1005 ; free virtual = 25987
INFO: [Constraints 18-11670] Building netlist checker database with flags, 0x8
Done building netlist checker database: Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2797.785 ; gain = 0.000 ; free physical = 1005 ; free virtual = 25986

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns.
Ending Power Optimization Task | Checksum: 14cdbd9d0

Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2797.785 ; gain = 0.000 ; free physical = 1005 ; free virtual = 25986

Starting Final Cleanup Task
Ending Final Cleanup Task | Checksum: 14cdbd9d0

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2797.785 ; gain = 0.000 ; free physical = 1005 ; free virtual = 25986

Starting Netlist Obfuscation Task
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2797.785 ; gain = 0.000 ; free physical = 1005 ; free virtual = 25986
Ending Netlist Obfuscation Task | Checksum: 14cdbd9d0

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2797.785 ; gain = 0.000 ; free physical = 1005 ; free virtual = 25986
INFO: [Common 17-83] Releasing license: Implementation
18 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:14 ; elapsed = 00:00:13 . Memory (MB): peak = 2797.785 ; gain = 445.762 ; free physical = 1005 ; free virtual = 25986
# place_design
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-83] Releasing license: Implementation
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 8 CPUs

Starting Placer Task

Phase 1 Placer Initialization

Phase 1.1 Placer Initialization Netlist Sorting
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2829.801 ; gain = 0.000 ; free physical = 1004 ; free virtual = 25986
Phase 1.1 Placer Initialization Netlist Sorting | Checksum: bb382781

Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2829.801 ; gain = 0.000 ; free physical = 1004 ; free virtual = 25986
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2829.801 ; gain = 0.000 ; free physical = 1004 ; free virtual = 25986

Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
INFO: [Timing 38-35] Done setting XDC timing constraints.
Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 188200509

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 2829.801 ; gain = 0.000 ; free physical = 997 ; free virtual = 25979

Phase 1.3 Build Placer Netlist Model
Phase 1.3 Build Placer Netlist Model | Checksum: 243a40509

Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 1009 ; free virtual = 25991

Phase 1.4 Constrain Clocks/Macros
Phase 1.4 Constrain Clocks/Macros | Checksum: 243a40509

Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 1009 ; free virtual = 25991
Phase 1 Placer Initialization | Checksum: 243a40509

Time (s): cpu = 00:00:07 ; elapsed = 00:00:04 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 1009 ; free virtual = 25991

Phase 2 Global Placement

Phase 2.1 Floorplanning
Phase 2.1 Floorplanning | Checksum: 2411280ee

Time (s): cpu = 00:00:08 ; elapsed = 00:00:05 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 1008 ; free virtual = 25990

Phase 2.2 Update Timing before SLR Path Opt
Phase 2.2 Update Timing before SLR Path Opt | Checksum: 1b120eb5c

Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 1010 ; free virtual = 25991

Phase 2.3 Post-Processing in Floorplanning
Phase 2.3 Post-Processing in Floorplanning | Checksum: 1b120eb5c

Time (s): cpu = 00:00:10 ; elapsed = 00:00:06 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 1010 ; free virtual = 25991

Phase 2.4 Global Placement Core

Phase 2.4.1 UpdateTiming Before Physical Synthesis
Phase 2.4.1 UpdateTiming Before Physical Synthesis | Checksum: 18cf55ff6

Time (s): cpu = 00:00:24 ; elapsed = 00:00:12 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 1017 ; free virtual = 25999

Phase 2.4.2 Physical Synthesis In Placer
INFO: [Physopt 32-1035] Found 0 LUTNM shape to break, 110 LUT instances to create LUTNM shape
INFO: [Physopt 32-1044] Break lutnm for timing: one critical 0, two critical 0, total 0, new lutff created 0
INFO: [Physopt 32-1138] End 1 Pass. Optimized 53 nets or LUTs. Breaked 0 LUT, combined 53 existing LUTs and moved 0 existing LUT
INFO: [Physopt 32-65] No nets found for high-fanout optimization.
INFO: [Physopt 32-232] Optimized 0 net. Created 0 new instance.
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
INFO: [Physopt 32-670] No setup violation found.  DSP Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  Shift Register to Pipeline Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  Shift Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  BRAM Register Optimization was not performed.
INFO: [Physopt 32-670] No setup violation found.  URAM Register Optimization was not performed.
INFO: [Physopt 32-949] No candidate nets found for dynamic/static region interface net replication
INFO: [Physopt 32-775] End 1 Pass. Optimized 0 net or cell. Created 0 new cell, deleted 0 existing cell and moved 0 existing cell
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 1014 ; free virtual = 25996

Summary of Physical Synthesis Optimizations
============================================


-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  Optimization                                     |  Added Cells  |  Removed Cells  |  Optimized Cells/Nets  |  Dont Touch  |  Iterations  |  Elapsed   |
-----------------------------------------------------------------------------------------------------------------------------------------------------------
|  LUT Combining                                    |            0  |             53  |                    53  |           0  |           1  |  00:00:01  |
|  Retime                                           |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Very High Fanout                                 |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  DSP Register                                     |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register to Pipeline                       |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Shift Register                                   |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  BRAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  URAM Register                                    |            0  |              0  |                     0  |           0  |           0  |  00:00:00  |
|  Dynamic/Static Region Interface Net Replication  |            0  |              0  |                     0  |           0  |           1  |  00:00:00  |
|  Total                                            |            0  |             53  |                    53  |           0  |           4  |  00:00:01  |
-----------------------------------------------------------------------------------------------------------------------------------------------------------


Phase 2.4.2 Physical Synthesis In Placer | Checksum: 1bd08795f

Time (s): cpu = 00:00:27 ; elapsed = 00:00:15 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 1012 ; free virtual = 25994
Phase 2.4 Global Placement Core | Checksum: 108e2b238

Time (s): cpu = 00:00:34 ; elapsed = 00:00:17 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 1017 ; free virtual = 25999
Phase 2 Global Placement | Checksum: 108e2b238

Time (s): cpu = 00:00:34 ; elapsed = 00:00:17 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 1017 ; free virtual = 25999

Phase 3 Detail Placement

Phase 3.1 Commit Multi Column Macros
Phase 3.1 Commit Multi Column Macros | Checksum: 1430f3728

Time (s): cpu = 00:00:35 ; elapsed = 00:00:17 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 1017 ; free virtual = 25999

Phase 3.2 Commit Most Macros & LUTRAMs
Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 17fa2ca8c

Time (s): cpu = 00:00:39 ; elapsed = 00:00:20 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 1009 ; free virtual = 25991

Phase 3.3 Area Swap Optimization
Phase 3.3 Area Swap Optimization | Checksum: 1d15566ef

Time (s): cpu = 00:00:39 ; elapsed = 00:00:20 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 1009 ; free virtual = 25991

Phase 3.4 Pipeline Register Optimization
Phase 3.4 Pipeline Register Optimization | Checksum: 193f5b553

Time (s): cpu = 00:00:39 ; elapsed = 00:00:20 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 1009 ; free virtual = 25991

Phase 3.5 Small Shape Detail Placement
Phase 3.5 Small Shape Detail Placement | Checksum: 182179238

Time (s): cpu = 00:00:41 ; elapsed = 00:00:21 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 999 ; free virtual = 25981

Phase 3.6 Re-assign LUT pins
Phase 3.6 Re-assign LUT pins | Checksum: 1dc024021

Time (s): cpu = 00:00:41 ; elapsed = 00:00:22 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 1001 ; free virtual = 25983

Phase 3.7 Pipeline Register Optimization
Phase 3.7 Pipeline Register Optimization | Checksum: 11b714645

Time (s): cpu = 00:00:41 ; elapsed = 00:00:22 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 1000 ; free virtual = 25982
Phase 3 Detail Placement | Checksum: 11b714645

Time (s): cpu = 00:00:41 ; elapsed = 00:00:22 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 1000 ; free virtual = 25982

Phase 4 Post Placement Optimization and Clean-Up

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 4.1.1 Post Placement Optimization
Post Placement Optimization Initialization | Checksum: 1c551fa5e

Phase 4.1.1.1 BUFG Insertion

Starting Physical Synthesis Task

Phase 1 Physical Synthesis Initialization
INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 8 CPUs
INFO: [Physopt 32-619] Estimated Timing Summary | WNS=2.179 | TNS=0.000 |
Phase 1 Physical Synthesis Initialization | Checksum: 161907a2a

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.77 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 1000 ; free virtual = 25982
INFO: [Place 46-56] BUFG insertion identified 0 candidate nets. Inserted BUFG: 0, Replicated BUFG Driver: 0, Skipped due to Placement/Routing Conflicts: 0, Skipped due to Timing Degradation: 0, Skipped due to netlist editing failed: 0.
Ending Physical Synthesis Task | Checksum: 161907a2a

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.88 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 997 ; free virtual = 25979
Phase 4.1.1.1 BUFG Insertion | Checksum: 1c551fa5e

Time (s): cpu = 00:00:47 ; elapsed = 00:00:25 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 998 ; free virtual = 25980

Phase 4.1.1.2 Post Placement Timing Optimization
INFO: [Place 30-746] Post Placement Timing Summary WNS=2.179. For the most accurate timing information please run report_timing.
Phase 4.1.1.2 Post Placement Timing Optimization | Checksum: 19ed9a8b1

Time (s): cpu = 00:00:47 ; elapsed = 00:00:25 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 1000 ; free virtual = 25982

Time (s): cpu = 00:00:47 ; elapsed = 00:00:25 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 1000 ; free virtual = 25982
Phase 4.1 Post Commit Optimization | Checksum: 19ed9a8b1

Time (s): cpu = 00:00:47 ; elapsed = 00:00:25 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 1000 ; free virtual = 25982

Phase 4.2 Post Placement Cleanup
Phase 4.2 Post Placement Cleanup | Checksum: 19ed9a8b1

Time (s): cpu = 00:00:48 ; elapsed = 00:00:26 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 1011 ; free virtual = 25993

Phase 4.3 Placer Reporting

Phase 4.3.1 Print Estimated Congestion
INFO: [Place 30-612] Post-Placement Estimated Congestion 
 ____________________________________________________
|           | Global Congestion | Short Congestion  |
| Direction | Region Size       | Region Size       |
|___________|___________________|___________________|
|      North|                1x1|                1x1|
|___________|___________________|___________________|
|      South|                1x1|                1x1|
|___________|___________________|___________________|
|       East|                1x1|                1x1|
|___________|___________________|___________________|
|       West|                1x1|                1x1|
|___________|___________________|___________________|

Phase 4.3.1 Print Estimated Congestion | Checksum: 19ed9a8b1

Time (s): cpu = 00:00:48 ; elapsed = 00:00:26 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 1008 ; free virtual = 25989
Phase 4.3 Placer Reporting | Checksum: 19ed9a8b1

Time (s): cpu = 00:00:48 ; elapsed = 00:00:26 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 1008 ; free virtual = 25990

Phase 4.4 Final Placement Cleanup
Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 1008 ; free virtual = 25990

Time (s): cpu = 00:00:48 ; elapsed = 00:00:26 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 1008 ; free virtual = 25990
Phase 4 Post Placement Optimization and Clean-Up | Checksum: 18cbdb64f

Time (s): cpu = 00:00:48 ; elapsed = 00:00:26 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 1004 ; free virtual = 25986
Ending Placer Task | Checksum: bdd0d579

Time (s): cpu = 00:00:48 ; elapsed = 00:00:26 . Memory (MB): peak = 2836.828 ; gain = 7.027 ; free physical = 1001 ; free virtual = 25983
29 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
place_design: Time (s): cpu = 00:00:50 ; elapsed = 00:00:27 . Memory (MB): peak = 2836.828 ; gain = 39.043 ; free physical = 1000 ; free virtual = 25982
# report_utilization -hierarchical -file digilent_nexys4ddr_utilization_hierarchical_place.rpt
# report_utilization -file digilent_nexys4ddr_utilization_place.rpt
# report_io -file digilent_nexys4ddr_io.rpt
report_io: Time (s): cpu = 00:00:00.25 ; elapsed = 00:00:00.36 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 1002 ; free virtual = 25984
# report_control_sets -verbose -file digilent_nexys4ddr_control_sets.rpt
report_control_sets: Time (s): cpu = 00:00:00.11 ; elapsed = 00:00:00.21 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 1002 ; free virtual = 25984
# report_clock_utilization -file digilent_nexys4ddr_clock_utilization.rpt
# route_design
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 8 CPUs

Phase 1 Build RT Design
Checksum: PlaceDB: a7e6f407 ConstDB: 0 ShapeSum: 15e9e172 RouteDB: 0
Post Restoration Checksum: NetGraph: 251e55a6 | NumContArr: 13120666 | Constraints: c2a8fa9d | Timing: c2a8fa9d
Phase 1 Build RT Design | Checksum: 1bd825146

Time (s): cpu = 00:01:17 ; elapsed = 00:01:06 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 995 ; free virtual = 25977

Phase 2 Router Initialization

Phase 2.1 Fix Topology Constraints
Phase 2.1 Fix Topology Constraints | Checksum: 1bd825146

Time (s): cpu = 00:01:17 ; elapsed = 00:01:06 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 993 ; free virtual = 25975

Phase 2.2 Pre Route Cleanup
Phase 2.2 Pre Route Cleanup | Checksum: 1bd825146

Time (s): cpu = 00:01:17 ; elapsed = 00:01:06 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 992 ; free virtual = 25974
 Number of Nodes with overlaps = 0

Phase 2.3 Update Timing
Phase 2.3 Update Timing | Checksum: 27d63150b

Time (s): cpu = 00:01:25 ; elapsed = 00:01:09 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 953 ; free virtual = 25935
INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.248  | TNS=0.000  | WHS=-0.153 | THS=-16.122|


Router Utilization Summary
  Global Vertical Routing Utilization    = 0 %
  Global Horizontal Routing Utilization  = 0 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 1451
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 1451
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 2 Router Initialization | Checksum: 26d39ddf6

Time (s): cpu = 00:01:28 ; elapsed = 00:01:11 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 955 ; free virtual = 25937

Phase 3 Initial Routing

Phase 3.1 Global Routing
Phase 3.1 Global Routing | Checksum: 26d39ddf6

Time (s): cpu = 00:01:28 ; elapsed = 00:01:11 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 955 ; free virtual = 25937

Phase 3.2 Initial Net Routing
Phase 3.2 Initial Net Routing | Checksum: 1eb803222

Time (s): cpu = 00:01:31 ; elapsed = 00:01:11 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 954 ; free virtual = 25936
Phase 3 Initial Routing | Checksum: 1eb803222

Time (s): cpu = 00:01:31 ; elapsed = 00:01:11 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 954 ; free virtual = 25936

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
 Number of Nodes with overlaps = 191
 Number of Nodes with overlaps = 23
 Number of Nodes with overlaps = 7
 Number of Nodes with overlaps = 2
 Number of Nodes with overlaps = 1
 Number of Nodes with overlaps = 0
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.779  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 4.1 Global Iteration 0 | Checksum: 2855ce1b4

Time (s): cpu = 00:01:36 ; elapsed = 00:01:15 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 962 ; free virtual = 25944
Phase 4 Rip-up And Reroute | Checksum: 2855ce1b4

Time (s): cpu = 00:01:36 ; elapsed = 00:01:15 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 962 ; free virtual = 25944

Phase 5 Delay and Skew Optimization

Phase 5.1 Delay CleanUp

Phase 5.1.1 Update Timing
Phase 5.1.1 Update Timing | Checksum: 2bf43cade

Time (s): cpu = 00:01:38 ; elapsed = 00:01:16 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 950 ; free virtual = 25932
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.859  | TNS=0.000  | WHS=N/A    | THS=N/A    |

Phase 5.1 Delay CleanUp | Checksum: 2bf43cade

Time (s): cpu = 00:01:38 ; elapsed = 00:01:16 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 950 ; free virtual = 25932

Phase 5.2 Clock Skew Optimization
Phase 5.2 Clock Skew Optimization | Checksum: 2bf43cade

Time (s): cpu = 00:01:38 ; elapsed = 00:01:16 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 950 ; free virtual = 25932
Phase 5 Delay and Skew Optimization | Checksum: 2bf43cade

Time (s): cpu = 00:01:38 ; elapsed = 00:01:16 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 950 ; free virtual = 25932

Phase 6 Post Hold Fix

Phase 6.1 Hold Fix Iter

Phase 6.1.1 Update Timing
Phase 6.1.1 Update Timing | Checksum: 298c3b1c3

Time (s): cpu = 00:01:40 ; elapsed = 00:01:17 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 951 ; free virtual = 25933
INFO: [Route 35-416] Intermediate Timing Summary | WNS=1.859  | TNS=0.000  | WHS=0.085  | THS=0.000  |

Phase 6.1 Hold Fix Iter | Checksum: 2a491ec07

Time (s): cpu = 00:01:40 ; elapsed = 00:01:17 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 951 ; free virtual = 25933
Phase 6 Post Hold Fix | Checksum: 2a491ec07

Time (s): cpu = 00:01:40 ; elapsed = 00:01:17 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 951 ; free virtual = 25933

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.591156 %
  Global Horizontal Routing Utilization  = 0.697641 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
    (Failed Nets is the sum of unrouted and partially routed nets)
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Phase 7 Route finalize | Checksum: 2a491ec07

Time (s): cpu = 00:01:40 ; elapsed = 00:01:17 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 951 ; free virtual = 25933

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 2a491ec07

Time (s): cpu = 00:01:40 ; elapsed = 00:01:17 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 951 ; free virtual = 25933

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 25b15f842

Time (s): cpu = 00:01:40 ; elapsed = 00:01:17 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 951 ; free virtual = 25933

Phase 10 Post Router Timing
INFO: [Route 35-57] Estimated Timing Summary | WNS=1.859  | TNS=0.000  | WHS=0.085  | THS=0.000  |

INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary.
Phase 10 Post Router Timing | Checksum: 25b15f842

Time (s): cpu = 00:01:42 ; elapsed = 00:01:18 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 951 ; free virtual = 25933
INFO: [Route 35-16] Router Completed Successfully

Phase 11 Post-Route Event Processing
Phase 11 Post-Route Event Processing | Checksum: 17b749b4c

Time (s): cpu = 00:01:42 ; elapsed = 00:01:18 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 951 ; free virtual = 25933
Ending Routing Task | Checksum: 17b749b4c

Time (s): cpu = 00:01:42 ; elapsed = 00:01:18 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 951 ; free virtual = 25933

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
13 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:01:45 ; elapsed = 00:01:19 . Memory (MB): peak = 2836.828 ; gain = 0.000 ; free physical = 951 ; free virtual = 25933
# report_timing_summary -no_header -no_detailed_paths
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes
  Inter-SLR Compensation                     :  Conservative

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

No report available as report_methodology has not been run prior. Run report_methodology on the current design for the summary of methodology violations.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (1)
6. checking no_output_delay (1)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (1)
------------------------------
 There is 1 input port with no input delay specified. (HIGH)

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (1)
-------------------------------
 There is 1 port with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      1.859        0.000                      0                11929        0.085        0.000                      0                11929        3.750        0.000                       0                  1660  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock        Waveform(ns)       Period(ns)      Frequency(MHz)
-----        ------------       ----------      --------------
sys_clk_pin  {0.000 5.000}      10.000          100.000         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
sys_clk_pin         1.859        0.000                      0                11929        0.085        0.000                      0                11929        3.750        0.000                       0                  1660  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


# report_route_status -file digilent_nexys4ddr_route_status.rpt
# report_drc -file digilent_nexys4ddr_drc.rpt
Command: report_drc -file digilent_nexys4ddr_drc.rpt
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/eda/vivado/Vivado/2023.2/data/ip'.
INFO: [DRC 23-27] Running DRC with 8 threads
INFO: [Vivado_Tcl 2-168] The results of DRC are in file /var/lib/jenkins/workspace/tinyriscv/tinyriscv/digilent_nexys4ddr_drc.rpt.
report_drc completed successfully
# report_timing_summary -datasheet -max_paths 10 -file digilent_nexys4ddr_timing.rpt
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 8 CPUs
# report_power -file digilent_nexys4ddr_power.rpt
Command: report_power -file digilent_nexys4ddr_power.rpt
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
WARNING: [Power 33-332] Found switching activity that implies high-fanout reset nets being asserted for excessive periods of time which may result in inaccurate power analysis.
Resolution: To review and fix problems, please run Power Constraints Advisor in the GUI from Tools > Power Constraints Advisor or run report_power with the -advisory option to generate a text report.
0 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
report_power completed successfully
# write_bitstream -force "digilent_nexys4_ddr.bit"
Command: write_bitstream -force digilent_nexys4_ddr.bit
Attempting to get a license for feature 'Implementation' and/or device 'xc7a100t'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7a100t'
Running DRC as a precondition to command write_bitstream
INFO: [IP_Flow 19-1839] IP Catalog is up to date.
INFO: [DRC 23-27] Running DRC with 8 threads
WARNING: [DRC CFGBVS-1] Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design.  Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0.  It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax:

 set_property CFGBVS value1 [current_design]
 #where value1 is either VCCO or GND

 set_property CONFIG_VOLTAGE value2 [current_design]
 #where value2 is the voltage provided to configuration bank 0

Refer to the device configuration user guide for more information.
INFO: [Vivado 12-3199] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado 12-3200] Please refer to the DRC report (report_drc) for more information.
INFO: [Designutils 20-2272] Running write_bitstream with 8 threads.
Loading data files...
Loading site data...
Loading route data...
Processing options...
Creating bitmap...
Creating bitstream...
Writing bitstream ./digilent_nexys4_ddr.bit...
INFO: [Vivado 12-1842] Bitgen Completed Successfully.
INFO: [Project 1-1876] WebTalk data collection is mandatory when using a ULT device. To see the specific WebTalk data collected for your design, open the usage_statistics_webtalk.html or usage_statistics_webtalk.xml file in the implementation directory.
INFO: [Common 17-83] Releasing license: Implementation
9 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_bitstream completed successfully
write_bitstream: Time (s): cpu = 00:00:26 ; elapsed = 00:00:28 . Memory (MB): peak = 3144.828 ; gain = 257.148 ; free physical = 593 ; free virtual = 25597
INFO: [Common 17-206] Exiting Vivado at Tue Oct 22 02:50:17 2024...

[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Flash digilent_nexys4_ddr)
[Pipeline] dir
Running in /var/lib/jenkins/workspace/tinyriscv/tinyriscv
[Pipeline] {
[Pipeline] echo
FPGA digilent_nexys4_ddr bloqueada para flash.
[Pipeline] sh
+ python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p tinyriscv -b digilent_nexys4_ddr -l
Arquivo de configura����o final gerado em /var/lib/jenkins/workspace/tinyriscv/tinyriscv/build_digilent_nexys4_ddr.tcl
Makefile executado com sucesso.
Sa��da do Makefile:
Flashing the FPGA...
/eda/oss-cad-suite/bin/openFPGALoader -b nexys_a7_100 digilent_nexys4_ddr.bit
empty
Jtag frequency : requested 6.00MHz   -> real 6.00MHz  
Parse file DONE
Erase SRAM Load SRAM 
Load SRAM: [======                                            ] 10.28%
Load SRAM: [===========                                       ] 20.56%
Load SRAM: [================                                  ] 30.83%
Load SRAM: [=====================                             ] 41.11%
Load SRAM: [==========================                        ] 51.39%
Load SRAM: [===============================                   ] 61.67%
Load SRAM: [====================================              ] 71.94%
Load SRAM: [==========================================        ] 82.22%
Load SRAM: [===============================================   ] 92.50%
Load SRAM: [===================================================] 100.00%
Done
DONE

[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Teste digilent_nexys4_ddr)
[Pipeline] echo
Testando FPGA digilent_nexys4_ddr.
[Pipeline] dir
Running in /var/lib/jenkins/workspace/tinyriscv/tinyriscv
[Pipeline] {
[Pipeline] }
[Pipeline] // dir
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
Lock released on resource [Resource: digilent_nexys4_ddr]
[Pipeline] // lock
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // parallel
[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Declarative: Post Actions)
[Pipeline] junit
Recording test results
[Checks API] No suitable checks publisher found.
[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
Finished: UNSTABLE