Skip to content
[Jenkins]Jenkins
log in

Workspace

/ tinyriscv /
.git
.Xil
fpga
pic
rtl
sim
tb
tests
tmp_venv
tools
.gitignoreJul 17, 2026, 2:42:20 AM30 B
build_digilent_arty_a7_100t.tclJul 17, 2026, 2:45:02 AM3.30 KiB
clockInfo.txtJul 17, 2026, 2:46:29 AM375 B
digilent_arty_a7_100t.bitJul 17, 2026, 2:47:42 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptJul 17, 2026, 2:46:39 AM22.33 KiB
digilent_arty_a7_control_sets.rptJul 17, 2026, 2:46:38 AM18.90 KiB
digilent_arty_a7_drc.rptJul 17, 2026, 2:47:20 AM9.43 KiB
digilent_arty_a7_io.rptJul 17, 2026, 2:46:38 AM96.81 KiB
digilent_arty_a7_power.rptJul 17, 2026, 2:47:21 AM8.74 KiB
digilent_arty_a7_route_status.rptJul 17, 2026, 2:47:18 AM651 B
digilent_arty_a7_timing.rptJul 17, 2026, 2:47:20 AM22.74 KiB
digilent_arty_a7_utilization_hierarchical_place.rptJul 17, 2026, 2:46:38 AM7.30 KiB
digilent_arty_a7_utilization_place.rptJul 17, 2026, 2:46:38 AM10.74 KiB
LICENSEJul 17, 2026, 2:42:20 AM11.09 KiB
processor_ci_defines.vhJul 17, 2026, 2:45:02 AM300 B
README.mdJul 17, 2026, 2:42:20 AM9.81 KiB
simulation.outJul 17, 2026, 2:42:22 AM201.33 KiB