Skip to content
[Jenkins]Jenkins
log in

Workspace

/ tinyriscv /
.git
.Xil
fpga
pic
rtl
sim
tb
tests
tmp_venv
tools
.gitignoreAug 29, 2026, 2:42:37 AM30 B
build_digilent_arty_a7_100t.tclAug 29, 2026, 2:44:50 AM3.30 KiB
clockInfo.txtAug 29, 2026, 2:46:18 AM375 B
digilent_arty_a7_100t.bitAug 29, 2026, 2:47:26 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptAug 29, 2026, 2:46:27 AM22.33 KiB
digilent_arty_a7_control_sets.rptAug 29, 2026, 2:46:27 AM18.90 KiB
digilent_arty_a7_drc.rptAug 29, 2026, 2:47:05 AM9.43 KiB
digilent_arty_a7_io.rptAug 29, 2026, 2:46:27 AM96.81 KiB
digilent_arty_a7_power.rptAug 29, 2026, 2:47:07 AM8.74 KiB
digilent_arty_a7_route_status.rptAug 29, 2026, 2:47:04 AM651 B
digilent_arty_a7_timing.rptAug 29, 2026, 2:47:05 AM22.74 KiB
digilent_arty_a7_utilization_hierarchical_place.rptAug 29, 2026, 2:46:26 AM7.30 KiB
digilent_arty_a7_utilization_place.rptAug 29, 2026, 2:46:26 AM10.74 KiB
LICENSEAug 29, 2026, 2:42:37 AM11.09 KiB
processor_ci_defines.vhAug 29, 2026, 2:44:50 AM300 B
README.mdAug 29, 2026, 2:42:37 AM9.81 KiB
simulation.outAug 29, 2026, 2:42:40 AM201.33 KiB