Skip to content

Workspace

/ tinyriscv /
.git
.Xil
fpga
pic
rtl
sim
tb
tests
tmp_venv
tools
.gitignoreAug 25, 2026, 2:42:00 AM30 B
build_digilent_arty_a7_100t.tclAug 25, 2026, 2:44:21 AM3.30 KiB
clockInfo.txtAug 25, 2026, 2:45:52 AM375 B
digilent_arty_a7_100t.bitAug 25, 2026, 2:47:01 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptAug 25, 2026, 2:46:01 AM22.33 KiB
digilent_arty_a7_control_sets.rptAug 25, 2026, 2:46:00 AM18.90 KiB
digilent_arty_a7_drc.rptAug 25, 2026, 2:46:39 AM9.43 KiB
digilent_arty_a7_io.rptAug 25, 2026, 2:46:00 AM96.81 KiB
digilent_arty_a7_power.rptAug 25, 2026, 2:46:41 AM8.74 KiB
digilent_arty_a7_route_status.rptAug 25, 2026, 2:46:38 AM651 B
digilent_arty_a7_timing.rptAug 25, 2026, 2:46:40 AM22.74 KiB
digilent_arty_a7_utilization_hierarchical_place.rptAug 25, 2026, 2:46:00 AM7.30 KiB
digilent_arty_a7_utilization_place.rptAug 25, 2026, 2:46:00 AM10.74 KiB
LICENSEAug 25, 2026, 2:42:00 AM11.09 KiB
processor_ci_defines.vhAug 25, 2026, 2:44:21 AM300 B
README.mdAug 25, 2026, 2:42:00 AM9.81 KiB
simulation.outAug 25, 2026, 2:42:02 AM201.33 KiB