![[Jenkins]](/jenkins/static/b6fe011e/images/svgs/logo.svg){kind=logo}
Started by user Gabriel Cabral [Pipeline] Start of Pipeline [Pipeline] node Running on Jenkins in /var/jenkins_home/workspace/tinyriscv@2 [Pipeline] { [Pipeline] stage [Pipeline] { (Git Clone) [Pipeline] sh + rm -rf tinyriscv [Pipeline] sh + git clone --recursive --depth=1 https://github.com/liangkangnan/tinyriscv tinyriscv Cloning into 'tinyriscv'... [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Simulation) [Pipeline] dir Running in /var/jenkins_home/workspace/tinyriscv@2/tinyriscv [Pipeline] { [Pipeline] sh + /eda/oss-cad-suite/bin/iverilog -o simulation.out -g2005 -s tinyriscv -I rtl/core/ rtl/core/clint.v rtl/core/csr_reg.v rtl/core/ctrl.v rtl/core/div.v rtl/core/ex.v rtl/core/id.v rtl/core/id_ex.v rtl/core/if_id.v rtl/core/pc_reg.v rtl/core/regs.v rtl/core/rib.v rtl/core/tinyriscv.v rtl/utils/gen_dff.v [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Utilities) [Pipeline] dir Running in /var/jenkins_home/workspace/tinyriscv@2/tinyriscv [Pipeline] { [Pipeline] sh + pwd + python3 /eda/processor-ci/labeler_prototype.py -d /var/jenkins_home/workspace/tinyriscv@2/tinyriscv -c /eda/processor-ci/config.json -o /jenkins/processor-ci_utils/labels.json Error writing to JSON file: [Errno 2] No such file or directory: '/jenkins/processor-ci_utils/labels.json' [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (FPGA Build Pipeline) [Pipeline] parallel [Pipeline] { (Branch: colorlight_i9) [Pipeline] { (Branch: digilent_nexys4_ddr) [Pipeline] stage [Pipeline] { (colorlight_i9) [Pipeline] stage [Pipeline] { (digilent_nexys4_ddr) [Pipeline] lock Trying to acquire lock on [Resource: colorlight_i9] The resource [colorlight_i9] is locked by build tinyriscv #74 #74 since Dec 9, 2024, 12:22 AM. [Resource: colorlight_i9] is not free, waiting for execution ... [Required resources: [colorlight_i9]] added into queue at position 0 [Pipeline] lock Trying to acquire lock on [Resource: digilent_nexys4_ddr] The resource [digilent_nexys4_ddr] is locked by build tinyriscv #74 #74 since Dec 9, 2024, 12:22 AM. [Resource: digilent_nexys4_ddr] is not free, waiting for execution ... [Required resources: [digilent_nexys4_ddr]] added into queue at position 1 Lock acquired on [Resource: colorlight_i9] [Pipeline] { [Pipeline] stage [Pipeline] { (Synthesis and PnR) Lock acquired on [Resource: digilent_nexys4_ddr] [Pipeline] dir Running in /var/jenkins_home/workspace/tinyriscv@2/tinyriscv [Pipeline] { [Pipeline] { [Pipeline] echo Starting synthesis for FPGA colorlight_i9. [Pipeline] sh + python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p tinyriscv -b colorlight_i9 [Pipeline] stage [Pipeline] { (Synthesis and PnR) [Pipeline] dir Running in /var/jenkins_home/workspace/tinyriscv@2/tinyriscv [Pipeline] { [Pipeline] echo Starting synthesis for FPGA digilent_nexys4_ddr. [Pipeline] sh + python3 /eda/processor-ci/main.py -c /eda/processor-ci/config.json -p tinyriscv -b digilent_nexys4_ddr Sending interrupt signal to process Aborted by Gabriel Cabral Sending interrupt signal to process Final configuration file generated at /var/jenkins_home/workspace/tinyriscv@2/tinyriscv/build_colorlight_i9.tcl Error executing Makefile. Info: constraining clock net 'sck' to 10.00 MHz Info: constraining clock net 'clk' to 25.00 MHz Info: Logic utilisation before packing: Info: Total LUT4s: 15668/43848 35% Info: logic LUTs: 8316/43848 18% Info: carry LUTs: 992/43848 2% Info: RAM LUTs: 4240/ 5481 77% Info: RAMW LUTs: 2120/10962 19% Info: Total DFFs: 1630/43848 3% Info: Packing IOs.. Info: pin 'tx$tr_io' constrained to Bel 'X90/Y20/PIOC'. Info: pin 'sck$tr_io' constrained to Bel 'X4/Y71/PIOA'. Info: pin 'rx$tr_io' constrained to Bel 'X90/Y20/PIOA'. Info: pin 'rw$tr_io' constrained to Bel 'X4/Y71/PIOB'. Info: pin 'reset$tr_io' constrained to Bel 'X6/Y71/PIOB'. Info: pin 'mosi$tr_io' constrained to Bel 'X9/Y71/PIOA'. Info: pin 'miso$tr_io' constrained to Bel 'X0/Y65/PIOB'. Info: pin 'intr$tr_io' constrained to Bel 'X9/Y71/PIOB'. Info: pin 'cs$tr_io' constrained to Bel 'X6/Y71/PIOA'. Info: pin 'clk$tr_io' constrained to Bel 'X0/Y68/PIOC'. Info: Packing constants.. Info: Packing carries... Info: Packing LUTs... Info: Packing LUT5-7s... Info: Packing FFs... Info: 1054 FFs paired with LUTs. Info: Generating derived timing constraints... Info: Promoting globals... Info: promoting clock net clk$TRELLIS_IO_IN to global network Info: promoting clock net clk_core to global network Info: Checksum: 0x54f4faac Info: Device utilisation: Info: TRELLIS_IO: 10/ 245 4% Info: DCCA: 2/ 56 3% Info: DP16KD: 0/ 108 0% Info: MULT18X18D: 4/ 72 5% Info: ALU54B: 0/ 36 0% Info: EHXPLLL: 0/ 4 0% Info: EXTREFB: 0/ 2 0% Info: DCUA: 0/ 2 0% Info: PCSCLKDIV: 0/ 2 0% Info: IOLOGIC: 0/ 160 0% Info: SIOLOGIC: 0/ 85 0% Info: GSR: 0/ 1 0% Info: JTAGG: 0/ 1 0% Info: OSCG: 0/ 1 0% Info: SEDGA: 0/ 1 0% Info: DTR: 0/ 1 0% Info: USRMCLK: 0/ 1 0% Info: CLKDIVF: 0/ 4 0% Info: ECLKSYNCB: 0/ 10 0% Info: DLLDELD: 0/ 8 0% Info: DDRDLL: 0/ 4 0% Info: DQSBUFM: 0/ 10 0% Info: TRELLIS_ECLKBUF: 0/ 8 0% Info: ECLKBRIDGECS: 0/ 2 0% Info: DCSC: 0/ 2 0% Info: TRELLIS_FF: 1630/ 43848 3% Info: TRELLIS_COMB: 15824/ 43848 36% Info: TRELLIS_RAMW: 1060/ 5481 19% Info: Placed 10 cells based on constraints. Info: Creating initial analytic placement for 8032 cells, random placement wirelen = 748864. Info: at initial placer iter 0, wirelen = 2163 Info: at initial placer iter 1, wirelen = 2358 Info: at initial placer iter 2, wirelen = 2293 Info: at initial placer iter 3, wirelen = 2030 Info: Running main analytical placer, max placement attempts per cell = 42920112. Info: at iteration #1, type ALL: wirelen solved = 2249, spread = 153562, legal = 154305; time = 0.47s Info: at iteration #2, type ALL: wirelen solved = 10100, spread = 108207, legal = 110577; time = 0.57s Info: at iteration #3, type ALL: wirelen solved = 21544, spread = 101511, legal = 102933; time = 0.52s Info: at iteration #4, type ALL: wirelen solved = 27298, spread = 87832, legal = 89758; time = 0.50s Info: at iteration #5, type ALL: wirelen solved = 31737, spread = 82790, legal = 85592; time = 0.49s Info: at iteration #6, type ALL: wirelen solved = 34830, spread = 79900, legal = 83410; time = 0.50s Info: at iteration #7, type ALL: wirelen solved = 38653, spread = 73638, legal = 76908; time = 0.48s Info: at iteration #8, type ALL: wirelen solved = 39348, spread = 72448, legal = 76829; time = 0.45s Info: at iteration #9, type ALL: wirelen solved = 41236, spread = 71825, legal = 77236; time = 0.46s Info: at iteration #10, type ALL: wirelen solved = 42306, spread = 73347, legal = 78528; time = 0.47s Info: at iteration #11, type ALL: wirelen solved = 45027, spread = 70319, legal = 75372; time = 0.44s Info: at iteration #12, type ALL: wirelen solved = 45728, spread = 71047, legal = 76358; time = 0.46s Info: at iteration #13, type ALL: wirelen solved = 46540, spread = 70170, legal = 77172; time = 0.51s Info: at iteration #14, type ALL: wirelen solved = 47190, spread = 71075, legal = 77759; time = 0.55s Info: at iteration #15, type ALL: wirelen solved = 48639, spread = 72851, legal = 76431; time = 0.49s Info: at iteration #16, type ALL: wirelen solved = 50523, spread = 70853, legal = 75938; time = 0.43s Info: HeAP Placer Time: 13.30s Info: of which solving equations: 7.65s Info: of which spreading cells: 1.06s Info: of which strict legalisation: 0.37s Info: Running simulated annealing placer for refinement. Info: at iteration #1: temp = 0.000000, timing cost = 16398, wirelen = 75372 make: *** [/eda/processor-ci/makefiles/colorlight_i9.mk:7: colorlight_i9.config] Terminated Traceback (most recent call last): File "/eda/processor-ci/main.py", line 135, in <module> main( File "/eda/processor-ci/main.py", line 82, in main build(build_file_path, board_name, toolchain_path) File "/eda/processor-ci/core/fpga.py", line 215, in build raise subprocess.CalledProcessError(process.returncode, 'make') subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2. script returned exit code 1 [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Flash colorlight_i9) Stage "Flash colorlight_i9" skipped due to earlier failure(s) Final configuration file generated at /var/jenkins_home/workspace/tinyriscv@2/tinyriscv/build_digilent_nexys4_ddr.tcl Error executing Makefile. Terminated Terminated make: *** [/eda/processor-ci/makefiles/digilent_nexys4_ddr.mk:12: digilent_nexys4_ddr.bit] Error 143 Traceback (most recent call last): File "/eda/processor-ci/main.py", line 135, in <module> main( File "/eda/processor-ci/main.py", line 82, in main build(build_file_path, board_name, toolchain_path) File "/eda/processor-ci/core/fpga.py", line 215, in build raise subprocess.CalledProcessError(process.returncode, 'make') subprocess.CalledProcessError: Command 'make' returned non-zero exit status 2. script returned exit code 1 [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // dir [Pipeline] } [Pipeline] stage [Pipeline] { (Test colorlight_i9) [Pipeline] // stage Stage "Test colorlight_i9" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] stage [Pipeline] { (Flash digilent_nexys4_ddr) [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: colorlight_i9] Stage "Flash digilent_nexys4_ddr" skipped due to earlier failure(s) [Pipeline] getContext [Pipeline] } [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] // stage [Pipeline] } Failed in branch colorlight_i9 [Pipeline] stage [Pipeline] { (Test digilent_nexys4_ddr) Stage "Test digilent_nexys4_ddr" skipped due to earlier failure(s) Click here to forcibly terminate running steps [Pipeline] getContext [Pipeline] } [Pipeline] // stage [Pipeline] } Lock released on resource [Resource: digilent_nexys4_ddr] [Pipeline] // lock [Pipeline] } [Pipeline] // stage [Pipeline] } Failed in branch digilent_nexys4_ddr [Pipeline] // parallel [Pipeline] } [Pipeline] // stage [Pipeline] stage [Pipeline] { (Declarative: Post Actions) [Pipeline] junit Recording test results No test report files were found. Configuration error? Error when executing always post condition: Also: org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: ce7b203c-a9a3-4c97-9431-2624883af35a hudson.AbortException: No test report files were found. Configuration error? at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser$ParseResultCallable.invoke(JUnitParser.java:253) at hudson.FilePath.act(FilePath.java:1234) at hudson.FilePath.act(FilePath.java:1217) at PluginClassLoader for junit//hudson.tasks.junit.JUnitParser.parseResult(JUnitParser.java:146) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parse(JUnitResultArchiver.java:177) at PluginClassLoader for junit//hudson.tasks.junit.JUnitResultArchiver.parseAndSummarize(JUnitResultArchiver.java:282) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:62) at PluginClassLoader for junit//hudson.tasks.junit.pipeline.JUnitResultsStepExecution.run(JUnitResultsStepExecution.java:27) at PluginClassLoader for workflow-step-api//org.jenkinsci.plugins.workflow.steps.SynchronousNonBlockingStepExecution.lambda$start$0(SynchronousNonBlockingStepExecution.java:47) at java.base/java.util.concurrent.Executors$RunnableAdapter.call(Unknown Source) at java.base/java.util.concurrent.FutureTask.run(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor.runWorker(Unknown Source) at java.base/java.util.concurrent.ThreadPoolExecutor$Worker.run(Unknown Source) at java.base/java.lang.Thread.run(Unknown Source) [Pipeline] } [Pipeline] // stage [Pipeline] } [Pipeline] // node [Pipeline] End of Pipeline org.jenkinsci.plugins.workflow.actions.ErrorAction$ErrorId: df3ee9d0-5f32-4e0f-ac83-fbcb0a45ef19 Finished: ABORTED