Skip to content

Workspace

/ tinyriscv /
.git
.Xil
fpga
pic
rtl
sim
tb
tests
tmp_venv
tools
.gitignoreJul 2, 2026, 2:41:42 AM30 B
build_digilent_arty_a7_100t.tclJul 2, 2026, 2:44:04 AM3.30 KiB
clockInfo.txtJul 2, 2026, 2:45:26 AM375 B
digilent_arty_a7_100t.bitJul 2, 2026, 2:46:42 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptJul 2, 2026, 2:45:39 AM22.33 KiB
digilent_arty_a7_control_sets.rptJul 2, 2026, 2:45:37 AM18.90 KiB
digilent_arty_a7_drc.rptJul 2, 2026, 2:46:21 AM9.43 KiB
digilent_arty_a7_io.rptJul 2, 2026, 2:45:37 AM96.81 KiB
digilent_arty_a7_power.rptJul 2, 2026, 2:46:23 AM8.74 KiB
digilent_arty_a7_route_status.rptJul 2, 2026, 2:46:20 AM651 B
digilent_arty_a7_timing.rptJul 2, 2026, 2:46:22 AM22.74 KiB
digilent_arty_a7_utilization_hierarchical_place.rptJul 2, 2026, 2:45:37 AM7.30 KiB
digilent_arty_a7_utilization_place.rptJul 2, 2026, 2:45:37 AM10.74 KiB
LICENSEJul 2, 2026, 2:41:42 AM11.09 KiB
processor_ci_defines.vhJul 2, 2026, 2:44:04 AM300 B
README.mdJul 2, 2026, 2:41:42 AM9.81 KiB
simulation.outJul 2, 2026, 2:41:44 AM201.33 KiB