Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2023.2 (lin64) Build 4029153 Fri Oct 13 20:13:54 MDT 2023
| Date         : Sat Sep  5 22:51:49 2026
| Host         : 685a421e500f running 64-bit unknown
| Command      : report_control_sets -verbose -file digilent_arty_a7_control_sets.rpt
| Design       : fpga_top
| Device       : xc7a100t
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Control Set Information

Table of Contents
-----------------
1. Summary
2. Histogram
3. Flip-Flop Distribution
4. Detailed Control Set Information

1. Summary
----------

+----------------------------------------------------------+-------+
|                          Status                          | Count |
+----------------------------------------------------------+-------+
| Total control sets                                       |   110 |
|    Minimum number of control sets                        |   110 |
|    Addition due to synthesis replication                 |     0 |
|    Addition due to physical synthesis replication        |     0 |
| Unused register locations in slices containing registers |   130 |
+----------------------------------------------------------+-------+
* Control sets can be merged at opt_design using control_set_merge or merge_equivalent_drivers
** Run report_qor_suggestions for automated merging and remapping suggestions


2. Histogram
------------

+--------------------+-------+
|       Fanout       | Count |
+--------------------+-------+
| Total control sets |   110 |
| >= 0 to < 4        |     3 |
| >= 4 to < 6        |    12 |
| >= 6 to < 8        |     3 |
| >= 8 to < 10       |     8 |
| >= 10 to < 12      |     4 |
| >= 12 to < 14      |     3 |
| >= 14 to < 16      |     0 |
| >= 16              |    77 |
+--------------------+-------+
* Control sets can be remapped at either synth_design or opt_design


3. Flip-Flop Distribution
-------------------------

+--------------+-----------------------+------------------------+-----------------+--------------+
| Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices |
+--------------+-----------------------+------------------------+-----------------+--------------+
| No           | No                    | No                     |              42 |           20 |
| No           | No                    | Yes                    |              58 |           26 |
| No           | Yes                   | No                     |             150 |           58 |
| Yes          | No                    | No                     |             313 |          128 |
| Yes          | No                    | Yes                    |            1557 |          721 |
| Yes          | Yes                   | No                     |             406 |          112 |
+--------------+-----------------------+------------------------+-----------------+--------------+


4. Detailed Control Set Information
-----------------------------------

+--------------------------------------+-------------------------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+
|             Clock Signal             |                                    Enable Signal                                    |                       Set/Reset Signal                       | Slice Load Count | Bel Load Count | Bels / Slice |
+--------------------------------------+-------------------------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+
|  clk_IBUF_BUFG                       |                                                                                     |                                                              |                1 |              1 |         1.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                                    | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_1_n_0             |                1 |              1 |         1.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/memory_page_number[23]_i_2_n_0                        |                                                              |                1 |              1 |         1.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/id_stage_i/controller_i/ctrl_fsm_ns                        | ptop/u_Controller/Interpreter/rst_core                       |                3 |              4 |         1.33 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_2__0_n_0                          | ptop/u_Controller/Uart/i_uart_tx/bit_counter[3]_i_1__0_n_0   |                2 |              4 |         2.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/E[0]                                                 |                                                              |                1 |              4 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/next_bit                                           | ptop/u_Controller/Uart/i_uart_rx/bit_counter[3]_i_1_n_0      |                1 |              4 |         4.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/instr_rdata_id_o_reg[26]_2[0]                   | ptop/u_Controller/Interpreter/rst_core                       |                1 |              4 |         4.00 |
|  clk_o_BUFG                          | ResetBootSystem/counter                                                             |                                                              |                2 |              5 |         2.50 |
|  clk_o_BUFG                          |                                                                                     |                                                              |                3 |              5 |         1.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/instr_rdata_id_o_reg[12]_2[0]                   | ptop/u_Controller/Interpreter/rst_core                       |                1 |              5 |         5.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/regfile_wsel_wb_reg[0]                          | ptop/u_Controller/Interpreter/rst_core                       |                2 |              5 |         2.50 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/instr_rdata_id_o_reg[4]_0                       | ptop/u_Controller/Interpreter/rst_core                       |                2 |              5 |         2.50 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/return_state                                          | ResetBootSystem/rst_o_reg_0                                  |                3 |              5 |         1.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/data_grant                                                                     | ptop/u_Controller/Interpreter/rst_core                       |                4 |              5 |         1.25 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/ctrl_fsm_cs_reg[0]_1[0]                         | ptop/u_Controller/Interpreter/rst_core                       |                3 |              6 |         2.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/regfile_wsel_wb_reg_0[0]                        | ptop/u_Controller/Interpreter/rst_core                       |                2 |              6 |         3.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/data_to_send[6]_i_1_n_0                            | ResetBootSystem/rst_o_reg_0                                  |                2 |              7 |         3.50 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/recieved_data0                                     | ptop/u_Controller/Uart/i_uart_rx/recieved_data[7]_i_1_n_0    |                1 |              8 |         8.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/E[0]                                               | ResetBootSystem/rst_o_reg_0                                  |                2 |              8 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/counter                                               | ResetBootSystem/rst_o_reg_0                                  |                3 |              8 |         2.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/uart_tx_en                                                   | ResetBootSystem/rst_o_reg_0                                  |                1 |              8 |         8.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/accumulator[7]_i_1_n_0                                | ResetBootSystem/rst_o_reg_0                                  |                2 |              8 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/counter_write_reg[2][0]                              | ResetBootSystem/rst_o_reg_0                                  |                1 |              8 |         8.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/uart_rx_data[7]_i_1_n_0                            | ResetBootSystem/rst_o_reg_0                                  |                1 |              8 |         8.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/instr_rdata_id_o_reg[12]_0[0]                   | ptop/u_Controller/Interpreter/rst_core                       |                4 |              9 |         2.25 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_tx/txd_reg_i_2_n_0                                    | ResetBootSystem/SR[0]                                        |                3 |             10 |         3.33 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/i_uart_rx/cycle_counter0                                     | ptop/u_Controller/Uart/i_uart_rx/cycle_counter[9]_i_1__0_n_0 |                4 |             10 |         2.50 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/rx_fifo/read_ptr0                                            | ResetBootSystem/rst_o_reg_0                                  |                3 |             11 |         3.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/read_ptr[2]_i_1_n_0                                  | ResetBootSystem/rst_o_reg_0                                  |                4 |             11 |         2.75 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/address[31]_i_1_n_0                                   |                                                              |                6 |             12 |         2.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/memory_reg_0_7_0_5_i_1_n_0                           |                                                              |                2 |             12 |         6.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/rx_fifo/memory_reg_0_7_0_5_i_1__0_n_0                        |                                                              |                2 |             12 |         6.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/memory_page_number[23]_i_2_n_0                        | ptop/u_Controller/Interpreter/memory_page_number[23]_i_1_n_0 |                6 |             23 |         3.83 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/num_of_pages                                          | ResetBootSystem/rst_o_reg_0                                  |                5 |             24 |         4.80 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/num_of_cycles_to_pulse[23]_i_1_n_0                    |                                                              |               10 |             24 |         2.40 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/timeout                                               | ResetBootSystem/rst_o_reg_0                                  |                6 |             24 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/accumulator0                                          | ResetBootSystem/rst_o_reg_0                                  |                6 |             24 |         4.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/id_stage_i/controller_i/FSM_sequential_CS_reg[0]_2[0]      | ptop/u_Controller/Interpreter/rst_core                       |               17 |             31 |         1.82 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/communication_buffer[31]_i_1_n_0                      | ResetBootSystem/rst_o_reg_0                                  |                7 |             32 |         4.57 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/prefetch_buffer_i/fifo_i/rdata_Q[0][31]_i_1_n_0 | ptop/u_Controller/Interpreter/rst_core                       |               14 |             32 |         2.29 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/ex_block_i/multdiv_i/mac_res_q[31]_i_1_n_0                 | ptop/u_Controller/Interpreter/rst_core                       |               27 |             32 |         1.19 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/instr_rdata_id_o_reg[7]_9[0]                    | ptop/u_Controller/Interpreter/rst_core                       |               11 |             32 |         2.91 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/regfile_waddr_wb_reg[2]_1[0]                    | ptop/u_Controller/Interpreter/rst_core                       |               12 |             32 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/instr_rdata_id_o_reg[7]_5[0]                    | ptop/u_Controller/Interpreter/rst_core                       |               14 |             32 |         2.29 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/regfile_waddr_wb_reg[2]_6[0]                    | ptop/u_Controller/Interpreter/rst_core                       |               13 |             32 |         2.46 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/regfile_waddr_wb_reg[3][0]                      | ptop/u_Controller/Interpreter/rst_core                       |               12 |             32 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/instr_rdata_id_o_reg[7]_4[0]                    | ptop/u_Controller/Interpreter/rst_core                       |               15 |             32 |         2.13 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/instr_rdata_id_o_reg[7]_8[0]                    | ptop/u_Controller/Interpreter/rst_core                       |               19 |             32 |         1.68 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/regfile_waddr_wb_reg[2]_3[0]                    | ptop/u_Controller/Interpreter/rst_core                       |               10 |             32 |         3.20 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/instr_rdata_id_o_reg[7]_10[0]                   | ptop/u_Controller/Interpreter/rst_core                       |               16 |             32 |         2.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/instr_rdata_id_o_reg[7]_3[0]                    | ptop/u_Controller/Interpreter/rst_core                       |               12 |             32 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/regfile_waddr_wb_reg[1]_2[0]                    | ptop/u_Controller/Interpreter/rst_core                       |               11 |             32 |         2.91 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/regfile_waddr_wb_reg[2]_2[0]                    | ptop/u_Controller/Interpreter/rst_core                       |               11 |             32 |         2.91 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/instr_rdata_id_o_reg[7]_0[0]                    | ptop/u_Controller/Interpreter/rst_core                       |               13 |             32 |         2.46 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/communication_write_data[31]_i_1_n_0                  |                                                              |               12 |             32 |         2.67 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/regfile_waddr_wb_reg[3]_1[0]                    | ptop/u_Controller/Interpreter/rst_core                       |               12 |             32 |         2.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/read_buffer                                           | ResetBootSystem/rst_o_reg_0                                  |               17 |             32 |         1.88 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/instr_rdata_id_o_reg[7]_7[0]                    | ptop/u_Controller/Interpreter/rst_core                       |               15 |             32 |         2.13 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/instr_rdata_id_o_reg[26]_3[0]                   | ptop/u_Controller/Interpreter/rst_core                       |               20 |             32 |         1.60 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/instr_rdata_id_o_reg[6]_2                       | ptop/u_Controller/Interpreter/rst_core                       |               15 |             32 |         2.13 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/instr_rdata_id_o_reg[7]_6[0]                    | ptop/u_Controller/Interpreter/rst_core                       |               17 |             32 |         1.88 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/regfile_waddr_wb_reg[2]_4[0]                    | ptop/u_Controller/Interpreter/rst_core                       |                9 |             32 |         3.56 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/ex_block_i/mmult_i/IP1_3[15]_i_1_n_0                       |                                                              |                8 |             32 |         4.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/regfile_waddr_wb_reg[1]_4[0]                    | ptop/u_Controller/Interpreter/rst_core                       |               17 |             32 |         1.88 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/regfile_waddr_wb_reg[1]_3[0]                    | ptop/u_Controller/Interpreter/rst_core                       |               12 |             32 |         2.67 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/write_data[31]_i_1_n_0                                |                                                              |               21 |             32 |         1.52 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/rx_fifo/E[0]                                                 | ResetBootSystem/rst_o_reg_0                                  |                7 |             32 |         4.57 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/regfile_waddr_wb_reg[2]_7[0]                    | ptop/u_Controller/Interpreter/rst_core                       |               13 |             32 |         2.46 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/regfile_waddr_wb_reg[3]_2[0]                    | ptop/u_Controller/Interpreter/rst_core                       |               14 |             32 |         2.29 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/PCCR_inc_q_reg[0][0]                            | ptop/u_Controller/Interpreter/rst_core                       |               14 |             32 |         2.29 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/timeout_counter                                       | ResetBootSystem/rst_o_reg_0                                  |                8 |             32 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Uart/tx_fifo/FSM_sequential_state_write_reg[2][0]                 | ResetBootSystem/rst_o_reg_0                                  |                5 |             32 |         6.40 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/ex_block_i/multdiv_i/op_quotient_q                         | ptop/u_Controller/Interpreter/rst_core                       |               15 |             32 |         2.13 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/id_stage_i/controller_i/ctrl_fsm_cs_reg[2]_3[0]            | ptop/u_Controller/Interpreter/rst_core                       |               20 |             32 |         1.60 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/end_position[31]_i_1_n_0                              | ResetBootSystem/rst_o_reg_0                                  |               11 |             32 |         2.91 |
|  clk_o_BUFG                          | ptop/u_Controller/ClkDivider/pulse_counter[0]_i_1_n_0                               | ResetBootSystem/rst_o_reg_0                                  |                8 |             32 |         4.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/regfile_waddr_wb_reg[1]_1[0]                    | ptop/u_Controller/Interpreter/rst_core                       |               20 |             32 |         1.60 |
|  u_Controller/ClkDivider/clk_o_pulse |                                                                                     | ptop/instr_data[31]_i_1_n_0                                  |               13 |             32 |         2.46 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/ex_block_i/multdiv_i/op_denominator_q                      | ptop/u_Controller/Interpreter/rst_core                       |               17 |             32 |         1.88 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/ex_block_i/multdiv_i/op_numerator_q                        | ptop/u_Controller/Interpreter/rst_core                       |               14 |             32 |         2.29 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/regfile_waddr_wb_reg[1][0]                      | ptop/u_Controller/Interpreter/rst_core                       |               30 |             32 |         1.07 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/regfile_waddr_wb_reg[2]_0[0]                    | ptop/u_Controller/Interpreter/rst_core                       |               21 |             32 |         1.52 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/regfile_waddr_wb_reg[1]_0[0]                    | ptop/u_Controller/Interpreter/rst_core                       |               14 |             32 |         2.29 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/instr_rdata_id_o_reg[7]_1[0]                    | ptop/u_Controller/Interpreter/rst_core                       |               13 |             32 |         2.46 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/regfile_waddr_wb_reg[2]_5[0]                    | ptop/u_Controller/Interpreter/rst_core                       |               11 |             32 |         2.91 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/instr_rdata_id_o_reg[7]_2[0]                    | ptop/u_Controller/Interpreter/rst_core                       |               13 |             32 |         2.46 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/regfile_waddr_wb_reg[3]_0[0]                    | ptop/u_Controller/Interpreter/rst_core                       |               17 |             32 |         1.88 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/instr_rdata_id_o_reg[11]_1[0]                   | ptop/u_Controller/Interpreter/rst_core                       |               13 |             32 |         2.46 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/regfile_waddr_wb_reg[2][0]                      | ptop/u_Controller/Interpreter/rst_core                       |               17 |             32 |         1.88 |
|  u_Controller/ClkDivider/clk_o_pulse |                                                                                     |                                                              |               16 |             36 |         2.25 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/num_of_positions[23]_i_1_n_0                          |                                                              |               17 |             55 |         3.24 |
|  u_Controller/ClkDivider/clk_o_pulse |                                                                                     | ptop/u_Controller/Interpreter/rst_core                       |               26 |             58 |         2.23 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/E[0]                                            |                                                              |               29 |             58 |         2.00 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/ex_block_i/mmult_i/ram0/mmult_en_1_reg                     |                                                              |               21 |             58 |         2.76 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/if_stage_i/prefetch_buffer_i/fifo_i/if_valid               | ptop/u_Controller/Interpreter/rst_core                       |               38 |             70 |         1.84 |
|  u_Controller/ClkDivider/clk_o_pulse | ptop/zeroriscy_core_inst/id_stage_i/controller_i/ctrl_fsm_cs_reg[2]_0               | ptop/u_Controller/Interpreter/rst_core                       |               33 |             95 |         2.88 |
|  clk_o_BUFG                          |                                                                                     | ResetBootSystem/rst_o_reg_0                                  |               45 |            118 |         2.62 |
|  clk_o_BUFG                          | ptop/zeroriscy_core_inst/id_stage_i/controller_i/address_reg[31]_1                  |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/zeroriscy_core_inst/id_stage_i/controller_i/address_reg[31]_2                  |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/zeroriscy_core_inst/id_stage_i/controller_i/FSM_sequential_CS_reg[0]_0         |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/zeroriscy_core_inst/id_stage_i/controller_i/FSM_sequential_CS_reg[0]_1         |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/zeroriscy_core_inst/id_stage_i/controller_i/address_reg[31]                    |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/zeroriscy_core_inst/id_stage_i/controller_i/memory_mux_selector_reg_2          |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/zeroriscy_core_inst/id_stage_i/controller_i/memory_mux_selector_reg_1          |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/zeroriscy_core_inst/id_stage_i/controller_i/address_reg[31]_0                  |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/memory_mux_selector_reg_8                             |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/address_reg[10]_0                                     |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/memory_mux_selector_reg_9                             |                                                              |               32 |            128 |         4.00 |
|  clk_o_BUFG                          | ptop/u_Controller/Interpreter/address_reg[11]_0                                     |                                                              |               32 |            128 |         4.00 |
+--------------------------------------+-------------------------------------------------------------------------------------+--------------------------------------------------------------+------------------+----------------+--------------+


