# Baby Risco 5 Documentation

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## Baby Risco 5

Baby Risco 5 is an open-source processor core that implements the RV32IE instruction set of the RISC-V architecture. It was developed for academic use and as the main core in small SoCs. The project focuses on facilitating integration and usage, offering a simplified and efficient architecture for various applications.

## Available Resources

### Baby Risco 5 Core

A RISC-V processor core implementing the RV32I/E[M] of RISC-V.

### Baby Risco 5 SoC

An SoC with the Risco-5 core containing memory and peripherals such as GPIOs and UART.

### Baby Risco 5 Tests

Tests written in RISC-V assembly for validating the Baby Risco 5.