Started by user Julio Nunes Avelar
[Pipeline] Start of Pipeline
[Pipeline] node
<span class="pipeline-node-3">Running on Jenkins in /var/lib/jenkins/workspace/DV-CPU-RV
</span>[Pipeline] {
[Pipeline] stage
[Pipeline] { (git_clone)
[Pipeline] sh
<span class="pipeline-node-7">+ rm -Rf dv-cpu-rv/ build/
</span>[Pipeline] sh
<span class="pipeline-node-8">+ git clone <a href='https://github.com/devindang/dv-cpu-rv.git'>https://github.com/devindang/dv-cpu-rv.git</a>
Cloning into 'dv-cpu-rv'...
</span>[Pipeline] sh
<span class="pipeline-node-9">+ cd dv-cpu-rv
</span>[Pipeline] }
[Pipeline] // stage
[Pipeline] stage
[Pipeline] { (Yosys)
[Pipeline] sh
<span class="pipeline-node-14">+ /eda/oss-cad-suite/bin/yosys -p                          read_verilog dv-cpu-rv/core/rtl/*.v;                         synth -top rv_core                     

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf &lt;claire@yosyshq.com&gt;         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.45+139 (git sha1 4d581a97d, clang++ 14.0.0-1ubuntu1.1 -fPIC -O3)

-- Running command `                         read_verilog dv-cpu-rv/core/rtl/*.v;                         synth -top rv_core                     ' --

1. Executing Verilog-2005 frontend: dv-cpu-rv/core/rtl/rv_alu.v
Parsing Verilog input from `dv-cpu-rv/core/rtl/rv_alu.v' to AST representation.
Generating RTLIL representation for module `\rv_alu'.
Note: Assuming pure combinatorial block at dv-cpu-rv/core/rtl/rv_alu.v:32.1-46.4 in
compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending
use of @* instead of @(...) for better match of synthesis and simulation.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: dv-cpu-rv/core/rtl/rv_alu_ctrl.v
Parsing Verilog input from `dv-cpu-rv/core/rtl/rv_alu_ctrl.v' to AST representation.
Generating RTLIL representation for module `\rv_alu_ctrl'.
Note: Assuming pure combinatorial block at dv-cpu-rv/core/rtl/rv_alu_ctrl.v:27.1-94.4 in
compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending
use of @* instead of @(...) for better match of synthesis and simulation.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: dv-cpu-rv/core/rtl/rv_branch_predict.v
Parsing Verilog input from `dv-cpu-rv/core/rtl/rv_branch_predict.v' to AST representation.
Generating RTLIL representation for module `\rv_branch_predict'.
Warning: Replacing memory \bpb with list of registers. See dv-cpu-rv/core/rtl/rv_branch_predict.v:44
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: dv-cpu-rv/core/rtl/rv_branch_test.v
Parsing Verilog input from `dv-cpu-rv/core/rtl/rv_branch_test.v' to AST representation.
Generating RTLIL representation for module `\rv_branch_test'.
Note: Assuming pure combinatorial block at dv-cpu-rv/core/rtl/rv_branch_test.v:30.1-40.4 in
compliance with IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002. Recommending
use of @* instead of @(...) for better match of synthesis and simulation.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: dv-cpu-rv/core/rtl/rv_core.v
Parsing Verilog input from `dv-cpu-rv/core/rtl/rv_core.v' to AST representation.
Generating RTLIL representation for module `\rv_core'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: dv-cpu-rv/core/rtl/rv_ctrl.v
dv-cpu-rv/core/rtl/rv_ctrl.v:35: ERROR: Found non-synthesizable event list!
</span>[Pipeline] }
[Pipeline] // stage
[Pipeline] }
[Pipeline] // node
[Pipeline] End of Pipeline
ERROR: script returned exit code 1
Finished: FAILURE