Skip to content

Workspace

/ F03x /
.git
.Xil
klessydra-f0-3th
build_digilent_arty_a7_100t.tclSep 2, 2026, 2:04:19 AM3.07 KiB
clockInfo.txtSep 2, 2026, 2:07:27 AM375 B
digilent_arty_a7_100t.bitSep 2, 2026, 2:09:25 AM3.65 MiB
digilent_arty_a7_clock_utilization.rptSep 2, 2026, 2:07:51 AM58.83 KiB
digilent_arty_a7_control_sets.rptSep 2, 2026, 2:07:50 AM70.99 KiB
digilent_arty_a7_drc.rptSep 2, 2026, 2:08:57 AM8.55 KiB
digilent_arty_a7_io.rptSep 2, 2026, 2:07:49 AM96.81 KiB
digilent_arty_a7_power.rptSep 2, 2026, 2:09:02 AM8.84 KiB
digilent_arty_a7_route_status.rptSep 2, 2026, 2:08:53 AM651 B
digilent_arty_a7_timing.rptSep 2, 2026, 2:08:59 AM47.47 KiB
digilent_arty_a7_utilization_hierarchical_place.rptSep 2, 2026, 2:07:49 AM25.25 KiB
digilent_arty_a7_utilization_place.rptSep 2, 2026, 2:07:49 AM10.77 KiB
processor_ci_defines.vhSep 2, 2026, 2:04:19 AM300 B
README.mdSep 2, 2026, 2:04:08 AM421 B
src_files.ymlSep 2, 2026, 2:04:08 AM522 B