//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name                         I/O  size props
// RDY_set_verbosity              O     1 const
// RDY_server_reset_request_put   O     1 reg
// RDY_server_reset_response_get  O     1
// valid                          O     1
// addr                           O    64 reg
// word64                         O    64
// st_amo_val                     O    64
// exc                            O     1
// exc_code                       O     4 reg
// RDY_server_flush_request_put   O     1 reg
// RDY_server_flush_response_get  O     1
// RDY_tlb_flush                  O     1 const
// mem_master_awvalid             O     1 reg
// mem_master_awid                O     4 reg
// mem_master_awaddr              O    64 reg
// mem_master_awlen               O     8 reg
// mem_master_awsize              O     3 reg
// mem_master_awburst             O     2 reg
// mem_master_awlock              O     1 reg
// mem_master_awcache             O     4 reg
// mem_master_awprot              O     3 reg
// mem_master_awqos               O     4 reg
// mem_master_awregion            O     4 reg
// mem_master_wvalid              O     1 reg
// mem_master_wdata               O    64 reg
// mem_master_wstrb               O     8 reg
// mem_master_wlast               O     1 reg
// mem_master_bready              O     1 reg
// mem_master_arvalid             O     1 reg
// mem_master_arid                O     4 reg
// mem_master_araddr              O    64 reg
// mem_master_arlen               O     8 reg
// mem_master_arsize              O     3 reg
// mem_master_arburst             O     2 reg
// mem_master_arlock              O     1 reg
// mem_master_arcache             O     4 reg
// mem_master_arprot              O     3 reg
// mem_master_arqos               O     4 reg
// mem_master_arregion            O     4 reg
// mem_master_rready              O     1 reg
// CLK                            I     1 clock
// RST_N                          I     1 reset
// set_verbosity_verbosity        I     4 reg
// req_op                         I     2
// req_f3                         I     3
// req_amo_funct7                 I     7 reg
// req_addr                       I    64
// req_st_value                   I    64
// req_priv                       I     2 reg
// req_sstatus_SUM                I     1 reg
// req_mstatus_MXR                I     1 reg
// req_satp                       I    64 reg
// mem_master_awready             I     1
// mem_master_wready              I     1
// mem_master_bvalid              I     1
// mem_master_bid                 I     4 reg
// mem_master_bresp               I     2 reg
// mem_master_arready             I     1
// mem_master_rvalid              I     1
// mem_master_rid                 I     4 reg
// mem_master_rdata               I    64 reg
// mem_master_rresp               I     2 reg
// mem_master_rlast               I     1 reg
// EN_set_verbosity               I     1
// EN_server_reset_request_put    I     1
// EN_server_reset_response_get   I     1
// EN_req                         I     1
// EN_server_flush_request_put    I     1
// EN_server_flush_response_get   I     1
// EN_tlb_flush                   I     1
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkMMU_Cache(CLK,
		   RST_N,

		   set_verbosity_verbosity,
		   EN_set_verbosity,
		   RDY_set_verbosity,

		   EN_server_reset_request_put,
		   RDY_server_reset_request_put,

		   EN_server_reset_response_get,
		   RDY_server_reset_response_get,

		   req_op,
		   req_f3,
		   req_amo_funct7,
		   req_addr,
		   req_st_value,
		   req_priv,
		   req_sstatus_SUM,
		   req_mstatus_MXR,
		   req_satp,
		   EN_req,

		   valid,

		   addr,

		   word64,

		   st_amo_val,

		   exc,

		   exc_code,

		   EN_server_flush_request_put,
		   RDY_server_flush_request_put,

		   EN_server_flush_response_get,
		   RDY_server_flush_response_get,

		   EN_tlb_flush,
		   RDY_tlb_flush,

		   mem_master_awvalid,

		   mem_master_awid,

		   mem_master_awaddr,

		   mem_master_awlen,

		   mem_master_awsize,

		   mem_master_awburst,

		   mem_master_awlock,

		   mem_master_awcache,

		   mem_master_awprot,

		   mem_master_awqos,

		   mem_master_awregion,

		   mem_master_awready,

		   mem_master_wvalid,

		   mem_master_wdata,

		   mem_master_wstrb,

		   mem_master_wlast,

		   mem_master_wready,

		   mem_master_bvalid,
		   mem_master_bid,
		   mem_master_bresp,

		   mem_master_bready,

		   mem_master_arvalid,

		   mem_master_arid,

		   mem_master_araddr,

		   mem_master_arlen,

		   mem_master_arsize,

		   mem_master_arburst,

		   mem_master_arlock,

		   mem_master_arcache,

		   mem_master_arprot,

		   mem_master_arqos,

		   mem_master_arregion,

		   mem_master_arready,

		   mem_master_rvalid,
		   mem_master_rid,
		   mem_master_rdata,
		   mem_master_rresp,
		   mem_master_rlast,

		   mem_master_rready);
  parameter [0 : 0] dmem_not_imem = 1'b0;
  input  CLK;
  input  RST_N;

  // action method set_verbosity
  input  [3 : 0] set_verbosity_verbosity;
  input  EN_set_verbosity;
  output RDY_set_verbosity;

  // action method server_reset_request_put
  input  EN_server_reset_request_put;
  output RDY_server_reset_request_put;

  // action method server_reset_response_get
  input  EN_server_reset_response_get;
  output RDY_server_reset_response_get;

  // action method req
  input  [1 : 0] req_op;
  input  [2 : 0] req_f3;
  input  [6 : 0] req_amo_funct7;
  input  [63 : 0] req_addr;
  input  [63 : 0] req_st_value;
  input  [1 : 0] req_priv;
  input  req_sstatus_SUM;
  input  req_mstatus_MXR;
  input  [63 : 0] req_satp;
  input  EN_req;

  // value method valid
  output valid;

  // value method addr
  output [63 : 0] addr;

  // value method word64
  output [63 : 0] word64;

  // value method st_amo_val
  output [63 : 0] st_amo_val;

  // value method exc
  output exc;

  // value method exc_code
  output [3 : 0] exc_code;

  // action method server_flush_request_put
  input  EN_server_flush_request_put;
  output RDY_server_flush_request_put;

  // action method server_flush_response_get
  input  EN_server_flush_response_get;
  output RDY_server_flush_response_get;

  // action method tlb_flush
  input  EN_tlb_flush;
  output RDY_tlb_flush;

  // value method mem_master_m_awvalid
  output mem_master_awvalid;

  // value method mem_master_m_awid
  output [3 : 0] mem_master_awid;

  // value method mem_master_m_awaddr
  output [63 : 0] mem_master_awaddr;

  // value method mem_master_m_awlen
  output [7 : 0] mem_master_awlen;

  // value method mem_master_m_awsize
  output [2 : 0] mem_master_awsize;

  // value method mem_master_m_awburst
  output [1 : 0] mem_master_awburst;

  // value method mem_master_m_awlock
  output mem_master_awlock;

  // value method mem_master_m_awcache
  output [3 : 0] mem_master_awcache;

  // value method mem_master_m_awprot
  output [2 : 0] mem_master_awprot;

  // value method mem_master_m_awqos
  output [3 : 0] mem_master_awqos;

  // value method mem_master_m_awregion
  output [3 : 0] mem_master_awregion;

  // value method mem_master_m_awuser

  // action method mem_master_m_awready
  input  mem_master_awready;

  // value method mem_master_m_wvalid
  output mem_master_wvalid;

  // value method mem_master_m_wdata
  output [63 : 0] mem_master_wdata;

  // value method mem_master_m_wstrb
  output [7 : 0] mem_master_wstrb;

  // value method mem_master_m_wlast
  output mem_master_wlast;

  // value method mem_master_m_wuser

  // action method mem_master_m_wready
  input  mem_master_wready;

  // action method mem_master_m_bvalid
  input  mem_master_bvalid;
  input  [3 : 0] mem_master_bid;
  input  [1 : 0] mem_master_bresp;

  // value method mem_master_m_bready
  output mem_master_bready;

  // value method mem_master_m_arvalid
  output mem_master_arvalid;

  // value method mem_master_m_arid
  output [3 : 0] mem_master_arid;

  // value method mem_master_m_araddr
  output [63 : 0] mem_master_araddr;

  // value method mem_master_m_arlen
  output [7 : 0] mem_master_arlen;

  // value method mem_master_m_arsize
  output [2 : 0] mem_master_arsize;

  // value method mem_master_m_arburst
  output [1 : 0] mem_master_arburst;

  // value method mem_master_m_arlock
  output mem_master_arlock;

  // value method mem_master_m_arcache
  output [3 : 0] mem_master_arcache;

  // value method mem_master_m_arprot
  output [2 : 0] mem_master_arprot;

  // value method mem_master_m_arqos
  output [3 : 0] mem_master_arqos;

  // value method mem_master_m_arregion
  output [3 : 0] mem_master_arregion;

  // value method mem_master_m_aruser

  // action method mem_master_m_arready
  input  mem_master_arready;

  // action method mem_master_m_rvalid
  input  mem_master_rvalid;
  input  [3 : 0] mem_master_rid;
  input  [63 : 0] mem_master_rdata;
  input  [1 : 0] mem_master_rresp;
  input  mem_master_rlast;

  // value method mem_master_m_rready
  output mem_master_rready;

  // signals for module outputs
  reg [63 : 0] word64;
  wire [63 : 0] addr,
		mem_master_araddr,
		mem_master_awaddr,
		mem_master_wdata,
		st_amo_val;
  wire [7 : 0] mem_master_arlen, mem_master_awlen, mem_master_wstrb;
  wire [3 : 0] exc_code,
	       mem_master_arcache,
	       mem_master_arid,
	       mem_master_arqos,
	       mem_master_arregion,
	       mem_master_awcache,
	       mem_master_awid,
	       mem_master_awqos,
	       mem_master_awregion;
  wire [2 : 0] mem_master_arprot,
	       mem_master_arsize,
	       mem_master_awprot,
	       mem_master_awsize;
  wire [1 : 0] mem_master_arburst, mem_master_awburst;
  wire RDY_server_flush_request_put,
       RDY_server_flush_response_get,
       RDY_server_reset_request_put,
       RDY_server_reset_response_get,
       RDY_set_verbosity,
       RDY_tlb_flush,
       exc,
       mem_master_arlock,
       mem_master_arvalid,
       mem_master_awlock,
       mem_master_awvalid,
       mem_master_bready,
       mem_master_rready,
       mem_master_wlast,
       mem_master_wvalid,
       valid;

  // inlined wires
  wire [3 : 0] ctr_wr_rsps_pending_crg$port0__write_1,
	       ctr_wr_rsps_pending_crg$port1__write_1,
	       ctr_wr_rsps_pending_crg$port2__read,
	       ctr_wr_rsps_pending_crg$port3__read;
  wire ctr_wr_rsps_pending_crg$EN_port2__write, dw_valid$whas;

  // register cfg_verbosity
  reg [3 : 0] cfg_verbosity;
  wire [3 : 0] cfg_verbosity$D_IN;
  wire cfg_verbosity$EN;

  // register ctr_wr_rsps_pending_crg
  reg [3 : 0] ctr_wr_rsps_pending_crg;
  wire [3 : 0] ctr_wr_rsps_pending_crg$D_IN;
  wire ctr_wr_rsps_pending_crg$EN;

  // register rg_addr
  reg [63 : 0] rg_addr;
  wire [63 : 0] rg_addr$D_IN;
  wire rg_addr$EN;

  // register rg_amo_funct7
  reg [6 : 0] rg_amo_funct7;
  wire [6 : 0] rg_amo_funct7$D_IN;
  wire rg_amo_funct7$EN;

  // register rg_cset_in_cache
  reg [5 : 0] rg_cset_in_cache;
  wire [5 : 0] rg_cset_in_cache$D_IN;
  wire rg_cset_in_cache$EN;

  // register rg_error_during_refill
  reg rg_error_during_refill;
  wire rg_error_during_refill$D_IN, rg_error_during_refill$EN;

  // register rg_exc_code
  reg [3 : 0] rg_exc_code;
  reg [3 : 0] rg_exc_code$D_IN;
  wire rg_exc_code$EN;

  // register rg_f3
  reg [2 : 0] rg_f3;
  wire [2 : 0] rg_f3$D_IN;
  wire rg_f3$EN;

  // register rg_ld_val
  reg [63 : 0] rg_ld_val;
  reg [63 : 0] rg_ld_val$D_IN;
  wire rg_ld_val$EN;

  // register rg_lower_word32
  reg [31 : 0] rg_lower_word32;
  wire [31 : 0] rg_lower_word32$D_IN;
  wire rg_lower_word32$EN;

  // register rg_lower_word32_full
  reg rg_lower_word32_full;
  wire rg_lower_word32_full$D_IN, rg_lower_word32_full$EN;

  // register rg_lrsc_pa
  reg [63 : 0] rg_lrsc_pa;
  wire [63 : 0] rg_lrsc_pa$D_IN;
  wire rg_lrsc_pa$EN;

  // register rg_lrsc_valid
  reg rg_lrsc_valid;
  wire rg_lrsc_valid$D_IN, rg_lrsc_valid$EN;

  // register rg_mstatus_MXR
  reg rg_mstatus_MXR;
  wire rg_mstatus_MXR$D_IN, rg_mstatus_MXR$EN;

  // register rg_op
  reg [1 : 0] rg_op;
  wire [1 : 0] rg_op$D_IN;
  wire rg_op$EN;

  // register rg_pa
  reg [63 : 0] rg_pa;
  wire [63 : 0] rg_pa$D_IN;
  wire rg_pa$EN;

  // register rg_priv
  reg [1 : 0] rg_priv;
  wire [1 : 0] rg_priv$D_IN;
  wire rg_priv$EN;

  // register rg_pte_pa
  reg [63 : 0] rg_pte_pa;
  reg [63 : 0] rg_pte_pa$D_IN;
  wire rg_pte_pa$EN;

  // register rg_satp
  reg [63 : 0] rg_satp;
  wire [63 : 0] rg_satp$D_IN;
  wire rg_satp$EN;

  // register rg_sstatus_SUM
  reg rg_sstatus_SUM;
  wire rg_sstatus_SUM$D_IN, rg_sstatus_SUM$EN;

  // register rg_st_amo_val
  reg [63 : 0] rg_st_amo_val;
  wire [63 : 0] rg_st_amo_val$D_IN;
  wire rg_st_amo_val$EN;

  // register rg_state
  reg [4 : 0] rg_state;
  reg [4 : 0] rg_state$D_IN;
  wire rg_state$EN;

  // register rg_victim_way
  reg rg_victim_way;
  wire rg_victim_way$D_IN, rg_victim_way$EN;

  // register rg_word64_set_in_cache
  reg [8 : 0] rg_word64_set_in_cache;
  wire [8 : 0] rg_word64_set_in_cache$D_IN;
  wire rg_word64_set_in_cache$EN;

  // ports of submodule f_fabric_write_reqs
  reg [130 : 0] f_fabric_write_reqs$D_IN;
  wire [130 : 0] f_fabric_write_reqs$D_OUT;
  wire f_fabric_write_reqs$CLR,
       f_fabric_write_reqs$DEQ,
       f_fabric_write_reqs$EMPTY_N,
       f_fabric_write_reqs$ENQ,
       f_fabric_write_reqs$FULL_N;

  // ports of submodule f_pte_writebacks
  wire [127 : 0] f_pte_writebacks$D_IN, f_pte_writebacks$D_OUT;
  wire f_pte_writebacks$CLR,
       f_pte_writebacks$DEQ,
       f_pte_writebacks$EMPTY_N,
       f_pte_writebacks$ENQ,
       f_pte_writebacks$FULL_N;

  // ports of submodule f_reset_reqs
  wire f_reset_reqs$CLR,
       f_reset_reqs$DEQ,
       f_reset_reqs$D_IN,
       f_reset_reqs$D_OUT,
       f_reset_reqs$EMPTY_N,
       f_reset_reqs$ENQ,
       f_reset_reqs$FULL_N;

  // ports of submodule f_reset_rsps
  wire f_reset_rsps$CLR,
       f_reset_rsps$DEQ,
       f_reset_rsps$D_IN,
       f_reset_rsps$D_OUT,
       f_reset_rsps$EMPTY_N,
       f_reset_rsps$ENQ,
       f_reset_rsps$FULL_N;

  // ports of submodule master_xactor_f_rd_addr
  reg [96 : 0] master_xactor_f_rd_addr$D_IN;
  wire [96 : 0] master_xactor_f_rd_addr$D_OUT;
  wire master_xactor_f_rd_addr$CLR,
       master_xactor_f_rd_addr$DEQ,
       master_xactor_f_rd_addr$EMPTY_N,
       master_xactor_f_rd_addr$ENQ,
       master_xactor_f_rd_addr$FULL_N;

  // ports of submodule master_xactor_f_rd_data
  wire [70 : 0] master_xactor_f_rd_data$D_IN, master_xactor_f_rd_data$D_OUT;
  wire master_xactor_f_rd_data$CLR,
       master_xactor_f_rd_data$DEQ,
       master_xactor_f_rd_data$EMPTY_N,
       master_xactor_f_rd_data$ENQ,
       master_xactor_f_rd_data$FULL_N;

  // ports of submodule master_xactor_f_wr_addr
  wire [96 : 0] master_xactor_f_wr_addr$D_IN, master_xactor_f_wr_addr$D_OUT;
  wire master_xactor_f_wr_addr$CLR,
       master_xactor_f_wr_addr$DEQ,
       master_xactor_f_wr_addr$EMPTY_N,
       master_xactor_f_wr_addr$ENQ,
       master_xactor_f_wr_addr$FULL_N;

  // ports of submodule master_xactor_f_wr_data
  wire [72 : 0] master_xactor_f_wr_data$D_IN, master_xactor_f_wr_data$D_OUT;
  wire master_xactor_f_wr_data$CLR,
       master_xactor_f_wr_data$DEQ,
       master_xactor_f_wr_data$EMPTY_N,
       master_xactor_f_wr_data$ENQ,
       master_xactor_f_wr_data$FULL_N;

  // ports of submodule master_xactor_f_wr_resp
  wire [5 : 0] master_xactor_f_wr_resp$D_IN, master_xactor_f_wr_resp$D_OUT;
  wire master_xactor_f_wr_resp$CLR,
       master_xactor_f_wr_resp$DEQ,
       master_xactor_f_wr_resp$EMPTY_N,
       master_xactor_f_wr_resp$ENQ,
       master_xactor_f_wr_resp$FULL_N;

  // ports of submodule ram_state_and_ctag_cset
  wire [105 : 0] ram_state_and_ctag_cset$DIA,
		 ram_state_and_ctag_cset$DIB,
		 ram_state_and_ctag_cset$DOB;
  wire [5 : 0] ram_state_and_ctag_cset$ADDRA, ram_state_and_ctag_cset$ADDRB;
  wire ram_state_and_ctag_cset$ENA,
       ram_state_and_ctag_cset$ENB,
       ram_state_and_ctag_cset$WEA,
       ram_state_and_ctag_cset$WEB;

  // ports of submodule ram_word64_set
  reg [127 : 0] ram_word64_set$DIB;
  reg [8 : 0] ram_word64_set$ADDRB;
  wire [127 : 0] ram_word64_set$DIA, ram_word64_set$DOB;
  wire [8 : 0] ram_word64_set$ADDRA;
  wire ram_word64_set$ENA,
       ram_word64_set$ENB,
       ram_word64_set$WEA,
       ram_word64_set$WEB;

  // ports of submodule soc_map
  wire [63 : 0] soc_map$m_is_IO_addr_addr,
		soc_map$m_is_mem_addr_addr,
		soc_map$m_is_near_mem_IO_addr_addr;
  wire soc_map$m_is_mem_addr;

  // ports of submodule tlb
  reg [1 : 0] tlb$insert_level;
  wire [130 : 0] tlb$lookup;
  wire [63 : 0] tlb$insert_pte, tlb$insert_pte_pa;
  wire [26 : 0] tlb$insert_vpn, tlb$lookup_vpn;
  wire [15 : 0] tlb$insert_asid, tlb$lookup_asid;
  wire tlb$EN_flush, tlb$EN_insert, tlb$RDY_insert, tlb$RDY_lookup;

  // rule scheduling signals
  wire CAN_FIRE_RL_rl_ST_AMO_response,
       CAN_FIRE_RL_rl_cache_refill_rsps_loop,
       CAN_FIRE_RL_rl_discard_write_rsp,
       CAN_FIRE_RL_rl_drive_exception_rsp,
       CAN_FIRE_RL_rl_fabric_send_write_req,
       CAN_FIRE_RL_rl_io_AMO_SC_req,
       CAN_FIRE_RL_rl_io_AMO_op_req,
       CAN_FIRE_RL_rl_io_AMO_read_rsp,
       CAN_FIRE_RL_rl_io_read_req,
       CAN_FIRE_RL_rl_io_read_rsp,
       CAN_FIRE_RL_rl_io_write_req,
       CAN_FIRE_RL_rl_maintain_io_read_rsp,
       CAN_FIRE_RL_rl_probe_and_immed_rsp,
       CAN_FIRE_RL_rl_ptw_level_0,
       CAN_FIRE_RL_rl_ptw_level_1,
       CAN_FIRE_RL_rl_ptw_level_2,
       CAN_FIRE_RL_rl_rereq,
       CAN_FIRE_RL_rl_reset,
       CAN_FIRE_RL_rl_start_cache_refill,
       CAN_FIRE_RL_rl_start_reset,
       CAN_FIRE_RL_rl_start_tlb_refill,
       CAN_FIRE_RL_rl_writeback_updated_PTE,
       CAN_FIRE_mem_master_m_arready,
       CAN_FIRE_mem_master_m_awready,
       CAN_FIRE_mem_master_m_bvalid,
       CAN_FIRE_mem_master_m_rvalid,
       CAN_FIRE_mem_master_m_wready,
       CAN_FIRE_req,
       CAN_FIRE_server_flush_request_put,
       CAN_FIRE_server_flush_response_get,
       CAN_FIRE_server_reset_request_put,
       CAN_FIRE_server_reset_response_get,
       CAN_FIRE_set_verbosity,
       CAN_FIRE_tlb_flush,
       WILL_FIRE_RL_rl_ST_AMO_response,
       WILL_FIRE_RL_rl_cache_refill_rsps_loop,
       WILL_FIRE_RL_rl_discard_write_rsp,
       WILL_FIRE_RL_rl_drive_exception_rsp,
       WILL_FIRE_RL_rl_fabric_send_write_req,
       WILL_FIRE_RL_rl_io_AMO_SC_req,
       WILL_FIRE_RL_rl_io_AMO_op_req,
       WILL_FIRE_RL_rl_io_AMO_read_rsp,
       WILL_FIRE_RL_rl_io_read_req,
       WILL_FIRE_RL_rl_io_read_rsp,
       WILL_FIRE_RL_rl_io_write_req,
       WILL_FIRE_RL_rl_maintain_io_read_rsp,
       WILL_FIRE_RL_rl_probe_and_immed_rsp,
       WILL_FIRE_RL_rl_ptw_level_0,
       WILL_FIRE_RL_rl_ptw_level_1,
       WILL_FIRE_RL_rl_ptw_level_2,
       WILL_FIRE_RL_rl_rereq,
       WILL_FIRE_RL_rl_reset,
       WILL_FIRE_RL_rl_start_cache_refill,
       WILL_FIRE_RL_rl_start_reset,
       WILL_FIRE_RL_rl_start_tlb_refill,
       WILL_FIRE_RL_rl_writeback_updated_PTE,
       WILL_FIRE_mem_master_m_arready,
       WILL_FIRE_mem_master_m_awready,
       WILL_FIRE_mem_master_m_bvalid,
       WILL_FIRE_mem_master_m_rvalid,
       WILL_FIRE_mem_master_m_wready,
       WILL_FIRE_req,
       WILL_FIRE_server_flush_request_put,
       WILL_FIRE_server_flush_response_get,
       WILL_FIRE_server_reset_request_put,
       WILL_FIRE_server_reset_response_get,
       WILL_FIRE_set_verbosity,
       WILL_FIRE_tlb_flush;

  // inputs to muxes for submodule ports
  wire [130 : 0] MUX_f_fabric_write_reqs$enq_1__VAL_1,
		 MUX_f_fabric_write_reqs$enq_1__VAL_2,
		 MUX_f_fabric_write_reqs$enq_1__VAL_3,
		 MUX_f_fabric_write_reqs$enq_1__VAL_4;
  wire [127 : 0] MUX_ram_word64_set$a_put_3__VAL_1,
		 MUX_ram_word64_set$a_put_3__VAL_2;
  wire [105 : 0] MUX_ram_state_and_ctag_cset$a_put_3__VAL_1;
  wire [96 : 0] MUX_master_xactor_f_rd_addr$enq_1__VAL_1,
		MUX_master_xactor_f_rd_addr$enq_1__VAL_2,
		MUX_master_xactor_f_rd_addr$enq_1__VAL_3,
		MUX_master_xactor_f_rd_addr$enq_1__VAL_4,
		MUX_master_xactor_f_rd_addr$enq_1__VAL_5;
  wire [63 : 0] MUX_dw_output_ld_val$wset_1__VAL_3,
		MUX_rg_ld_val$write_1__VAL_2;
  wire [8 : 0] MUX_ram_word64_set$b_put_2__VAL_2,
	       MUX_ram_word64_set$b_put_2__VAL_4;
  wire [5 : 0] MUX_rg_cset_in_cache$write_1__VAL_1;
  wire [4 : 0] MUX_rg_state$write_1__VAL_11,
	       MUX_rg_state$write_1__VAL_13,
	       MUX_rg_state$write_1__VAL_14,
	       MUX_rg_state$write_1__VAL_15,
	       MUX_rg_state$write_1__VAL_17,
	       MUX_rg_state$write_1__VAL_2,
	       MUX_rg_state$write_1__VAL_4;
  wire [3 : 0] MUX_rg_exc_code$write_1__VAL_1, MUX_rg_exc_code$write_1__VAL_5;
  wire MUX_dw_output_ld_val$wset_1__SEL_1,
       MUX_dw_output_ld_val$wset_1__SEL_2,
       MUX_dw_output_ld_val$wset_1__SEL_3,
       MUX_dw_output_ld_val$wset_1__SEL_4,
       MUX_f_fabric_write_reqs$enq_1__SEL_2,
       MUX_master_xactor_f_rd_addr$enq_1__SEL_1,
       MUX_master_xactor_f_rd_addr$enq_1__SEL_2,
       MUX_master_xactor_f_rd_addr$enq_1__SEL_3,
       MUX_ram_state_and_ctag_cset$a_put_1__SEL_1,
       MUX_ram_state_and_ctag_cset$b_put_1__SEL_1,
       MUX_ram_word64_set$a_put_1__SEL_1,
       MUX_ram_word64_set$b_put_1__SEL_2,
       MUX_rg_error_during_refill$write_1__SEL_1,
       MUX_rg_exc_code$write_1__SEL_1,
       MUX_rg_exc_code$write_1__SEL_2,
       MUX_rg_exc_code$write_1__SEL_3,
       MUX_rg_exc_code$write_1__SEL_5,
       MUX_rg_exc_code$write_1__SEL_6,
       MUX_rg_exc_code$write_1__SEL_7,
       MUX_rg_exc_code$write_1__SEL_8,
       MUX_rg_ld_val$write_1__SEL_2,
       MUX_rg_lrsc_valid$write_1__SEL_2,
       MUX_rg_state$write_1__SEL_11,
       MUX_rg_state$write_1__SEL_17,
       MUX_rg_state$write_1__SEL_18,
       MUX_rg_state$write_1__SEL_3,
       MUX_tlb$insert_1__SEL_1,
       MUX_tlb$insert_1__SEL_2,
       MUX_tlb$insert_1__SEL_3,
       MUX_tlb$insert_1__SEL_4;

  // declarations used by system tasks
  // synopsys translate_off
  reg [31 : 0] v__h3294;
  reg [31 : 0] v__h4543;
  reg [31 : 0] v__h4642;
  reg [31 : 0] v__h4791;
  reg [31 : 0] v__h21326;
  reg [31 : 0] v__h25042;
  reg [31 : 0] v__h28554;
  reg [31 : 0] v__h29472;
  reg [31 : 0] v__h29229;
  reg [31 : 0] v__h29760;
  reg [31 : 0] v__h29872;
  reg [31 : 0] v__h29401;
  reg [31 : 0] v__h30505;
  reg [31 : 0] v__h30265;
  reg [31 : 0] v__h30905;
  reg [31 : 0] v__h30793;
  reg [31 : 0] v__h30434;
  reg [31 : 0] v__h31376;
  reg [31 : 0] v__h31447;
  reg [31 : 0] v__h31529;
  reg [31 : 0] v__h31305;
  reg [31 : 0] v__h31656;
  reg [31 : 0] v__h32347;
  reg [31 : 0] v__h32569;
  reg [31 : 0] v__h34960;
  reg [31 : 0] v__h35310;
  reg [31 : 0] v__h36410;
  reg [31 : 0] v__h36517;
  reg [31 : 0] v__h36622;
  reg [31 : 0] v__h36702;
  reg [31 : 0] v__h36912;
  reg [31 : 0] v__h37030;
  reg [31 : 0] v__h37324;
  reg [31 : 0] v__h37499;
  reg [31 : 0] v__h39758;
  reg [31 : 0] v__h37595;
  reg [31 : 0] v__h40365;
  reg [31 : 0] v__h40326;
  reg [31 : 0] v__h4069;
  reg [31 : 0] v__h40714;
  reg [31 : 0] v__h42089;
  reg [31 : 0] v__h3288;
  reg [31 : 0] v__h4063;
  reg [31 : 0] v__h4537;
  reg [31 : 0] v__h4636;
  reg [31 : 0] v__h4785;
  reg [31 : 0] v__h21320;
  reg [31 : 0] v__h25036;
  reg [31 : 0] v__h28548;
  reg [31 : 0] v__h29223;
  reg [31 : 0] v__h29395;
  reg [31 : 0] v__h29466;
  reg [31 : 0] v__h29754;
  reg [31 : 0] v__h29866;
  reg [31 : 0] v__h30259;
  reg [31 : 0] v__h30428;
  reg [31 : 0] v__h30499;
  reg [31 : 0] v__h30787;
  reg [31 : 0] v__h30899;
  reg [31 : 0] v__h31299;
  reg [31 : 0] v__h31370;
  reg [31 : 0] v__h31441;
  reg [31 : 0] v__h31523;
  reg [31 : 0] v__h31650;
  reg [31 : 0] v__h32341;
  reg [31 : 0] v__h32563;
  reg [31 : 0] v__h34954;
  reg [31 : 0] v__h35304;
  reg [31 : 0] v__h36404;
  reg [31 : 0] v__h36511;
  reg [31 : 0] v__h36616;
  reg [31 : 0] v__h36696;
  reg [31 : 0] v__h36906;
  reg [31 : 0] v__h37024;
  reg [31 : 0] v__h37318;
  reg [31 : 0] v__h37493;
  reg [31 : 0] v__h37589;
  reg [31 : 0] v__h39752;
  reg [31 : 0] v__h40320;
  reg [31 : 0] v__h40359;
  reg [31 : 0] v__h40708;
  reg [31 : 0] v__h42083;
  // synopsys translate_on

  // remaining internal signals
  reg [63 : 0] CASE_rg_addr_BITS_2_TO_0_0x0_result1146_0x4_re_ETC__q30,
	       CASE_rg_addr_BITS_2_TO_0_0x0_result6190_0x4_re_ETC__q35,
	       CASE_rg_addr_BITS_2_TO_0_0x0_result6255_0x4_re_ETC__q36,
	       CASE_rg_addr_BITS_2_TO_0_0x0_result9466_0x4_re_ETC__q51,
	       CASE_rg_f3_0b0_IF_rg_addr_5_BITS_2_TO_0_19_EQ__ETC__q53,
	       CASE_x1_avValue_pa058_BITS_2_TO_0_0x0_old_word_ETC__q31,
	       CASE_x1_avValue_pa058_BITS_2_TO_0_0x0_old_word_ETC__q34,
	       IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d756,
	       IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d765,
	       IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d824,
	       IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d833,
	       IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1205,
	       IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1225,
	       IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1314,
	       IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1334,
	       IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1344,
	       IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d613,
	       IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d633,
	       IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d643,
	       IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1189,
	       IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1217,
	       IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1298,
	       IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1326,
	       IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d597,
	       IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d625,
	       IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_5_BITS_2_ETC___d651,
	       IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_IF_rg_f3_15_E_ETC___d712,
	       _theResult_____2__h25564,
	       _theResult_____2__h37671,
	       _theResult___fst__h6561,
	       ld_val__h35419,
	       mem_req_wr_data_wdata__h3045,
	       n__h22492,
	       n__h25426,
	       new_ld_val__h37625,
	       old_word64__h22481,
	       w1__h25556,
	       w1__h37659,
	       w1__h37663;
  reg [7 : 0] mem_req_wr_data_wstrb__h3046;
  reg [2 : 0] value__h37211, x__h2866;
  reg CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_15_ETC__q29,
      IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d322,
      IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d328,
      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_OR_rg_ad_ETC___d239,
      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_OR_rg_ad_ETC___d247,
      IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b100_17__ETC___d261,
      IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b1_40_OR_ETC___d277,
      IF_rg_f3_15_EQ_0b0_16_THEN_NOT_rg_priv_4_ULE_0_ETC___d337;
  wire [63 : 0] IF_NOT_ram_state_and_ctag_cset_b_read__98_BIT__ETC___d776,
		IF_NOT_ram_state_and_ctag_cset_b_read__98_BIT__ETC___d844,
		IF_ram_state_and_ctag_cset_b_read__98_BIT_105__ETC___d775,
		IF_ram_state_and_ctag_cset_b_read__98_BIT_105__ETC___d843,
		IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_1_E_ETC___d659,
		IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_IF__ETC___d1345,
		IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_ram_ETC___d644,
		IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_rg_st_amo_val_ETC___d781,
		IF_rg_op_11_EQ_1_64_OR_rg_op_11_EQ_2_14_AND_rg_ETC___d853,
		_theResult___fst__h6147,
		_theResult___fst__h6218,
		_theResult___snd_fst__h3053,
		_theResult___snd_fst__h6149,
		_theResult___snd_fst__h6220,
		_theResult___snd_fst__h6790,
		cline_fabric_addr__h31709,
		lev_0_pte_pa__h30537,
		lev_0_pte_pa_w64_fa__h30539,
		lev_1_PTN_pa__h29502,
		lev_1_pte_pa__h29504,
		lev_1_pte_pa_w64_fa__h29506,
		lev_2_pte_pa__h28607,
		lev_2_pte_pa_w64_fa__h28609,
		new_st_val__h25262,
		new_st_val__h25568,
		new_st_val__h25659,
		new_st_val__h26639,
		new_st_val__h26643,
		new_st_val__h26647,
		new_st_val__h26651,
		new_st_val__h26656,
		new_st_val__h26662,
		new_st_val__h26667,
		new_st_val__h37675,
		new_st_val__h37766,
		new_st_val__h39626,
		new_st_val__h39630,
		new_st_val__h39634,
		new_st_val__h39638,
		new_st_val__h39643,
		new_st_val__h39649,
		new_st_val__h39654,
		new_value__h24132,
		new_value__h7705,
		pa___1__h6567,
		pa___1__h6616,
		pa___1__h6685,
		pte___1__h6839,
		pte___1__h6867,
		pte___2__h6559,
		result__h20414,
		result__h20442,
		result__h20470,
		result__h20498,
		result__h20526,
		result__h20554,
		result__h20582,
		result__h20610,
		result__h20655,
		result__h20683,
		result__h20711,
		result__h20739,
		result__h20767,
		result__h20795,
		result__h20823,
		result__h20851,
		result__h20896,
		result__h20924,
		result__h20952,
		result__h20980,
		result__h21021,
		result__h21049,
		result__h21077,
		result__h21105,
		result__h21146,
		result__h21174,
		result__h21213,
		result__h21241,
		result__h35479,
		result__h35509,
		result__h35536,
		result__h35563,
		result__h35590,
		result__h35617,
		result__h35644,
		result__h35671,
		result__h35715,
		result__h35742,
		result__h35769,
		result__h35796,
		result__h35823,
		result__h35850,
		result__h35877,
		result__h35904,
		result__h35948,
		result__h35975,
		result__h36002,
		result__h36029,
		result__h36069,
		result__h36096,
		result__h36123,
		result__h36150,
		result__h36190,
		result__h36217,
		result__h36255,
		result__h36282,
		result__h37854,
		result__h38762,
		result__h38790,
		result__h38818,
		result__h38846,
		result__h38874,
		result__h38902,
		result__h38930,
		result__h38975,
		result__h39003,
		result__h39031,
		result__h39059,
		result__h39087,
		result__h39115,
		result__h39143,
		result__h39171,
		result__h39216,
		result__h39244,
		result__h39272,
		result__h39300,
		result__h39341,
		result__h39369,
		result__h39397,
		result__h39425,
		result__h39466,
		result__h39494,
		result__h39533,
		result__h39561,
		satp_pa__h1898,
		value__h6884,
		vpn_0_pa__h30536,
		vpn_1_pa__h29503,
		vpn_2_pa__h28606,
		w1___1__h25627,
		w1___1__h37734,
		w2___1__h37735,
		w2__h37665,
		word64__h7577,
		x1_avValue_pa__h6058,
		x__h21713,
		x__h37654,
		x__h7728,
		y__h14058,
		y__h7729,
		y__h7743;
  wire [55 : 0] x__h29583, x__h4911, x__h6570, x__h6619, x__h6688;
  wire [31 : 0] IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_5_BITS_2_ETC__q32,
		ld_val5419_BITS_31_TO_0__q39,
		ld_val5419_BITS_63_TO_32__q46,
		master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3,
		master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10,
		rg_st_amo_val_BITS_31_TO_0__q33,
		w17659_BITS_31_TO_0__q52,
		word64577_BITS_31_TO_0__q17,
		word64577_BITS_63_TO_32__q24;
  wire [15 : 0] ld_val5419_BITS_15_TO_0__q38,
		ld_val5419_BITS_31_TO_16__q42,
		ld_val5419_BITS_47_TO_32__q45,
		ld_val5419_BITS_63_TO_48__q49,
		master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2,
		master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q6,
		master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9,
		master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13,
		word64577_BITS_15_TO_0__q16,
		word64577_BITS_31_TO_16__q20,
		word64577_BITS_47_TO_32__q23,
		word64577_BITS_63_TO_48__q27;
  wire [7 : 0] ld_val5419_BITS_15_TO_8__q40,
	       ld_val5419_BITS_23_TO_16__q41,
	       ld_val5419_BITS_31_TO_24__q43,
	       ld_val5419_BITS_39_TO_32__q44,
	       ld_val5419_BITS_47_TO_40__q47,
	       ld_val5419_BITS_55_TO_48__q48,
	       ld_val5419_BITS_63_TO_56__q50,
	       ld_val5419_BITS_7_TO_0__q37,
	       master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1,
	       master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4,
	       master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q5,
	       master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q7,
	       master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q8,
	       master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11,
	       master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12,
	       master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14,
	       strobe64__h2983,
	       strobe64__h2985,
	       strobe64__h2987,
	       word64577_BITS_15_TO_8__q18,
	       word64577_BITS_23_TO_16__q19,
	       word64577_BITS_31_TO_24__q21,
	       word64577_BITS_39_TO_32__q22,
	       word64577_BITS_47_TO_40__q25,
	       word64577_BITS_55_TO_48__q26,
	       word64577_BITS_63_TO_56__q28,
	       word64577_BITS_7_TO_0__q15;
  wire [5 : 0] shift_bits__h2833;
  wire [4 : 0] IF_NOT_ram_state_and_ctag_cset_b_read__98_BIT__ETC___d438,
	       IF_rg_op_11_EQ_0_12_OR_rg_op_11_EQ_2_14_AND_rg_ETC___d440,
	       IF_rg_op_11_EQ_1_64_OR_rg_op_11_EQ_2_14_AND_rg_ETC___d439,
	       IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_T_ETC___d442;
  wire [3 : 0] access_exc_code__h2602,
	       b__h28508,
	       exc_code___1__h6459,
	       x1_avValue_exc_code__h6059;
  wire [1 : 0] tmp__h31848, tmp__h31849;
  wire IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d332,
       IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_NOT_ETC___d253,
       IF_rg_op_11_EQ_0_12_OR_rg_op_11_EQ_2_14_AND_rg_ETC___d346,
       IF_rg_op_11_EQ_1_64_OR_rg_op_11_EQ_2_14_AND_rg_ETC___d345,
       IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_T_ETC___d482,
       NOT_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS__ETC___d321,
       NOT_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS__ETC___d327,
       NOT_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS__ETC___d331,
       NOT_cfg_verbosity_read__9_ULE_2_103___d1104,
       NOT_cfg_verbosity_read__9_ULT_2_46___d447,
       NOT_dmem_not_imem_26_AND_rg_op_11_EQ_0_12_OR_r_ETC___d382,
       NOT_dmem_not_imem_26_OR_NOT_rg_op_11_EQ_0_12_1_ETC___d133,
       NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d476,
       NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d672,
       NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d684,
       NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d689,
       NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d697,
       NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d706,
       NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d719,
       NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d856,
       NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d874,
       NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d920,
       NOT_master_xactor_f_rd_data_first__38_BITS_2_T_ETC___d1025,
       NOT_master_xactor_f_rd_data_first__38_BITS_2_T_ETC___d962,
       NOT_master_xactor_f_rd_data_first__38_BIT_3_42_ETC___d1031,
       NOT_master_xactor_f_rd_data_first__38_BIT_3_42_ETC___d969,
       NOT_ram_state_and_ctag_cset_b_read__98_BIT_105_ETC___d234,
       NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d233,
       NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d263,
       NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d283,
       NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d344,
       NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d484,
       NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d687,
       NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d694,
       NOT_req_f3_BITS_1_TO_0_430_EQ_0b0_431_432_AND__ETC___d1451,
       NOT_rg_op_11_EQ_0_12_13_AND_NOT_rg_op_11_EQ_2__ETC___d433,
       NOT_rg_op_11_EQ_1_64_90_AND_NOT_rg_op_11_EQ_2__ETC___d716,
       NOT_rg_op_11_EQ_1_64_90_AND_ram_state_and_ctag_ETC___d703,
       NOT_rg_op_11_EQ_2_14_15_OR_NOT_rg_amo_funct7_1_ETC___d714,
       NOT_rg_op_11_EQ_2_14_15_OR_NOT_rg_amo_funct7_1_ETC___d877,
       NOT_rg_op_11_EQ_2_14_15_OR_NOT_rg_amo_funct7_1_ETC___d883,
       NOT_rg_op_11_EQ_2_14_15_OR_NOT_rg_amo_funct7_1_ETC___d889,
       NOT_rg_priv_4_EQ_0b0_01_75_OR_tlb_lookup_rg_sa_ETC___d389,
       NOT_rg_priv_4_EQ_0b0_01_75_OR_tlb_lookup_rg_sa_ETC___d412,
       NOT_rg_priv_4_EQ_0b0_01_75_OR_tlb_lookup_rg_sa_ETC___d450,
       NOT_rg_priv_4_EQ_0b0_01_75_OR_tlb_lookup_rg_sa_ETC___d666,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d167,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d348,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d394,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d409,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d461,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d462,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d469,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d472,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d478,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d499,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d505,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d506,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d669,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d674,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d680,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d686,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d691,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d699,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d702,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d708,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d721,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d851,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d852,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d858,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d864,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d870,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d876,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d881,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d882,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d887,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d893,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d894,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d899,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d900,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d906,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d911,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d912,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d917,
       NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d922,
       NOT_tlb_lookup_rg_satp_7_BITS_59_TO_44_4_rg_ad_ETC___d148,
       NOT_tlb_lookup_rg_satp_7_BITS_59_TO_44_4_rg_ad_ETC___d164,
       cfg_verbosity_read__9_ULE_1___d40,
       dmem_not_imem_AND_rg_op_11_EQ_0_12_OR_rg_op_11_ETC___d384,
       dmem_not_imem_OR_NOT_rg_op_11_EQ_0_12_13_AND_N_ETC___d125,
       lrsc_result__h21703,
       master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1004,
       master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1012,
       master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1016,
       master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1047,
       master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1051,
       master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1057,
       master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1082,
       master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d978,
       master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988,
       ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209,
       ram_state_and_ctag_cset_b_read__98_BITS_51_TO__ETC___d203,
       ram_state_and_ctag_cset_b_read__98_BIT_52_99_A_ETC___d481,
       ram_state_and_ctag_cset_b_read__98_BIT_52_99_A_ETC___d492,
       ram_state_and_ctag_cset_b_read__98_BIT_52_99_A_ETC___d670,
       ram_state_and_ctag_cset_b_read__98_BIT_52_99_A_ETC___d913,
       req_f3_BITS_1_TO_0_430_EQ_0b0_431_OR_req_f3_BI_ETC___d1460,
       rg_amo_funct7_16_BITS_6_TO_2_17_EQ_0b10_18_AND_ETC___d677,
       rg_amo_funct7_16_BITS_6_TO_2_17_EQ_0b1_86_OR_I_ETC___d342,
       rg_lrsc_pa_68_EQ_IF_rg_priv_4_ULE_0b1_5_AND_rg_ETC___d269,
       rg_op_11_EQ_0_12_OR_rg_op_11_EQ_2_14_AND_rg_am_ETC___d428,
       rg_op_11_EQ_0_12_OR_rg_op_11_EQ_2_14_AND_rg_am_ETC___d465,
       rg_op_11_EQ_0_12_OR_rg_op_11_EQ_2_14_AND_rg_am_ETC___d486,
       rg_op_11_EQ_0_12_OR_rg_op_11_EQ_2_14_AND_rg_am_ETC___d496,
       rg_op_11_EQ_0_12_OR_rg_op_11_EQ_2_14_AND_rg_am_ETC___d500,
       rg_op_11_EQ_1_64_OR_rg_op_11_EQ_2_14_AND_rg_am_ETC___d494,
       rg_op_11_EQ_1_64_OR_rg_op_11_EQ_2_14_AND_rg_am_ETC___d717,
       rg_op_11_EQ_1_64_OR_rg_op_11_EQ_2_14_AND_rg_am_ETC___d847,
       rg_op_11_EQ_2_14_AND_rg_amo_funct7_16_BITS_6_T_ETC___d285,
       rg_priv_4_EQ_0b0_01_AND_NOT_tlb_lookup_rg_satp_ETC___d142,
       rg_priv_4_EQ_0b0_01_AND_NOT_tlb_lookup_rg_satp_ETC___d155,
       rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d151,
       rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d350,
       rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d397,
       rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d419,
       rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d436,
       rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d437,
       rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d455,
       rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d458,
       rg_priv_4_ULE_0b1___d85,
       rg_state_9_EQ_13_145_AND_rg_op_11_EQ_0_12_OR_r_ETC___d1147,
       tlb_lookup_rg_satp_7_BITS_59_TO_44_4_rg_addr_5_ETC___d131,
       tlb_lookup_rg_satp_7_BITS_59_TO_44_4_rg_addr_5_ETC___d391,
       y__h6385;

  // action method set_verbosity
  assign RDY_set_verbosity = 1'd1 ;
  assign CAN_FIRE_set_verbosity = 1'd1 ;
  assign WILL_FIRE_set_verbosity = EN_set_verbosity ;

  // action method server_reset_request_put
  assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ;
  assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ;
  assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;

  // action method server_reset_response_get
  assign RDY_server_reset_response_get =
	     !f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
  assign CAN_FIRE_server_reset_response_get =
	     !f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
  assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;

  // action method req
  assign CAN_FIRE_req = 1'd1 ;
  assign WILL_FIRE_req = EN_req ;

  // value method valid
  assign valid = dw_valid$whas ;

  // value method addr
  assign addr = rg_addr ;

  // value method word64
  always@(MUX_dw_output_ld_val$wset_1__SEL_1 or
	  ld_val__h35419 or
	  MUX_dw_output_ld_val$wset_1__SEL_2 or
	  new_ld_val__h37625 or
	  MUX_dw_output_ld_val$wset_1__SEL_3 or
	  MUX_dw_output_ld_val$wset_1__VAL_3 or
	  MUX_dw_output_ld_val$wset_1__SEL_4 or rg_ld_val)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_dw_output_ld_val$wset_1__SEL_1: word64 = ld_val__h35419;
      MUX_dw_output_ld_val$wset_1__SEL_2: word64 = new_ld_val__h37625;
      MUX_dw_output_ld_val$wset_1__SEL_3:
	  word64 = MUX_dw_output_ld_val$wset_1__VAL_3;
      MUX_dw_output_ld_val$wset_1__SEL_4: word64 = rg_ld_val;
      default: word64 = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end

  // value method st_amo_val
  assign st_amo_val =
	     MUX_dw_output_ld_val$wset_1__SEL_3 ? 64'd0 : rg_st_amo_val ;

  // value method exc
  assign exc = rg_state == 5'd4 ;

  // value method exc_code
  assign exc_code = rg_exc_code ;

  // action method server_flush_request_put
  assign RDY_server_flush_request_put = f_reset_reqs$FULL_N ;
  assign CAN_FIRE_server_flush_request_put = f_reset_reqs$FULL_N ;
  assign WILL_FIRE_server_flush_request_put = EN_server_flush_request_put ;

  // action method server_flush_response_get
  assign RDY_server_flush_response_get =
	     f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
  assign CAN_FIRE_server_flush_response_get =
	     f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
  assign WILL_FIRE_server_flush_response_get = EN_server_flush_response_get ;

  // action method tlb_flush
  assign RDY_tlb_flush = 1'd1 ;
  assign CAN_FIRE_tlb_flush = 1'd1 ;
  assign WILL_FIRE_tlb_flush = EN_tlb_flush ;

  // value method mem_master_m_awvalid
  assign mem_master_awvalid = master_xactor_f_wr_addr$EMPTY_N ;

  // value method mem_master_m_awid
  assign mem_master_awid = master_xactor_f_wr_addr$D_OUT[96:93] ;

  // value method mem_master_m_awaddr
  assign mem_master_awaddr = master_xactor_f_wr_addr$D_OUT[92:29] ;

  // value method mem_master_m_awlen
  assign mem_master_awlen = master_xactor_f_wr_addr$D_OUT[28:21] ;

  // value method mem_master_m_awsize
  assign mem_master_awsize = master_xactor_f_wr_addr$D_OUT[20:18] ;

  // value method mem_master_m_awburst
  assign mem_master_awburst = master_xactor_f_wr_addr$D_OUT[17:16] ;

  // value method mem_master_m_awlock
  assign mem_master_awlock = master_xactor_f_wr_addr$D_OUT[15] ;

  // value method mem_master_m_awcache
  assign mem_master_awcache = master_xactor_f_wr_addr$D_OUT[14:11] ;

  // value method mem_master_m_awprot
  assign mem_master_awprot = master_xactor_f_wr_addr$D_OUT[10:8] ;

  // value method mem_master_m_awqos
  assign mem_master_awqos = master_xactor_f_wr_addr$D_OUT[7:4] ;

  // value method mem_master_m_awregion
  assign mem_master_awregion = master_xactor_f_wr_addr$D_OUT[3:0] ;

  // action method mem_master_m_awready
  assign CAN_FIRE_mem_master_m_awready = 1'd1 ;
  assign WILL_FIRE_mem_master_m_awready = 1'd1 ;

  // value method mem_master_m_wvalid
  assign mem_master_wvalid = master_xactor_f_wr_data$EMPTY_N ;

  // value method mem_master_m_wdata
  assign mem_master_wdata = master_xactor_f_wr_data$D_OUT[72:9] ;

  // value method mem_master_m_wstrb
  assign mem_master_wstrb = master_xactor_f_wr_data$D_OUT[8:1] ;

  // value method mem_master_m_wlast
  assign mem_master_wlast = master_xactor_f_wr_data$D_OUT[0] ;

  // action method mem_master_m_wready
  assign CAN_FIRE_mem_master_m_wready = 1'd1 ;
  assign WILL_FIRE_mem_master_m_wready = 1'd1 ;

  // action method mem_master_m_bvalid
  assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ;
  assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ;

  // value method mem_master_m_bready
  assign mem_master_bready = master_xactor_f_wr_resp$FULL_N ;

  // value method mem_master_m_arvalid
  assign mem_master_arvalid = master_xactor_f_rd_addr$EMPTY_N ;

  // value method mem_master_m_arid
  assign mem_master_arid = master_xactor_f_rd_addr$D_OUT[96:93] ;

  // value method mem_master_m_araddr
  assign mem_master_araddr = master_xactor_f_rd_addr$D_OUT[92:29] ;

  // value method mem_master_m_arlen
  assign mem_master_arlen = master_xactor_f_rd_addr$D_OUT[28:21] ;

  // value method mem_master_m_arsize
  assign mem_master_arsize = master_xactor_f_rd_addr$D_OUT[20:18] ;

  // value method mem_master_m_arburst
  assign mem_master_arburst = master_xactor_f_rd_addr$D_OUT[17:16] ;

  // value method mem_master_m_arlock
  assign mem_master_arlock = master_xactor_f_rd_addr$D_OUT[15] ;

  // value method mem_master_m_arcache
  assign mem_master_arcache = master_xactor_f_rd_addr$D_OUT[14:11] ;

  // value method mem_master_m_arprot
  assign mem_master_arprot = master_xactor_f_rd_addr$D_OUT[10:8] ;

  // value method mem_master_m_arqos
  assign mem_master_arqos = master_xactor_f_rd_addr$D_OUT[7:4] ;

  // value method mem_master_m_arregion
  assign mem_master_arregion = master_xactor_f_rd_addr$D_OUT[3:0] ;

  // action method mem_master_m_arready
  assign CAN_FIRE_mem_master_m_arready = 1'd1 ;
  assign WILL_FIRE_mem_master_m_arready = 1'd1 ;

  // action method mem_master_m_rvalid
  assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ;
  assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ;

  // value method mem_master_m_rready
  assign mem_master_rready = master_xactor_f_rd_data$FULL_N ;

  // submodule f_fabric_write_reqs
  FIFO2 #(.width(32'd131), .guarded(32'd1)) f_fabric_write_reqs(.RST(RST_N),
								.CLK(CLK),
								.D_IN(f_fabric_write_reqs$D_IN),
								.ENQ(f_fabric_write_reqs$ENQ),
								.DEQ(f_fabric_write_reqs$DEQ),
								.CLR(f_fabric_write_reqs$CLR),
								.D_OUT(f_fabric_write_reqs$D_OUT),
								.FULL_N(f_fabric_write_reqs$FULL_N),
								.EMPTY_N(f_fabric_write_reqs$EMPTY_N));

  // submodule f_pte_writebacks
  FIFO2 #(.width(32'd128), .guarded(32'd1)) f_pte_writebacks(.RST(RST_N),
							     .CLK(CLK),
							     .D_IN(f_pte_writebacks$D_IN),
							     .ENQ(f_pte_writebacks$ENQ),
							     .DEQ(f_pte_writebacks$DEQ),
							     .CLR(f_pte_writebacks$CLR),
							     .D_OUT(f_pte_writebacks$D_OUT),
							     .FULL_N(f_pte_writebacks$FULL_N),
							     .EMPTY_N(f_pte_writebacks$EMPTY_N));

  // submodule f_reset_reqs
  FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N),
						       .CLK(CLK),
						       .D_IN(f_reset_reqs$D_IN),
						       .ENQ(f_reset_reqs$ENQ),
						       .DEQ(f_reset_reqs$DEQ),
						       .CLR(f_reset_reqs$CLR),
						       .D_OUT(f_reset_reqs$D_OUT),
						       .FULL_N(f_reset_reqs$FULL_N),
						       .EMPTY_N(f_reset_reqs$EMPTY_N));

  // submodule f_reset_rsps
  FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N),
						       .CLK(CLK),
						       .D_IN(f_reset_rsps$D_IN),
						       .ENQ(f_reset_rsps$ENQ),
						       .DEQ(f_reset_rsps$DEQ),
						       .CLR(f_reset_rsps$CLR),
						       .D_OUT(f_reset_rsps$D_OUT),
						       .FULL_N(f_reset_rsps$FULL_N),
						       .EMPTY_N(f_reset_rsps$EMPTY_N));

  // submodule master_xactor_f_rd_addr
  FIFO2 #(.width(32'd97),
	  .guarded(32'd1)) master_xactor_f_rd_addr(.RST(RST_N),
						   .CLK(CLK),
						   .D_IN(master_xactor_f_rd_addr$D_IN),
						   .ENQ(master_xactor_f_rd_addr$ENQ),
						   .DEQ(master_xactor_f_rd_addr$DEQ),
						   .CLR(master_xactor_f_rd_addr$CLR),
						   .D_OUT(master_xactor_f_rd_addr$D_OUT),
						   .FULL_N(master_xactor_f_rd_addr$FULL_N),
						   .EMPTY_N(master_xactor_f_rd_addr$EMPTY_N));

  // submodule master_xactor_f_rd_data
  FIFO2 #(.width(32'd71),
	  .guarded(32'd1)) master_xactor_f_rd_data(.RST(RST_N),
						   .CLK(CLK),
						   .D_IN(master_xactor_f_rd_data$D_IN),
						   .ENQ(master_xactor_f_rd_data$ENQ),
						   .DEQ(master_xactor_f_rd_data$DEQ),
						   .CLR(master_xactor_f_rd_data$CLR),
						   .D_OUT(master_xactor_f_rd_data$D_OUT),
						   .FULL_N(master_xactor_f_rd_data$FULL_N),
						   .EMPTY_N(master_xactor_f_rd_data$EMPTY_N));

  // submodule master_xactor_f_wr_addr
  FIFO2 #(.width(32'd97),
	  .guarded(32'd1)) master_xactor_f_wr_addr(.RST(RST_N),
						   .CLK(CLK),
						   .D_IN(master_xactor_f_wr_addr$D_IN),
						   .ENQ(master_xactor_f_wr_addr$ENQ),
						   .DEQ(master_xactor_f_wr_addr$DEQ),
						   .CLR(master_xactor_f_wr_addr$CLR),
						   .D_OUT(master_xactor_f_wr_addr$D_OUT),
						   .FULL_N(master_xactor_f_wr_addr$FULL_N),
						   .EMPTY_N(master_xactor_f_wr_addr$EMPTY_N));

  // submodule master_xactor_f_wr_data
  FIFO2 #(.width(32'd73),
	  .guarded(32'd1)) master_xactor_f_wr_data(.RST(RST_N),
						   .CLK(CLK),
						   .D_IN(master_xactor_f_wr_data$D_IN),
						   .ENQ(master_xactor_f_wr_data$ENQ),
						   .DEQ(master_xactor_f_wr_data$DEQ),
						   .CLR(master_xactor_f_wr_data$CLR),
						   .D_OUT(master_xactor_f_wr_data$D_OUT),
						   .FULL_N(master_xactor_f_wr_data$FULL_N),
						   .EMPTY_N(master_xactor_f_wr_data$EMPTY_N));

  // submodule master_xactor_f_wr_resp
  FIFO2 #(.width(32'd6), .guarded(32'd1)) master_xactor_f_wr_resp(.RST(RST_N),
								  .CLK(CLK),
								  .D_IN(master_xactor_f_wr_resp$D_IN),
								  .ENQ(master_xactor_f_wr_resp$ENQ),
								  .DEQ(master_xactor_f_wr_resp$DEQ),
								  .CLR(master_xactor_f_wr_resp$CLR),
								  .D_OUT(master_xactor_f_wr_resp$D_OUT),
								  .FULL_N(master_xactor_f_wr_resp$FULL_N),
								  .EMPTY_N(master_xactor_f_wr_resp$EMPTY_N));

  // submodule ram_state_and_ctag_cset
  BRAM2 #(.PIPELINED(1'd0),
	  .ADDR_WIDTH(32'd6),
	  .DATA_WIDTH(32'd106),
	  .MEMSIZE(7'd64)) ram_state_and_ctag_cset(.CLKA(CLK),
						   .CLKB(CLK),
						   .ADDRA(ram_state_and_ctag_cset$ADDRA),
						   .ADDRB(ram_state_and_ctag_cset$ADDRB),
						   .DIA(ram_state_and_ctag_cset$DIA),
						   .DIB(ram_state_and_ctag_cset$DIB),
						   .WEA(ram_state_and_ctag_cset$WEA),
						   .WEB(ram_state_and_ctag_cset$WEB),
						   .ENA(ram_state_and_ctag_cset$ENA),
						   .ENB(ram_state_and_ctag_cset$ENB),
						   .DOA(),
						   .DOB(ram_state_and_ctag_cset$DOB));

  // submodule ram_word64_set
  BRAM2 #(.PIPELINED(1'd0),
	  .ADDR_WIDTH(32'd9),
	  .DATA_WIDTH(32'd128),
	  .MEMSIZE(10'd512)) ram_word64_set(.CLKA(CLK),
					    .CLKB(CLK),
					    .ADDRA(ram_word64_set$ADDRA),
					    .ADDRB(ram_word64_set$ADDRB),
					    .DIA(ram_word64_set$DIA),
					    .DIB(ram_word64_set$DIB),
					    .WEA(ram_word64_set$WEA),
					    .WEB(ram_word64_set$WEB),
					    .ENA(ram_word64_set$ENA),
					    .ENB(ram_word64_set$ENB),
					    .DOA(),
					    .DOB(ram_word64_set$DOB));

  // submodule soc_map
  mkSoC_Map soc_map(.CLK(CLK),
		    .RST_N(RST_N),
		    .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
		    .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
		    .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
		    .m_near_mem_io_addr_base(),
		    .m_near_mem_io_addr_size(),
		    .m_near_mem_io_addr_lim(),
		    .m_plic_addr_base(),
		    .m_plic_addr_size(),
		    .m_plic_addr_lim(),
		    .m_uart0_addr_base(),
		    .m_uart0_addr_size(),
		    .m_uart0_addr_lim(),
		    .m_boot_rom_addr_base(),
		    .m_boot_rom_addr_size(),
		    .m_boot_rom_addr_lim(),
		    .m_mem0_controller_addr_base(),
		    .m_mem0_controller_addr_size(),
		    .m_mem0_controller_addr_lim(),
		    .m_tcm_addr_base(),
		    .m_tcm_addr_size(),
		    .m_tcm_addr_lim(),
		    .m_is_mem_addr(soc_map$m_is_mem_addr),
		    .m_is_IO_addr(),
		    .m_is_near_mem_IO_addr(),
		    .m_pc_reset_value(),
		    .m_mtvec_reset_value(),
		    .m_nmivec_reset_value());

  // submodule tlb
  mkTLB #(.dmem_not_imem(dmem_not_imem)) tlb(.CLK(CLK),
					     .RST_N(RST_N),
					     .insert_asid(tlb$insert_asid),
					     .insert_level(tlb$insert_level),
					     .insert_pte(tlb$insert_pte),
					     .insert_pte_pa(tlb$insert_pte_pa),
					     .insert_vpn(tlb$insert_vpn),
					     .lookup_asid(tlb$lookup_asid),
					     .lookup_vpn(tlb$lookup_vpn),
					     .EN_flush(tlb$EN_flush),
					     .EN_insert(tlb$EN_insert),
					     .RDY_flush(),
					     .lookup(tlb$lookup),
					     .RDY_lookup(tlb$RDY_lookup),
					     .RDY_insert(tlb$RDY_insert));

  // rule RL_rl_fabric_send_write_req
  assign CAN_FIRE_RL_rl_fabric_send_write_req =
	     f_fabric_write_reqs$EMPTY_N && master_xactor_f_wr_addr$FULL_N &&
	     master_xactor_f_wr_data$FULL_N ;
  assign WILL_FIRE_RL_rl_fabric_send_write_req =
	     CAN_FIRE_RL_rl_fabric_send_write_req ;

  // rule RL_rl_reset
  assign CAN_FIRE_RL_rl_reset =
	     (rg_cset_in_cache != 6'd63 ||
	      f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N) &&
	     rg_state == 5'd1 ;
  assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ;

  // rule RL_rl_probe_and_immed_rsp
  assign CAN_FIRE_RL_rl_probe_and_immed_rsp =
	     (cfg_verbosity_read__9_ULE_1___d40 || tlb$RDY_lookup) &&
	     (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	      tlb$RDY_lookup) &&
	     rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d350 &&
	     rg_state == 5'd3 ;
  assign WILL_FIRE_RL_rl_probe_and_immed_rsp =
	     CAN_FIRE_RL_rl_probe_and_immed_rsp &&
	     !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_start_tlb_refill
  assign CAN_FIRE_RL_rl_start_tlb_refill =
	     master_xactor_f_rd_addr$FULL_N && rg_state == 5'd5 &&
	     b__h28508 == 4'd0 ;
  assign WILL_FIRE_RL_rl_start_tlb_refill =
	     CAN_FIRE_RL_rl_start_tlb_refill && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_ptw_level_2
  assign CAN_FIRE_RL_rl_ptw_level_2 =
	     master_xactor_f_rd_data$EMPTY_N &&
	     NOT_master_xactor_f_rd_data_first__38_BITS_2_T_ETC___d962 &&
	     rg_state == 5'd6 ;
  assign WILL_FIRE_RL_rl_ptw_level_2 =
	     CAN_FIRE_RL_rl_ptw_level_2 && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_ptw_level_1
  assign CAN_FIRE_RL_rl_ptw_level_1 =
	     master_xactor_f_rd_data$EMPTY_N &&
	     NOT_master_xactor_f_rd_data_first__38_BITS_2_T_ETC___d1025 &&
	     rg_state == 5'd7 ;
  assign WILL_FIRE_RL_rl_ptw_level_1 =
	     CAN_FIRE_RL_rl_ptw_level_1 && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_ptw_level_0
  assign CAN_FIRE_RL_rl_ptw_level_0 =
	     master_xactor_f_rd_data$EMPTY_N &&
	     (master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	      !master_xactor_f_rd_data$D_OUT[3] ||
	      !master_xactor_f_rd_data$D_OUT[4] &&
	      master_xactor_f_rd_data$D_OUT[5] ||
	      !master_xactor_f_rd_data$D_OUT[6] &&
	      !master_xactor_f_rd_data$D_OUT[4] ||
	      tlb$RDY_insert) &&
	     rg_state == 5'd8 ;
  assign WILL_FIRE_RL_rl_ptw_level_0 =
	     CAN_FIRE_RL_rl_ptw_level_0 && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_start_cache_refill
  assign CAN_FIRE_RL_rl_start_cache_refill =
	     master_xactor_f_rd_addr$FULL_N && rg_state == 5'd9 &&
	     b__h28508 == 4'd0 ;
  assign WILL_FIRE_RL_rl_start_cache_refill =
	     CAN_FIRE_RL_rl_start_cache_refill &&
	     !WILL_FIRE_RL_rl_start_reset &&
	     !EN_req ;

  // rule RL_rl_cache_refill_rsps_loop
  assign CAN_FIRE_RL_rl_cache_refill_rsps_loop =
	     master_xactor_f_rd_data$EMPTY_N && rg_state == 5'd10 ;
  assign WILL_FIRE_RL_rl_cache_refill_rsps_loop =
	     CAN_FIRE_RL_rl_cache_refill_rsps_loop &&
	     !WILL_FIRE_RL_rl_start_reset &&
	     !EN_req ;

  // rule RL_rl_rereq
  assign CAN_FIRE_RL_rl_rereq = rg_state == 5'd11 ;
  assign WILL_FIRE_RL_rl_rereq =
	     CAN_FIRE_RL_rl_rereq && !WILL_FIRE_RL_rl_start_reset && !EN_req ;

  // rule RL_rl_ST_AMO_response
  assign CAN_FIRE_RL_rl_ST_AMO_response = rg_state == 5'd12 ;
  assign WILL_FIRE_RL_rl_ST_AMO_response = CAN_FIRE_RL_rl_ST_AMO_response ;

  // rule RL_rl_io_read_req
  assign CAN_FIRE_RL_rl_io_read_req =
	     master_xactor_f_rd_addr$FULL_N &&
	     rg_state_9_EQ_13_145_AND_rg_op_11_EQ_0_12_OR_r_ETC___d1147 ;
  assign WILL_FIRE_RL_rl_io_read_req =
	     CAN_FIRE_RL_rl_io_read_req && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_io_read_rsp
  assign CAN_FIRE_RL_rl_io_read_rsp =
	     master_xactor_f_rd_data$EMPTY_N && rg_state == 5'd14 ;
  assign WILL_FIRE_RL_rl_io_read_rsp =
	     CAN_FIRE_RL_rl_io_read_rsp && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_maintain_io_read_rsp
  assign CAN_FIRE_RL_rl_maintain_io_read_rsp = rg_state == 5'd15 ;
  assign WILL_FIRE_RL_rl_maintain_io_read_rsp =
	     CAN_FIRE_RL_rl_maintain_io_read_rsp ;

  // rule RL_rl_io_write_req
  assign CAN_FIRE_RL_rl_io_write_req =
	     f_fabric_write_reqs$FULL_N && rg_state == 5'd13 &&
	     rg_op == 2'd1 ;
  assign WILL_FIRE_RL_rl_io_write_req =
	     CAN_FIRE_RL_rl_io_write_req && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_io_AMO_SC_req
  assign CAN_FIRE_RL_rl_io_AMO_SC_req =
	     rg_state == 5'd13 && rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00011 ;
  assign WILL_FIRE_RL_rl_io_AMO_SC_req =
	     CAN_FIRE_RL_rl_io_AMO_SC_req && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_io_AMO_op_req
  assign CAN_FIRE_RL_rl_io_AMO_op_req =
	     master_xactor_f_rd_addr$FULL_N && rg_state == 5'd13 &&
	     rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] != 5'b00010 &&
	     rg_amo_funct7[6:2] != 5'b00011 ;
  assign WILL_FIRE_RL_rl_io_AMO_op_req =
	     CAN_FIRE_RL_rl_io_AMO_op_req && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_writeback_updated_PTE
  assign CAN_FIRE_RL_rl_writeback_updated_PTE =
	     f_pte_writebacks$EMPTY_N && f_fabric_write_reqs$FULL_N ;
  assign WILL_FIRE_RL_rl_writeback_updated_PTE =
	     CAN_FIRE_RL_rl_writeback_updated_PTE &&
	     !WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	     !WILL_FIRE_RL_rl_io_write_req &&
	     !WILL_FIRE_RL_rl_probe_and_immed_rsp ;

  // rule RL_rl_io_AMO_read_rsp
  assign CAN_FIRE_RL_rl_io_AMO_read_rsp =
	     master_xactor_f_rd_data$EMPTY_N &&
	     (master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	      f_fabric_write_reqs$FULL_N) &&
	     rg_state == 5'd16 ;
  assign WILL_FIRE_RL_rl_io_AMO_read_rsp =
	     CAN_FIRE_RL_rl_io_AMO_read_rsp && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_discard_write_rsp
  assign CAN_FIRE_RL_rl_discard_write_rsp =
	     b__h28508 != 4'd0 && master_xactor_f_wr_resp$EMPTY_N ;
  assign WILL_FIRE_RL_rl_discard_write_rsp =
	     CAN_FIRE_RL_rl_discard_write_rsp ;

  // rule RL_rl_drive_exception_rsp
  assign CAN_FIRE_RL_rl_drive_exception_rsp = rg_state == 5'd4 ;
  assign WILL_FIRE_RL_rl_drive_exception_rsp = rg_state == 5'd4 ;

  // rule RL_rl_start_reset
  assign CAN_FIRE_RL_rl_start_reset = MUX_rg_state$write_1__SEL_3 ;
  assign WILL_FIRE_RL_rl_start_reset = MUX_rg_state$write_1__SEL_3 ;

  // inputs to muxes for submodule ports
  assign MUX_dw_output_ld_val$wset_1__SEL_1 =
	     WILL_FIRE_RL_rl_io_read_rsp &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
  assign MUX_dw_output_ld_val$wset_1__SEL_2 =
	     WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
  assign MUX_dw_output_ld_val$wset_1__SEL_3 =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d506 ;
  assign MUX_dw_output_ld_val$wset_1__SEL_4 =
	     WILL_FIRE_RL_rl_maintain_io_read_rsp ||
	     WILL_FIRE_RL_rl_ST_AMO_response ;
  assign MUX_f_fabric_write_reqs$enq_1__SEL_2 =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d852 ;
  assign MUX_master_xactor_f_rd_addr$enq_1__SEL_1 =
	     WILL_FIRE_RL_rl_ptw_level_2 &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     !master_xactor_f_rd_data$D_OUT[5] &&
	     !master_xactor_f_rd_data$D_OUT[6] &&
	     !master_xactor_f_rd_data$D_OUT[4] ;
  assign MUX_master_xactor_f_rd_addr$enq_1__SEL_2 =
	     WILL_FIRE_RL_rl_ptw_level_1 &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     !master_xactor_f_rd_data$D_OUT[5] &&
	     !master_xactor_f_rd_data$D_OUT[6] &&
	     !master_xactor_f_rd_data$D_OUT[4] ;
  assign MUX_master_xactor_f_rd_addr$enq_1__SEL_3 =
	     WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req ;
  assign MUX_ram_state_and_ctag_cset$a_put_1__SEL_1 =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     rg_word64_set_in_cache[2:0] == 3'd0 &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
  assign MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 =
	     EN_req &&
	     req_f3_BITS_1_TO_0_430_EQ_0b0_431_OR_req_f3_BI_ETC___d1460 ;
  assign MUX_ram_word64_set$a_put_1__SEL_1 =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
  assign MUX_ram_word64_set$b_put_1__SEL_2 =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     rg_word64_set_in_cache[2:0] != 3'd7 ;
  assign MUX_rg_error_during_refill$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
  assign MUX_rg_exc_code$write_1__SEL_1 =
	     EN_req &&
	     NOT_req_f3_BITS_1_TO_0_430_EQ_0b0_431_432_AND__ETC___d1451 ;
  assign MUX_rg_exc_code$write_1__SEL_2 =
	     WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
  assign MUX_rg_exc_code$write_1__SEL_3 =
	     WILL_FIRE_RL_rl_io_read_rsp &&
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
  assign MUX_rg_exc_code$write_1__SEL_5 =
	     WILL_FIRE_RL_rl_ptw_level_0 &&
	     (!master_xactor_f_rd_data$D_OUT[3] ||
	      !master_xactor_f_rd_data$D_OUT[4] &&
	      master_xactor_f_rd_data$D_OUT[5] ||
	      !master_xactor_f_rd_data$D_OUT[6] &&
	      !master_xactor_f_rd_data$D_OUT[4] ||
	      master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) ;
  assign MUX_rg_exc_code$write_1__SEL_6 =
	     WILL_FIRE_RL_rl_ptw_level_1 &&
	     NOT_master_xactor_f_rd_data_first__38_BIT_3_42_ETC___d1031 ;
  assign MUX_rg_exc_code$write_1__SEL_7 =
	     WILL_FIRE_RL_rl_ptw_level_2 &&
	     NOT_master_xactor_f_rd_data_first__38_BIT_3_42_ETC___d969 ;
  assign MUX_rg_exc_code$write_1__SEL_8 =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d151 ;
  assign MUX_rg_ld_val$write_1__SEL_2 =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d708 ;
  assign MUX_rg_lrsc_valid$write_1__SEL_2 =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d499 ;
  assign MUX_rg_state$write_1__SEL_3 =
	     f_reset_reqs$EMPTY_N && rg_state != 5'd1 ;
  assign MUX_rg_state$write_1__SEL_11 =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     rg_word64_set_in_cache[2:0] == 3'd7 ;
  assign MUX_rg_state$write_1__SEL_17 =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d437 ;
  assign MUX_rg_state$write_1__SEL_18 =
	     WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ;
  assign MUX_tlb$insert_1__SEL_1 =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d419 ;
  assign MUX_tlb$insert_1__SEL_2 =
	     WILL_FIRE_RL_rl_ptw_level_2 &&
	     master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1012 ;
  assign MUX_tlb$insert_1__SEL_3 =
	     WILL_FIRE_RL_rl_ptw_level_1 &&
	     master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1047 ;
  assign MUX_tlb$insert_1__SEL_4 =
	     WILL_FIRE_RL_rl_ptw_level_0 &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     (master_xactor_f_rd_data$D_OUT[4] ||
	      !master_xactor_f_rd_data$D_OUT[5]) &&
	     (master_xactor_f_rd_data$D_OUT[6] ||
	      master_xactor_f_rd_data$D_OUT[4]) ;
  assign MUX_dw_output_ld_val$wset_1__VAL_3 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
	       new_value__h7705 :
	       new_value__h24132 ;
  assign MUX_f_fabric_write_reqs$enq_1__VAL_1 = { rg_f3, rg_pa, x__h37654 } ;
  assign MUX_f_fabric_write_reqs$enq_1__VAL_2 =
	     { rg_f3,
	       x1_avValue_pa__h6058,
	       IF_rg_op_11_EQ_1_64_OR_rg_op_11_EQ_2_14_AND_rg_ETC___d853 } ;
  assign MUX_f_fabric_write_reqs$enq_1__VAL_3 =
	     { 3'b011, f_pte_writebacks$D_OUT } ;
  assign MUX_f_fabric_write_reqs$enq_1__VAL_4 =
	     { rg_f3, rg_pa, rg_st_amo_val } ;
  assign MUX_master_xactor_f_rd_addr$enq_1__VAL_1 =
	     { 4'd0, lev_1_pte_pa_w64_fa__h29506, 29'd851968 } ;
  assign MUX_master_xactor_f_rd_addr$enq_1__VAL_2 =
	     { 4'd0, lev_0_pte_pa_w64_fa__h30539, 29'd851968 } ;
  assign MUX_master_xactor_f_rd_addr$enq_1__VAL_3 =
	     { 4'd0, rg_pa, 8'd0, value__h37211, 18'd65536 } ;
  assign MUX_master_xactor_f_rd_addr$enq_1__VAL_4 =
	     { 4'd0, lev_2_pte_pa_w64_fa__h28609, 29'd851968 } ;
  assign MUX_master_xactor_f_rd_addr$enq_1__VAL_5 =
	     { 4'd0, cline_fabric_addr__h31709, 29'd15532032 } ;
  assign MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 =
	     { rg_victim_way || ram_state_and_ctag_cset$DOB[105],
	       rg_victim_way ?
		 rg_pa[63:12] :
		 ram_state_and_ctag_cset$DOB[104:53],
	       !rg_victim_way || ram_state_and_ctag_cset$DOB[52],
	       rg_victim_way ?
		 ram_state_and_ctag_cset$DOB[51:0] :
		 rg_pa[63:12] } ;
  assign MUX_ram_word64_set$a_put_3__VAL_1 =
	     rg_victim_way ?
	       { master_xactor_f_rd_data$D_OUT[66:3],
		 ram_word64_set$DOB[63:0] } :
	       { ram_word64_set$DOB[127:64],
		 master_xactor_f_rd_data$D_OUT[66:3] } ;
  assign MUX_ram_word64_set$a_put_3__VAL_2 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
	       { IF_ram_state_and_ctag_cset_b_read__98_BIT_105__ETC___d775,
		 IF_NOT_ram_state_and_ctag_cset_b_read__98_BIT__ETC___d776 } :
	       { IF_ram_state_and_ctag_cset_b_read__98_BIT_105__ETC___d843,
		 IF_NOT_ram_state_and_ctag_cset_b_read__98_BIT__ETC___d844 } ;
  assign MUX_ram_word64_set$b_put_2__VAL_2 = rg_word64_set_in_cache + 9'd1 ;
  assign MUX_ram_word64_set$b_put_2__VAL_4 = { rg_addr[11:6], 3'd0 } ;
  assign MUX_rg_cset_in_cache$write_1__VAL_1 = rg_cset_in_cache + 6'd1 ;
  assign MUX_rg_exc_code$write_1__VAL_1 = (req_op == 2'd0) ? 4'd4 : 4'd6 ;
  assign MUX_rg_exc_code$write_1__VAL_5 =
	     (master_xactor_f_rd_data$D_OUT[2:1] == 2'b0) ?
	       exc_code___1__h6459 :
	       access_exc_code__h2602 ;
  assign MUX_rg_ld_val$write_1__VAL_2 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
	       x__h21713 :
	       IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_IF_rg_f3_15_E_ETC___d712 ;
  assign MUX_rg_state$write_1__VAL_2 =
	     NOT_req_f3_BITS_1_TO_0_430_EQ_0b0_431_432_AND__ETC___d1451 ?
	       5'd4 :
	       5'd3 ;
  assign MUX_rg_state$write_1__VAL_4 =
	     (master_xactor_f_rd_data$D_OUT[2:1] == 2'b0) ? 5'd15 : 5'd4 ;
  assign MUX_rg_state$write_1__VAL_11 =
	     (master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	      rg_error_during_refill) ?
	       5'd4 :
	       5'd11 ;
  assign MUX_rg_state$write_1__VAL_13 =
	     (master_xactor_f_rd_data$D_OUT[2:1] == 2'b0) ?
	       ((!master_xactor_f_rd_data$D_OUT[3] ||
		 !master_xactor_f_rd_data$D_OUT[4] &&
		 master_xactor_f_rd_data$D_OUT[5] ||
		 !master_xactor_f_rd_data$D_OUT[6] &&
		 !master_xactor_f_rd_data$D_OUT[4]) ?
		  5'd4 :
		  5'd11) :
	       5'd4 ;
  assign MUX_rg_state$write_1__VAL_14 =
	     (master_xactor_f_rd_data$D_OUT[2:1] == 2'b0) ?
	       ((!master_xactor_f_rd_data$D_OUT[3] ||
		 !master_xactor_f_rd_data$D_OUT[4] &&
		 master_xactor_f_rd_data$D_OUT[5]) ?
		  5'd4 :
		  ((!master_xactor_f_rd_data$D_OUT[6] &&
		    !master_xactor_f_rd_data$D_OUT[4]) ?
		     5'd8 :
		     ((master_xactor_f_rd_data$D_OUT[21:13] == 9'd0) ?
			5'd11 :
			5'd4))) :
	       5'd4 ;
  assign MUX_rg_state$write_1__VAL_15 =
	     (master_xactor_f_rd_data$D_OUT[2:1] == 2'b0) ?
	       ((!master_xactor_f_rd_data$D_OUT[3] ||
		 !master_xactor_f_rd_data$D_OUT[4] &&
		 master_xactor_f_rd_data$D_OUT[5]) ?
		  5'd4 :
		  ((!master_xactor_f_rd_data$D_OUT[6] &&
		    !master_xactor_f_rd_data$D_OUT[4]) ?
		     5'd7 :
		     ((master_xactor_f_rd_data$D_OUT[30:22] != 9'd0 ||
		       master_xactor_f_rd_data$D_OUT[21:13] != 9'd0) ?
			5'd4 :
			5'd11))) :
	       5'd4 ;
  assign MUX_rg_state$write_1__VAL_17 =
	     (rg_priv_4_ULE_0b1___d85 && rg_satp[63:60] == 4'd8 &&
	      !tlb$lookup[130]) ?
	       5'd5 :
	       IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_T_ETC___d442 ;

  // inlined wires
  assign dw_valid$whas =
	     (WILL_FIRE_RL_rl_io_read_rsp ||
	      WILL_FIRE_RL_rl_io_AMO_read_rsp) &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d506 ||
	     WILL_FIRE_RL_rl_drive_exception_rsp ||
	     WILL_FIRE_RL_rl_maintain_io_read_rsp ||
	     WILL_FIRE_RL_rl_ST_AMO_response ;
  assign ctr_wr_rsps_pending_crg$port0__write_1 =
	     ctr_wr_rsps_pending_crg + 4'd1 ;
  assign ctr_wr_rsps_pending_crg$port1__write_1 = b__h28508 - 4'd1 ;
  assign ctr_wr_rsps_pending_crg$port2__read =
	     CAN_FIRE_RL_rl_discard_write_rsp ?
	       ctr_wr_rsps_pending_crg$port1__write_1 :
	       b__h28508 ;
  assign ctr_wr_rsps_pending_crg$EN_port2__write =
	     WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
  assign ctr_wr_rsps_pending_crg$port3__read =
	     ctr_wr_rsps_pending_crg$EN_port2__write ?
	       4'd0 :
	       ctr_wr_rsps_pending_crg$port2__read ;

  // register cfg_verbosity
  assign cfg_verbosity$D_IN = set_verbosity_verbosity ;
  assign cfg_verbosity$EN = EN_set_verbosity ;

  // register ctr_wr_rsps_pending_crg
  assign ctr_wr_rsps_pending_crg$D_IN = ctr_wr_rsps_pending_crg$port3__read ;
  assign ctr_wr_rsps_pending_crg$EN = 1'b1 ;

  // register rg_addr
  assign rg_addr$D_IN = req_addr ;
  assign rg_addr$EN = EN_req ;

  // register rg_amo_funct7
  assign rg_amo_funct7$D_IN = req_amo_funct7 ;
  assign rg_amo_funct7$EN = EN_req ;

  // register rg_cset_in_cache
  assign rg_cset_in_cache$D_IN =
	     WILL_FIRE_RL_rl_reset ?
	       MUX_rg_cset_in_cache$write_1__VAL_1 :
	       6'd0 ;
  assign rg_cset_in_cache$EN =
	     WILL_FIRE_RL_rl_reset || WILL_FIRE_RL_rl_start_reset ;

  // register rg_error_during_refill
  assign rg_error_during_refill$D_IN =
	     MUX_rg_error_during_refill$write_1__SEL_1 ;
  assign rg_error_during_refill$EN =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	     WILL_FIRE_RL_rl_start_cache_refill ;

  // register rg_exc_code
  always@(MUX_rg_exc_code$write_1__SEL_1 or
	  MUX_rg_exc_code$write_1__VAL_1 or
	  MUX_rg_exc_code$write_1__SEL_2 or
	  MUX_rg_exc_code$write_1__SEL_3 or
	  MUX_rg_error_during_refill$write_1__SEL_1 or
	  access_exc_code__h2602 or
	  MUX_rg_exc_code$write_1__SEL_5 or
	  MUX_rg_exc_code$write_1__VAL_5 or
	  MUX_rg_exc_code$write_1__SEL_6 or
	  MUX_rg_exc_code$write_1__SEL_7 or
	  MUX_rg_exc_code$write_1__SEL_8 or x1_avValue_exc_code__h6059)
  case (1'b1)
    MUX_rg_exc_code$write_1__SEL_1:
	rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_1;
    MUX_rg_exc_code$write_1__SEL_2: rg_exc_code$D_IN = 4'd7;
    MUX_rg_exc_code$write_1__SEL_3: rg_exc_code$D_IN = 4'd5;
    MUX_rg_error_during_refill$write_1__SEL_1:
	rg_exc_code$D_IN = access_exc_code__h2602;
    MUX_rg_exc_code$write_1__SEL_5:
	rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_5;
    MUX_rg_exc_code$write_1__SEL_6:
	rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_5;
    MUX_rg_exc_code$write_1__SEL_7:
	rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_5;
    MUX_rg_exc_code$write_1__SEL_8:
	rg_exc_code$D_IN = x1_avValue_exc_code__h6059;
    default: rg_exc_code$D_IN = 4'b1010 /* unspecified value */ ;
  endcase
  assign rg_exc_code$EN =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d151 ||
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	     WILL_FIRE_RL_rl_io_read_rsp &&
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	     WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	     EN_req &&
	     NOT_req_f3_BITS_1_TO_0_430_EQ_0b0_431_432_AND__ETC___d1451 ||
	     WILL_FIRE_RL_rl_ptw_level_2 &&
	     NOT_master_xactor_f_rd_data_first__38_BIT_3_42_ETC___d969 ||
	     WILL_FIRE_RL_rl_ptw_level_1 &&
	     NOT_master_xactor_f_rd_data_first__38_BIT_3_42_ETC___d1031 ||
	     WILL_FIRE_RL_rl_ptw_level_0 &&
	     (!master_xactor_f_rd_data$D_OUT[3] ||
	      !master_xactor_f_rd_data$D_OUT[4] &&
	      master_xactor_f_rd_data$D_OUT[5] ||
	      !master_xactor_f_rd_data$D_OUT[6] &&
	      !master_xactor_f_rd_data$D_OUT[4] ||
	      master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) ;

  // register rg_f3
  assign rg_f3$D_IN = req_f3 ;
  assign rg_f3$EN = EN_req ;

  // register rg_ld_val
  always@(MUX_dw_output_ld_val$wset_1__SEL_2 or
	  new_ld_val__h37625 or
	  MUX_rg_ld_val$write_1__SEL_2 or
	  MUX_rg_ld_val$write_1__VAL_2 or
	  WILL_FIRE_RL_rl_io_read_rsp or
	  ld_val__h35419 or WILL_FIRE_RL_rl_io_AMO_SC_req)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_dw_output_ld_val$wset_1__SEL_2: rg_ld_val$D_IN = new_ld_val__h37625;
      MUX_rg_ld_val$write_1__SEL_2:
	  rg_ld_val$D_IN = MUX_rg_ld_val$write_1__VAL_2;
      WILL_FIRE_RL_rl_io_read_rsp: rg_ld_val$D_IN = ld_val__h35419;
      WILL_FIRE_RL_rl_io_AMO_SC_req: rg_ld_val$D_IN = 64'd1;
      default: rg_ld_val$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign rg_ld_val$EN =
	     WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d708 ||
	     WILL_FIRE_RL_rl_io_read_rsp ||
	     WILL_FIRE_RL_rl_io_AMO_SC_req ;

  // register rg_lower_word32
  assign rg_lower_word32$D_IN = 32'h0 ;
  assign rg_lower_word32$EN = 1'b0 ;

  // register rg_lower_word32_full
  assign rg_lower_word32_full$D_IN = 1'd0 ;
  assign rg_lower_word32_full$EN =
	     WILL_FIRE_RL_rl_start_cache_refill ||
	     WILL_FIRE_RL_rl_start_reset ;

  // register rg_lrsc_pa
  assign rg_lrsc_pa$D_IN = soc_map$m_is_mem_addr_addr ;
  assign rg_lrsc_pa$EN =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d680 ;

  // register rg_lrsc_valid
  assign rg_lrsc_valid$D_IN =
	     MUX_rg_lrsc_valid$write_1__SEL_2 &&
	     rg_op_11_EQ_0_12_OR_rg_op_11_EQ_2_14_AND_rg_am_ETC___d500 ;
  assign rg_lrsc_valid$EN =
	     WILL_FIRE_RL_rl_io_read_req && rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00010 ||
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d499 ||
	     WILL_FIRE_RL_rl_start_reset ;

  // register rg_mstatus_MXR
  assign rg_mstatus_MXR$D_IN = req_mstatus_MXR ;
  assign rg_mstatus_MXR$EN = EN_req ;

  // register rg_op
  assign rg_op$D_IN = req_op ;
  assign rg_op$EN = EN_req ;

  // register rg_pa
  assign rg_pa$D_IN = EN_req ? req_addr : soc_map$m_is_mem_addr_addr ;
  assign rg_pa$EN =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d462 ||
	     EN_req ;

  // register rg_priv
  assign rg_priv$D_IN = req_priv ;
  assign rg_priv$EN = EN_req ;

  // register rg_pte_pa
  always@(MUX_master_xactor_f_rd_addr$enq_1__SEL_1 or
	  lev_1_pte_pa__h29504 or
	  MUX_master_xactor_f_rd_addr$enq_1__SEL_2 or
	  lev_0_pte_pa__h30537 or
	  WILL_FIRE_RL_rl_start_tlb_refill or lev_2_pte_pa__h28607)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_master_xactor_f_rd_addr$enq_1__SEL_1:
	  rg_pte_pa$D_IN = lev_1_pte_pa__h29504;
      MUX_master_xactor_f_rd_addr$enq_1__SEL_2:
	  rg_pte_pa$D_IN = lev_0_pte_pa__h30537;
      WILL_FIRE_RL_rl_start_tlb_refill: rg_pte_pa$D_IN = lev_2_pte_pa__h28607;
      default: rg_pte_pa$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign rg_pte_pa$EN =
	     WILL_FIRE_RL_rl_ptw_level_2 &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     !master_xactor_f_rd_data$D_OUT[5] &&
	     !master_xactor_f_rd_data$D_OUT[6] &&
	     !master_xactor_f_rd_data$D_OUT[4] ||
	     WILL_FIRE_RL_rl_ptw_level_1 &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     !master_xactor_f_rd_data$D_OUT[5] &&
	     !master_xactor_f_rd_data$D_OUT[6] &&
	     !master_xactor_f_rd_data$D_OUT[4] ||
	     WILL_FIRE_RL_rl_start_tlb_refill ;

  // register rg_satp
  assign rg_satp$D_IN = req_satp ;
  assign rg_satp$EN = EN_req ;

  // register rg_sstatus_SUM
  assign rg_sstatus_SUM$D_IN = req_sstatus_SUM ;
  assign rg_sstatus_SUM$EN = EN_req ;

  // register rg_st_amo_val
  assign rg_st_amo_val$D_IN = EN_req ? req_st_value : new_st_val__h25262 ;
  assign rg_st_amo_val$EN =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d922 ||
	     EN_req ;

  // register rg_state
  always@(EN_tlb_flush or
	  EN_req or
	  MUX_rg_state$write_1__VAL_2 or
	  WILL_FIRE_RL_rl_start_reset or
	  WILL_FIRE_RL_rl_io_AMO_read_rsp or
	  MUX_rg_state$write_1__VAL_4 or
	  WILL_FIRE_RL_rl_io_AMO_op_req or
	  WILL_FIRE_RL_rl_io_AMO_SC_req or
	  WILL_FIRE_RL_rl_io_write_req or
	  WILL_FIRE_RL_rl_io_read_rsp or
	  WILL_FIRE_RL_rl_io_read_req or
	  WILL_FIRE_RL_rl_rereq or
	  MUX_rg_state$write_1__SEL_11 or
	  MUX_rg_state$write_1__VAL_11 or
	  WILL_FIRE_RL_rl_start_cache_refill or
	  WILL_FIRE_RL_rl_ptw_level_0 or
	  MUX_rg_state$write_1__VAL_13 or
	  WILL_FIRE_RL_rl_ptw_level_1 or
	  MUX_rg_state$write_1__VAL_14 or
	  WILL_FIRE_RL_rl_ptw_level_2 or
	  MUX_rg_state$write_1__VAL_15 or
	  WILL_FIRE_RL_rl_start_tlb_refill or
	  MUX_rg_state$write_1__SEL_17 or
	  MUX_rg_state$write_1__VAL_17 or MUX_rg_state$write_1__SEL_18)
  case (1'b1)
    EN_tlb_flush: rg_state$D_IN = 5'd2;
    EN_req: rg_state$D_IN = MUX_rg_state$write_1__VAL_2;
    WILL_FIRE_RL_rl_start_reset: rg_state$D_IN = 5'd1;
    WILL_FIRE_RL_rl_io_AMO_read_rsp:
	rg_state$D_IN = MUX_rg_state$write_1__VAL_4;
    WILL_FIRE_RL_rl_io_AMO_op_req: rg_state$D_IN = 5'd16;
    WILL_FIRE_RL_rl_io_AMO_SC_req || WILL_FIRE_RL_rl_io_write_req:
	rg_state$D_IN = 5'd12;
    WILL_FIRE_RL_rl_io_read_rsp: rg_state$D_IN = MUX_rg_state$write_1__VAL_4;
    WILL_FIRE_RL_rl_io_read_req: rg_state$D_IN = 5'd14;
    WILL_FIRE_RL_rl_rereq: rg_state$D_IN = 5'd3;
    MUX_rg_state$write_1__SEL_11:
	rg_state$D_IN = MUX_rg_state$write_1__VAL_11;
    WILL_FIRE_RL_rl_start_cache_refill: rg_state$D_IN = 5'd10;
    WILL_FIRE_RL_rl_ptw_level_0: rg_state$D_IN = MUX_rg_state$write_1__VAL_13;
    WILL_FIRE_RL_rl_ptw_level_1: rg_state$D_IN = MUX_rg_state$write_1__VAL_14;
    WILL_FIRE_RL_rl_ptw_level_2: rg_state$D_IN = MUX_rg_state$write_1__VAL_15;
    WILL_FIRE_RL_rl_start_tlb_refill: rg_state$D_IN = 5'd6;
    MUX_rg_state$write_1__SEL_17:
	rg_state$D_IN = MUX_rg_state$write_1__VAL_17;
    MUX_rg_state$write_1__SEL_18: rg_state$D_IN = 5'd2;
    default: rg_state$D_IN = 5'b01010 /* unspecified value */ ;
  endcase
  assign rg_state$EN =
	     WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ||
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     rg_word64_set_in_cache[2:0] == 3'd7 ||
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d437 ||
	     WILL_FIRE_RL_rl_io_read_rsp ||
	     WILL_FIRE_RL_rl_io_AMO_read_rsp ||
	     WILL_FIRE_RL_rl_ptw_level_2 ||
	     WILL_FIRE_RL_rl_ptw_level_1 ||
	     WILL_FIRE_RL_rl_ptw_level_0 ||
	     EN_req ||
	     WILL_FIRE_RL_rl_start_reset ||
	     EN_tlb_flush ||
	     WILL_FIRE_RL_rl_rereq ||
	     WILL_FIRE_RL_rl_start_tlb_refill ||
	     WILL_FIRE_RL_rl_start_cache_refill ||
	     WILL_FIRE_RL_rl_io_AMO_SC_req ||
	     WILL_FIRE_RL_rl_io_write_req ||
	     WILL_FIRE_RL_rl_io_read_req ||
	     WILL_FIRE_RL_rl_io_AMO_op_req ;

  // register rg_victim_way
  assign rg_victim_way$D_IN = tmp__h31849[0] ;
  assign rg_victim_way$EN = WILL_FIRE_RL_rl_start_cache_refill ;

  // register rg_word64_set_in_cache
  assign rg_word64_set_in_cache$D_IN =
	     MUX_ram_word64_set$b_put_1__SEL_2 ?
	       MUX_ram_word64_set$b_put_2__VAL_2 :
	       MUX_ram_word64_set$b_put_2__VAL_4 ;
  assign rg_word64_set_in_cache$EN =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     rg_word64_set_in_cache[2:0] != 3'd7 ||
	     WILL_FIRE_RL_rl_start_cache_refill ;

  // submodule f_fabric_write_reqs
  always@(MUX_dw_output_ld_val$wset_1__SEL_2 or
	  MUX_f_fabric_write_reqs$enq_1__VAL_1 or
	  MUX_f_fabric_write_reqs$enq_1__SEL_2 or
	  MUX_f_fabric_write_reqs$enq_1__VAL_2 or
	  WILL_FIRE_RL_rl_writeback_updated_PTE or
	  MUX_f_fabric_write_reqs$enq_1__VAL_3 or
	  WILL_FIRE_RL_rl_io_write_req or
	  MUX_f_fabric_write_reqs$enq_1__VAL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_dw_output_ld_val$wset_1__SEL_2:
	  f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_1;
      MUX_f_fabric_write_reqs$enq_1__SEL_2:
	  f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_2;
      WILL_FIRE_RL_rl_writeback_updated_PTE:
	  f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_3;
      WILL_FIRE_RL_rl_io_write_req:
	  f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_4;
      default: f_fabric_write_reqs$D_IN =
		   131'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign f_fabric_write_reqs$ENQ =
	     WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d852 ||
	     WILL_FIRE_RL_rl_writeback_updated_PTE ||
	     WILL_FIRE_RL_rl_io_write_req ;
  assign f_fabric_write_reqs$DEQ = CAN_FIRE_RL_rl_fabric_send_write_req ;
  assign f_fabric_write_reqs$CLR = 1'b0 ;

  // submodule f_pte_writebacks
  assign f_pte_writebacks$D_IN = { tlb$lookup[63:0], value__h6884 } ;
  assign f_pte_writebacks$ENQ = MUX_tlb$insert_1__SEL_1 ;
  assign f_pte_writebacks$DEQ = WILL_FIRE_RL_rl_writeback_updated_PTE ;
  assign f_pte_writebacks$CLR = 1'b0 ;

  // submodule f_reset_reqs
  assign f_reset_reqs$D_IN = !EN_server_reset_request_put ;
  assign f_reset_reqs$ENQ =
	     EN_server_reset_request_put || EN_server_flush_request_put ;
  assign f_reset_reqs$DEQ =
	     WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ;
  assign f_reset_reqs$CLR = 1'b0 ;

  // submodule f_reset_rsps
  assign f_reset_rsps$D_IN = f_reset_reqs$D_OUT ;
  assign f_reset_rsps$ENQ =
	     WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ;
  assign f_reset_rsps$DEQ =
	     EN_server_flush_response_get || EN_server_reset_response_get ;
  assign f_reset_rsps$CLR = 1'b0 ;

  // submodule master_xactor_f_rd_addr
  always@(MUX_master_xactor_f_rd_addr$enq_1__SEL_1 or
	  MUX_master_xactor_f_rd_addr$enq_1__VAL_1 or
	  MUX_master_xactor_f_rd_addr$enq_1__SEL_2 or
	  MUX_master_xactor_f_rd_addr$enq_1__VAL_2 or
	  MUX_master_xactor_f_rd_addr$enq_1__SEL_3 or
	  MUX_master_xactor_f_rd_addr$enq_1__VAL_3 or
	  WILL_FIRE_RL_rl_start_tlb_refill or
	  MUX_master_xactor_f_rd_addr$enq_1__VAL_4 or
	  WILL_FIRE_RL_rl_start_cache_refill or
	  MUX_master_xactor_f_rd_addr$enq_1__VAL_5)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_master_xactor_f_rd_addr$enq_1__SEL_1:
	  master_xactor_f_rd_addr$D_IN =
	      MUX_master_xactor_f_rd_addr$enq_1__VAL_1;
      MUX_master_xactor_f_rd_addr$enq_1__SEL_2:
	  master_xactor_f_rd_addr$D_IN =
	      MUX_master_xactor_f_rd_addr$enq_1__VAL_2;
      MUX_master_xactor_f_rd_addr$enq_1__SEL_3:
	  master_xactor_f_rd_addr$D_IN =
	      MUX_master_xactor_f_rd_addr$enq_1__VAL_3;
      WILL_FIRE_RL_rl_start_tlb_refill:
	  master_xactor_f_rd_addr$D_IN =
	      MUX_master_xactor_f_rd_addr$enq_1__VAL_4;
      WILL_FIRE_RL_rl_start_cache_refill:
	  master_xactor_f_rd_addr$D_IN =
	      MUX_master_xactor_f_rd_addr$enq_1__VAL_5;
      default: master_xactor_f_rd_addr$D_IN =
		   97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign master_xactor_f_rd_addr$ENQ =
	     WILL_FIRE_RL_rl_ptw_level_2 &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     !master_xactor_f_rd_data$D_OUT[5] &&
	     !master_xactor_f_rd_data$D_OUT[6] &&
	     !master_xactor_f_rd_data$D_OUT[4] ||
	     WILL_FIRE_RL_rl_ptw_level_1 &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     !master_xactor_f_rd_data$D_OUT[5] &&
	     !master_xactor_f_rd_data$D_OUT[6] &&
	     !master_xactor_f_rd_data$D_OUT[4] ||
	     WILL_FIRE_RL_rl_io_AMO_op_req ||
	     WILL_FIRE_RL_rl_io_read_req ||
	     WILL_FIRE_RL_rl_start_tlb_refill ||
	     WILL_FIRE_RL_rl_start_cache_refill ;
  assign master_xactor_f_rd_addr$DEQ =
	     master_xactor_f_rd_addr$EMPTY_N && mem_master_arready ;
  assign master_xactor_f_rd_addr$CLR =
	     WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;

  // submodule master_xactor_f_rd_data
  assign master_xactor_f_rd_data$D_IN =
	     { mem_master_rid,
	       mem_master_rdata,
	       mem_master_rresp,
	       mem_master_rlast } ;
  assign master_xactor_f_rd_data$ENQ =
	     mem_master_rvalid && master_xactor_f_rd_data$FULL_N ;
  assign master_xactor_f_rd_data$DEQ =
	     WILL_FIRE_RL_rl_io_read_rsp ||
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop ||
	     WILL_FIRE_RL_rl_ptw_level_0 ||
	     WILL_FIRE_RL_rl_ptw_level_1 ||
	     WILL_FIRE_RL_rl_ptw_level_2 ||
	     WILL_FIRE_RL_rl_io_AMO_read_rsp ;
  assign master_xactor_f_rd_data$CLR =
	     WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;

  // submodule master_xactor_f_wr_addr
  assign master_xactor_f_wr_addr$D_IN =
	     { 4'd0,
	       f_fabric_write_reqs$D_OUT[127:64],
	       8'd0,
	       x__h2866,
	       18'd65536 } ;
  assign master_xactor_f_wr_addr$ENQ = CAN_FIRE_RL_rl_fabric_send_write_req ;
  assign master_xactor_f_wr_addr$DEQ =
	     master_xactor_f_wr_addr$EMPTY_N && mem_master_awready ;
  assign master_xactor_f_wr_addr$CLR =
	     WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;

  // submodule master_xactor_f_wr_data
  assign master_xactor_f_wr_data$D_IN =
	     { mem_req_wr_data_wdata__h3045,
	       mem_req_wr_data_wstrb__h3046,
	       1'd1 } ;
  assign master_xactor_f_wr_data$ENQ = CAN_FIRE_RL_rl_fabric_send_write_req ;
  assign master_xactor_f_wr_data$DEQ =
	     master_xactor_f_wr_data$EMPTY_N && mem_master_wready ;
  assign master_xactor_f_wr_data$CLR =
	     WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;

  // submodule master_xactor_f_wr_resp
  assign master_xactor_f_wr_resp$D_IN = { mem_master_bid, mem_master_bresp } ;
  assign master_xactor_f_wr_resp$ENQ =
	     mem_master_bvalid && master_xactor_f_wr_resp$FULL_N ;
  assign master_xactor_f_wr_resp$DEQ = CAN_FIRE_RL_rl_discard_write_rsp ;
  assign master_xactor_f_wr_resp$CLR =
	     WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;

  // submodule ram_state_and_ctag_cset
  assign ram_state_and_ctag_cset$ADDRA =
	     MUX_ram_state_and_ctag_cset$a_put_1__SEL_1 ?
	       rg_addr[11:6] :
	       rg_cset_in_cache ;
  assign ram_state_and_ctag_cset$ADDRB =
	     MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 ?
	       req_addr[11:6] :
	       rg_addr[11:6] ;
  assign ram_state_and_ctag_cset$DIA =
	     MUX_ram_state_and_ctag_cset$a_put_1__SEL_1 ?
	       MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 :
	       106'h15555555555554AAAAAAAAAAAAA ;
  assign ram_state_and_ctag_cset$DIB =
	     MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 ?
	       106'h2AAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */  :
	       106'h2AAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */  ;
  assign ram_state_and_ctag_cset$WEA = 1'd1 ;
  assign ram_state_and_ctag_cset$WEB = 1'd0 ;
  assign ram_state_and_ctag_cset$ENA =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     rg_word64_set_in_cache[2:0] == 3'd0 &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
	     WILL_FIRE_RL_rl_reset ;
  assign ram_state_and_ctag_cset$ENB =
	     EN_req &&
	     req_f3_BITS_1_TO_0_430_EQ_0b0_431_OR_req_f3_BI_ETC___d1460 ||
	     WILL_FIRE_RL_rl_rereq ;

  // submodule ram_word64_set
  assign ram_word64_set$ADDRA =
	     MUX_ram_word64_set$a_put_1__SEL_1 ?
	       rg_word64_set_in_cache :
	       rg_addr[11:3] ;
  always@(MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 or
	  req_addr or
	  MUX_ram_word64_set$b_put_1__SEL_2 or
	  MUX_ram_word64_set$b_put_2__VAL_2 or
	  WILL_FIRE_RL_rl_rereq or
	  rg_addr or
	  WILL_FIRE_RL_rl_start_cache_refill or
	  MUX_ram_word64_set$b_put_2__VAL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_ram_state_and_ctag_cset$b_put_1__SEL_1:
	  ram_word64_set$ADDRB = req_addr[11:3];
      MUX_ram_word64_set$b_put_1__SEL_2:
	  ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_2;
      WILL_FIRE_RL_rl_rereq: ram_word64_set$ADDRB = rg_addr[11:3];
      WILL_FIRE_RL_rl_start_cache_refill:
	  ram_word64_set$ADDRB = MUX_ram_word64_set$b_put_2__VAL_4;
      default: ram_word64_set$ADDRB = 9'b010101010 /* unspecified value */ ;
    endcase
  end
  assign ram_word64_set$DIA =
	     MUX_ram_word64_set$a_put_1__SEL_1 ?
	       MUX_ram_word64_set$a_put_3__VAL_1 :
	       MUX_ram_word64_set$a_put_3__VAL_2 ;
  always@(MUX_ram_state_and_ctag_cset$b_put_1__SEL_1 or
	  MUX_ram_word64_set$b_put_1__SEL_2 or
	  WILL_FIRE_RL_rl_rereq or WILL_FIRE_RL_rl_start_cache_refill)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_ram_state_and_ctag_cset$b_put_1__SEL_1:
	  ram_word64_set$DIB =
	      128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
      MUX_ram_word64_set$b_put_1__SEL_2:
	  ram_word64_set$DIB =
	      128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
      WILL_FIRE_RL_rl_rereq:
	  ram_word64_set$DIB =
	      128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
      WILL_FIRE_RL_rl_start_cache_refill:
	  ram_word64_set$DIB =
	      128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
      default: ram_word64_set$DIB =
		   128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign ram_word64_set$WEA = 1'd1 ;
  assign ram_word64_set$WEB = 1'd0 ;
  assign ram_word64_set$ENA =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d721 ;
  assign ram_word64_set$ENB =
	     EN_req &&
	     req_f3_BITS_1_TO_0_430_EQ_0b0_431_OR_req_f3_BI_ETC___d1460 ||
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     rg_word64_set_in_cache[2:0] != 3'd7 ||
	     WILL_FIRE_RL_rl_rereq ||
	     WILL_FIRE_RL_rl_start_cache_refill ;

  // submodule soc_map
  assign soc_map$m_is_IO_addr_addr = 64'h0 ;
  assign soc_map$m_is_mem_addr_addr =
	     (rg_priv_4_ULE_0b1___d85 && rg_satp[63:60] == 4'd8) ?
	       _theResult___fst__h6147 :
	       rg_addr ;
  assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;

  // submodule tlb
  assign tlb$insert_asid = rg_satp[59:44] ;
  always@(MUX_tlb$insert_1__SEL_1 or
	  tlb$lookup or
	  MUX_tlb$insert_1__SEL_2 or
	  MUX_tlb$insert_1__SEL_3 or MUX_tlb$insert_1__SEL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_tlb$insert_1__SEL_1: tlb$insert_level = tlb$lookup[65:64];
      MUX_tlb$insert_1__SEL_2: tlb$insert_level = 2'd2;
      MUX_tlb$insert_1__SEL_3: tlb$insert_level = 2'd1;
      MUX_tlb$insert_1__SEL_4: tlb$insert_level = 2'd0;
      default: tlb$insert_level = 2'b10 /* unspecified value */ ;
    endcase
  end
  assign tlb$insert_pte =
	     (MUX_tlb$insert_1__SEL_2 || MUX_tlb$insert_1__SEL_3 ||
	      MUX_tlb$insert_1__SEL_4) ?
	       master_xactor_f_rd_data$D_OUT[66:3] :
	       value__h6884 ;
  assign tlb$insert_pte_pa =
	     MUX_tlb$insert_1__SEL_1 ? tlb$lookup[63:0] : rg_pte_pa ;
  assign tlb$insert_vpn = rg_addr[38:12] ;
  assign tlb$lookup_asid = rg_satp[59:44] ;
  assign tlb$lookup_vpn = rg_addr[38:12] ;
  assign tlb$EN_flush = WILL_FIRE_RL_rl_start_reset || EN_tlb_flush ;
  assign tlb$EN_insert =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d419 ||
	     WILL_FIRE_RL_rl_ptw_level_2 &&
	     master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1012 ||
	     WILL_FIRE_RL_rl_ptw_level_1 &&
	     master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1047 ||
	     WILL_FIRE_RL_rl_ptw_level_0 &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     (master_xactor_f_rd_data$D_OUT[4] ||
	      !master_xactor_f_rd_data$D_OUT[5]) &&
	     (master_xactor_f_rd_data$D_OUT[6] ||
	      master_xactor_f_rd_data$D_OUT[4]) ;

  // remaining internal signals
  assign IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d332 =
	     (x1_avValue_pa__h6058[2:0] == 3'h0) ?
	       CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_15_ETC__q29 :
	       NOT_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS__ETC___d331 ;
  assign IF_NOT_ram_state_and_ctag_cset_b_read__98_BIT__ETC___d438 =
	     ((!ram_state_and_ctag_cset$DOB[52] ||
	       !ram_state_and_ctag_cset_b_read__98_BITS_51_TO__ETC___d203) &&
	      (!ram_state_and_ctag_cset$DOB[105] ||
	       !ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209)) ?
	       5'd9 :
	       5'd12 ;
  assign IF_NOT_ram_state_and_ctag_cset_b_read__98_BIT__ETC___d776 =
	     (!ram_state_and_ctag_cset$DOB[105] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209) ?
	       n__h22492 :
	       ram_word64_set$DOB[63:0] ;
  assign IF_NOT_ram_state_and_ctag_cset_b_read__98_BIT__ETC___d844 =
	     (!ram_state_and_ctag_cset$DOB[105] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209) ?
	       n__h25426 :
	       ram_word64_set$DOB[63:0] ;
  assign IF_ram_state_and_ctag_cset_b_read__98_BIT_105__ETC___d775 =
	     (ram_state_and_ctag_cset$DOB[105] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209) ?
	       n__h22492 :
	       ram_word64_set$DOB[127:64] ;
  assign IF_ram_state_and_ctag_cset_b_read__98_BIT_105__ETC___d843 =
	     (ram_state_and_ctag_cset$DOB[105] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209) ?
	       n__h25426 :
	       ram_word64_set$DOB[127:64] ;
  assign IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_1_E_ETC___d659 =
	     (rg_addr[2:0] == 3'h0) ? 64'd1 : 64'd0 ;
  assign IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_IF__ETC___d1345 =
	     (rg_addr[2:0] == 3'h0) ? ld_val__h35419 : 64'd0 ;
  assign IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_NOT_ETC___d253 =
	     (rg_addr[2:0] == 3'h0) ?
	       NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d233 &&
	       NOT_ram_state_and_ctag_cset_b_read__98_BIT_105_ETC___d234 :
	       rg_addr[2:0] != 3'h4 ||
	       NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d233 &&
	       NOT_ram_state_and_ctag_cset_b_read__98_BIT_105_ETC___d234 ;
  assign IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_ram_ETC___d644 =
	     (rg_addr[2:0] == 3'h0) ? word64__h7577 : 64'd0 ;
  assign IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_5_BITS_2_ETC__q32 =
	     IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_5_BITS_2_ETC___d651[31:0] ;
  assign IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_rg_st_amo_val_ETC___d781 =
	     (rg_f3 == 3'b010) ?
	       { {32{rg_st_amo_val_BITS_31_TO_0__q33[31]}},
		 rg_st_amo_val_BITS_31_TO_0__q33 } :
	       rg_st_amo_val ;
  assign IF_rg_op_11_EQ_0_12_OR_rg_op_11_EQ_2_14_AND_rg_ETC___d346 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
	       NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d263 :
	       IF_rg_op_11_EQ_1_64_OR_rg_op_11_EQ_2_14_AND_rg_ETC___d345 ;
  assign IF_rg_op_11_EQ_0_12_OR_rg_op_11_EQ_2_14_AND_rg_ETC___d440 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
	       5'd9 :
	       IF_rg_op_11_EQ_1_64_OR_rg_op_11_EQ_2_14_AND_rg_ETC___d439 ;
  assign IF_rg_op_11_EQ_1_64_OR_rg_op_11_EQ_2_14_AND_rg_ETC___d345 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
	       rg_op_11_EQ_2_14_AND_rg_amo_funct7_16_BITS_6_T_ETC___d285 :
	       NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d344 ;
  assign IF_rg_op_11_EQ_1_64_OR_rg_op_11_EQ_2_14_AND_rg_ETC___d439 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
	       5'd12 :
	       IF_NOT_ram_state_and_ctag_cset_b_read__98_BIT__ETC___d438 ;
  assign IF_rg_op_11_EQ_1_64_OR_rg_op_11_EQ_2_14_AND_rg_ETC___d853 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
	       rg_st_amo_val :
	       new_st_val__h25262 ;
  assign IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_T_ETC___d442 =
	     rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d151 ?
	       5'd4 :
	       ((dmem_not_imem && !soc_map$m_is_mem_addr) ?
		  5'd13 :
		  IF_rg_op_11_EQ_0_12_OR_rg_op_11_EQ_2_14_AND_rg_ETC___d440) ;
  assign IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_T_ETC___d482 =
	     x1_avValue_pa__h6058 == rg_lrsc_pa ;
  assign NOT_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS__ETC___d321 =
	     x1_avValue_pa__h6058[2:0] != 3'h7 ||
	     CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_15_ETC__q29 ;
  assign NOT_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS__ETC___d327 =
	     x1_avValue_pa__h6058[2:0] != 3'h6 ||
	     CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_15_ETC__q29 ;
  assign NOT_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS__ETC___d331 =
	     x1_avValue_pa__h6058[2:0] != 3'h4 ||
	     CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_15_ETC__q29 ;
  assign NOT_cfg_verbosity_read__9_ULE_2_103___d1104 = cfg_verbosity > 4'd2 ;
  assign NOT_cfg_verbosity_read__9_ULT_2_46___d447 = cfg_verbosity >= 4'd2 ;
  assign NOT_dmem_not_imem_26_AND_rg_op_11_EQ_0_12_OR_r_ETC___d382 =
	     !dmem_not_imem &&
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     tlb$lookup[69] ;
  assign NOT_dmem_not_imem_26_OR_NOT_rg_op_11_EQ_0_12_1_ETC___d133 =
	     !dmem_not_imem ||
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ||
	     !tlb_lookup_rg_satp_7_BITS_59_TO_44_4_rg_addr_5_ETC___d131 ;
  assign NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d476 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     ram_state_and_ctag_cset$DOB[52] &&
	     ram_state_and_ctag_cset_b_read__98_BITS_51_TO__ETC___d203 &&
	     ram_state_and_ctag_cset$DOB[105] &&
	     ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209 ;
  assign NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d672 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     ram_state_and_ctag_cset_b_read__98_BIT_52_99_A_ETC___d670 ;
  assign NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d684 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00010 &&
	     ram_state_and_ctag_cset_b_read__98_BIT_52_99_A_ETC___d670 ;
  assign NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d689 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d687 ;
  assign NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d697 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00010 &&
	     NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d694 ;
  assign NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d706 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     (rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 ||
	      NOT_rg_op_11_EQ_1_64_90_AND_ram_state_and_ctag_ETC___d703) ;
  assign NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d719 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     rg_op_11_EQ_1_64_OR_rg_op_11_EQ_2_14_AND_rg_am_ETC___d717 ;
  assign NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d856 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd1 &&
	     IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_T_ETC___d482 &&
	     !cfg_verbosity_read__9_ULE_1___d40 ;
  assign NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d874 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00011 &&
	     !cfg_verbosity_read__9_ULE_1___d40 ;
  assign NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d920 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     NOT_rg_op_11_EQ_1_64_90_AND_NOT_rg_op_11_EQ_2__ETC___d716 ;
  assign NOT_master_xactor_f_rd_data_first__38_BITS_2_T_ETC___d1025 =
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	     !master_xactor_f_rd_data$D_OUT[3] ||
	     !master_xactor_f_rd_data$D_OUT[4] &&
	     master_xactor_f_rd_data$D_OUT[5] ||
	     ((!master_xactor_f_rd_data$D_OUT[6] &&
	       !master_xactor_f_rd_data$D_OUT[4]) ?
		master_xactor_f_rd_addr$FULL_N :
		master_xactor_f_rd_data$D_OUT[21:13] != 9'd0 ||
		tlb$RDY_insert) ;
  assign NOT_master_xactor_f_rd_data_first__38_BITS_2_T_ETC___d962 =
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	     !master_xactor_f_rd_data$D_OUT[3] ||
	     !master_xactor_f_rd_data$D_OUT[4] &&
	     master_xactor_f_rd_data$D_OUT[5] ||
	     ((!master_xactor_f_rd_data$D_OUT[6] &&
	       !master_xactor_f_rd_data$D_OUT[4]) ?
		master_xactor_f_rd_addr$FULL_N :
		master_xactor_f_rd_data$D_OUT[30:22] != 9'd0 ||
		master_xactor_f_rd_data$D_OUT[21:13] != 9'd0 ||
		tlb$RDY_insert) ;
  assign NOT_master_xactor_f_rd_data_first__38_BIT_3_42_ETC___d1031 =
	     !master_xactor_f_rd_data$D_OUT[3] ||
	     !master_xactor_f_rd_data$D_OUT[4] &&
	     master_xactor_f_rd_data$D_OUT[5] ||
	     (master_xactor_f_rd_data$D_OUT[6] ||
	      master_xactor_f_rd_data$D_OUT[4]) &&
	     master_xactor_f_rd_data$D_OUT[21:13] != 9'd0 ||
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
  assign NOT_master_xactor_f_rd_data_first__38_BIT_3_42_ETC___d969 =
	     !master_xactor_f_rd_data$D_OUT[3] ||
	     !master_xactor_f_rd_data$D_OUT[4] &&
	     master_xactor_f_rd_data$D_OUT[5] ||
	     (master_xactor_f_rd_data$D_OUT[6] ||
	      master_xactor_f_rd_data$D_OUT[4]) &&
	     (master_xactor_f_rd_data$D_OUT[30:22] != 9'd0 ||
	      master_xactor_f_rd_data$D_OUT[21:13] != 9'd0) ||
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
  assign NOT_ram_state_and_ctag_cset_b_read__98_BIT_105_ETC___d234 =
	     !ram_state_and_ctag_cset$DOB[105] || !rg_priv_4_ULE_0b1___d85 ||
	     rg_satp[63:60] != 4'd8 ||
	     tlb$RDY_lookup ;
  assign NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d233 =
	     !ram_state_and_ctag_cset$DOB[52] || !rg_priv_4_ULE_0b1___d85 ||
	     rg_satp[63:60] != 4'd8 ||
	     tlb$RDY_lookup ;
  assign NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d263 =
	     (!ram_state_and_ctag_cset$DOB[52] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_51_TO__ETC___d203) &&
	     (!ram_state_and_ctag_cset$DOB[105] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209) ||
	     rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 ||
	     IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b100_17__ETC___d261 ;
  assign NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d283 =
	     (!ram_state_and_ctag_cset$DOB[52] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_51_TO__ETC___d203) &&
	     (!ram_state_and_ctag_cset$DOB[105] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209) ||
	     (!ram_state_and_ctag_cset$DOB[105] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209 ||
	      IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b1_40_OR_ETC___d277) &&
	     (ram_state_and_ctag_cset$DOB[105] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209 ||
	      IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b1_40_OR_ETC___d277) ;
  assign NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d344 =
	     (!ram_state_and_ctag_cset$DOB[52] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_51_TO__ETC___d203) &&
	     (!ram_state_and_ctag_cset$DOB[105] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209) ||
	     f_fabric_write_reqs$FULL_N &&
	     rg_amo_funct7_16_BITS_6_TO_2_17_EQ_0b1_86_OR_I_ETC___d342 ;
  assign NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d484 =
	     (!ram_state_and_ctag_cset$DOB[52] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_51_TO__ETC___d203) &&
	     (!ram_state_and_ctag_cset$DOB[105] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209) &&
	     rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00010 &&
	     IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_T_ETC___d482 ;
  assign NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d687 =
	     (!ram_state_and_ctag_cset$DOB[52] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_51_TO__ETC___d203) &&
	     (!ram_state_and_ctag_cset$DOB[105] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209) &&
	     !cfg_verbosity_read__9_ULE_1___d40 ;
  assign NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d694 =
	     (!ram_state_and_ctag_cset$DOB[52] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_51_TO__ETC___d203) &&
	     (!ram_state_and_ctag_cset$DOB[105] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209) &&
	     IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_T_ETC___d482 &&
	     !cfg_verbosity_read__9_ULE_1___d40 ;
  assign NOT_req_f3_BITS_1_TO_0_430_EQ_0b0_431_432_AND__ETC___d1451 =
	     req_f3[1:0] != 2'b0 && (req_f3[1:0] != 2'b01 || req_addr[0]) &&
	     (req_f3[1:0] != 2'b10 || req_addr[1:0] != 2'b0) &&
	     (req_f3[1:0] != 2'b11 || req_addr[2:0] != 3'b0) ;
  assign NOT_rg_op_11_EQ_0_12_13_AND_NOT_rg_op_11_EQ_2__ETC___d433 =
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
	      rg_lrsc_valid &&
	      rg_lrsc_pa_68_EQ_IF_rg_priv_4_ULE_0b1_5_AND_rg_ETC___d269) ;
  assign NOT_rg_op_11_EQ_1_64_90_AND_NOT_rg_op_11_EQ_2__ETC___d716 =
	     rg_op != 2'd1 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
	     (ram_state_and_ctag_cset$DOB[52] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_51_TO__ETC___d203 ||
	      ram_state_and_ctag_cset$DOB[105] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209) ;
  assign NOT_rg_op_11_EQ_1_64_90_AND_ram_state_and_ctag_ETC___d703 =
	     rg_op != 2'd1 &&
	     (ram_state_and_ctag_cset$DOB[52] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_51_TO__ETC___d203 ||
	      ram_state_and_ctag_cset$DOB[105] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209) ;
  assign NOT_rg_op_11_EQ_2_14_15_OR_NOT_rg_amo_funct7_1_ETC___d714 =
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
	      rg_lrsc_valid &&
	      rg_lrsc_pa_68_EQ_IF_rg_priv_4_ULE_0b1_5_AND_rg_ETC___d269) &&
	     (ram_state_and_ctag_cset$DOB[52] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_51_TO__ETC___d203 ||
	      ram_state_and_ctag_cset$DOB[105] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209) ;
  assign NOT_rg_op_11_EQ_2_14_15_OR_NOT_rg_amo_funct7_1_ETC___d877 =
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
	      rg_lrsc_valid &&
	      rg_lrsc_pa_68_EQ_IF_rg_priv_4_ULE_0b1_5_AND_rg_ETC___d269) &&
	     ram_state_and_ctag_cset_b_read__98_BIT_52_99_A_ETC___d670 ;
  assign NOT_rg_op_11_EQ_2_14_15_OR_NOT_rg_amo_funct7_1_ETC___d883 =
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
	      rg_lrsc_valid &&
	      rg_lrsc_pa_68_EQ_IF_rg_priv_4_ULE_0b1_5_AND_rg_ETC___d269) &&
	     NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d687 ;
  assign NOT_rg_op_11_EQ_2_14_15_OR_NOT_rg_amo_funct7_1_ETC___d889 =
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
	      rg_lrsc_valid &&
	      rg_lrsc_pa_68_EQ_IF_rg_priv_4_ULE_0b1_5_AND_rg_ETC___d269) &&
	     !cfg_verbosity_read__9_ULE_1___d40 ;
  assign NOT_rg_priv_4_EQ_0b0_01_75_OR_tlb_lookup_rg_sa_ETC___d389 =
	     (rg_priv != 2'b0 || tlb$lookup[70]) &&
	     (rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) &&
	     (NOT_dmem_not_imem_26_AND_rg_op_11_EQ_0_12_OR_r_ETC___d382 ||
	      dmem_not_imem_AND_rg_op_11_EQ_0_12_OR_rg_op_11_ETC___d384 ||
	      dmem_not_imem && rg_op != 2'd0 &&
	      (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	      tlb$lookup[68]) ;
  assign NOT_rg_priv_4_EQ_0b0_01_75_OR_tlb_lookup_rg_sa_ETC___d412 =
	     (rg_priv != 2'b0 || tlb$lookup[70]) &&
	     (rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) &&
	     dmem_not_imem &&
	     tlb$lookup[68] ;
  assign NOT_rg_priv_4_EQ_0b0_01_75_OR_tlb_lookup_rg_sa_ETC___d450 =
	     (rg_priv != 2'b0 || tlb$lookup[70]) &&
	     (rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) &&
	     tlb$lookup[72] &&
	     !pte___2__h6559[7] &&
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ;
  assign NOT_rg_priv_4_EQ_0b0_01_75_OR_tlb_lookup_rg_sa_ETC___d666 =
	     (rg_priv != 2'b0 || tlb$lookup[70]) &&
	     (rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) &&
	     (!dmem_not_imem && tlb$lookup[69] ||
	      dmem_not_imem &&
	      tlb_lookup_rg_satp_7_BITS_59_TO_44_4_rg_addr_5_ETC___d131) ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d167 =
	     !rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	     !tlb$lookup[130] ||
	     rg_priv_4_EQ_0b0_01_AND_NOT_tlb_lookup_rg_satp_ETC___d155 ||
	     NOT_tlb_lookup_rg_satp_7_BITS_59_TO_44_4_rg_ad_ETC___d164 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d348 =
	     (NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d167 ||
	      tlb$RDY_insert && tlb$RDY_lookup && f_pte_writebacks$FULL_N) &&
	     (dmem_not_imem && !soc_map$m_is_mem_addr ||
	      IF_rg_op_11_EQ_0_12_OR_rg_op_11_EQ_2_14_AND_rg_ETC___d346) ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d394 =
	     !rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	     tlb$lookup[130] &&
	     NOT_rg_priv_4_EQ_0b0_01_75_OR_tlb_lookup_rg_sa_ETC___d389 &&
	     tlb_lookup_rg_satp_7_BITS_59_TO_44_4_rg_addr_5_ETC___d391 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d409 =
	     !rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	     !tlb$lookup[130] ||
	     rg_priv_4_EQ_0b0_01_AND_NOT_tlb_lookup_rg_satp_ETC___d155 ||
	     NOT_tlb_lookup_rg_satp_7_BITS_59_TO_44_4_rg_ad_ETC___d164 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d461 =
	     !rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	     !tlb$lookup[130] ||
	     NOT_rg_priv_4_EQ_0b0_01_75_OR_tlb_lookup_rg_sa_ETC___d389 &&
	     tlb_lookup_rg_satp_7_BITS_59_TO_44_4_rg_addr_5_ETC___d391 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d462 =
	     (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d461 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d469 =
	     !rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	     !tlb$lookup[130] ||
	     (rg_priv != 2'b0 || tlb$lookup[70]) &&
	     (rg_priv != 2'b01 || !tlb$lookup[70] || rg_sstatus_SUM) &&
	     rg_op_11_EQ_0_12_OR_rg_op_11_EQ_2_14_AND_rg_am_ETC___d465 &&
	     tlb_lookup_rg_satp_7_BITS_59_TO_44_4_rg_addr_5_ETC___d391 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d472 =
	     (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d469 &&
	     dmem_not_imem &&
	     !soc_map$m_is_mem_addr &&
	     !cfg_verbosity_read__9_ULE_1___d40 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d478 =
	     (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d461 &&
	     NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d476 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d499 =
	     (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d461 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op_11_EQ_0_12_OR_rg_op_11_EQ_2_14_AND_rg_am_ETC___d496 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d505 =
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d461 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     (rg_op_11_EQ_0_12_OR_rg_op_11_EQ_2_14_AND_rg_am_ETC___d500 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 &&
	      lrsc_result__h21703) ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d506 =
	     (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d505 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d669 =
	     !rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	     !tlb$lookup[130] ||
	     NOT_rg_priv_4_EQ_0b0_01_75_OR_tlb_lookup_rg_sa_ETC___d666 &&
	     tlb$lookup[72] ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d674 =
	     (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d669 &&
	     NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d672 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d680 =
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d669 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op == 2'd2 &&
	     rg_amo_funct7_16_BITS_6_TO_2_17_EQ_0b10_18_AND_ETC___d677 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d686 =
	     (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d669 &&
	     NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d684 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d691 =
	     (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d669 &&
	     NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d689 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d699 =
	     (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d669 &&
	     NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d697 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d702 =
	     !rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	     !tlb$lookup[130] ||
	     NOT_rg_priv_4_EQ_0b0_01_75_OR_tlb_lookup_rg_sa_ETC___d412 &&
	     tlb$lookup[72] &&
	     tlb$lookup[73] ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d708 =
	     (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d702 &&
	     NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d706 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d721 =
	     (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d702 &&
	     NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d719 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d851 =
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d702 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     (rg_op_11_EQ_1_64_OR_rg_op_11_EQ_2_14_AND_rg_am_ETC___d847 ||
	      NOT_rg_op_11_EQ_1_64_90_AND_NOT_rg_op_11_EQ_2__ETC___d716) ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d852 =
	     (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d851 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d858 =
	     (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d702 &&
	     NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d856 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d864 =
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d702 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00011 &&
	     rg_lrsc_valid &&
	     !rg_lrsc_pa_68_EQ_IF_rg_priv_4_ULE_0b1_5_AND_rg_ETC___d269 &&
	     !cfg_verbosity_read__9_ULE_1___d40 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d870 =
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d702 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00011 &&
	     !rg_lrsc_valid &&
	     !cfg_verbosity_read__9_ULE_1___d40 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d876 =
	     (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d702 &&
	     NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d874 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d881 =
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d702 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
	     NOT_rg_op_11_EQ_2_14_15_OR_NOT_rg_amo_funct7_1_ETC___d877 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d882 =
	     (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d881 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d887 =
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d702 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
	     NOT_rg_op_11_EQ_2_14_15_OR_NOT_rg_amo_funct7_1_ETC___d883 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d893 =
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d702 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
	     NOT_rg_op_11_EQ_2_14_15_OR_NOT_rg_amo_funct7_1_ETC___d889 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d894 =
	     (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d893 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d899 =
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d702 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00011 &&
	     lrsc_result__h21703 &&
	     !cfg_verbosity_read__9_ULE_1___d40 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d900 =
	     (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d899 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d906 =
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d702 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     rg_op != 2'd1 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
	     NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d687 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d911 =
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d702 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     rg_op != 2'd1 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
	     ram_state_and_ctag_cset_b_read__98_BIT_52_99_A_ETC___d670 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d912 =
	     (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d911 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d917 =
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d702 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     rg_op != 2'd1 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
	     ram_state_and_ctag_cset_b_read__98_BIT_52_99_A_ETC___d913 ;
  assign NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d922 =
	     (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	      tlb$lookup[130]) &&
	     NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d702 &&
	     NOT_dmem_not_imem_26_OR_soc_map_m_is_mem_addr__ETC___d920 ;
  assign NOT_tlb_lookup_rg_satp_7_BITS_59_TO_44_4_rg_ad_ETC___d148 =
	     !tlb$lookup[72] ||
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     !tlb$lookup[73] ;
  assign NOT_tlb_lookup_rg_satp_7_BITS_59_TO_44_4_rg_ad_ETC___d164 =
	     !tlb$lookup[72] || !tlb$lookup[73] || pte___2__h6559[7] ||
	     rg_op == 2'd0 ||
	     rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 ;
  assign _theResult___fst__h6147 =
	     tlb$lookup[130] ? _theResult___fst__h6218 : rg_addr ;
  assign _theResult___fst__h6218 =
	     (rg_priv_4_EQ_0b0_01_AND_NOT_tlb_lookup_rg_satp_ETC___d142 ||
	      NOT_tlb_lookup_rg_satp_7_BITS_59_TO_44_4_rg_ad_ETC___d148) ?
	       rg_addr :
	       _theResult___fst__h6561 ;
  assign _theResult___snd_fst__h3053 =
	     f_fabric_write_reqs$D_OUT[63:0] << shift_bits__h2833 ;
  assign _theResult___snd_fst__h6149 =
	     tlb$lookup[130] ?
	       _theResult___snd_fst__h6220 :
	       tlb$lookup[129:66] ;
  assign _theResult___snd_fst__h6220 =
	     (rg_priv_4_EQ_0b0_01_AND_NOT_tlb_lookup_rg_satp_ETC___d142 ||
	      NOT_tlb_lookup_rg_satp_7_BITS_59_TO_44_4_rg_ad_ETC___d148) ?
	       tlb$lookup[129:66] :
	       _theResult___snd_fst__h6790 ;
  assign _theResult___snd_fst__h6790 =
	     (!pte___2__h6559[7] && rg_op != 2'd0 &&
	      (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010)) ?
	       pte___1__h6867 :
	       pte___2__h6559 ;
  assign access_exc_code__h2602 =
	     dmem_not_imem ?
	       ((rg_op == 2'd0 ||
		 rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
		  4'd5 :
		  4'd7) :
	       4'd1 ;
  assign b__h28508 =
	     CAN_FIRE_RL_rl_fabric_send_write_req ?
	       ctr_wr_rsps_pending_crg$port0__write_1 :
	       ctr_wr_rsps_pending_crg ;
  assign cfg_verbosity_read__9_ULE_1___d40 = cfg_verbosity <= 4'd1 ;
  assign cline_fabric_addr__h31709 = { rg_pa[63:6], 6'd0 } ;
  assign dmem_not_imem_AND_rg_op_11_EQ_0_12_OR_rg_op_11_ETC___d384 =
	     dmem_not_imem &&
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     tlb_lookup_rg_satp_7_BITS_59_TO_44_4_rg_addr_5_ETC___d131 ;
  assign dmem_not_imem_OR_NOT_rg_op_11_EQ_0_12_13_AND_N_ETC___d125 =
	     dmem_not_imem ||
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ||
	     !tlb$lookup[69] ;
  assign exc_code___1__h6459 = x1_avValue_exc_code__h6059 ;
  assign ld_val5419_BITS_15_TO_0__q38 = ld_val__h35419[15:0] ;
  assign ld_val5419_BITS_15_TO_8__q40 = ld_val__h35419[15:8] ;
  assign ld_val5419_BITS_23_TO_16__q41 = ld_val__h35419[23:16] ;
  assign ld_val5419_BITS_31_TO_0__q39 = ld_val__h35419[31:0] ;
  assign ld_val5419_BITS_31_TO_16__q42 = ld_val__h35419[31:16] ;
  assign ld_val5419_BITS_31_TO_24__q43 = ld_val__h35419[31:24] ;
  assign ld_val5419_BITS_39_TO_32__q44 = ld_val__h35419[39:32] ;
  assign ld_val5419_BITS_47_TO_32__q45 = ld_val__h35419[47:32] ;
  assign ld_val5419_BITS_47_TO_40__q47 = ld_val__h35419[47:40] ;
  assign ld_val5419_BITS_55_TO_48__q48 = ld_val__h35419[55:48] ;
  assign ld_val5419_BITS_63_TO_32__q46 = ld_val__h35419[63:32] ;
  assign ld_val5419_BITS_63_TO_48__q49 = ld_val__h35419[63:48] ;
  assign ld_val5419_BITS_63_TO_56__q50 = ld_val__h35419[63:56] ;
  assign ld_val5419_BITS_7_TO_0__q37 = ld_val__h35419[7:0] ;
  assign lev_0_pte_pa__h30537 = lev_1_PTN_pa__h29502 + vpn_0_pa__h30536 ;
  assign lev_0_pte_pa_w64_fa__h30539 = { lev_0_pte_pa__h30537[63:3], 3'b0 } ;
  assign lev_1_PTN_pa__h29502 = { 8'd0, x__h29583 } ;
  assign lev_1_pte_pa__h29504 = lev_1_PTN_pa__h29502 + vpn_1_pa__h29503 ;
  assign lev_1_pte_pa_w64_fa__h29506 = { lev_1_pte_pa__h29504[63:3], 3'b0 } ;
  assign lev_2_pte_pa__h28607 = satp_pa__h1898 + vpn_2_pa__h28606 ;
  assign lev_2_pte_pa_w64_fa__h28609 = { lev_2_pte_pa__h28607[63:3], 3'b0 } ;
  assign lrsc_result__h21703 =
	     !rg_lrsc_valid ||
	     !rg_lrsc_pa_68_EQ_IF_rg_priv_4_ULE_0b1_5_AND_rg_ETC___d269 ;
  assign master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1 =
	     master_xactor_f_rd_data$D_OUT[10:3] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4 =
	     master_xactor_f_rd_data$D_OUT[18:11] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2 =
	     master_xactor_f_rd_data$D_OUT[18:3] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q5 =
	     master_xactor_f_rd_data$D_OUT[26:19] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q6 =
	     master_xactor_f_rd_data$D_OUT[34:19] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q7 =
	     master_xactor_f_rd_data$D_OUT[34:27] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3 =
	     master_xactor_f_rd_data$D_OUT[34:3] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q8 =
	     master_xactor_f_rd_data$D_OUT[42:35] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9 =
	     master_xactor_f_rd_data$D_OUT[50:35] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11 =
	     master_xactor_f_rd_data$D_OUT[50:43] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12 =
	     master_xactor_f_rd_data$D_OUT[58:51] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10 =
	     master_xactor_f_rd_data$D_OUT[66:35] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13 =
	     master_xactor_f_rd_data$D_OUT[66:51] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14 =
	     master_xactor_f_rd_data$D_OUT[66:59] ;
  assign master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1004 =
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     (master_xactor_f_rd_data$D_OUT[4] ||
	      !master_xactor_f_rd_data$D_OUT[5]) &&
	     (master_xactor_f_rd_data$D_OUT[6] ||
	      master_xactor_f_rd_data$D_OUT[4]) &&
	     (master_xactor_f_rd_data$D_OUT[30:22] != 9'd0 ||
	      master_xactor_f_rd_data$D_OUT[21:13] != 9'd0) &&
	     !cfg_verbosity_read__9_ULE_1___d40 ;
  assign master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1012 =
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     (master_xactor_f_rd_data$D_OUT[4] ||
	      !master_xactor_f_rd_data$D_OUT[5]) &&
	     (master_xactor_f_rd_data$D_OUT[6] ||
	      master_xactor_f_rd_data$D_OUT[4]) &&
	     master_xactor_f_rd_data$D_OUT[30:22] == 9'd0 &&
	     master_xactor_f_rd_data$D_OUT[21:13] == 9'd0 ;
  assign master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1016 =
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     (master_xactor_f_rd_data$D_OUT[4] ||
	      !master_xactor_f_rd_data$D_OUT[5]) &&
	     (master_xactor_f_rd_data$D_OUT[6] ||
	      master_xactor_f_rd_data$D_OUT[4]) &&
	     master_xactor_f_rd_data$D_OUT[30:22] == 9'd0 &&
	     master_xactor_f_rd_data$D_OUT[21:13] == 9'd0 &&
	     !cfg_verbosity_read__9_ULE_1___d40 ;
  assign master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1047 =
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     (master_xactor_f_rd_data$D_OUT[4] ||
	      !master_xactor_f_rd_data$D_OUT[5]) &&
	     (master_xactor_f_rd_data$D_OUT[6] ||
	      master_xactor_f_rd_data$D_OUT[4]) &&
	     master_xactor_f_rd_data$D_OUT[21:13] == 9'd0 ;
  assign master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1051 =
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     (master_xactor_f_rd_data$D_OUT[4] ||
	      !master_xactor_f_rd_data$D_OUT[5]) &&
	     (master_xactor_f_rd_data$D_OUT[6] ||
	      master_xactor_f_rd_data$D_OUT[4]) &&
	     master_xactor_f_rd_data$D_OUT[21:13] == 9'd0 &&
	     !cfg_verbosity_read__9_ULE_1___d40 ;
  assign master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1057 =
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     (master_xactor_f_rd_data$D_OUT[4] ||
	      !master_xactor_f_rd_data$D_OUT[5]) &&
	     (master_xactor_f_rd_data$D_OUT[6] ||
	      master_xactor_f_rd_data$D_OUT[4]) &&
	     master_xactor_f_rd_data$D_OUT[21:13] != 9'd0 &&
	     !cfg_verbosity_read__9_ULE_1___d40 ;
  assign master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1082 =
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     (master_xactor_f_rd_data$D_OUT[4] ||
	      !master_xactor_f_rd_data$D_OUT[5]) &&
	     (master_xactor_f_rd_data$D_OUT[6] ||
	      master_xactor_f_rd_data$D_OUT[4]) &&
	     !cfg_verbosity_read__9_ULE_1___d40 ;
  assign master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d978 =
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     (!master_xactor_f_rd_data$D_OUT[3] ||
	      !master_xactor_f_rd_data$D_OUT[4] &&
	      master_xactor_f_rd_data$D_OUT[5]) &&
	     !cfg_verbosity_read__9_ULE_1___d40 ;
  assign master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988 =
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     master_xactor_f_rd_data$D_OUT[3] &&
	     !master_xactor_f_rd_data$D_OUT[5] &&
	     !master_xactor_f_rd_data$D_OUT[6] &&
	     !master_xactor_f_rd_data$D_OUT[4] &&
	     !cfg_verbosity_read__9_ULE_1___d40 ;
  assign new_st_val__h25262 =
	     (rg_f3 == 3'b010) ?
	       new_st_val__h25568 :
	       _theResult_____2__h25564 ;
  assign new_st_val__h25568 = { 32'd0, _theResult_____2__h25564[31:0] } ;
  assign new_st_val__h25659 =
	     IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_IF_rg_f3_15_E_ETC___d712 +
	     IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_rg_st_amo_val_ETC___d781 ;
  assign new_st_val__h26639 = w1__h25556 ^ w2__h37665 ;
  assign new_st_val__h26643 = w1__h25556 & w2__h37665 ;
  assign new_st_val__h26647 = w1__h25556 | w2__h37665 ;
  assign new_st_val__h26651 =
	     (w1__h25556 < w2__h37665) ? w1__h25556 : w2__h37665 ;
  assign new_st_val__h26656 =
	     (w1__h25556 <= w2__h37665) ? w2__h37665 : w1__h25556 ;
  assign new_st_val__h26662 =
	     ((IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_IF_rg_f3_15_E_ETC___d712 ^
	       64'h8000000000000000) <
	      (IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_rg_st_amo_val_ETC___d781 ^
	       64'h8000000000000000)) ?
	       w1__h25556 :
	       w2__h37665 ;
  assign new_st_val__h26667 =
	     ((IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_IF_rg_f3_15_E_ETC___d712 ^
	       64'h8000000000000000) <=
	      (IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_rg_st_amo_val_ETC___d781 ^
	       64'h8000000000000000)) ?
	       w2__h37665 :
	       w1__h25556 ;
  assign new_st_val__h37675 = { 32'd0, _theResult_____2__h37671[31:0] } ;
  assign new_st_val__h37766 =
	     new_ld_val__h37625 +
	     IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_rg_st_amo_val_ETC___d781 ;
  assign new_st_val__h39626 = w1__h37663 ^ w2__h37665 ;
  assign new_st_val__h39630 = w1__h37663 & w2__h37665 ;
  assign new_st_val__h39634 = w1__h37663 | w2__h37665 ;
  assign new_st_val__h39638 =
	     (w1__h37663 < w2__h37665) ? w1__h37663 : w2__h37665 ;
  assign new_st_val__h39643 =
	     (w1__h37663 <= w2__h37665) ? w2__h37665 : w1__h37663 ;
  assign new_st_val__h39649 =
	     ((new_ld_val__h37625 ^ 64'h8000000000000000) <
	      (IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_rg_st_amo_val_ETC___d781 ^
	       64'h8000000000000000)) ?
	       w1__h37663 :
	       w2__h37665 ;
  assign new_st_val__h39654 =
	     ((new_ld_val__h37625 ^ 64'h8000000000000000) <=
	      (IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_rg_st_amo_val_ETC___d781 ^
	       64'h8000000000000000)) ?
	       w2__h37665 :
	       w1__h37663 ;
  assign new_value__h24132 =
	     (rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
	       64'd1 :
	       CASE_rg_f3_0b0_IF_rg_addr_5_BITS_2_TO_0_19_EQ__ETC__q53 ;
  assign new_value__h7705 =
	     (rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
	       word64__h7577 :
	       IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_5_BITS_2_ETC___d651 ;
  assign pa___1__h6567 = { 8'd0, x__h6570 } ;
  assign pa___1__h6616 = { 8'd0, x__h6619 } ;
  assign pa___1__h6685 = { 8'd0, x__h6688 } ;
  assign pte___1__h6839 = { tlb$lookup[129:73], 1'd1, tlb$lookup[71:66] } ;
  assign pte___1__h6867 =
	     { pte___2__h6559[63:8], 1'd1, pte___2__h6559[6:0] } ;
  assign pte___2__h6559 =
	     tlb$lookup[72] ? tlb$lookup[129:66] : pte___1__h6839 ;
  assign ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209 =
	     ram_state_and_ctag_cset$DOB[104:53] ==
	     x1_avValue_pa__h6058[63:12] ;
  assign ram_state_and_ctag_cset_b_read__98_BITS_51_TO__ETC___d203 =
	     ram_state_and_ctag_cset$DOB[51:0] ==
	     x1_avValue_pa__h6058[63:12] ;
  assign ram_state_and_ctag_cset_b_read__98_BIT_52_99_A_ETC___d481 =
	     (ram_state_and_ctag_cset$DOB[52] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_51_TO__ETC___d203 ||
	      ram_state_and_ctag_cset$DOB[105] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209) &&
	     rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00010 ;
  assign ram_state_and_ctag_cset_b_read__98_BIT_52_99_A_ETC___d492 =
	     (ram_state_and_ctag_cset$DOB[52] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_51_TO__ETC___d203 ||
	      ram_state_and_ctag_cset$DOB[105] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209) &&
	     IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_T_ETC___d482 ;
  assign ram_state_and_ctag_cset_b_read__98_BIT_52_99_A_ETC___d670 =
	     (ram_state_and_ctag_cset$DOB[52] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_51_TO__ETC___d203 ||
	      ram_state_and_ctag_cset$DOB[105] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209) &&
	     !cfg_verbosity_read__9_ULE_1___d40 ;
  assign ram_state_and_ctag_cset_b_read__98_BIT_52_99_A_ETC___d913 =
	     (ram_state_and_ctag_cset$DOB[52] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_51_TO__ETC___d203 ||
	      ram_state_and_ctag_cset$DOB[105] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209) &&
	     IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_T_ETC___d482 &&
	     !cfg_verbosity_read__9_ULE_1___d40 ;
  assign req_f3_BITS_1_TO_0_430_EQ_0b0_431_OR_req_f3_BI_ETC___d1460 =
	     req_f3[1:0] == 2'b0 || req_f3[1:0] == 2'b01 && !req_addr[0] ||
	     req_f3[1:0] == 2'b10 && req_addr[1:0] == 2'b0 ||
	     req_f3[1:0] == 2'b11 && req_addr[2:0] == 3'b0 ;
  assign result__h20414 =
	     { {56{word64577_BITS_7_TO_0__q15[7]}},
	       word64577_BITS_7_TO_0__q15 } ;
  assign result__h20442 =
	     { {56{word64577_BITS_15_TO_8__q18[7]}},
	       word64577_BITS_15_TO_8__q18 } ;
  assign result__h20470 =
	     { {56{word64577_BITS_23_TO_16__q19[7]}},
	       word64577_BITS_23_TO_16__q19 } ;
  assign result__h20498 =
	     { {56{word64577_BITS_31_TO_24__q21[7]}},
	       word64577_BITS_31_TO_24__q21 } ;
  assign result__h20526 =
	     { {56{word64577_BITS_39_TO_32__q22[7]}},
	       word64577_BITS_39_TO_32__q22 } ;
  assign result__h20554 =
	     { {56{word64577_BITS_47_TO_40__q25[7]}},
	       word64577_BITS_47_TO_40__q25 } ;
  assign result__h20582 =
	     { {56{word64577_BITS_55_TO_48__q26[7]}},
	       word64577_BITS_55_TO_48__q26 } ;
  assign result__h20610 =
	     { {56{word64577_BITS_63_TO_56__q28[7]}},
	       word64577_BITS_63_TO_56__q28 } ;
  assign result__h20655 = { 56'd0, word64__h7577[7:0] } ;
  assign result__h20683 = { 56'd0, word64__h7577[15:8] } ;
  assign result__h20711 = { 56'd0, word64__h7577[23:16] } ;
  assign result__h20739 = { 56'd0, word64__h7577[31:24] } ;
  assign result__h20767 = { 56'd0, word64__h7577[39:32] } ;
  assign result__h20795 = { 56'd0, word64__h7577[47:40] } ;
  assign result__h20823 = { 56'd0, word64__h7577[55:48] } ;
  assign result__h20851 = { 56'd0, word64__h7577[63:56] } ;
  assign result__h20896 =
	     { {48{word64577_BITS_15_TO_0__q16[15]}},
	       word64577_BITS_15_TO_0__q16 } ;
  assign result__h20924 =
	     { {48{word64577_BITS_31_TO_16__q20[15]}},
	       word64577_BITS_31_TO_16__q20 } ;
  assign result__h20952 =
	     { {48{word64577_BITS_47_TO_32__q23[15]}},
	       word64577_BITS_47_TO_32__q23 } ;
  assign result__h20980 =
	     { {48{word64577_BITS_63_TO_48__q27[15]}},
	       word64577_BITS_63_TO_48__q27 } ;
  assign result__h21021 = { 48'd0, word64__h7577[15:0] } ;
  assign result__h21049 = { 48'd0, word64__h7577[31:16] } ;
  assign result__h21077 = { 48'd0, word64__h7577[47:32] } ;
  assign result__h21105 = { 48'd0, word64__h7577[63:48] } ;
  assign result__h21146 =
	     { {32{word64577_BITS_31_TO_0__q17[31]}},
	       word64577_BITS_31_TO_0__q17 } ;
  assign result__h21174 =
	     { {32{word64577_BITS_63_TO_32__q24[31]}},
	       word64577_BITS_63_TO_32__q24 } ;
  assign result__h21213 = { 32'd0, word64__h7577[31:0] } ;
  assign result__h21241 = { 32'd0, word64__h7577[63:32] } ;
  assign result__h35479 =
	     { {56{master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1[7]}},
	       master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1 } ;
  assign result__h35509 =
	     { {56{master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4[7]}},
	       master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4 } ;
  assign result__h35536 =
	     { {56{master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q5[7]}},
	       master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q5 } ;
  assign result__h35563 =
	     { {56{master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q7[7]}},
	       master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q7 } ;
  assign result__h35590 =
	     { {56{master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q8[7]}},
	       master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q8 } ;
  assign result__h35617 =
	     { {56{master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11[7]}},
	       master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11 } ;
  assign result__h35644 =
	     { {56{master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12[7]}},
	       master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12 } ;
  assign result__h35671 =
	     { {56{master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14[7]}},
	       master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14 } ;
  assign result__h35715 = { 56'd0, master_xactor_f_rd_data$D_OUT[10:3] } ;
  assign result__h35742 = { 56'd0, master_xactor_f_rd_data$D_OUT[18:11] } ;
  assign result__h35769 = { 56'd0, master_xactor_f_rd_data$D_OUT[26:19] } ;
  assign result__h35796 = { 56'd0, master_xactor_f_rd_data$D_OUT[34:27] } ;
  assign result__h35823 = { 56'd0, master_xactor_f_rd_data$D_OUT[42:35] } ;
  assign result__h35850 = { 56'd0, master_xactor_f_rd_data$D_OUT[50:43] } ;
  assign result__h35877 = { 56'd0, master_xactor_f_rd_data$D_OUT[58:51] } ;
  assign result__h35904 = { 56'd0, master_xactor_f_rd_data$D_OUT[66:59] } ;
  assign result__h35948 =
	     { {48{master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2[15]}},
	       master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2 } ;
  assign result__h35975 =
	     { {48{master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q6[15]}},
	       master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q6 } ;
  assign result__h36002 =
	     { {48{master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9[15]}},
	       master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9 } ;
  assign result__h36029 =
	     { {48{master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13[15]}},
	       master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13 } ;
  assign result__h36069 = { 48'd0, master_xactor_f_rd_data$D_OUT[18:3] } ;
  assign result__h36096 = { 48'd0, master_xactor_f_rd_data$D_OUT[34:19] } ;
  assign result__h36123 = { 48'd0, master_xactor_f_rd_data$D_OUT[50:35] } ;
  assign result__h36150 = { 48'd0, master_xactor_f_rd_data$D_OUT[66:51] } ;
  assign result__h36190 =
	     { {32{master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3[31]}},
	       master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3 } ;
  assign result__h36217 =
	     { {32{master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10[31]}},
	       master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10 } ;
  assign result__h36255 = { 32'd0, master_xactor_f_rd_data$D_OUT[34:3] } ;
  assign result__h36282 = { 32'd0, master_xactor_f_rd_data$D_OUT[66:35] } ;
  assign result__h37854 =
	     { {56{ld_val5419_BITS_7_TO_0__q37[7]}},
	       ld_val5419_BITS_7_TO_0__q37 } ;
  assign result__h38762 =
	     { {56{ld_val5419_BITS_15_TO_8__q40[7]}},
	       ld_val5419_BITS_15_TO_8__q40 } ;
  assign result__h38790 =
	     { {56{ld_val5419_BITS_23_TO_16__q41[7]}},
	       ld_val5419_BITS_23_TO_16__q41 } ;
  assign result__h38818 =
	     { {56{ld_val5419_BITS_31_TO_24__q43[7]}},
	       ld_val5419_BITS_31_TO_24__q43 } ;
  assign result__h38846 =
	     { {56{ld_val5419_BITS_39_TO_32__q44[7]}},
	       ld_val5419_BITS_39_TO_32__q44 } ;
  assign result__h38874 =
	     { {56{ld_val5419_BITS_47_TO_40__q47[7]}},
	       ld_val5419_BITS_47_TO_40__q47 } ;
  assign result__h38902 =
	     { {56{ld_val5419_BITS_55_TO_48__q48[7]}},
	       ld_val5419_BITS_55_TO_48__q48 } ;
  assign result__h38930 =
	     { {56{ld_val5419_BITS_63_TO_56__q50[7]}},
	       ld_val5419_BITS_63_TO_56__q50 } ;
  assign result__h38975 = { 56'd0, ld_val__h35419[7:0] } ;
  assign result__h39003 = { 56'd0, ld_val__h35419[15:8] } ;
  assign result__h39031 = { 56'd0, ld_val__h35419[23:16] } ;
  assign result__h39059 = { 56'd0, ld_val__h35419[31:24] } ;
  assign result__h39087 = { 56'd0, ld_val__h35419[39:32] } ;
  assign result__h39115 = { 56'd0, ld_val__h35419[47:40] } ;
  assign result__h39143 = { 56'd0, ld_val__h35419[55:48] } ;
  assign result__h39171 = { 56'd0, ld_val__h35419[63:56] } ;
  assign result__h39216 =
	     { {48{ld_val5419_BITS_15_TO_0__q38[15]}},
	       ld_val5419_BITS_15_TO_0__q38 } ;
  assign result__h39244 =
	     { {48{ld_val5419_BITS_31_TO_16__q42[15]}},
	       ld_val5419_BITS_31_TO_16__q42 } ;
  assign result__h39272 =
	     { {48{ld_val5419_BITS_47_TO_32__q45[15]}},
	       ld_val5419_BITS_47_TO_32__q45 } ;
  assign result__h39300 =
	     { {48{ld_val5419_BITS_63_TO_48__q49[15]}},
	       ld_val5419_BITS_63_TO_48__q49 } ;
  assign result__h39341 = { 48'd0, ld_val__h35419[15:0] } ;
  assign result__h39369 = { 48'd0, ld_val__h35419[31:16] } ;
  assign result__h39397 = { 48'd0, ld_val__h35419[47:32] } ;
  assign result__h39425 = { 48'd0, ld_val__h35419[63:48] } ;
  assign result__h39466 =
	     { {32{ld_val5419_BITS_31_TO_0__q39[31]}},
	       ld_val5419_BITS_31_TO_0__q39 } ;
  assign result__h39494 =
	     { {32{ld_val5419_BITS_63_TO_32__q46[31]}},
	       ld_val5419_BITS_63_TO_32__q46 } ;
  assign result__h39533 = { 32'd0, ld_val__h35419[31:0] } ;
  assign result__h39561 = { 32'd0, ld_val__h35419[63:32] } ;
  assign rg_amo_funct7_16_BITS_6_TO_2_17_EQ_0b10_18_AND_ETC___d677 =
	     rg_amo_funct7[6:2] == 5'b00010 &&
	     (ram_state_and_ctag_cset$DOB[52] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_51_TO__ETC___d203 ||
	      ram_state_and_ctag_cset$DOB[105] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209) ;
  assign rg_amo_funct7_16_BITS_6_TO_2_17_EQ_0b1_86_OR_I_ETC___d342 =
	     IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b100_17__ETC___d261 &&
	     (!ram_state_and_ctag_cset$DOB[105] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209 ||
	      IF_rg_f3_15_EQ_0b0_16_THEN_NOT_rg_priv_4_ULE_0_ETC___d337) &&
	     (ram_state_and_ctag_cset$DOB[105] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209 ||
	      IF_rg_f3_15_EQ_0b0_16_THEN_NOT_rg_priv_4_ULE_0_ETC___d337) ;
  assign rg_lrsc_pa_68_EQ_IF_rg_priv_4_ULE_0b1_5_AND_rg_ETC___d269 =
	     rg_lrsc_pa == x1_avValue_pa__h6058 ;
  assign rg_op_11_EQ_0_12_OR_rg_op_11_EQ_2_14_AND_rg_am_ETC___d428 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     (!ram_state_and_ctag_cset$DOB[52] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_51_TO__ETC___d203) &&
	     (!ram_state_and_ctag_cset$DOB[105] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209) ;
  assign rg_op_11_EQ_0_12_OR_rg_op_11_EQ_2_14_AND_rg_am_ETC___d465 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     tlb_lookup_rg_satp_7_BITS_59_TO_44_4_rg_addr_5_ETC___d131 ||
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     tlb$lookup[68] ;
  assign rg_op_11_EQ_0_12_OR_rg_op_11_EQ_2_14_AND_rg_am_ETC___d486 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     (ram_state_and_ctag_cset_b_read__98_BIT_52_99_A_ETC___d481 ||
	      NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d484) ;
  assign rg_op_11_EQ_0_12_OR_rg_op_11_EQ_2_14_AND_rg_am_ETC___d496 =
	     rg_op_11_EQ_0_12_OR_rg_op_11_EQ_2_14_AND_rg_am_ETC___d486 ||
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     rg_op_11_EQ_1_64_OR_rg_op_11_EQ_2_14_AND_rg_am_ETC___d494 ;
  assign rg_op_11_EQ_0_12_OR_rg_op_11_EQ_2_14_AND_rg_am_ETC___d500 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     (ram_state_and_ctag_cset$DOB[52] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_51_TO__ETC___d203 ||
	      ram_state_and_ctag_cset$DOB[105] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209) ;
  assign rg_op_11_EQ_1_64_OR_rg_op_11_EQ_2_14_AND_rg_am_ETC___d494 =
	     rg_op == 2'd1 &&
	     IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_T_ETC___d482 ||
	     rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 ||
	     rg_op != 2'd1 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
	     ram_state_and_ctag_cset_b_read__98_BIT_52_99_A_ETC___d492 ;
  assign rg_op_11_EQ_1_64_OR_rg_op_11_EQ_2_14_AND_rg_am_ETC___d717 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
	     NOT_rg_op_11_EQ_2_14_15_OR_NOT_rg_amo_funct7_1_ETC___d714 ||
	     NOT_rg_op_11_EQ_1_64_90_AND_NOT_rg_op_11_EQ_2__ETC___d716 ;
  assign rg_op_11_EQ_1_64_OR_rg_op_11_EQ_2_14_AND_rg_am_ETC___d847 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
	      rg_lrsc_valid &&
	      rg_lrsc_pa_68_EQ_IF_rg_priv_4_ULE_0b1_5_AND_rg_ETC___d269) ;
  assign rg_op_11_EQ_2_14_AND_rg_amo_funct7_16_BITS_6_T_ETC___d285 =
	     rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 &&
	     lrsc_result__h21703 ||
	     f_fabric_write_reqs$FULL_N &&
	     NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d283 ;
  assign rg_priv_4_EQ_0b0_01_AND_NOT_tlb_lookup_rg_satp_ETC___d142 =
	     rg_priv == 2'b0 && !tlb$lookup[70] ||
	     rg_priv == 2'b01 && tlb$lookup[70] && !rg_sstatus_SUM ||
	     dmem_not_imem_OR_NOT_rg_op_11_EQ_0_12_13_AND_N_ETC___d125 &&
	     NOT_dmem_not_imem_26_OR_NOT_rg_op_11_EQ_0_12_1_ETC___d133 &&
	     (!dmem_not_imem || rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 ||
	      !tlb$lookup[68]) ;
  assign rg_priv_4_EQ_0b0_01_AND_NOT_tlb_lookup_rg_satp_ETC___d155 =
	     rg_priv == 2'b0 && !tlb$lookup[70] ||
	     rg_priv == 2'b01 && tlb$lookup[70] && !rg_sstatus_SUM ||
	     !dmem_not_imem ||
	     !tlb$lookup[68] ;
  assign rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d151 =
	     rg_priv_4_ULE_0b1___d85 && rg_satp[63:60] == 4'd8 &&
	     tlb$lookup[130] &&
	     (rg_priv_4_EQ_0b0_01_AND_NOT_tlb_lookup_rg_satp_ETC___d142 ||
	      NOT_tlb_lookup_rg_satp_7_BITS_59_TO_44_4_rg_ad_ETC___d148) ;
  assign rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d350 =
	     rg_priv_4_ULE_0b1___d85 && rg_satp[63:60] == 4'd8 &&
	     !tlb$lookup[130] ||
	     (rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d151 ?
		tlb$RDY_lookup :
		NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d348) ;
  assign rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d397 =
	     rg_priv_4_ULE_0b1___d85 && rg_satp[63:60] == 4'd8 &&
	     (rg_priv_4_EQ_0b0_01_AND_NOT_tlb_lookup_rg_satp_ETC___d142 ||
	      NOT_tlb_lookup_rg_satp_7_BITS_59_TO_44_4_rg_ad_ETC___d148) &&
	     tlb$lookup[130] ;
  assign rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d419 =
	     rg_priv_4_ULE_0b1___d85 && rg_satp[63:60] == 4'd8 &&
	     tlb$lookup[130] &&
	     NOT_rg_priv_4_EQ_0b0_01_75_OR_tlb_lookup_rg_sa_ETC___d412 &&
	     tlb$lookup[72] &&
	     tlb$lookup[73] &&
	     !pte___2__h6559[7] &&
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ;
  assign rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d436 =
	     rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d151 ||
	     dmem_not_imem && !soc_map$m_is_mem_addr ||
	     rg_op_11_EQ_0_12_OR_rg_op_11_EQ_2_14_AND_rg_am_ETC___d428 ||
	     NOT_rg_op_11_EQ_0_12_13_AND_NOT_rg_op_11_EQ_2__ETC___d433 ;
  assign rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d437 =
	     rg_priv_4_ULE_0b1___d85 && rg_satp[63:60] == 4'd8 &&
	     !tlb$lookup[130] ||
	     rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d436 ;
  assign rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d455 =
	     rg_priv_4_ULE_0b1___d85 && rg_satp[63:60] == 4'd8 &&
	     tlb$lookup[130] &&
	     NOT_rg_priv_4_EQ_0b0_01_75_OR_tlb_lookup_rg_sa_ETC___d450 &&
	     NOT_cfg_verbosity_read__9_ULT_2_46___d447 &&
	     dmem_not_imem &&
	     tlb$lookup[68] &&
	     tlb$lookup[73] ;
  assign rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d458 =
	     rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d419 &&
	     NOT_cfg_verbosity_read__9_ULT_2_46___d447 &&
	     (!dmem_not_imem || !tlb$lookup[68] || !tlb$lookup[73]) ;
  assign rg_priv_4_ULE_0b1___d85 = rg_priv <= 2'b01 ;
  assign rg_st_amo_val_BITS_31_TO_0__q33 = rg_st_amo_val[31:0] ;
  assign rg_state_9_EQ_13_145_AND_rg_op_11_EQ_0_12_OR_r_ETC___d1147 =
	     rg_state == 5'd13 &&
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     b__h28508 == 4'd0 ;
  assign satp_pa__h1898 = { 8'd0, x__h4911 } ;
  assign shift_bits__h2833 = { f_fabric_write_reqs$D_OUT[66:64], 3'b0 } ;
  assign strobe64__h2983 = 8'b00000001 << f_fabric_write_reqs$D_OUT[66:64] ;
  assign strobe64__h2985 = 8'b00000011 << f_fabric_write_reqs$D_OUT[66:64] ;
  assign strobe64__h2987 = 8'b00001111 << f_fabric_write_reqs$D_OUT[66:64] ;
  assign tlb_lookup_rg_satp_7_BITS_59_TO_44_4_rg_addr_5_ETC___d131 =
	     tlb$lookup[67] | y__h6385 ;
  assign tlb_lookup_rg_satp_7_BITS_59_TO_44_4_rg_addr_5_ETC___d391 =
	     tlb$lookup[72] &&
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 ||
	      tlb$lookup[73]) ;
  assign tmp__h31848 = { 1'd0, rg_victim_way } ;
  assign tmp__h31849 = tmp__h31848 + 2'd1 ;
  assign value__h6884 =
	     (rg_priv_4_ULE_0b1___d85 && rg_satp[63:60] == 4'd8) ?
	       _theResult___snd_fst__h6149 :
	       tlb$lookup[129:66] ;
  assign vpn_0_pa__h30536 = { 52'd0, rg_addr[20:12], 3'd0 } ;
  assign vpn_1_pa__h29503 = { 52'd0, rg_addr[29:21], 3'd0 } ;
  assign vpn_2_pa__h28606 = { 52'd0, rg_addr[38:30], 3'd0 } ;
  assign w17659_BITS_31_TO_0__q52 = w1__h37659[31:0] ;
  assign w1___1__h25627 =
	     { 32'd0,
	       IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_5_BITS_2_ETC___d651[31:0] } ;
  assign w1___1__h37734 = { 32'd0, w1__h37659[31:0] } ;
  assign w2___1__h37735 = { 32'd0, rg_st_amo_val[31:0] } ;
  assign w2__h37665 = (rg_f3 == 3'b010) ? w2___1__h37735 : rg_st_amo_val ;
  assign word64577_BITS_15_TO_0__q16 = word64__h7577[15:0] ;
  assign word64577_BITS_15_TO_8__q18 = word64__h7577[15:8] ;
  assign word64577_BITS_23_TO_16__q19 = word64__h7577[23:16] ;
  assign word64577_BITS_31_TO_0__q17 = word64__h7577[31:0] ;
  assign word64577_BITS_31_TO_16__q20 = word64__h7577[31:16] ;
  assign word64577_BITS_31_TO_24__q21 = word64__h7577[31:24] ;
  assign word64577_BITS_39_TO_32__q22 = word64__h7577[39:32] ;
  assign word64577_BITS_47_TO_32__q23 = word64__h7577[47:32] ;
  assign word64577_BITS_47_TO_40__q25 = word64__h7577[47:40] ;
  assign word64577_BITS_55_TO_48__q26 = word64__h7577[55:48] ;
  assign word64577_BITS_63_TO_32__q24 = word64__h7577[63:32] ;
  assign word64577_BITS_63_TO_48__q27 = word64__h7577[63:48] ;
  assign word64577_BITS_63_TO_56__q28 = word64__h7577[63:56] ;
  assign word64577_BITS_7_TO_0__q15 = word64__h7577[7:0] ;
  assign word64__h7577 = x__h7728 | y__h7729 ;
  assign x1_avValue_exc_code__h6059 =
	     dmem_not_imem ?
	       ((rg_op == 2'd0 ||
		 rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
		  4'd13 :
		  4'd15) :
	       4'd12 ;
  assign x1_avValue_pa__h6058 = soc_map$m_is_mem_addr_addr ;
  assign x__h21713 = { 63'd0, lrsc_result__h21703 } ;
  assign x__h29583 = { master_xactor_f_rd_data$D_OUT[56:13], 12'b0 } ;
  assign x__h37654 =
	     (rg_f3 == 3'b010) ?
	       new_st_val__h37675 :
	       _theResult_____2__h37671 ;
  assign x__h4911 = { rg_satp[43:0], 12'b0 } ;
  assign x__h6570 = { tlb$lookup[119:76], rg_addr[11:0] } ;
  assign x__h6619 = { tlb$lookup[119:85], rg_addr[20:0] } ;
  assign x__h6688 = { tlb$lookup[119:94], rg_addr[29:0] } ;
  assign x__h7728 = ram_word64_set$DOB[63:0] & y__h7743 ;
  assign y__h14058 =
	     {64{ram_state_and_ctag_cset$DOB[105] &&
		 ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209}} ;
  assign y__h6385 = rg_mstatus_MXR & tlb$lookup[69] ;
  assign y__h7729 = ram_word64_set$DOB[127:64] & y__h14058 ;
  assign y__h7743 =
	     {64{ram_state_and_ctag_cset$DOB[52] &&
		 ram_state_and_ctag_cset_b_read__98_BITS_51_TO__ETC___d203}} ;
  always@(f_fabric_write_reqs$D_OUT)
  begin
    case (f_fabric_write_reqs$D_OUT[129:128])
      2'b0: x__h2866 = 3'b0;
      2'b01: x__h2866 = 3'b001;
      2'b10: x__h2866 = 3'b010;
      2'b11: x__h2866 = 3'b011;
    endcase
  end
  always@(rg_f3)
  begin
    case (rg_f3[1:0])
      2'b0: value__h37211 = 3'b0;
      2'b01: value__h37211 = 3'b001;
      2'b10: value__h37211 = 3'b010;
      2'd3: value__h37211 = 3'b011;
    endcase
  end
  always@(tlb$lookup or
	  rg_addr or pa___1__h6567 or pa___1__h6616 or pa___1__h6685)
  begin
    case (tlb$lookup[65:64])
      2'd0: _theResult___fst__h6561 = pa___1__h6567;
      2'd1: _theResult___fst__h6561 = pa___1__h6616;
      2'd2: _theResult___fst__h6561 = pa___1__h6685;
      2'd3: _theResult___fst__h6561 = rg_addr;
    endcase
  end
  always@(f_fabric_write_reqs$D_OUT or
	  strobe64__h2983 or strobe64__h2985 or strobe64__h2987)
  begin
    case (f_fabric_write_reqs$D_OUT[129:128])
      2'b0: mem_req_wr_data_wstrb__h3046 = strobe64__h2983;
      2'b01: mem_req_wr_data_wstrb__h3046 = strobe64__h2985;
      2'b10: mem_req_wr_data_wstrb__h3046 = strobe64__h2987;
      2'b11: mem_req_wr_data_wstrb__h3046 = 8'b11111111;
    endcase
  end
  always@(f_fabric_write_reqs$D_OUT or _theResult___snd_fst__h3053)
  begin
    case (f_fabric_write_reqs$D_OUT[129:128])
      2'b0, 2'b01, 2'b10:
	  mem_req_wr_data_wdata__h3045 = _theResult___snd_fst__h3053;
      2'd3: mem_req_wr_data_wdata__h3045 = f_fabric_write_reqs$D_OUT[63:0];
    endcase
  end
  always@(ram_state_and_ctag_cset$DOB or
	  ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209 or
	  ram_word64_set$DOB)
  begin
    case (ram_state_and_ctag_cset$DOB[105] &&
	  ram_state_and_ctag_cset_b_read__98_BITS_104_TO_ETC___d209)
      1'd0: old_word64__h22481 = ram_word64_set$DOB[63:0];
      1'd1: old_word64__h22481 = ram_word64_set$DOB[127:64];
    endcase
  end
  always@(rg_f3 or
	  NOT_ram_state_and_ctag_cset_b_read__98_BIT_105_ETC___d234 or
	  rg_priv_4_ULE_0b1___d85 or rg_satp or tlb$RDY_lookup)
  begin
    case (rg_f3)
      3'b0, 3'b001, 3'b010:
	  IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b1_40_OR_ETC___d277 =
	      !rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	      tlb$RDY_lookup;
      default: IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b1_40_OR_ETC___d277 =
		   rg_f3 == 3'b011 ||
		   NOT_ram_state_and_ctag_cset_b_read__98_BIT_105_ETC___d234;
    endcase
  end
  always@(rg_addr or
	  NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d233 or
	  NOT_ram_state_and_ctag_cset_b_read__98_BIT_105_ETC___d234)
  begin
    case (rg_addr[2:0])
      3'h0, 3'h1, 3'h2, 3'h3, 3'h4, 3'h5, 3'h6:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_OR_rg_ad_ETC___d239 =
	      NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d233 &&
	      NOT_ram_state_and_ctag_cset_b_read__98_BIT_105_ETC___d234;
      3'd7:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_OR_rg_ad_ETC___d239 =
	      rg_addr[2:0] != 3'h7 ||
	      NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d233 &&
	      NOT_ram_state_and_ctag_cset_b_read__98_BIT_105_ETC___d234;
    endcase
  end
  always@(rg_addr or
	  NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d233 or
	  NOT_ram_state_and_ctag_cset_b_read__98_BIT_105_ETC___d234)
  begin
    case (rg_addr[2:0])
      3'h0, 3'h2, 3'h4:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_OR_rg_ad_ETC___d247 =
	      NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d233 &&
	      NOT_ram_state_and_ctag_cset_b_read__98_BIT_105_ETC___d234;
      default: IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_OR_rg_ad_ETC___d247 =
		   rg_addr[2:0] != 3'h6 ||
		   NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d233 &&
		   NOT_ram_state_and_ctag_cset_b_read__98_BIT_105_ETC___d234;
    endcase
  end
  always@(rg_f3 or
	  rg_addr or
	  NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d233 or
	  NOT_ram_state_and_ctag_cset_b_read__98_BIT_105_ETC___d234 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_OR_rg_ad_ETC___d239 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_OR_rg_ad_ETC___d247 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_NOT_ETC___d253)
  begin
    case (rg_f3)
      3'b0, 3'b100:
	  IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b100_17__ETC___d261 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_OR_rg_ad_ETC___d239;
      3'b001, 3'b101:
	  IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b100_17__ETC___d261 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_OR_rg_ad_ETC___d247;
      3'b010, 3'b110:
	  IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b100_17__ETC___d261 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_NOT_ETC___d253;
      default: IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b100_17__ETC___d261 =
		   rg_f3 != 3'b011 || rg_addr[2:0] != 3'h0 ||
		   NOT_ram_state_and_ctag_cset_b_read__98_BIT_52__ETC___d233 &&
		   NOT_ram_state_and_ctag_cset_b_read__98_BIT_105_ETC___d234;
    endcase
  end
  always@(rg_amo_funct7 or
	  IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b100_17__ETC___d261)
  begin
    case (rg_amo_funct7[6:2])
      5'b0, 5'b00100, 5'b01000, 5'b01100, 5'b10000, 5'b11000, 5'b11100:
	  CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_15_ETC__q29 =
	      IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b100_17__ETC___d261;
      default: CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_15_ETC__q29 =
		   rg_amo_funct7[6:2] != 5'b10100 ||
		   IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b100_17__ETC___d261;
    endcase
  end
  always@(x1_avValue_pa__h6058 or
	  NOT_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS__ETC___d327 or
	  CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_15_ETC__q29)
  begin
    case (x1_avValue_pa__h6058[2:0])
      3'h0, 3'h2, 3'h4:
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d328 =
	      CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_15_ETC__q29;
      default: IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d328 =
		   NOT_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS__ETC___d327;
    endcase
  end
  always@(x1_avValue_pa__h6058 or
	  NOT_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS__ETC___d321 or
	  CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_15_ETC__q29)
  begin
    case (x1_avValue_pa__h6058[2:0])
      3'h0, 3'h1, 3'h2, 3'h3, 3'h4, 3'h5, 3'h6:
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d322 =
	      CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_15_ETC__q29;
      3'd7:
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d322 =
	      NOT_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS__ETC___d321;
    endcase
  end
  always@(rg_f3 or
	  NOT_ram_state_and_ctag_cset_b_read__98_BIT_105_ETC___d234 or
	  rg_priv_4_ULE_0b1___d85 or
	  rg_satp or
	  tlb$RDY_lookup or
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d322 or
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d328 or
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d332 or
	  CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_15_ETC__q29)
  begin
    case (rg_f3)
      3'b0:
	  IF_rg_f3_15_EQ_0b0_16_THEN_NOT_rg_priv_4_ULE_0_ETC___d337 =
	      (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	       tlb$RDY_lookup) &&
	      IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d322;
      3'b001:
	  IF_rg_f3_15_EQ_0b0_16_THEN_NOT_rg_priv_4_ULE_0_ETC___d337 =
	      (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	       tlb$RDY_lookup) &&
	      IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d328;
      3'b010:
	  IF_rg_f3_15_EQ_0b0_16_THEN_NOT_rg_priv_4_ULE_0_ETC___d337 =
	      (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	       tlb$RDY_lookup) &&
	      IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d332;
      3'b011:
	  IF_rg_f3_15_EQ_0b0_16_THEN_NOT_rg_priv_4_ULE_0_ETC___d337 =
	      CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_15_ETC__q29;
      default: IF_rg_f3_15_EQ_0b0_16_THEN_NOT_rg_priv_4_ULE_0_ETC___d337 =
		   NOT_ram_state_and_ctag_cset_b_read__98_BIT_105_ETC___d234;
    endcase
  end
  always@(rg_addr or
	  result__h20414 or
	  result__h20442 or
	  result__h20470 or
	  result__h20498 or
	  result__h20526 or
	  result__h20554 or result__h20582 or result__h20610)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d597 =
	      result__h20414;
      3'h1:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d597 =
	      result__h20442;
      3'h2:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d597 =
	      result__h20470;
      3'h3:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d597 =
	      result__h20498;
      3'h4:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d597 =
	      result__h20526;
      3'h5:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d597 =
	      result__h20554;
      3'h6:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d597 =
	      result__h20582;
      3'h7:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d597 =
	      result__h20610;
    endcase
  end
  always@(rg_addr or
	  result__h20655 or
	  result__h20683 or
	  result__h20711 or
	  result__h20739 or
	  result__h20767 or
	  result__h20795 or result__h20823 or result__h20851)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d613 =
	      result__h20655;
      3'h1:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d613 =
	      result__h20683;
      3'h2:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d613 =
	      result__h20711;
      3'h3:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d613 =
	      result__h20739;
      3'h4:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d613 =
	      result__h20767;
      3'h5:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d613 =
	      result__h20795;
      3'h6:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d613 =
	      result__h20823;
      3'h7:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d613 =
	      result__h20851;
    endcase
  end
  always@(rg_addr or
	  result__h20896 or
	  result__h20924 or result__h20952 or result__h20980)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d625 =
	      result__h20896;
      3'h2:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d625 =
	      result__h20924;
      3'h4:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d625 =
	      result__h20952;
      3'h6:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d625 =
	      result__h20980;
      default: IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d625 =
		   64'd0;
    endcase
  end
  always@(rg_addr or
	  result__h21021 or
	  result__h21049 or result__h21077 or result__h21105)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d633 =
	      result__h21021;
      3'h2:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d633 =
	      result__h21049;
      3'h4:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d633 =
	      result__h21077;
      3'h6:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d633 =
	      result__h21105;
      default: IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d633 =
		   64'd0;
    endcase
  end
  always@(rg_addr or result__h21213 or result__h21241)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d643 =
	      result__h21213;
      3'h4:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d643 =
	      result__h21241;
      default: IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d643 =
		   64'd0;
    endcase
  end
  always@(rg_addr or result__h21146 or result__h21174)
  begin
    case (rg_addr[2:0])
      3'h0:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result1146_0x4_re_ETC__q30 =
	      result__h21146;
      3'h4:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result1146_0x4_re_ETC__q30 =
	      result__h21174;
      default: CASE_rg_addr_BITS_2_TO_0_0x0_result1146_0x4_re_ETC__q30 =
		   64'd0;
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d597 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d625 or
	  CASE_rg_addr_BITS_2_TO_0_0x0_result1146_0x4_re_ETC__q30 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_ram_ETC___d644 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d613 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d633 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d643)
  begin
    case (rg_f3)
      3'b0:
	  IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_5_BITS_2_ETC___d651 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d597;
      3'b001:
	  IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_5_BITS_2_ETC___d651 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d625;
      3'b010:
	  IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_5_BITS_2_ETC___d651 =
	      CASE_rg_addr_BITS_2_TO_0_0x0_result1146_0x4_re_ETC__q30;
      3'b011:
	  IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_5_BITS_2_ETC___d651 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_ram_ETC___d644;
      3'b100:
	  IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_5_BITS_2_ETC___d651 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d613;
      3'b101:
	  IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_5_BITS_2_ETC___d651 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d633;
      3'b110:
	  IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_5_BITS_2_ETC___d651 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d643;
      3'd7: IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_5_BITS_2_ETC___d651 = 64'd0;
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d597 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d625 or
	  w1___1__h25627 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_ram_ETC___d644 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d613 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d633 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d643)
  begin
    case (rg_f3)
      3'b0:
	  w1__h25556 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d597;
      3'b001:
	  w1__h25556 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d625;
      3'b010: w1__h25556 = w1___1__h25627;
      3'b011:
	  w1__h25556 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_ram_ETC___d644;
      3'b100:
	  w1__h25556 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d613;
      3'b101:
	  w1__h25556 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d633;
      3'b110:
	  w1__h25556 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d643;
      3'd7: w1__h25556 = 64'd0;
    endcase
  end
  always@(x1_avValue_pa__h6058 or old_word64__h22481 or rg_st_amo_val)
  begin
    case (x1_avValue_pa__h6058[2:0])
      3'h0:
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d765 =
	      { old_word64__h22481[63:16], rg_st_amo_val[15:0] };
      3'h2:
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d765 =
	      { old_word64__h22481[63:32],
		rg_st_amo_val[15:0],
		old_word64__h22481[15:0] };
      3'h4:
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d765 =
	      { old_word64__h22481[63:48],
		rg_st_amo_val[15:0],
		old_word64__h22481[31:0] };
      3'h6:
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d765 =
	      { rg_st_amo_val[15:0], old_word64__h22481[47:0] };
      default: IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d765 =
		   old_word64__h22481;
    endcase
  end
  always@(x1_avValue_pa__h6058 or old_word64__h22481 or rg_st_amo_val)
  begin
    case (x1_avValue_pa__h6058[2:0])
      3'h0:
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d756 =
	      { old_word64__h22481[63:8], rg_st_amo_val[7:0] };
      3'h1:
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d756 =
	      { old_word64__h22481[63:16],
		rg_st_amo_val[7:0],
		old_word64__h22481[7:0] };
      3'h2:
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d756 =
	      { old_word64__h22481[63:24],
		rg_st_amo_val[7:0],
		old_word64__h22481[15:0] };
      3'h3:
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d756 =
	      { old_word64__h22481[63:32],
		rg_st_amo_val[7:0],
		old_word64__h22481[23:0] };
      3'h4:
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d756 =
	      { old_word64__h22481[63:40],
		rg_st_amo_val[7:0],
		old_word64__h22481[31:0] };
      3'h5:
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d756 =
	      { old_word64__h22481[63:48],
		rg_st_amo_val[7:0],
		old_word64__h22481[39:0] };
      3'h6:
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d756 =
	      { old_word64__h22481[63:56],
		rg_st_amo_val[7:0],
		old_word64__h22481[47:0] };
      3'h7:
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d756 =
	      { rg_st_amo_val[7:0], old_word64__h22481[55:0] };
    endcase
  end
  always@(x1_avValue_pa__h6058 or old_word64__h22481 or rg_st_amo_val)
  begin
    case (x1_avValue_pa__h6058[2:0])
      3'h0:
	  CASE_x1_avValue_pa058_BITS_2_TO_0_0x0_old_word_ETC__q31 =
	      { old_word64__h22481[63:32], rg_st_amo_val[31:0] };
      3'h4:
	  CASE_x1_avValue_pa058_BITS_2_TO_0_0x0_old_word_ETC__q31 =
	      { rg_st_amo_val[31:0], old_word64__h22481[31:0] };
      default: CASE_x1_avValue_pa058_BITS_2_TO_0_0x0_old_word_ETC__q31 =
		   old_word64__h22481;
    endcase
  end
  always@(rg_f3 or
	  old_word64__h22481 or
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d756 or
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d765 or
	  CASE_x1_avValue_pa058_BITS_2_TO_0_0x0_old_word_ETC__q31 or
	  rg_st_amo_val)
  begin
    case (rg_f3)
      3'b0:
	  n__h22492 =
	      IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d756;
      3'b001:
	  n__h22492 =
	      IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d765;
      3'b010:
	  n__h22492 = CASE_x1_avValue_pa058_BITS_2_TO_0_0x0_old_word_ETC__q31;
      3'b011: n__h22492 = rg_st_amo_val;
      default: n__h22492 = old_word64__h22481;
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d597 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d625 or
	  IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_5_BITS_2_ETC__q32 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_ram_ETC___d644 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d613 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d633 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d643)
  begin
    case (rg_f3)
      3'b0:
	  IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_IF_rg_f3_15_E_ETC___d712 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d597;
      3'b001:
	  IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_IF_rg_f3_15_E_ETC___d712 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d625;
      3'b010:
	  IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_IF_rg_f3_15_E_ETC___d712 =
	      { {32{IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_5_BITS_2_ETC__q32[31]}},
		IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_5_BITS_2_ETC__q32 };
      3'b011:
	  IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_IF_rg_f3_15_E_ETC___d712 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_ram_ETC___d644;
      3'b100:
	  IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_IF_rg_f3_15_E_ETC___d712 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d613;
      3'b101:
	  IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_IF_rg_f3_15_E_ETC___d712 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d633;
      3'b110:
	  IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_IF_rg_f3_15_E_ETC___d712 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d643;
      3'd7: IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_IF_rg_f3_15_E_ETC___d712 = 64'd0;
    endcase
  end
  always@(rg_amo_funct7 or
	  new_st_val__h26667 or
	  new_st_val__h25659 or
	  w2__h37665 or
	  new_st_val__h26639 or
	  new_st_val__h26647 or
	  new_st_val__h26643 or
	  new_st_val__h26662 or new_st_val__h26651 or new_st_val__h26656)
  begin
    case (rg_amo_funct7[6:2])
      5'b0: _theResult_____2__h25564 = new_st_val__h25659;
      5'b00001: _theResult_____2__h25564 = w2__h37665;
      5'b00100: _theResult_____2__h25564 = new_st_val__h26639;
      5'b01000: _theResult_____2__h25564 = new_st_val__h26647;
      5'b01100: _theResult_____2__h25564 = new_st_val__h26643;
      5'b10000: _theResult_____2__h25564 = new_st_val__h26662;
      5'b11000: _theResult_____2__h25564 = new_st_val__h26651;
      5'b11100: _theResult_____2__h25564 = new_st_val__h26656;
      default: _theResult_____2__h25564 = new_st_val__h26667;
    endcase
  end
  always@(x1_avValue_pa__h6058 or old_word64__h22481 or new_st_val__h25262)
  begin
    case (x1_avValue_pa__h6058[2:0])
      3'h0:
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d833 =
	      { old_word64__h22481[63:16], new_st_val__h25262[15:0] };
      3'h2:
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d833 =
	      { old_word64__h22481[63:32],
		new_st_val__h25262[15:0],
		old_word64__h22481[15:0] };
      3'h4:
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d833 =
	      { old_word64__h22481[63:48],
		new_st_val__h25262[15:0],
		old_word64__h22481[31:0] };
      3'h6:
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d833 =
	      { new_st_val__h25262[15:0], old_word64__h22481[47:0] };
      default: IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d833 =
		   old_word64__h22481;
    endcase
  end
  always@(x1_avValue_pa__h6058 or old_word64__h22481 or new_st_val__h25262)
  begin
    case (x1_avValue_pa__h6058[2:0])
      3'h0:
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d824 =
	      { old_word64__h22481[63:8], new_st_val__h25262[7:0] };
      3'h1:
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d824 =
	      { old_word64__h22481[63:16],
		new_st_val__h25262[7:0],
		old_word64__h22481[7:0] };
      3'h2:
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d824 =
	      { old_word64__h22481[63:24],
		new_st_val__h25262[7:0],
		old_word64__h22481[15:0] };
      3'h3:
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d824 =
	      { old_word64__h22481[63:32],
		new_st_val__h25262[7:0],
		old_word64__h22481[23:0] };
      3'h4:
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d824 =
	      { old_word64__h22481[63:40],
		new_st_val__h25262[7:0],
		old_word64__h22481[31:0] };
      3'h5:
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d824 =
	      { old_word64__h22481[63:48],
		new_st_val__h25262[7:0],
		old_word64__h22481[39:0] };
      3'h6:
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d824 =
	      { old_word64__h22481[63:56],
		new_st_val__h25262[7:0],
		old_word64__h22481[47:0] };
      3'h7:
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d824 =
	      { new_st_val__h25262[7:0], old_word64__h22481[55:0] };
    endcase
  end
  always@(x1_avValue_pa__h6058 or old_word64__h22481 or new_st_val__h25262)
  begin
    case (x1_avValue_pa__h6058[2:0])
      3'h0:
	  CASE_x1_avValue_pa058_BITS_2_TO_0_0x0_old_word_ETC__q34 =
	      { old_word64__h22481[63:32], new_st_val__h25262[31:0] };
      3'h4:
	  CASE_x1_avValue_pa058_BITS_2_TO_0_0x0_old_word_ETC__q34 =
	      { new_st_val__h25262[31:0], old_word64__h22481[31:0] };
      default: CASE_x1_avValue_pa058_BITS_2_TO_0_0x0_old_word_ETC__q34 =
		   old_word64__h22481;
    endcase
  end
  always@(rg_f3 or
	  old_word64__h22481 or
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d824 or
	  IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d833 or
	  CASE_x1_avValue_pa058_BITS_2_TO_0_0x0_old_word_ETC__q34 or
	  new_st_val__h25262)
  begin
    case (rg_f3)
      3'b0:
	  n__h25426 =
	      IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d824;
      3'b001:
	  n__h25426 =
	      IF_IF_rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_6_ETC___d833;
      3'b010:
	  n__h25426 = CASE_x1_avValue_pa058_BITS_2_TO_0_0x0_old_word_ETC__q34;
      3'b011: n__h25426 = new_st_val__h25262;
      default: n__h25426 = old_word64__h22481;
    endcase
  end
  always@(rg_addr or
	  result__h36069 or
	  result__h36096 or result__h36123 or result__h36150)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1225 =
	      result__h36069;
      3'h2:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1225 =
	      result__h36096;
      3'h4:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1225 =
	      result__h36123;
      3'h6:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1225 =
	      result__h36150;
      default: IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1225 =
		   64'd0;
    endcase
  end
  always@(rg_addr or
	  result__h35948 or
	  result__h35975 or result__h36002 or result__h36029)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1217 =
	      result__h35948;
      3'h2:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1217 =
	      result__h35975;
      3'h4:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1217 =
	      result__h36002;
      3'h6:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1217 =
	      result__h36029;
      default: IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1217 =
		   64'd0;
    endcase
  end
  always@(rg_addr or
	  result__h35715 or
	  result__h35742 or
	  result__h35769 or
	  result__h35796 or
	  result__h35823 or
	  result__h35850 or result__h35877 or result__h35904)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1205 =
	      result__h35715;
      3'h1:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1205 =
	      result__h35742;
      3'h2:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1205 =
	      result__h35769;
      3'h3:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1205 =
	      result__h35796;
      3'h4:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1205 =
	      result__h35823;
      3'h5:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1205 =
	      result__h35850;
      3'h6:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1205 =
	      result__h35877;
      3'h7:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1205 =
	      result__h35904;
    endcase
  end
  always@(rg_addr or
	  result__h35479 or
	  result__h35509 or
	  result__h35536 or
	  result__h35563 or
	  result__h35590 or
	  result__h35617 or result__h35644 or result__h35671)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1189 =
	      result__h35479;
      3'h1:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1189 =
	      result__h35509;
      3'h2:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1189 =
	      result__h35536;
      3'h3:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1189 =
	      result__h35563;
      3'h4:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1189 =
	      result__h35590;
      3'h5:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1189 =
	      result__h35617;
      3'h6:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1189 =
	      result__h35644;
      3'h7:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1189 =
	      result__h35671;
    endcase
  end
  always@(rg_addr or result__h36190 or result__h36217)
  begin
    case (rg_addr[2:0])
      3'h0:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result6190_0x4_re_ETC__q35 =
	      result__h36190;
      3'h4:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result6190_0x4_re_ETC__q35 =
	      result__h36217;
      default: CASE_rg_addr_BITS_2_TO_0_0x0_result6190_0x4_re_ETC__q35 =
		   64'd0;
    endcase
  end
  always@(rg_addr or result__h36255 or result__h36282)
  begin
    case (rg_addr[2:0])
      3'h0:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result6255_0x4_re_ETC__q36 =
	      result__h36255;
      3'h4:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result6255_0x4_re_ETC__q36 =
	      result__h36282;
      default: CASE_rg_addr_BITS_2_TO_0_0x0_result6255_0x4_re_ETC__q36 =
		   64'd0;
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1189 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1217 or
	  CASE_rg_addr_BITS_2_TO_0_0x0_result6190_0x4_re_ETC__q35 or
	  rg_addr or
	  master_xactor_f_rd_data$D_OUT or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1205 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1225 or
	  CASE_rg_addr_BITS_2_TO_0_0x0_result6255_0x4_re_ETC__q36)
  begin
    case (rg_f3)
      3'b0:
	  ld_val__h35419 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1189;
      3'b001:
	  ld_val__h35419 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1217;
      3'b010:
	  ld_val__h35419 =
	      CASE_rg_addr_BITS_2_TO_0_0x0_result6190_0x4_re_ETC__q35;
      3'b011:
	  ld_val__h35419 =
	      (rg_addr[2:0] == 3'h0) ?
		master_xactor_f_rd_data$D_OUT[66:3] :
		64'd0;
      3'b100:
	  ld_val__h35419 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1205;
      3'b101:
	  ld_val__h35419 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1225;
      3'b110:
	  ld_val__h35419 =
	      CASE_rg_addr_BITS_2_TO_0_0x0_result6255_0x4_re_ETC__q36;
      3'd7: ld_val__h35419 = 64'd0;
    endcase
  end
  always@(rg_addr or result__h39533 or result__h39561)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1344 =
	      result__h39533;
      3'h4:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1344 =
	      result__h39561;
      default: IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1344 =
		   64'd0;
    endcase
  end
  always@(rg_addr or
	  result__h39341 or
	  result__h39369 or result__h39397 or result__h39425)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1334 =
	      result__h39341;
      3'h2:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1334 =
	      result__h39369;
      3'h4:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1334 =
	      result__h39397;
      3'h6:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1334 =
	      result__h39425;
      default: IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1334 =
		   64'd0;
    endcase
  end
  always@(rg_addr or
	  result__h39216 or
	  result__h39244 or result__h39272 or result__h39300)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1326 =
	      result__h39216;
      3'h2:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1326 =
	      result__h39244;
      3'h4:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1326 =
	      result__h39272;
      3'h6:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1326 =
	      result__h39300;
      default: IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1326 =
		   64'd0;
    endcase
  end
  always@(rg_addr or
	  result__h38975 or
	  result__h39003 or
	  result__h39031 or
	  result__h39059 or
	  result__h39087 or
	  result__h39115 or result__h39143 or result__h39171)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1314 =
	      result__h38975;
      3'h1:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1314 =
	      result__h39003;
      3'h2:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1314 =
	      result__h39031;
      3'h3:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1314 =
	      result__h39059;
      3'h4:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1314 =
	      result__h39087;
      3'h5:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1314 =
	      result__h39115;
      3'h6:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1314 =
	      result__h39143;
      3'h7:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1314 =
	      result__h39171;
    endcase
  end
  always@(rg_addr or
	  result__h37854 or
	  result__h38762 or
	  result__h38790 or
	  result__h38818 or
	  result__h38846 or
	  result__h38874 or result__h38902 or result__h38930)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1298 =
	      result__h37854;
      3'h1:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1298 =
	      result__h38762;
      3'h2:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1298 =
	      result__h38790;
      3'h3:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1298 =
	      result__h38818;
      3'h4:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1298 =
	      result__h38846;
      3'h5:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1298 =
	      result__h38874;
      3'h6:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1298 =
	      result__h38902;
      3'h7:
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1298 =
	      result__h38930;
    endcase
  end
  always@(rg_addr or result__h39466 or result__h39494)
  begin
    case (rg_addr[2:0])
      3'h0:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result9466_0x4_re_ETC__q51 =
	      result__h39466;
      3'h4:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result9466_0x4_re_ETC__q51 =
	      result__h39494;
      default: CASE_rg_addr_BITS_2_TO_0_0x0_result9466_0x4_re_ETC__q51 =
		   64'd0;
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1298 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1326 or
	  CASE_rg_addr_BITS_2_TO_0_0x0_result9466_0x4_re_ETC__q51 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_IF__ETC___d1345 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1314 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1334 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1344)
  begin
    case (rg_f3)
      3'b0:
	  w1__h37659 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1298;
      3'b001:
	  w1__h37659 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1326;
      3'b010:
	  w1__h37659 =
	      CASE_rg_addr_BITS_2_TO_0_0x0_result9466_0x4_re_ETC__q51;
      3'b011:
	  w1__h37659 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_IF__ETC___d1345;
      3'b100:
	  w1__h37659 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1314;
      3'b101:
	  w1__h37659 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1334;
      3'b110:
	  w1__h37659 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1344;
      3'd7: w1__h37659 = 64'd0;
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1298 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1326 or
	  w1___1__h37734 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_IF__ETC___d1345 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1314 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1334 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1344)
  begin
    case (rg_f3)
      3'b0:
	  w1__h37663 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1298;
      3'b001:
	  w1__h37663 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1326;
      3'b010: w1__h37663 = w1___1__h37734;
      3'b011:
	  w1__h37663 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_IF__ETC___d1345;
      3'b100:
	  w1__h37663 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1314;
      3'b101:
	  w1__h37663 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1334;
      3'b110:
	  w1__h37663 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1344;
      3'd7: w1__h37663 = 64'd0;
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1298 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1326 or
	  w17659_BITS_31_TO_0__q52 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_IF__ETC___d1345 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1314 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1334 or
	  IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1344)
  begin
    case (rg_f3)
      3'b0:
	  new_ld_val__h37625 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1298;
      3'b001:
	  new_ld_val__h37625 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_SEX_ETC___d1326;
      3'b010:
	  new_ld_val__h37625 =
	      { {32{w17659_BITS_31_TO_0__q52[31]}},
		w17659_BITS_31_TO_0__q52 };
      3'b011:
	  new_ld_val__h37625 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_IF__ETC___d1345;
      3'b100:
	  new_ld_val__h37625 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1314;
      3'b101:
	  new_ld_val__h37625 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1334;
      3'b110:
	  new_ld_val__h37625 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_0_C_ETC___d1344;
      3'd7: new_ld_val__h37625 = 64'd0;
    endcase
  end
  always@(rg_amo_funct7 or
	  new_st_val__h39654 or
	  new_st_val__h37766 or
	  w2__h37665 or
	  new_st_val__h39626 or
	  new_st_val__h39634 or
	  new_st_val__h39630 or
	  new_st_val__h39649 or new_st_val__h39638 or new_st_val__h39643)
  begin
    case (rg_amo_funct7[6:2])
      5'b0: _theResult_____2__h37671 = new_st_val__h37766;
      5'b00001: _theResult_____2__h37671 = w2__h37665;
      5'b00100: _theResult_____2__h37671 = new_st_val__h39626;
      5'b01000: _theResult_____2__h37671 = new_st_val__h39634;
      5'b01100: _theResult_____2__h37671 = new_st_val__h39630;
      5'b10000: _theResult_____2__h37671 = new_st_val__h39649;
      5'b11000: _theResult_____2__h37671 = new_st_val__h39638;
      5'b11100: _theResult_____2__h37671 = new_st_val__h39643;
      default: _theResult_____2__h37671 = new_st_val__h39654;
    endcase
  end
  always@(rg_f3 or IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_1_E_ETC___d659)
  begin
    case (rg_f3)
      3'b0, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110:
	  CASE_rg_f3_0b0_IF_rg_addr_5_BITS_2_TO_0_19_EQ__ETC__q53 =
	      IF_rg_addr_5_BITS_2_TO_0_19_EQ_0x0_20_THEN_1_E_ETC___d659;
      3'd7: CASE_rg_f3_0b0_IF_rg_addr_5_BITS_2_TO_0_19_EQ__ETC__q53 = 64'd0;
    endcase
  end

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
	ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY 4'd0;
	rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY 6'd0;
	rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY 1'd0;
	rg_state <= `BSV_ASSIGNMENT_DELAY 5'd0;
      end
    else
      begin
        if (cfg_verbosity$EN)
	  cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
	if (ctr_wr_rsps_pending_crg$EN)
	  ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY
	      ctr_wr_rsps_pending_crg$D_IN;
	if (rg_cset_in_cache$EN)
	  rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY rg_cset_in_cache$D_IN;
	if (rg_lower_word32_full$EN)
	  rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY
	      rg_lower_word32_full$D_IN;
	if (rg_lrsc_valid$EN)
	  rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY rg_lrsc_valid$D_IN;
	if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
      end
    if (rg_addr$EN) rg_addr <= `BSV_ASSIGNMENT_DELAY rg_addr$D_IN;
    if (rg_amo_funct7$EN)
      rg_amo_funct7 <= `BSV_ASSIGNMENT_DELAY rg_amo_funct7$D_IN;
    if (rg_error_during_refill$EN)
      rg_error_during_refill <= `BSV_ASSIGNMENT_DELAY
	  rg_error_during_refill$D_IN;
    if (rg_exc_code$EN) rg_exc_code <= `BSV_ASSIGNMENT_DELAY rg_exc_code$D_IN;
    if (rg_f3$EN) rg_f3 <= `BSV_ASSIGNMENT_DELAY rg_f3$D_IN;
    if (rg_ld_val$EN) rg_ld_val <= `BSV_ASSIGNMENT_DELAY rg_ld_val$D_IN;
    if (rg_lower_word32$EN)
      rg_lower_word32 <= `BSV_ASSIGNMENT_DELAY rg_lower_word32$D_IN;
    if (rg_lrsc_pa$EN) rg_lrsc_pa <= `BSV_ASSIGNMENT_DELAY rg_lrsc_pa$D_IN;
    if (rg_mstatus_MXR$EN)
      rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY rg_mstatus_MXR$D_IN;
    if (rg_op$EN) rg_op <= `BSV_ASSIGNMENT_DELAY rg_op$D_IN;
    if (rg_pa$EN) rg_pa <= `BSV_ASSIGNMENT_DELAY rg_pa$D_IN;
    if (rg_priv$EN) rg_priv <= `BSV_ASSIGNMENT_DELAY rg_priv$D_IN;
    if (rg_pte_pa$EN) rg_pte_pa <= `BSV_ASSIGNMENT_DELAY rg_pte_pa$D_IN;
    if (rg_satp$EN) rg_satp <= `BSV_ASSIGNMENT_DELAY rg_satp$D_IN;
    if (rg_sstatus_SUM$EN)
      rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY rg_sstatus_SUM$D_IN;
    if (rg_st_amo_val$EN)
      rg_st_amo_val <= `BSV_ASSIGNMENT_DELAY rg_st_amo_val$D_IN;
    if (rg_victim_way$EN)
      rg_victim_way <= `BSV_ASSIGNMENT_DELAY rg_victim_way$D_IN;
    if (rg_word64_set_in_cache$EN)
      rg_word64_set_in_cache <= `BSV_ASSIGNMENT_DELAY
	  rg_word64_set_in_cache$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    cfg_verbosity = 4'hA;
    ctr_wr_rsps_pending_crg = 4'hA;
    rg_addr = 64'hAAAAAAAAAAAAAAAA;
    rg_amo_funct7 = 7'h2A;
    rg_cset_in_cache = 6'h2A;
    rg_error_during_refill = 1'h0;
    rg_exc_code = 4'hA;
    rg_f3 = 3'h2;
    rg_ld_val = 64'hAAAAAAAAAAAAAAAA;
    rg_lower_word32 = 32'hAAAAAAAA;
    rg_lower_word32_full = 1'h0;
    rg_lrsc_pa = 64'hAAAAAAAAAAAAAAAA;
    rg_lrsc_valid = 1'h0;
    rg_mstatus_MXR = 1'h0;
    rg_op = 2'h2;
    rg_pa = 64'hAAAAAAAAAAAAAAAA;
    rg_priv = 2'h2;
    rg_pte_pa = 64'hAAAAAAAAAAAAAAAA;
    rg_satp = 64'hAAAAAAAAAAAAAAAA;
    rg_sstatus_SUM = 1'h0;
    rg_st_amo_val = 64'hAAAAAAAAAAAAAAAA;
    rg_state = 5'h0A;
    rg_victim_way = 1'h0;
    rg_word64_set_in_cache = 9'h0AA;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  ctr_wr_rsps_pending_crg == 4'd15)
	begin
	  v__h3294 = $stime;
	  #0;
	end
    v__h3288 = v__h3294 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  ctr_wr_rsps_pending_crg == 4'd15)
	$display("%0d: ERROR: CreditCounter: overflow", v__h3288);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  ctr_wr_rsps_pending_crg == 4'd15)
	$finish(32'd1);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("            To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("AXI4_Wr_Addr { ", "awid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "awaddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", f_fabric_write_reqs$D_OUT[127:64]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "awlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "awsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", x__h2866);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "awburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "awlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "awcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "awprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "awqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "awregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "awuser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("                       ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("AXI4_Wr_Data { ", "wdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", mem_req_wr_data_wdata__h3045);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "wstrb: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", mem_req_wr_data_wstrb__h3046);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "wlast: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "wuser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
	  cfg_verbosity != 4'd0 &&
	  !f_reset_reqs$D_OUT)
	begin
	  v__h4543 = $stime;
	  #0;
	end
    v__h4537 = v__h4543 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
	  cfg_verbosity != 4'd0 &&
	  !f_reset_reqs$D_OUT)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY",
		   v__h4537,
		   "D_MMU_Cache",
		   $signed(32'd64),
		   $signed(32'd2));
	else
	  $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY",
		   v__h4537,
		   "I_MMU_Cache",
		   $signed(32'd64),
		   $signed(32'd2));
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
	  !cfg_verbosity_read__9_ULE_1___d40 &&
	  f_reset_reqs$D_OUT)
	begin
	  v__h4642 = $stime;
	  #0;
	end
    v__h4636 = v__h4642 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
	  !cfg_verbosity_read__9_ULE_1___d40 &&
	  f_reset_reqs$D_OUT)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_reset: Flushed", v__h4636, "D_MMU_Cache");
	else
	  $display("%0d: %s.rl_reset: Flushed", v__h4636, "I_MMU_Cache");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	begin
	  v__h4791 = $stime;
	  #0;
	end
    v__h4785 = v__h4791 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	if (dmem_not_imem)
	  $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h",
		   v__h4785,
		   "D_MMU_Cache",
		   rg_addr);
	else
	  $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h",
		   v__h4785,
		   "I_MMU_Cache",
		   rg_addr);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40 &&
	  rg_satp[63:60] != 4'd0)
	$display("        Priv:%0d  SATP:{mode %0d asid %0h pa %0h}  VA:%0h.%0h.%0h",
		 rg_priv,
		 rg_satp[63:60],
		 rg_satp[59:44],
		 satp_pa__h1898,
		 rg_addr[29:21],
		 rg_addr[20:12],
		 rg_addr[11:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$display("        eaddr = {CTag 0x%0h  CSet 0x%0h  Word64 0x%0h  Byte 0x%0h}",
		 rg_addr[63:12],
		 rg_addr[11:6],
		 rg_addr[5:3],
		 rg_addr[2:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("        CSet 0x%0x: (state, tag):", rg_addr[11:6]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(" (");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40 &&
	  ram_state_and_ctag_cset$DOB[52])
	$write("CTAG_CLEAN");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40 &&
	  !ram_state_and_ctag_cset$DOB[52])
	$write("CTAG_EMPTY");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40 &&
	  ram_state_and_ctag_cset$DOB[52])
	$write(", 0x%0x", ram_state_and_ctag_cset$DOB[51:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40 &&
	  !ram_state_and_ctag_cset$DOB[52])
	$write(", --");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(")");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(" (");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40 &&
	  ram_state_and_ctag_cset$DOB[105])
	$write("CTAG_CLEAN");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40 &&
	  !ram_state_and_ctag_cset$DOB[105])
	$write("CTAG_EMPTY");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40 &&
	  ram_state_and_ctag_cset$DOB[105])
	$write(", 0x%0x", ram_state_and_ctag_cset$DOB[104:53]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40 &&
	  !ram_state_and_ctag_cset$DOB[105])
	$write(", --");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(")");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("        CSet 0x%0x, Word64 0x%0x: ",
	       rg_addr[11:6],
	       rg_addr[5:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(" 0x%0x", ram_word64_set$DOB[63:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(" 0x%0x", ram_word64_set$DOB[127:64]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("    TLB result: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("VM_Xlate_Result { ", "outcome: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40 &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d394)
	$write("VM_XLATE_OK");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40 &&
	  rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d397)
	$write("VM_XLATE_EXCEPTION");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40 &&
	  rg_priv_4_ULE_0b1___d85 &&
	  rg_satp[63:60] == 4'd8 &&
	  !tlb$lookup[130])
	$write("VM_XLATE_TLB_MISS");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "pa: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", x1_avValue_pa__h6058);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "exc_code: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", x1_avValue_exc_code__h6059);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "pte_modified: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40 &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d409)
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40 &&
	  rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d419)
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "pte: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", value__h6884, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d419 &&
	  NOT_cfg_verbosity_read__9_ULT_2_46___d447)
	$display("    fa_record_pte_A_D_updates:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d419 &&
	  NOT_cfg_verbosity_read__9_ULT_2_46___d447)
	$write("      ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d419 &&
	  NOT_cfg_verbosity_read__9_ULT_2_46___d447)
	$write("TLB_Lookup_Result { ", "hit: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d419 &&
	  NOT_cfg_verbosity_read__9_ULT_2_46___d447)
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d419 &&
	  NOT_cfg_verbosity_read__9_ULT_2_46___d447)
	$write(", ", "pte: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d419 &&
	  NOT_cfg_verbosity_read__9_ULT_2_46___d447)
	$write("'h%h", tlb$lookup[129:66]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d419 &&
	  NOT_cfg_verbosity_read__9_ULT_2_46___d447)
	$write(", ", "pte_level: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d419 &&
	  NOT_cfg_verbosity_read__9_ULT_2_46___d447)
	$write("'h%h", tlb$lookup[65:64]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d419 &&
	  NOT_cfg_verbosity_read__9_ULT_2_46___d447)
	$write(", ", "pte_pa: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d419 &&
	  NOT_cfg_verbosity_read__9_ULT_2_46___d447)
	$write("'h%h", tlb$lookup[63:0], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d419 &&
	  NOT_cfg_verbosity_read__9_ULT_2_46___d447)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d419 &&
	  NOT_cfg_verbosity_read__9_ULT_2_46___d447)
	$write("      ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d419 &&
	  NOT_cfg_verbosity_read__9_ULT_2_46___d447)
	$write("VM_Xlate_Result { ", "outcome: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d455)
	$write("VM_XLATE_OK");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d458)
	$write("VM_XLATE_EXCEPTION");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d419 &&
	  NOT_cfg_verbosity_read__9_ULT_2_46___d447)
	$write(", ", "pa: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d419 &&
	  NOT_cfg_verbosity_read__9_ULT_2_46___d447)
	$write("'h%h", x1_avValue_pa__h6058);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d419 &&
	  NOT_cfg_verbosity_read__9_ULT_2_46___d447)
	$write(", ", "exc_code: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d419 &&
	  NOT_cfg_verbosity_read__9_ULT_2_46___d447)
	$write("'h%h", x1_avValue_exc_code__h6059);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d419 &&
	  NOT_cfg_verbosity_read__9_ULT_2_46___d447)
	$write(", ", "pte_modified: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d458)
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d455)
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d419 &&
	  NOT_cfg_verbosity_read__9_ULT_2_46___d447)
	$write(", ", "pte: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d419 &&
	  NOT_cfg_verbosity_read__9_ULT_2_46___d447)
	$write("'h%h", value__h6884, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_4_ULE_0b1_5_AND_rg_satp_7_BITS_63_TO_6_ETC___d419 &&
	  NOT_cfg_verbosity_read__9_ULT_2_46___d447)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d472)
	$display("    => IO_REQ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d478)
	$display("        ASSERTION ERROR: fn_test_cache_hit_or_miss: multiple hits in set at [%0d] and [%0d]",
		 $signed(32'd1),
		 1'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d674)
	begin
	  v__h21326 = $stime;
	  #0;
	end
    v__h21320 = v__h21326 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d674)
	if (dmem_not_imem)
	  $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
		   v__h21320,
		   "D_MMU_Cache",
		   rg_addr,
		   word64__h7577,
		   64'd0);
	else
	  $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
		   v__h21320,
		   "I_MMU_Cache",
		   rg_addr,
		   word64__h7577,
		   64'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d686)
	$display("        AMO LR: reserving PA 0x%0h", x1_avValue_pa__h6058);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d674)
	$display("        Read-hit: addr 0x%0h word64 0x%0h",
		 rg_addr,
		 word64__h7577);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d691)
	$display("        Read Miss: -> CACHE_START_REFILL.");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d699)
	$display("        AMO LR: cache refill: cancelling LR/SC reservation for PA 0x%0h",
		 rg_lrsc_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d858)
	$display("        ST: cancelling LR/SC reservation for PA",
		 x1_avValue_pa__h6058);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	   tlb$lookup[130]) &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d864)
	$display("        AMO SC: fail: reserved addr 0x%0h, this address 0x%0h",
		 rg_lrsc_pa,
		 x1_avValue_pa__h6058);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	   tlb$lookup[130]) &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d870)
	$display("        AMO SC: fail due to invalid LR/SC reservation");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d876)
	$display("        AMO SC result = %0d", lrsc_result__h21703);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d882)
	$display("        Write-Cache-Hit: pa 0x%0h word64 0x%0h",
		 x1_avValue_pa__h6058,
		 rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d882)
	$write("        New Word64_Set:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d882)
	$write("        CSet 0x%0x, Word64 0x%0x: ",
	       rg_addr[11:6],
	       rg_addr[5:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d882)
	$write(" 0x%0x",
	       IF_NOT_ram_state_and_ctag_cset_b_read__98_BIT__ETC___d776);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d882)
	$write(" 0x%0x",
	       IF_ram_state_and_ctag_cset_b_read__98_BIT_105__ETC___d775);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d882)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	   tlb$lookup[130]) &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d887)
	$display("        Write-Cache-Miss: pa 0x%0h word64 0x%0h",
		 x1_avValue_pa__h6058,
		 rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d894)
	$display("        Write-Cache-Hit/Miss: eaddr 0x%0h word64 0x%0h",
		 rg_addr,
		 rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d894)
	$display("        => rl_write_response");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d900)
	begin
	  v__h25042 = $stime;
	  #0;
	end
    v__h25036 = v__h25042 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d900)
	if (dmem_not_imem)
	  $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
		   v__h25036,
		   "D_MMU_Cache",
		   rg_addr,
		   64'd1,
		   64'd0);
	else
	  $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
		   v__h25036,
		   "I_MMU_Cache",
		   rg_addr,
		   64'd1,
		   64'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d900)
	$display("        AMO SC: Fail response for addr 0x%0h", rg_addr);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	   tlb$lookup[130]) &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d906)
	$display("        AMO Miss: -> CACHE_START_REFILL.");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d912)
	$display("        AMO: addr 0x%0h amo_f7 0x%0h f3 %0d rs2_val 0x%0h",
		 rg_addr,
		 rg_amo_funct7,
		 rg_f3,
		 rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d912)
	$display("          PA 0x%0h ", x1_avValue_pa__h6058);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d912)
	$display("          Cache word64 0x%0h, load-result 0x%0h",
		 word64__h7577,
		 word64__h7577);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d912)
	$display("          0x%0h  op  0x%0h -> 0x%0h",
		 word64__h7577,
		 word64__h7577,
		 new_st_val__h25262);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d912)
	$write("          New Word64_Set:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d912)
	$write("        CSet 0x%0x, Word64 0x%0x: ",
	       rg_addr[11:6],
	       rg_addr[5:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d912)
	$write(" 0x%0x",
	       IF_NOT_ram_state_and_ctag_cset_b_read__98_BIT__ETC___d844);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d912)
	$write(" 0x%0x",
	       IF_ram_state_and_ctag_cset_b_read__98_BIT_105__ETC___d843);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d912)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!rg_priv_4_ULE_0b1___d85 || rg_satp[63:60] != 4'd8 ||
	   tlb$lookup[130]) &&
	  NOT_rg_priv_4_ULE_0b1_5_6_OR_NOT_rg_satp_7_BIT_ETC___d917)
	$display("        AMO_op: cancelling LR/SC reservation for PA",
		 x1_avValue_pa__h6058);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	begin
	  v__h28554 = $stime;
	  #0;
	end
    v__h28548 = v__h28554 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_start_tlb_refill for eaddr 0x%0h; req for level 2 PTE",
		   v__h28548,
		   "D_MMU_Cache",
		   rg_addr);
	else
	  $display("%0d: %s.rl_start_tlb_refill for eaddr 0x%0h; req for level 2 PTE",
		   v__h28548,
		   "I_MMU_Cache",
		   rg_addr);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("            To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("AXI4_Rd_Addr { ", "arid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "araddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", lev_2_pte_pa_w64_fa__h28609);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 3'b011);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "aruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d978)
	begin
	  v__h29472 = $stime;
	  #0;
	end
    v__h29466 = v__h29472 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d978)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
		   v__h29466,
		   "D_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa,
		   exc_code___1__h6459);
	else
	  $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
		   v__h29466,
		   "I_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa,
		   exc_code___1__h6459);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	begin
	  v__h29229 = $stime;
	  #0;
	end
    v__h29223 = v__h29229 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 1",
		   v__h29223,
		   "D_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
	else
	  $display("%0d: %s.rl_rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 1",
		   v__h29223,
		   "I_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$display("    Req for level 1 PTE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("            To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("AXI4_Rd_Addr { ", "arid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write(", ", "araddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("'h%h", lev_1_pte_pa_w64_fa__h29506);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write(", ", "arlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("'h%h", 8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write(", ", "arsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("'h%h", 3'b011);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write(", ", "arburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write(", ", "arlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write(", ", "arcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write(", ", "arprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write(", ", "arqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write(", ", "arregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write(", ", "aruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1004)
	begin
	  v__h29760 = $stime;
	  #0;
	end
    v__h29754 = v__h29760 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1004)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: gigapage pte 0x%0h @ 0x%0h",
		   v__h29754,
		   "D_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
	else
	  $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: gigapage pte 0x%0h @ 0x%0h",
		   v__h29754,
		   "I_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  master_xactor_f_rd_data$D_OUT[3] &&
	  (master_xactor_f_rd_data$D_OUT[4] ||
	   !master_xactor_f_rd_data$D_OUT[5]) &&
	  (master_xactor_f_rd_data$D_OUT[6] ||
	   master_xactor_f_rd_data$D_OUT[4]) &&
	  (master_xactor_f_rd_data$D_OUT[30:22] != 9'd0 ||
	   master_xactor_f_rd_data$D_OUT[21:13] != 9'd0))
	$display("    Invalid PTE: PPN[1] or PPN[0] is not zero; page fault %0d",
		 exc_code___1__h6459);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1016)
	begin
	  v__h29872 = $stime;
	  #0;
	end
    v__h29866 = v__h29872 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1016)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for gigapage",
		   v__h29866,
		   "D_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
	else
	  $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for gigapage",
		   v__h29866,
		   "I_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1016)
	$display("    Addr Space megapage pa: 0x%0h", lev_1_PTN_pa__h29502);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	begin
	  v__h29401 = $stime;
	  #0;
	end
    v__h29395 = v__h29401 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_2 &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
		   v__h29395,
		   "D_MMU_Cache",
		   rg_addr,
		   rg_pte_pa,
		   access_exc_code__h2602);
	else
	  $display("%0d: %s.rl_ptw_level_2: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
		   v__h29395,
		   "I_MMU_Cache",
		   rg_addr,
		   rg_pte_pa,
		   access_exc_code__h2602);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d978)
	begin
	  v__h30505 = $stime;
	  #0;
	end
    v__h30499 = v__h30505 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d978)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
		   v__h30499,
		   "D_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa,
		   exc_code___1__h6459);
	else
	  $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
		   v__h30499,
		   "I_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa,
		   exc_code___1__h6459);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	begin
	  v__h30265 = $stime;
	  #0;
	end
    v__h30259 = v__h30265 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 0",
		   v__h30259,
		   "D_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
	else
	  $display("%0d: %s.rl_rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 0",
		   v__h30259,
		   "I_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$display("    Req for level 0 PTE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("            To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("AXI4_Rd_Addr { ", "arid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write(", ", "araddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("'h%h", lev_0_pte_pa_w64_fa__h30539);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write(", ", "arlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("'h%h", 8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write(", ", "arsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("'h%h", 3'b011);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write(", ", "arburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write(", ", "arlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write(", ", "arcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write(", ", "arprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write(", ", "arqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write(", ", "arregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write(", ", "aruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1051)
	begin
	  v__h30905 = $stime;
	  #0;
	end
    v__h30899 = v__h30905 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1051)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for megapage",
		   v__h30899,
		   "D_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
	else
	  $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for megapage",
		   v__h30899,
		   "I_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1051)
	$display("    Addr Space megapage pa: 0x%0h", lev_1_PTN_pa__h29502);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1057)
	begin
	  v__h30793 = $stime;
	  #0;
	end
    v__h30787 = v__h30793 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1057)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: megapage pte 0x%0h @ 0x%0h",
		   v__h30787,
		   "D_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
	else
	  $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: megapage pte 0x%0h @ 0x%0h",
		   v__h30787,
		   "I_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  master_xactor_f_rd_data$D_OUT[3] &&
	  (master_xactor_f_rd_data$D_OUT[4] ||
	   !master_xactor_f_rd_data$D_OUT[5]) &&
	  (master_xactor_f_rd_data$D_OUT[6] ||
	   master_xactor_f_rd_data$D_OUT[4]) &&
	  master_xactor_f_rd_data$D_OUT[21:13] != 9'd0)
	$display("    Invalid PTE: PPN [0] is not zero; page fault %0d",
		 exc_code___1__h6459);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	begin
	  v__h30434 = $stime;
	  #0;
	end
    v__h30428 = v__h30434 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
		   v__h30428,
		   "D_MMU_Cache",
		   rg_addr,
		   rg_pte_pa,
		   access_exc_code__h2602);
	else
	  $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
		   v__h30428,
		   "I_MMU_Cache",
		   rg_addr,
		   rg_pte_pa,
		   access_exc_code__h2602);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d978)
	begin
	  v__h31376 = $stime;
	  #0;
	end
    v__h31370 = v__h31376 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d978)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
		   v__h31370,
		   "D_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa,
		   exc_code___1__h6459);
	else
	  $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
		   v__h31370,
		   "I_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa,
		   exc_code___1__h6459);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	begin
	  v__h31447 = $stime;
	  #0;
	end
    v__h31441 = v__h31447 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d988)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x50h: Not a leaf PTE; page fault %0d",
		   v__h31441,
		   "D_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa,
		   exc_code___1__h6459);
	else
	  $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x50h: Not a leaf PTE; page fault %0d",
		   v__h31441,
		   "I_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa,
		   exc_code___1__h6459);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1082)
	begin
	  v__h31529 = $stime;
	  #0;
	end
    v__h31523 = v__h31529 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1082)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE",
		   v__h31523,
		   "D_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
	else
	  $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE",
		   v__h31523,
		   "I_MMU_Cache",
		   rg_addr,
		   master_xactor_f_rd_data$D_OUT[66:3],
		   rg_pte_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 &&
	  master_xactor_f_rd_data_first__38_BITS_2_TO_1__ETC___d1082)
	$display("    Addr Space page pa: 0x%0h", lev_1_PTN_pa__h29502);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	begin
	  v__h31305 = $stime;
	  #0;
	end
    v__h31299 = v__h31305 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
		   v__h31299,
		   "D_MMU_Cache",
		   rg_addr,
		   rg_pte_pa,
		   access_exc_code__h2602);
	else
	  $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
		   v__h31299,
		   "I_MMU_Cache",
		   rg_addr,
		   rg_pte_pa,
		   access_exc_code__h2602);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	begin
	  v__h31656 = $stime;
	  #0;
	end
    v__h31650 = v__h31656 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_start_cache_refill: ",
		   v__h31650,
		   "D_MMU_Cache");
	else
	  $display("%0d: %s.rl_start_cache_refill: ",
		   v__h31650,
		   "I_MMU_Cache");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("    To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("AXI4_Rd_Addr { ", "arid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "araddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", cline_fabric_addr__h31709);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 8'd7);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 3'b011);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "aruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$display("    Victim way %0d; => CACHE_REFILL", tmp__h31849[0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__9_ULE_2_103___d1104)
	begin
	  v__h32347 = $stime;
	  #0;
	end
    v__h32341 = v__h32347 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__9_ULE_2_103___d1104)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_cache_refill_rsps_loop:",
		   v__h32341,
		   "D_MMU_Cache");
	else
	  $display("%0d: %s.rl_cache_refill_rsps_loop:",
		   v__h32341,
		   "I_MMU_Cache");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__9_ULE_2_103___d1104)
	$write("        ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__9_ULE_2_103___d1104)
	$write("AXI4_Rd_Data { ", "rid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__9_ULE_2_103___d1104)
	$write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__9_ULE_2_103___d1104)
	$write(", ", "rdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__9_ULE_2_103___d1104)
	$write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__9_ULE_2_103___d1104)
	$write(", ", "rresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__9_ULE_2_103___d1104)
	$write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__9_ULE_2_103___d1104)
	$write(", ", "rlast: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__9_ULE_2_103___d1104 &&
	  master_xactor_f_rd_data$D_OUT[0])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__9_ULE_2_103___d1104 &&
	  !master_xactor_f_rd_data$D_OUT[0])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__9_ULE_2_103___d1104)
	$write(", ", "ruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__9_ULE_2_103___d1104)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__9_ULE_2_103___d1104)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	begin
	  v__h32569 = $stime;
	  #0;
	end
    v__h32563 = v__h32569 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d",
		   v__h32563,
		   "D_MMU_Cache",
		   access_exc_code__h2602);
	else
	  $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d",
		   v__h32563,
		   "I_MMU_Cache",
		   access_exc_code__h2602);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  rg_word64_set_in_cache[2:0] == 3'd7 &&
	  (master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	   rg_error_during_refill) &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$display("    => MODULE_EXCEPTION_RSP");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  rg_word64_set_in_cache[2:0] == 3'd7 &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  !rg_error_during_refill &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$display("    => CACHE_REREQ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__9_ULE_2_103___d1104)
	$display("        Updating Cache word64_set 0x%0h, word64_in_cline %0d) old => new",
		 rg_word64_set_in_cache,
		 rg_word64_set_in_cache[2:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__9_ULE_2_103___d1104)
	$write("        CSet 0x%0x, Word64 0x%0x: ",
	       rg_addr[11:6],
	       rg_word64_set_in_cache[2:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__9_ULE_2_103___d1104)
	$write(" 0x%0x", ram_word64_set$DOB[63:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__9_ULE_2_103___d1104)
	$write(" 0x%0x", ram_word64_set$DOB[127:64]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__9_ULE_2_103___d1104)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__9_ULE_2_103___d1104)
	$write("        CSet 0x%0x, Word64 0x%0x: ",
	       rg_addr[11:6],
	       rg_word64_set_in_cache[2:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__9_ULE_2_103___d1104)
	$write(" 0x%0x",
	       rg_victim_way ?
		 ram_word64_set$DOB[63:0] :
		 master_xactor_f_rd_data$D_OUT[66:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__9_ULE_2_103___d1104)
	$write(" 0x%0x",
	       rg_victim_way ?
		 master_xactor_f_rd_data$D_OUT[66:3] :
		 ram_word64_set$DOB[127:64]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__9_ULE_2_103___d1104)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_rereq && !cfg_verbosity_read__9_ULE_1___d40)
	$display("    fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]",
		 rg_addr[11:6],
		 rg_addr[11:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__9_ULE_1___d40)
	begin
	  v__h34960 = $stime;
	  #0;
	end
    v__h34954 = v__h34960 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__9_ULE_1___d40)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h  paddr %0h",
		   v__h34954,
		   "D_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa);
	else
	  $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h  paddr %0h",
		   v__h34954,
		   "I_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("            To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("AXI4_Rd_Addr { ", "arid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "araddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", rg_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", value__h37211);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "aruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__9_ULE_1___d40)
	begin
	  v__h35310 = $stime;
	  #0;
	end
    v__h35304 = v__h35310 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__9_ULE_1___d40)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h  paddr 0x%0h",
		   v__h35304,
		   "D_MMU_Cache",
		   rg_addr,
		   rg_pa);
	else
	  $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h  paddr 0x%0h",
		   v__h35304,
		   "I_MMU_Cache",
		   rg_addr,
		   rg_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__9_ULE_1___d40)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__9_ULE_1___d40)
	$write("AXI4_Rd_Data { ", "rid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "rdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "rresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "rlast: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__9_ULE_1___d40 &&
	  master_xactor_f_rd_data$D_OUT[0])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__9_ULE_1___d40 &&
	  !master_xactor_f_rd_data$D_OUT[0])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "ruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__9_ULE_1___d40)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	begin
	  v__h36410 = $stime;
	  #0;
	end
    v__h36404 = v__h36410 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	if (dmem_not_imem)
	  $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
		   v__h36404,
		   "D_MMU_Cache",
		   rg_addr,
		   ld_val__h35419);
	else
	  $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
		   v__h36404,
		   "I_MMU_Cache",
		   rg_addr,
		   ld_val__h35419);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	begin
	  v__h36517 = $stime;
	  #0;
	end
    v__h36511 = v__h36517 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT",
		   v__h36511,
		   "D_MMU_Cache");
	else
	  $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT",
		   v__h36511,
		   "I_MMU_Cache");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_maintain_io_read_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	begin
	  v__h36622 = $stime;
	  #0;
	end
    v__h36616 = v__h36622 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_maintain_io_read_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	if (dmem_not_imem)
	  $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
		   v__h36616,
		   "D_MMU_Cache",
		   rg_addr,
		   rg_ld_val);
	else
	  $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
		   v__h36616,
		   "I_MMU_Cache",
		   rg_addr,
		   rg_ld_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__9_ULE_1___d40)
	begin
	  v__h36702 = $stime;
	  #0;
	end
    v__h36696 = v__h36702 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__9_ULE_1___d40)
	if (dmem_not_imem)
	  $display("%0d: %s: rl_io_write_req; f3 0x%0h  vaddr %0h  paddr %0h  word64 0x%0h",
		   v__h36696,
		   "D_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa,
		   rg_st_amo_val);
	else
	  $display("%0d: %s: rl_io_write_req; f3 0x%0h  vaddr %0h  paddr %0h  word64 0x%0h",
		   v__h36696,
		   "I_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa,
		   rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__9_ULE_1___d40)
	$display("    => rl_ST_AMO_response");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__9_ULE_1___d40)
	begin
	  v__h36912 = $stime;
	  #0;
	end
    v__h36906 = v__h36912 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__9_ULE_1___d40)
	if (dmem_not_imem)
	  $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h  vaddr %0h  paddr %0h  word64 0x%0h",
		   v__h36906,
		   "D_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa,
		   rg_st_amo_val);
	else
	  $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h  vaddr %0h  paddr %0h  word64 0x%0h",
		   v__h36906,
		   "I_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa,
		   rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__9_ULE_1___d40)
	$display("    FAIL due to I/O address.");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__9_ULE_1___d40)
	$display("    => rl_ST_AMO_response");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__9_ULE_1___d40)
	begin
	  v__h37030 = $stime;
	  #0;
	end
    v__h37024 = v__h37030 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__9_ULE_1___d40)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h  paddr %0h",
		   v__h37024,
		   "D_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa);
	else
	  $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h  paddr %0h",
		   v__h37024,
		   "I_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("            To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("AXI4_Rd_Addr { ", "arid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "araddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", rg_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", value__h37211);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "arregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "aruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	begin
	  v__h37324 = $stime;
	  #0;
	end
    v__h37318 = v__h37324 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h  paddr 0x%0h",
		   v__h37318,
		   "D_MMU_Cache",
		   rg_addr,
		   rg_pa);
	else
	  $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h  paddr 0x%0h",
		   v__h37318,
		   "I_MMU_Cache",
		   rg_addr,
		   rg_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("AXI4_Rd_Data { ", "rid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "rdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "rresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "rlast: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40 &&
	  master_xactor_f_rd_data$D_OUT[0])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40 &&
	  !master_xactor_f_rd_data$D_OUT[0])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "ruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	begin
	  v__h37499 = $stime;
	  #0;
	end
    v__h37493 = v__h37499 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	if (dmem_not_imem)
	  $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h  vaddr %0h  paddr %0h  word64 0x%0h",
		   v__h37493,
		   "D_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa,
		   rg_st_amo_val);
	else
	  $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h  vaddr %0h  paddr %0h  word64 0x%0h",
		   v__h37493,
		   "I_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa,
		   rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	begin
	  v__h39758 = $stime;
	  #0;
	end
    v__h39752 = v__h39758 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	if (dmem_not_imem)
	  $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
		   v__h39752,
		   "D_MMU_Cache",
		   rg_addr,
		   new_ld_val__h37625);
	else
	  $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
		   v__h39752,
		   "I_MMU_Cache",
		   rg_addr,
		   new_ld_val__h37625);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$display("    => rl_ST_AMO_response");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	begin
	  v__h37595 = $stime;
	  #0;
	end
    v__h37589 = v__h37595 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT",
		   v__h37589,
		   "D_MMU_Cache");
	else
	  $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT",
		   v__h37589,
		   "I_MMU_Cache");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	begin
	  v__h40365 = $stime;
	  #0;
	end
    v__h40359 = v__h40365 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	if (dmem_not_imem)
	  $write("%0d: %s.rl_discard_write_rsp: pending %0d ",
		 v__h40359,
		 "D_MMU_Cache",
		 $unsigned(b__h28508));
	else
	  $write("%0d: %s.rl_discard_write_rsp: pending %0d ",
		 v__h40359,
		 "I_MMU_Cache",
		 $unsigned(b__h28508));
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("AXI4_Wr_Resp { ", "bid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", master_xactor_f_wr_resp$D_OUT[5:2]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "bresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", master_xactor_f_wr_resp$D_OUT[1:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write(", ", "buser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	begin
	  v__h40326 = $stime;
	  #0;
	end
    v__h40320 = v__h40326 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit",
		   v__h40320,
		   "D_MMU_Cache");
	else
	  $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit",
		   v__h40320,
		   "I_MMU_Cache");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	$write("AXI4_Wr_Resp { ", "bid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	$write("'h%h", master_xactor_f_wr_resp$D_OUT[5:2]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	$write(", ", "bresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	$write("'h%h", master_xactor_f_wr_resp$D_OUT[1:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	$write(", ", "buser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_reset)
	begin
	  v__h4069 = $stime;
	  #0;
	end
    v__h4063 = v__h4069 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_reset)
	if (dmem_not_imem)
	  $display("%0d: %s: cache size %0d KB, associativity %0d, line size %0d bytes (= %0d XLEN words)",
		   v__h4063,
		   "D_MMU_Cache",
		   $signed(32'd8),
		   $signed(32'd2),
		   $signed(32'd64),
		   $signed(32'd8));
	else
	  $display("%0d: %s: cache size %0d KB, associativity %0d, line size %0d bytes (= %0d XLEN words)",
		   v__h4063,
		   "I_MMU_Cache",
		   $signed(32'd8),
		   $signed(32'd2),
		   $signed(32'd64),
		   $signed(32'd8));
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__9_ULE_1___d40)
	begin
	  v__h40714 = $stime;
	  #0;
	end
    v__h40708 = v__h40714 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write("%0d: %m.req: op:", v__h40708);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__9_ULE_1___d40 && req_op == 2'd0)
	$write("CACHE_LD");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__9_ULE_1___d40 && req_op == 2'd1)
	$write("CACHE_ST");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__9_ULE_1___d40 && req_op != 2'd0 &&
	  req_op != 2'd1)
	$write("CACHE_AMO");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write(" f3:%0d addr:0x%0h st_value:0x%0h",
	       req_f3,
	       req_addr,
	       req_st_value,
	       "\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__9_ULE_1___d40) $write("    priv:");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__9_ULE_1___d40 && req_priv == 2'b0)
	$write("U");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__9_ULE_1___d40 && req_priv == 2'b01)
	$write("S");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__9_ULE_1___d40 && req_priv == 2'b11)
	$write("M");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__9_ULE_1___d40 && req_priv != 2'b0 &&
	  req_priv != 2'b01 &&
	  req_priv != 2'b11)
	$write("RESERVED");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__9_ULE_1___d40)
	$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
	       req_sstatus_SUM,
	       req_mstatus_MXR,
	       req_satp,
	       "\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__9_ULE_1___d40)
	$display("    amo_funct7 = 0x%0h", req_amo_funct7);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req &&
	  req_f3_BITS_1_TO_0_430_EQ_0b0_431_OR_req_f3_BI_ETC___d1460 &&
	  !cfg_verbosity_read__9_ULE_1___d40)
	$display("    fa_req_ram_B tagCSet [0x%0x] word64_set [0x%0d]",
		 req_addr[11:6],
		 req_addr[11:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_tlb_flush && !cfg_verbosity_read__9_ULE_1___d40)
	begin
	  v__h42089 = $stime;
	  #0;
	end
    v__h42083 = v__h42089 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_tlb_flush && !cfg_verbosity_read__9_ULE_1___d40)
	if (dmem_not_imem)
	  $display("%0d: %s.tlb_flush", v__h42083, "D_MMU_Cache");
	else
	  $display("%0d: %s.tlb_flush", v__h42083, "I_MMU_Cache");
  end
  // synopsys translate_on
endmodule  // mkMMU_Cache

