//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name                         I/O  size props
// RDY_hart0_server_reset_request_put  O     1 reg
// hart0_server_reset_response_get  O     1 reg
// RDY_hart0_server_reset_response_get  O     1 reg
// imem_master_awvalid            O     1 reg
// imem_master_awid               O    16 reg
// imem_master_awaddr             O    64 reg
// imem_master_awlen              O     8 reg
// imem_master_awsize             O     3 reg
// imem_master_awburst            O     2 reg
// imem_master_awlock             O     1 reg
// imem_master_awcache            O     4 reg
// imem_master_awprot             O     3 reg
// imem_master_awqos              O     4 reg
// imem_master_awregion           O     4 reg
// imem_master_wvalid             O     1 reg
// imem_master_wdata              O    64 reg
// imem_master_wstrb              O     8 reg
// imem_master_wlast              O     1 reg
// imem_master_bready             O     1 reg
// imem_master_arvalid            O     1 reg
// imem_master_arid               O    16 reg
// imem_master_araddr             O    64 reg
// imem_master_arlen              O     8 reg
// imem_master_arsize             O     3 reg
// imem_master_arburst            O     2 reg
// imem_master_arlock             O     1 reg
// imem_master_arcache            O     4 reg
// imem_master_arprot             O     3 reg
// imem_master_arqos              O     4 reg
// imem_master_arregion           O     4 reg
// imem_master_rready             O     1 reg
// mem_master_awvalid             O     1
// mem_master_awid                O    16 reg
// mem_master_awaddr              O    64 reg
// mem_master_awlen               O     8 reg
// mem_master_awsize              O     3 reg
// mem_master_awburst             O     2 reg
// mem_master_awlock              O     1 reg
// mem_master_awcache             O     4 reg
// mem_master_awprot              O     3 reg
// mem_master_awqos               O     4 reg
// mem_master_awregion            O     4 reg
// mem_master_wvalid              O     1
// mem_master_wdata               O    64 reg
// mem_master_wstrb               O     8 reg
// mem_master_wlast               O     1 reg
// mem_master_bready              O     1
// mem_master_arvalid             O     1
// mem_master_arid                O    16 reg
// mem_master_araddr              O    64 reg
// mem_master_arlen               O     8 reg
// mem_master_arsize              O     3 reg
// mem_master_arburst             O     2 reg
// mem_master_arlock              O     1 reg
// mem_master_arcache             O     4 reg
// mem_master_arprot              O     3 reg
// mem_master_arqos               O     4 reg
// mem_master_arregion            O     4 reg
// mem_master_rready              O     1
// dma_server_awready             O     1 reg
// dma_server_wready              O     1 reg
// dma_server_bvalid              O     1 reg
// dma_server_bid                 O    16 reg
// dma_server_bresp               O     2 reg
// dma_server_arready             O     1 reg
// dma_server_rvalid              O     1 reg
// dma_server_rid                 O    16 reg
// dma_server_rdata               O   512 reg
// dma_server_rresp               O     2 reg
// dma_server_rlast               O     1 reg
// trace_data_out_get             O   427 reg
// RDY_trace_data_out_get         O     1 reg
// RDY_hart0_server_run_halt_request_put  O     1 reg
// hart0_server_run_halt_response_get  O     1 reg
// RDY_hart0_server_run_halt_response_get  O     1 reg
// RDY_hart0_put_other_req_put    O     1 const
// RDY_hart0_gpr_mem_server_request_put  O     1 reg
// hart0_gpr_mem_server_response_get  O    65 reg
// RDY_hart0_gpr_mem_server_response_get  O     1 reg
// RDY_hart0_fpr_mem_server_request_put  O     1 reg
// hart0_fpr_mem_server_response_get  O    65 reg
// RDY_hart0_fpr_mem_server_response_get  O     1 reg
// RDY_hart0_csr_mem_server_request_put  O     1 reg
// hart0_csr_mem_server_response_get  O    65 reg
// RDY_hart0_csr_mem_server_response_get  O     1 reg
// RDY_set_verbosity              O     1 const
// RDY_ma_ddr4_ready              O     1 const
// mv_status                      O     8
// CLK                            I     1 clock
// RST_N                          I     1 reset
// hart0_server_reset_request_put  I     1 reg
// imem_master_awready            I     1
// imem_master_wready             I     1
// imem_master_bvalid             I     1
// imem_master_bid                I    16 reg
// imem_master_bresp              I     2 reg
// imem_master_arready            I     1
// imem_master_rvalid             I     1
// imem_master_rid                I    16 reg
// imem_master_rdata              I    64 reg
// imem_master_rresp              I     2 reg
// imem_master_rlast              I     1 reg
// mem_master_awready             I     1
// mem_master_wready              I     1
// mem_master_bvalid              I     1
// mem_master_bid                 I    16 reg
// mem_master_bresp               I     2 reg
// mem_master_arready             I     1
// mem_master_rvalid              I     1
// mem_master_rid                 I    16 reg
// mem_master_rdata               I    64 reg
// mem_master_rresp               I     2 reg
// mem_master_rlast               I     1 reg
// dma_server_awvalid             I     1
// dma_server_awid                I    16 reg
// dma_server_awaddr              I    64 reg
// dma_server_awlen               I     8 reg
// dma_server_awsize              I     3 reg
// dma_server_awburst             I     2 reg
// dma_server_awlock              I     1 reg
// dma_server_awcache             I     4 reg
// dma_server_awprot              I     3 reg
// dma_server_awqos               I     4 reg
// dma_server_awregion            I     4 reg
// dma_server_wvalid              I     1
// dma_server_wdata               I   512 reg
// dma_server_wstrb               I    64 reg
// dma_server_wlast               I     1 reg
// dma_server_bready              I     1
// dma_server_arvalid             I     1
// dma_server_arid                I    16 reg
// dma_server_araddr              I    64 reg
// dma_server_arlen               I     8 reg
// dma_server_arsize              I     3 reg
// dma_server_arburst             I     2 reg
// dma_server_arlock              I     1 reg
// dma_server_arcache             I     4 reg
// dma_server_arprot              I     3 reg
// dma_server_arqos               I     4 reg
// dma_server_arregion            I     4 reg
// dma_server_rready              I     1
// m_external_interrupt_req_set_not_clear  I     1 reg
// s_external_interrupt_req_set_not_clear  I     1 reg
// software_interrupt_req_set_not_clear  I     1 reg
// timer_interrupt_req_set_not_clear  I     1 reg
// nmi_req_set_not_clear          I     1
// hart0_server_run_halt_request_put  I     1 reg
// hart0_put_other_req_put        I     4
// hart0_gpr_mem_server_request_put  I    70 reg
// hart0_fpr_mem_server_request_put  I    70 reg
// hart0_csr_mem_server_request_put  I    77 reg
// set_verbosity_verbosity        I     4
// set_verbosity_logdelay         I    64 reg
// EN_hart0_server_reset_request_put  I     1
// EN_hart0_server_run_halt_request_put  I     1
// EN_hart0_put_other_req_put     I     1
// EN_hart0_gpr_mem_server_request_put  I     1
// EN_hart0_fpr_mem_server_request_put  I     1
// EN_hart0_csr_mem_server_request_put  I     1
// EN_set_verbosity               I     1
// EN_ma_ddr4_ready               I     1
// EN_hart0_server_reset_response_get  I     1
// EN_trace_data_out_get          I     1
// EN_hart0_server_run_halt_response_get  I     1
// EN_hart0_gpr_mem_server_response_get  I     1
// EN_hart0_fpr_mem_server_response_get  I     1
// EN_hart0_csr_mem_server_response_get  I     1
//
// Combinational paths from inputs to outputs:
//   (mem_master_awready, mem_master_wready) -> mem_master_bready
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkCPU(CLK,
	     RST_N,

	     hart0_server_reset_request_put,
	     EN_hart0_server_reset_request_put,
	     RDY_hart0_server_reset_request_put,

	     EN_hart0_server_reset_response_get,
	     hart0_server_reset_response_get,
	     RDY_hart0_server_reset_response_get,

	     imem_master_awvalid,

	     imem_master_awid,

	     imem_master_awaddr,

	     imem_master_awlen,

	     imem_master_awsize,

	     imem_master_awburst,

	     imem_master_awlock,

	     imem_master_awcache,

	     imem_master_awprot,

	     imem_master_awqos,

	     imem_master_awregion,

	     imem_master_awready,

	     imem_master_wvalid,

	     imem_master_wdata,

	     imem_master_wstrb,

	     imem_master_wlast,

	     imem_master_wready,

	     imem_master_bvalid,
	     imem_master_bid,
	     imem_master_bresp,

	     imem_master_bready,

	     imem_master_arvalid,

	     imem_master_arid,

	     imem_master_araddr,

	     imem_master_arlen,

	     imem_master_arsize,

	     imem_master_arburst,

	     imem_master_arlock,

	     imem_master_arcache,

	     imem_master_arprot,

	     imem_master_arqos,

	     imem_master_arregion,

	     imem_master_arready,

	     imem_master_rvalid,
	     imem_master_rid,
	     imem_master_rdata,
	     imem_master_rresp,
	     imem_master_rlast,

	     imem_master_rready,

	     mem_master_awvalid,

	     mem_master_awid,

	     mem_master_awaddr,

	     mem_master_awlen,

	     mem_master_awsize,

	     mem_master_awburst,

	     mem_master_awlock,

	     mem_master_awcache,

	     mem_master_awprot,

	     mem_master_awqos,

	     mem_master_awregion,

	     mem_master_awready,

	     mem_master_wvalid,

	     mem_master_wdata,

	     mem_master_wstrb,

	     mem_master_wlast,

	     mem_master_wready,

	     mem_master_bvalid,
	     mem_master_bid,
	     mem_master_bresp,

	     mem_master_bready,

	     mem_master_arvalid,

	     mem_master_arid,

	     mem_master_araddr,

	     mem_master_arlen,

	     mem_master_arsize,

	     mem_master_arburst,

	     mem_master_arlock,

	     mem_master_arcache,

	     mem_master_arprot,

	     mem_master_arqos,

	     mem_master_arregion,

	     mem_master_arready,

	     mem_master_rvalid,
	     mem_master_rid,
	     mem_master_rdata,
	     mem_master_rresp,
	     mem_master_rlast,

	     mem_master_rready,

	     dma_server_awvalid,
	     dma_server_awid,
	     dma_server_awaddr,
	     dma_server_awlen,
	     dma_server_awsize,
	     dma_server_awburst,
	     dma_server_awlock,
	     dma_server_awcache,
	     dma_server_awprot,
	     dma_server_awqos,
	     dma_server_awregion,

	     dma_server_awready,

	     dma_server_wvalid,
	     dma_server_wdata,
	     dma_server_wstrb,
	     dma_server_wlast,

	     dma_server_wready,

	     dma_server_bvalid,

	     dma_server_bid,

	     dma_server_bresp,

	     dma_server_bready,

	     dma_server_arvalid,
	     dma_server_arid,
	     dma_server_araddr,
	     dma_server_arlen,
	     dma_server_arsize,
	     dma_server_arburst,
	     dma_server_arlock,
	     dma_server_arcache,
	     dma_server_arprot,
	     dma_server_arqos,
	     dma_server_arregion,

	     dma_server_arready,

	     dma_server_rvalid,

	     dma_server_rid,

	     dma_server_rdata,

	     dma_server_rresp,

	     dma_server_rlast,

	     dma_server_rready,

	     m_external_interrupt_req_set_not_clear,

	     s_external_interrupt_req_set_not_clear,

	     software_interrupt_req_set_not_clear,

	     timer_interrupt_req_set_not_clear,

	     nmi_req_set_not_clear,

	     EN_trace_data_out_get,
	     trace_data_out_get,
	     RDY_trace_data_out_get,

	     hart0_server_run_halt_request_put,
	     EN_hart0_server_run_halt_request_put,
	     RDY_hart0_server_run_halt_request_put,

	     EN_hart0_server_run_halt_response_get,
	     hart0_server_run_halt_response_get,
	     RDY_hart0_server_run_halt_response_get,

	     hart0_put_other_req_put,
	     EN_hart0_put_other_req_put,
	     RDY_hart0_put_other_req_put,

	     hart0_gpr_mem_server_request_put,
	     EN_hart0_gpr_mem_server_request_put,
	     RDY_hart0_gpr_mem_server_request_put,

	     EN_hart0_gpr_mem_server_response_get,
	     hart0_gpr_mem_server_response_get,
	     RDY_hart0_gpr_mem_server_response_get,

	     hart0_fpr_mem_server_request_put,
	     EN_hart0_fpr_mem_server_request_put,
	     RDY_hart0_fpr_mem_server_request_put,

	     EN_hart0_fpr_mem_server_response_get,
	     hart0_fpr_mem_server_response_get,
	     RDY_hart0_fpr_mem_server_response_get,

	     hart0_csr_mem_server_request_put,
	     EN_hart0_csr_mem_server_request_put,
	     RDY_hart0_csr_mem_server_request_put,

	     EN_hart0_csr_mem_server_response_get,
	     hart0_csr_mem_server_response_get,
	     RDY_hart0_csr_mem_server_response_get,

	     set_verbosity_verbosity,
	     set_verbosity_logdelay,
	     EN_set_verbosity,
	     RDY_set_verbosity,

	     EN_ma_ddr4_ready,
	     RDY_ma_ddr4_ready,

	     mv_status);
  input  CLK;
  input  RST_N;

  // action method hart0_server_reset_request_put
  input  hart0_server_reset_request_put;
  input  EN_hart0_server_reset_request_put;
  output RDY_hart0_server_reset_request_put;

  // actionvalue method hart0_server_reset_response_get
  input  EN_hart0_server_reset_response_get;
  output hart0_server_reset_response_get;
  output RDY_hart0_server_reset_response_get;

  // value method imem_master_m_awvalid
  output imem_master_awvalid;

  // value method imem_master_m_awid
  output [15 : 0] imem_master_awid;

  // value method imem_master_m_awaddr
  output [63 : 0] imem_master_awaddr;

  // value method imem_master_m_awlen
  output [7 : 0] imem_master_awlen;

  // value method imem_master_m_awsize
  output [2 : 0] imem_master_awsize;

  // value method imem_master_m_awburst
  output [1 : 0] imem_master_awburst;

  // value method imem_master_m_awlock
  output imem_master_awlock;

  // value method imem_master_m_awcache
  output [3 : 0] imem_master_awcache;

  // value method imem_master_m_awprot
  output [2 : 0] imem_master_awprot;

  // value method imem_master_m_awqos
  output [3 : 0] imem_master_awqos;

  // value method imem_master_m_awregion
  output [3 : 0] imem_master_awregion;

  // value method imem_master_m_awuser

  // action method imem_master_m_awready
  input  imem_master_awready;

  // value method imem_master_m_wvalid
  output imem_master_wvalid;

  // value method imem_master_m_wdata
  output [63 : 0] imem_master_wdata;

  // value method imem_master_m_wstrb
  output [7 : 0] imem_master_wstrb;

  // value method imem_master_m_wlast
  output imem_master_wlast;

  // value method imem_master_m_wuser

  // action method imem_master_m_wready
  input  imem_master_wready;

  // action method imem_master_m_bvalid
  input  imem_master_bvalid;
  input  [15 : 0] imem_master_bid;
  input  [1 : 0] imem_master_bresp;

  // value method imem_master_m_bready
  output imem_master_bready;

  // value method imem_master_m_arvalid
  output imem_master_arvalid;

  // value method imem_master_m_arid
  output [15 : 0] imem_master_arid;

  // value method imem_master_m_araddr
  output [63 : 0] imem_master_araddr;

  // value method imem_master_m_arlen
  output [7 : 0] imem_master_arlen;

  // value method imem_master_m_arsize
  output [2 : 0] imem_master_arsize;

  // value method imem_master_m_arburst
  output [1 : 0] imem_master_arburst;

  // value method imem_master_m_arlock
  output imem_master_arlock;

  // value method imem_master_m_arcache
  output [3 : 0] imem_master_arcache;

  // value method imem_master_m_arprot
  output [2 : 0] imem_master_arprot;

  // value method imem_master_m_arqos
  output [3 : 0] imem_master_arqos;

  // value method imem_master_m_arregion
  output [3 : 0] imem_master_arregion;

  // value method imem_master_m_aruser

  // action method imem_master_m_arready
  input  imem_master_arready;

  // action method imem_master_m_rvalid
  input  imem_master_rvalid;
  input  [15 : 0] imem_master_rid;
  input  [63 : 0] imem_master_rdata;
  input  [1 : 0] imem_master_rresp;
  input  imem_master_rlast;

  // value method imem_master_m_rready
  output imem_master_rready;

  // value method mem_master_m_awvalid
  output mem_master_awvalid;

  // value method mem_master_m_awid
  output [15 : 0] mem_master_awid;

  // value method mem_master_m_awaddr
  output [63 : 0] mem_master_awaddr;

  // value method mem_master_m_awlen
  output [7 : 0] mem_master_awlen;

  // value method mem_master_m_awsize
  output [2 : 0] mem_master_awsize;

  // value method mem_master_m_awburst
  output [1 : 0] mem_master_awburst;

  // value method mem_master_m_awlock
  output mem_master_awlock;

  // value method mem_master_m_awcache
  output [3 : 0] mem_master_awcache;

  // value method mem_master_m_awprot
  output [2 : 0] mem_master_awprot;

  // value method mem_master_m_awqos
  output [3 : 0] mem_master_awqos;

  // value method mem_master_m_awregion
  output [3 : 0] mem_master_awregion;

  // value method mem_master_m_awuser

  // action method mem_master_m_awready
  input  mem_master_awready;

  // value method mem_master_m_wvalid
  output mem_master_wvalid;

  // value method mem_master_m_wdata
  output [63 : 0] mem_master_wdata;

  // value method mem_master_m_wstrb
  output [7 : 0] mem_master_wstrb;

  // value method mem_master_m_wlast
  output mem_master_wlast;

  // value method mem_master_m_wuser

  // action method mem_master_m_wready
  input  mem_master_wready;

  // action method mem_master_m_bvalid
  input  mem_master_bvalid;
  input  [15 : 0] mem_master_bid;
  input  [1 : 0] mem_master_bresp;

  // value method mem_master_m_bready
  output mem_master_bready;

  // value method mem_master_m_arvalid
  output mem_master_arvalid;

  // value method mem_master_m_arid
  output [15 : 0] mem_master_arid;

  // value method mem_master_m_araddr
  output [63 : 0] mem_master_araddr;

  // value method mem_master_m_arlen
  output [7 : 0] mem_master_arlen;

  // value method mem_master_m_arsize
  output [2 : 0] mem_master_arsize;

  // value method mem_master_m_arburst
  output [1 : 0] mem_master_arburst;

  // value method mem_master_m_arlock
  output mem_master_arlock;

  // value method mem_master_m_arcache
  output [3 : 0] mem_master_arcache;

  // value method mem_master_m_arprot
  output [2 : 0] mem_master_arprot;

  // value method mem_master_m_arqos
  output [3 : 0] mem_master_arqos;

  // value method mem_master_m_arregion
  output [3 : 0] mem_master_arregion;

  // value method mem_master_m_aruser

  // action method mem_master_m_arready
  input  mem_master_arready;

  // action method mem_master_m_rvalid
  input  mem_master_rvalid;
  input  [15 : 0] mem_master_rid;
  input  [63 : 0] mem_master_rdata;
  input  [1 : 0] mem_master_rresp;
  input  mem_master_rlast;

  // value method mem_master_m_rready
  output mem_master_rready;

  // action method dma_server_m_awvalid
  input  dma_server_awvalid;
  input  [15 : 0] dma_server_awid;
  input  [63 : 0] dma_server_awaddr;
  input  [7 : 0] dma_server_awlen;
  input  [2 : 0] dma_server_awsize;
  input  [1 : 0] dma_server_awburst;
  input  dma_server_awlock;
  input  [3 : 0] dma_server_awcache;
  input  [2 : 0] dma_server_awprot;
  input  [3 : 0] dma_server_awqos;
  input  [3 : 0] dma_server_awregion;

  // value method dma_server_m_awready
  output dma_server_awready;

  // action method dma_server_m_wvalid
  input  dma_server_wvalid;
  input  [511 : 0] dma_server_wdata;
  input  [63 : 0] dma_server_wstrb;
  input  dma_server_wlast;

  // value method dma_server_m_wready
  output dma_server_wready;

  // value method dma_server_m_bvalid
  output dma_server_bvalid;

  // value method dma_server_m_bid
  output [15 : 0] dma_server_bid;

  // value method dma_server_m_bresp
  output [1 : 0] dma_server_bresp;

  // value method dma_server_m_buser

  // action method dma_server_m_bready
  input  dma_server_bready;

  // action method dma_server_m_arvalid
  input  dma_server_arvalid;
  input  [15 : 0] dma_server_arid;
  input  [63 : 0] dma_server_araddr;
  input  [7 : 0] dma_server_arlen;
  input  [2 : 0] dma_server_arsize;
  input  [1 : 0] dma_server_arburst;
  input  dma_server_arlock;
  input  [3 : 0] dma_server_arcache;
  input  [2 : 0] dma_server_arprot;
  input  [3 : 0] dma_server_arqos;
  input  [3 : 0] dma_server_arregion;

  // value method dma_server_m_arready
  output dma_server_arready;

  // value method dma_server_m_rvalid
  output dma_server_rvalid;

  // value method dma_server_m_rid
  output [15 : 0] dma_server_rid;

  // value method dma_server_m_rdata
  output [511 : 0] dma_server_rdata;

  // value method dma_server_m_rresp
  output [1 : 0] dma_server_rresp;

  // value method dma_server_m_rlast
  output dma_server_rlast;

  // value method dma_server_m_ruser

  // action method dma_server_m_rready
  input  dma_server_rready;

  // action method m_external_interrupt_req
  input  m_external_interrupt_req_set_not_clear;

  // action method s_external_interrupt_req
  input  s_external_interrupt_req_set_not_clear;

  // action method software_interrupt_req
  input  software_interrupt_req_set_not_clear;

  // action method timer_interrupt_req
  input  timer_interrupt_req_set_not_clear;

  // action method nmi_req
  input  nmi_req_set_not_clear;

  // actionvalue method trace_data_out_get
  input  EN_trace_data_out_get;
  output [426 : 0] trace_data_out_get;
  output RDY_trace_data_out_get;

  // action method hart0_server_run_halt_request_put
  input  hart0_server_run_halt_request_put;
  input  EN_hart0_server_run_halt_request_put;
  output RDY_hart0_server_run_halt_request_put;

  // actionvalue method hart0_server_run_halt_response_get
  input  EN_hart0_server_run_halt_response_get;
  output hart0_server_run_halt_response_get;
  output RDY_hart0_server_run_halt_response_get;

  // action method hart0_put_other_req_put
  input  [3 : 0] hart0_put_other_req_put;
  input  EN_hart0_put_other_req_put;
  output RDY_hart0_put_other_req_put;

  // action method hart0_gpr_mem_server_request_put
  input  [69 : 0] hart0_gpr_mem_server_request_put;
  input  EN_hart0_gpr_mem_server_request_put;
  output RDY_hart0_gpr_mem_server_request_put;

  // actionvalue method hart0_gpr_mem_server_response_get
  input  EN_hart0_gpr_mem_server_response_get;
  output [64 : 0] hart0_gpr_mem_server_response_get;
  output RDY_hart0_gpr_mem_server_response_get;

  // action method hart0_fpr_mem_server_request_put
  input  [69 : 0] hart0_fpr_mem_server_request_put;
  input  EN_hart0_fpr_mem_server_request_put;
  output RDY_hart0_fpr_mem_server_request_put;

  // actionvalue method hart0_fpr_mem_server_response_get
  input  EN_hart0_fpr_mem_server_response_get;
  output [64 : 0] hart0_fpr_mem_server_response_get;
  output RDY_hart0_fpr_mem_server_response_get;

  // action method hart0_csr_mem_server_request_put
  input  [76 : 0] hart0_csr_mem_server_request_put;
  input  EN_hart0_csr_mem_server_request_put;
  output RDY_hart0_csr_mem_server_request_put;

  // actionvalue method hart0_csr_mem_server_response_get
  input  EN_hart0_csr_mem_server_response_get;
  output [64 : 0] hart0_csr_mem_server_response_get;
  output RDY_hart0_csr_mem_server_response_get;

  // action method set_verbosity
  input  [3 : 0] set_verbosity_verbosity;
  input  [63 : 0] set_verbosity_logdelay;
  input  EN_set_verbosity;
  output RDY_set_verbosity;

  // action method ma_ddr4_ready
  input  EN_ma_ddr4_ready;
  output RDY_ma_ddr4_ready;

  // value method mv_status
  output [7 : 0] mv_status;

  // signals for module outputs
  wire [511 : 0] dma_server_rdata;
  wire [426 : 0] trace_data_out_get;
  wire [64 : 0] hart0_csr_mem_server_response_get,
		hart0_fpr_mem_server_response_get,
		hart0_gpr_mem_server_response_get;
  wire [63 : 0] imem_master_araddr,
		imem_master_awaddr,
		imem_master_wdata,
		mem_master_araddr,
		mem_master_awaddr,
		mem_master_wdata;
  wire [15 : 0] dma_server_bid,
		dma_server_rid,
		imem_master_arid,
		imem_master_awid,
		mem_master_arid,
		mem_master_awid;
  wire [7 : 0] imem_master_arlen,
	       imem_master_awlen,
	       imem_master_wstrb,
	       mem_master_arlen,
	       mem_master_awlen,
	       mem_master_wstrb,
	       mv_status;
  wire [3 : 0] imem_master_arcache,
	       imem_master_arqos,
	       imem_master_arregion,
	       imem_master_awcache,
	       imem_master_awqos,
	       imem_master_awregion,
	       mem_master_arcache,
	       mem_master_arqos,
	       mem_master_arregion,
	       mem_master_awcache,
	       mem_master_awqos,
	       mem_master_awregion;
  wire [2 : 0] imem_master_arprot,
	       imem_master_arsize,
	       imem_master_awprot,
	       imem_master_awsize,
	       mem_master_arprot,
	       mem_master_arsize,
	       mem_master_awprot,
	       mem_master_awsize;
  wire [1 : 0] dma_server_bresp,
	       dma_server_rresp,
	       imem_master_arburst,
	       imem_master_awburst,
	       mem_master_arburst,
	       mem_master_awburst;
  wire RDY_hart0_csr_mem_server_request_put,
       RDY_hart0_csr_mem_server_response_get,
       RDY_hart0_fpr_mem_server_request_put,
       RDY_hart0_fpr_mem_server_response_get,
       RDY_hart0_gpr_mem_server_request_put,
       RDY_hart0_gpr_mem_server_response_get,
       RDY_hart0_put_other_req_put,
       RDY_hart0_server_reset_request_put,
       RDY_hart0_server_reset_response_get,
       RDY_hart0_server_run_halt_request_put,
       RDY_hart0_server_run_halt_response_get,
       RDY_ma_ddr4_ready,
       RDY_set_verbosity,
       RDY_trace_data_out_get,
       dma_server_arready,
       dma_server_awready,
       dma_server_bvalid,
       dma_server_rlast,
       dma_server_rvalid,
       dma_server_wready,
       hart0_server_reset_response_get,
       hart0_server_run_halt_response_get,
       imem_master_arlock,
       imem_master_arvalid,
       imem_master_awlock,
       imem_master_awvalid,
       imem_master_bready,
       imem_master_rready,
       imem_master_wlast,
       imem_master_wvalid,
       mem_master_arlock,
       mem_master_arvalid,
       mem_master_awlock,
       mem_master_awvalid,
       mem_master_bready,
       mem_master_rready,
       mem_master_wlast,
       mem_master_wvalid;

  // register cfg_logdelay
  reg [63 : 0] cfg_logdelay;
  wire [63 : 0] cfg_logdelay$D_IN;
  wire cfg_logdelay$EN;

  // register cfg_verbosity
  reg [3 : 0] cfg_verbosity;
  wire [3 : 0] cfg_verbosity$D_IN;
  wire cfg_verbosity$EN;

  // register imem_rg_cache_addr
  reg [63 : 0] imem_rg_cache_addr;
  wire [63 : 0] imem_rg_cache_addr$D_IN;
  wire imem_rg_cache_addr$EN;

  // register imem_rg_cache_b16
  reg [15 : 0] imem_rg_cache_b16;
  wire [15 : 0] imem_rg_cache_b16$D_IN;
  wire imem_rg_cache_b16$EN;

  // register imem_rg_f3
  reg [2 : 0] imem_rg_f3;
  wire [2 : 0] imem_rg_f3$D_IN;
  wire imem_rg_f3$EN;

  // register imem_rg_mstatus_MXR
  reg imem_rg_mstatus_MXR;
  wire imem_rg_mstatus_MXR$D_IN, imem_rg_mstatus_MXR$EN;

  // register imem_rg_pc
  reg [63 : 0] imem_rg_pc;
  reg [63 : 0] imem_rg_pc$D_IN;
  wire imem_rg_pc$EN;

  // register imem_rg_priv
  reg [1 : 0] imem_rg_priv;
  wire [1 : 0] imem_rg_priv$D_IN;
  wire imem_rg_priv$EN;

  // register imem_rg_satp
  reg [63 : 0] imem_rg_satp;
  wire [63 : 0] imem_rg_satp$D_IN;
  wire imem_rg_satp$EN;

  // register imem_rg_sstatus_SUM
  reg imem_rg_sstatus_SUM;
  wire imem_rg_sstatus_SUM$D_IN, imem_rg_sstatus_SUM$EN;

  // register imem_rg_tval
  reg [63 : 0] imem_rg_tval;
  reg [63 : 0] imem_rg_tval$D_IN;
  wire imem_rg_tval$EN;

  // register rg_csr_pc
  reg [63 : 0] rg_csr_pc;
  wire [63 : 0] rg_csr_pc$D_IN;
  wire rg_csr_pc$EN;

  // register rg_csr_val1
  reg [63 : 0] rg_csr_val1;
  wire [63 : 0] rg_csr_val1$D_IN;
  wire rg_csr_val1$EN;

  // register rg_cur_priv
  reg [1 : 0] rg_cur_priv;
  reg [1 : 0] rg_cur_priv$D_IN;
  wire rg_cur_priv$EN;

  // register rg_epoch
  reg [1 : 0] rg_epoch;
  reg [1 : 0] rg_epoch$D_IN;
  wire rg_epoch$EN;

  // register rg_mstatus_MXR
  reg rg_mstatus_MXR;
  wire rg_mstatus_MXR$D_IN, rg_mstatus_MXR$EN;

  // register rg_next_pc
  reg [63 : 0] rg_next_pc;
  reg [63 : 0] rg_next_pc$D_IN;
  wire rg_next_pc$EN;

  // register rg_prev_mip
  reg [63 : 0] rg_prev_mip;
  wire [63 : 0] rg_prev_mip$D_IN;
  wire rg_prev_mip$EN;

  // register rg_run_on_reset
  reg rg_run_on_reset;
  wire rg_run_on_reset$D_IN, rg_run_on_reset$EN;

  // register rg_sstatus_SUM
  reg rg_sstatus_SUM;
  wire rg_sstatus_SUM$D_IN, rg_sstatus_SUM$EN;

  // register rg_start_CPI_cycles
  reg [63 : 0] rg_start_CPI_cycles;
  wire [63 : 0] rg_start_CPI_cycles$D_IN;
  wire rg_start_CPI_cycles$EN;

  // register rg_start_CPI_instrs
  reg [63 : 0] rg_start_CPI_instrs;
  wire [63 : 0] rg_start_CPI_instrs$D_IN;
  wire rg_start_CPI_instrs$EN;

  // register rg_state
  reg [3 : 0] rg_state;
  reg [3 : 0] rg_state$D_IN;
  wire rg_state$EN;

  // register rg_step_count
  reg rg_step_count;
  wire rg_step_count$D_IN, rg_step_count$EN;

  // register rg_stop_req
  reg rg_stop_req;
  wire rg_stop_req$D_IN, rg_stop_req$EN;

  // register rg_trap_info
  reg [131 : 0] rg_trap_info;
  reg [131 : 0] rg_trap_info$D_IN;
  wire rg_trap_info$EN;

  // register rg_trap_instr
  reg [31 : 0] rg_trap_instr;
  wire [31 : 0] rg_trap_instr$D_IN;
  wire rg_trap_instr$EN;

  // register rg_trap_interrupt
  reg rg_trap_interrupt;
  wire rg_trap_interrupt$D_IN, rg_trap_interrupt$EN;

  // register rg_trap_trace_data
  reg [426 : 0] rg_trap_trace_data;
  wire [426 : 0] rg_trap_trace_data$D_IN;
  wire rg_trap_trace_data$EN;

  // register stage1_rg_full
  reg stage1_rg_full;
  reg stage1_rg_full$D_IN;
  wire stage1_rg_full$EN;

  // register stage1_rg_stage_input
  reg [401 : 0] stage1_rg_stage_input;
  wire [401 : 0] stage1_rg_stage_input$D_IN;
  wire stage1_rg_stage_input$EN;

  // register stage2_rg_full
  reg stage2_rg_full;
  reg stage2_rg_full$D_IN;
  wire stage2_rg_full$EN;

  // register stage2_rg_resetting
  reg stage2_rg_resetting;
  wire stage2_rg_resetting$D_IN, stage2_rg_resetting$EN;

  // register stage2_rg_stage2
  reg [922 : 0] stage2_rg_stage2;
  wire [922 : 0] stage2_rg_stage2$D_IN;
  wire stage2_rg_stage2$EN;

  // register stage3_rg_full
  reg stage3_rg_full;
  reg stage3_rg_full$D_IN;
  wire stage3_rg_full$EN;

  // register stage3_rg_stage3
  reg [665 : 0] stage3_rg_stage3;
  wire [665 : 0] stage3_rg_stage3$D_IN;
  wire stage3_rg_stage3$EN;

  // register stageD_rg_data
  reg [233 : 0] stageD_rg_data;
  wire [233 : 0] stageD_rg_data$D_IN;
  wire stageD_rg_data$EN;

  // register stageD_rg_full
  reg stageD_rg_full;
  reg stageD_rg_full$D_IN;
  wire stageD_rg_full$EN;

  // register stageF_rg_epoch
  reg [1 : 0] stageF_rg_epoch;
  reg [1 : 0] stageF_rg_epoch$D_IN;
  wire stageF_rg_epoch$EN;

  // register stageF_rg_full
  reg stageF_rg_full;
  reg stageF_rg_full$D_IN;
  wire stageF_rg_full$EN;

  // register stageF_rg_priv
  reg [1 : 0] stageF_rg_priv;
  wire [1 : 0] stageF_rg_priv$D_IN;
  wire stageF_rg_priv$EN;

  // ports of submodule csr_regfile
  reg [63 : 0] csr_regfile$mav_csr_write_word;
  reg [2 : 0] csr_regfile$write_dcsr_cause_priv_cause;
  reg [1 : 0] csr_regfile$csr_ret_actions_from_priv;
  wire [193 : 0] csr_regfile$csr_trap_actions;
  wire [129 : 0] csr_regfile$csr_ret_actions;
  wire [128 : 0] csr_regfile$mav_csr_write;
  wire [64 : 0] csr_regfile$read_csr, csr_regfile$read_csr_port2;
  wire [63 : 0] csr_regfile$csr_mip_read,
		csr_regfile$csr_trap_actions_pc,
		csr_regfile$csr_trap_actions_xtval,
		csr_regfile$mv_update_mstatus_fs,
		csr_regfile$read_csr_mcycle,
		csr_regfile$read_csr_minstret,
		csr_regfile$read_dpc,
		csr_regfile$read_mstatus,
		csr_regfile$read_satp,
		csr_regfile$read_sstatus,
		csr_regfile$write_dpc_pc;
  wire [27 : 0] csr_regfile$read_misa;
  wire [11 : 0] csr_regfile$access_permitted_1_csr_addr,
		csr_regfile$access_permitted_2_csr_addr,
		csr_regfile$csr_counter_read_fault_csr_addr,
		csr_regfile$mav_csr_write_csr_addr,
		csr_regfile$mav_read_csr_csr_addr,
		csr_regfile$read_csr_csr_addr,
		csr_regfile$read_csr_port2_csr_addr;
  wire [4 : 0] csr_regfile$interrupt_pending,
	       csr_regfile$ma_update_fcsr_fflags_flags,
	       csr_regfile$mv_update_fcsr_fflags,
	       csr_regfile$mv_update_fcsr_fflags_flags,
	       csr_regfile$read_fflags;
  wire [3 : 0] csr_regfile$csr_trap_actions_exc_code;
  wire [2 : 0] csr_regfile$read_frm;
  wire [1 : 0] csr_regfile$access_permitted_1_priv,
	       csr_regfile$access_permitted_2_priv,
	       csr_regfile$csr_counter_read_fault_priv,
	       csr_regfile$csr_trap_actions_from_priv,
	       csr_regfile$dcsr_break_enters_debug_cur_priv,
	       csr_regfile$interrupt_pending_cur_priv,
	       csr_regfile$ma_update_mstatus_fs_fs,
	       csr_regfile$mv_update_mstatus_fs_fs,
	       csr_regfile$write_dcsr_cause_priv_priv;
  wire csr_regfile$EN_csr_minstret_incr,
       csr_regfile$EN_csr_ret_actions,
       csr_regfile$EN_csr_trap_actions,
       csr_regfile$EN_debug,
       csr_regfile$EN_ma_update_fcsr_fflags,
       csr_regfile$EN_ma_update_mstatus_fs,
       csr_regfile$EN_mav_csr_write,
       csr_regfile$EN_mav_read_csr,
       csr_regfile$EN_server_reset_request_put,
       csr_regfile$EN_server_reset_response_get,
       csr_regfile$EN_write_dcsr_cause_priv,
       csr_regfile$EN_write_dpc,
       csr_regfile$RDY_server_reset_request_put,
       csr_regfile$RDY_server_reset_response_get,
       csr_regfile$access_permitted_1,
       csr_regfile$access_permitted_1_read_not_write,
       csr_regfile$access_permitted_2,
       csr_regfile$access_permitted_2_read_not_write,
       csr_regfile$csr_trap_actions_interrupt,
       csr_regfile$csr_trap_actions_nmi,
       csr_regfile$dcsr_break_enters_debug,
       csr_regfile$m_external_interrupt_req_set_not_clear,
       csr_regfile$nmi_pending,
       csr_regfile$nmi_req_set_not_clear,
       csr_regfile$read_dcsr_step,
       csr_regfile$s_external_interrupt_req_set_not_clear,
       csr_regfile$software_interrupt_req_set_not_clear,
       csr_regfile$timer_interrupt_req_set_not_clear,
       csr_regfile$wfi_resume;

  // ports of submodule f_csr_reqs
  wire [76 : 0] f_csr_reqs$D_IN, f_csr_reqs$D_OUT;
  wire f_csr_reqs$CLR,
       f_csr_reqs$DEQ,
       f_csr_reqs$EMPTY_N,
       f_csr_reqs$ENQ,
       f_csr_reqs$FULL_N;

  // ports of submodule f_csr_rsps
  reg [64 : 0] f_csr_rsps$D_IN;
  wire [64 : 0] f_csr_rsps$D_OUT;
  wire f_csr_rsps$CLR,
       f_csr_rsps$DEQ,
       f_csr_rsps$EMPTY_N,
       f_csr_rsps$ENQ,
       f_csr_rsps$FULL_N;

  // ports of submodule f_fpr_reqs
  wire [69 : 0] f_fpr_reqs$D_IN, f_fpr_reqs$D_OUT;
  wire f_fpr_reqs$CLR,
       f_fpr_reqs$DEQ,
       f_fpr_reqs$EMPTY_N,
       f_fpr_reqs$ENQ,
       f_fpr_reqs$FULL_N;

  // ports of submodule f_fpr_rsps
  reg [64 : 0] f_fpr_rsps$D_IN;
  wire [64 : 0] f_fpr_rsps$D_OUT;
  wire f_fpr_rsps$CLR,
       f_fpr_rsps$DEQ,
       f_fpr_rsps$EMPTY_N,
       f_fpr_rsps$ENQ,
       f_fpr_rsps$FULL_N;

  // ports of submodule f_gpr_reqs
  wire [69 : 0] f_gpr_reqs$D_IN, f_gpr_reqs$D_OUT;
  wire f_gpr_reqs$CLR,
       f_gpr_reqs$DEQ,
       f_gpr_reqs$EMPTY_N,
       f_gpr_reqs$ENQ,
       f_gpr_reqs$FULL_N;

  // ports of submodule f_gpr_rsps
  reg [64 : 0] f_gpr_rsps$D_IN;
  wire [64 : 0] f_gpr_rsps$D_OUT;
  wire f_gpr_rsps$CLR,
       f_gpr_rsps$DEQ,
       f_gpr_rsps$EMPTY_N,
       f_gpr_rsps$ENQ,
       f_gpr_rsps$FULL_N;

  // ports of submodule f_reset_reqs
  wire f_reset_reqs$CLR,
       f_reset_reqs$DEQ,
       f_reset_reqs$D_IN,
       f_reset_reqs$D_OUT,
       f_reset_reqs$EMPTY_N,
       f_reset_reqs$ENQ,
       f_reset_reqs$FULL_N;

  // ports of submodule f_reset_rsps
  wire f_reset_rsps$CLR,
       f_reset_rsps$DEQ,
       f_reset_rsps$D_IN,
       f_reset_rsps$D_OUT,
       f_reset_rsps$EMPTY_N,
       f_reset_rsps$ENQ,
       f_reset_rsps$FULL_N;

  // ports of submodule f_run_halt_reqs
  wire f_run_halt_reqs$CLR,
       f_run_halt_reqs$DEQ,
       f_run_halt_reqs$D_IN,
       f_run_halt_reqs$D_OUT,
       f_run_halt_reqs$EMPTY_N,
       f_run_halt_reqs$ENQ,
       f_run_halt_reqs$FULL_N;

  // ports of submodule f_run_halt_rsps
  wire f_run_halt_rsps$CLR,
       f_run_halt_rsps$DEQ,
       f_run_halt_rsps$D_IN,
       f_run_halt_rsps$D_OUT,
       f_run_halt_rsps$EMPTY_N,
       f_run_halt_rsps$ENQ,
       f_run_halt_rsps$FULL_N;

  // ports of submodule f_trace_data
  reg [426 : 0] f_trace_data$D_IN;
  wire [426 : 0] f_trace_data$D_OUT;
  wire f_trace_data$CLR,
       f_trace_data$DEQ,
       f_trace_data$EMPTY_N,
       f_trace_data$ENQ,
       f_trace_data$FULL_N;

  // ports of submodule fpr_regfile
  wire [63 : 0] fpr_regfile$read_rs1,
		fpr_regfile$read_rs1_port2,
		fpr_regfile$read_rs2,
		fpr_regfile$read_rs3,
		fpr_regfile$write_rd_rd_val;
  wire [4 : 0] fpr_regfile$read_rs1_port2_rs1,
	       fpr_regfile$read_rs1_rs1,
	       fpr_regfile$read_rs2_rs2,
	       fpr_regfile$read_rs3_rs3,
	       fpr_regfile$write_rd_rd;
  wire fpr_regfile$EN_server_reset_request_put,
       fpr_regfile$EN_server_reset_response_get,
       fpr_regfile$EN_write_rd,
       fpr_regfile$RDY_server_reset_request_put,
       fpr_regfile$RDY_server_reset_response_get;

  // ports of submodule gpr_regfile
  reg [63 : 0] gpr_regfile$write_rd_rd_val;
  reg [4 : 0] gpr_regfile$write_rd_rd;
  wire [63 : 0] gpr_regfile$read_rs1,
		gpr_regfile$read_rs1_port2,
		gpr_regfile$read_rs2;
  wire [4 : 0] gpr_regfile$read_rs1_port2_rs1,
	       gpr_regfile$read_rs1_rs1,
	       gpr_regfile$read_rs2_rs2;
  wire gpr_regfile$EN_server_reset_request_put,
       gpr_regfile$EN_server_reset_response_get,
       gpr_regfile$EN_write_rd,
       gpr_regfile$RDY_server_reset_request_put,
       gpr_regfile$RDY_server_reset_response_get;

  // ports of submodule near_mem
  reg [63 : 0] near_mem$dmem_req_store_value, near_mem$imem_req_addr;
  reg [1 : 0] near_mem$dmem_req_op;
  wire [511 : 0] near_mem$dma_server_rdata, near_mem$dma_server_wdata;
  wire [63 : 0] near_mem$dma_server_araddr,
		near_mem$dma_server_awaddr,
		near_mem$dma_server_wstrb,
		near_mem$dmem_req_addr,
		near_mem$dmem_req_satp,
		near_mem$dmem_word64,
		near_mem$imem_master_araddr,
		near_mem$imem_master_awaddr,
		near_mem$imem_master_rdata,
		near_mem$imem_master_wdata,
		near_mem$imem_pc,
		near_mem$imem_req_satp,
		near_mem$mem_master_araddr,
		near_mem$mem_master_awaddr,
		near_mem$mem_master_rdata,
		near_mem$mem_master_wdata;
  wire [31 : 0] near_mem$imem_instr;
  wire [15 : 0] near_mem$dma_server_arid,
		near_mem$dma_server_awid,
		near_mem$dma_server_bid,
		near_mem$dma_server_rid,
		near_mem$imem_master_arid,
		near_mem$imem_master_awid,
		near_mem$imem_master_bid,
		near_mem$imem_master_rid,
		near_mem$mem_master_arid,
		near_mem$mem_master_awid,
		near_mem$mem_master_bid,
		near_mem$mem_master_rid;
  wire [7 : 0] near_mem$dma_server_arlen,
	       near_mem$dma_server_awlen,
	       near_mem$imem_master_arlen,
	       near_mem$imem_master_awlen,
	       near_mem$imem_master_wstrb,
	       near_mem$mem_master_arlen,
	       near_mem$mem_master_awlen,
	       near_mem$mem_master_wstrb,
	       near_mem$mv_status,
	       near_mem$server_fence_request_put;
  wire [6 : 0] near_mem$dmem_req_amo_funct7;
  wire [3 : 0] near_mem$dma_server_arcache,
	       near_mem$dma_server_arqos,
	       near_mem$dma_server_arregion,
	       near_mem$dma_server_awcache,
	       near_mem$dma_server_awqos,
	       near_mem$dma_server_awregion,
	       near_mem$dmem_exc_code,
	       near_mem$imem_exc_code,
	       near_mem$imem_master_arcache,
	       near_mem$imem_master_arqos,
	       near_mem$imem_master_arregion,
	       near_mem$imem_master_awcache,
	       near_mem$imem_master_awqos,
	       near_mem$imem_master_awregion,
	       near_mem$mem_master_arcache,
	       near_mem$mem_master_arqos,
	       near_mem$mem_master_arregion,
	       near_mem$mem_master_awcache,
	       near_mem$mem_master_awqos,
	       near_mem$mem_master_awregion;
  wire [2 : 0] near_mem$dma_server_arprot,
	       near_mem$dma_server_arsize,
	       near_mem$dma_server_awprot,
	       near_mem$dma_server_awsize,
	       near_mem$dmem_req_f3,
	       near_mem$imem_master_arprot,
	       near_mem$imem_master_arsize,
	       near_mem$imem_master_awprot,
	       near_mem$imem_master_awsize,
	       near_mem$imem_req_f3,
	       near_mem$mem_master_arprot,
	       near_mem$mem_master_arsize,
	       near_mem$mem_master_awprot,
	       near_mem$mem_master_awsize;
  wire [1 : 0] near_mem$dma_server_arburst,
	       near_mem$dma_server_awburst,
	       near_mem$dma_server_bresp,
	       near_mem$dma_server_rresp,
	       near_mem$dmem_req_priv,
	       near_mem$imem_master_arburst,
	       near_mem$imem_master_awburst,
	       near_mem$imem_master_bresp,
	       near_mem$imem_master_rresp,
	       near_mem$imem_req_priv,
	       near_mem$mem_master_arburst,
	       near_mem$mem_master_awburst,
	       near_mem$mem_master_bresp,
	       near_mem$mem_master_rresp;
  wire near_mem$EN_dmem_req,
       near_mem$EN_imem_req,
       near_mem$EN_ma_ddr4_ready,
       near_mem$EN_server_fence_i_request_put,
       near_mem$EN_server_fence_i_response_get,
       near_mem$EN_server_fence_request_put,
       near_mem$EN_server_fence_response_get,
       near_mem$EN_server_reset_request_put,
       near_mem$EN_server_reset_response_get,
       near_mem$EN_sfence_vma_server_request_put,
       near_mem$EN_sfence_vma_server_response_get,
       near_mem$RDY_server_reset_request_put,
       near_mem$RDY_server_reset_response_get,
       near_mem$dma_server_arlock,
       near_mem$dma_server_arready,
       near_mem$dma_server_arvalid,
       near_mem$dma_server_awlock,
       near_mem$dma_server_awready,
       near_mem$dma_server_awvalid,
       near_mem$dma_server_bready,
       near_mem$dma_server_bvalid,
       near_mem$dma_server_rlast,
       near_mem$dma_server_rready,
       near_mem$dma_server_rvalid,
       near_mem$dma_server_wlast,
       near_mem$dma_server_wready,
       near_mem$dma_server_wvalid,
       near_mem$dmem_exc,
       near_mem$dmem_req_mstatus_MXR,
       near_mem$dmem_req_sstatus_SUM,
       near_mem$dmem_valid,
       near_mem$imem_exc,
       near_mem$imem_is_i32_not_i16,
       near_mem$imem_master_arlock,
       near_mem$imem_master_arready,
       near_mem$imem_master_arvalid,
       near_mem$imem_master_awlock,
       near_mem$imem_master_awready,
       near_mem$imem_master_awvalid,
       near_mem$imem_master_bready,
       near_mem$imem_master_bvalid,
       near_mem$imem_master_rlast,
       near_mem$imem_master_rready,
       near_mem$imem_master_rvalid,
       near_mem$imem_master_wlast,
       near_mem$imem_master_wready,
       near_mem$imem_master_wvalid,
       near_mem$imem_req_mstatus_MXR,
       near_mem$imem_req_sstatus_SUM,
       near_mem$imem_valid,
       near_mem$mem_master_arlock,
       near_mem$mem_master_arready,
       near_mem$mem_master_arvalid,
       near_mem$mem_master_awlock,
       near_mem$mem_master_awready,
       near_mem$mem_master_awvalid,
       near_mem$mem_master_bready,
       near_mem$mem_master_bvalid,
       near_mem$mem_master_rlast,
       near_mem$mem_master_rready,
       near_mem$mem_master_rvalid,
       near_mem$mem_master_wlast,
       near_mem$mem_master_wready,
       near_mem$mem_master_wvalid;

  // ports of submodule soc_map
  wire [63 : 0] soc_map$m_is_IO_addr_addr,
		soc_map$m_is_mem_addr_addr,
		soc_map$m_is_near_mem_IO_addr_addr,
		soc_map$m_pc_reset_value;

  // ports of submodule stage1_f_reset_reqs
  wire stage1_f_reset_reqs$CLR,
       stage1_f_reset_reqs$DEQ,
       stage1_f_reset_reqs$EMPTY_N,
       stage1_f_reset_reqs$ENQ,
       stage1_f_reset_reqs$FULL_N;

  // ports of submodule stage1_f_reset_rsps
  wire stage1_f_reset_rsps$CLR,
       stage1_f_reset_rsps$DEQ,
       stage1_f_reset_rsps$EMPTY_N,
       stage1_f_reset_rsps$ENQ,
       stage1_f_reset_rsps$FULL_N;

  // ports of submodule stage2_f_reset_reqs
  wire stage2_f_reset_reqs$CLR,
       stage2_f_reset_reqs$DEQ,
       stage2_f_reset_reqs$EMPTY_N,
       stage2_f_reset_reqs$ENQ,
       stage2_f_reset_reqs$FULL_N;

  // ports of submodule stage2_f_reset_rsps
  wire stage2_f_reset_rsps$CLR,
       stage2_f_reset_rsps$DEQ,
       stage2_f_reset_rsps$EMPTY_N,
       stage2_f_reset_rsps$ENQ,
       stage2_f_reset_rsps$FULL_N;

  // ports of submodule stage2_fbox
  wire [63 : 0] stage2_fbox$req_v1,
		stage2_fbox$req_v2,
		stage2_fbox$req_v3,
		stage2_fbox$word_fst;
  wire [6 : 0] stage2_fbox$req_f7, stage2_fbox$req_opcode;
  wire [4 : 0] stage2_fbox$req_rs2, stage2_fbox$word_snd;
  wire [2 : 0] stage2_fbox$req_rm;
  wire stage2_fbox$EN_req,
       stage2_fbox$EN_server_reset_request_put,
       stage2_fbox$EN_server_reset_response_get,
       stage2_fbox$RDY_server_reset_request_put,
       stage2_fbox$RDY_server_reset_response_get,
       stage2_fbox$valid;

  // ports of submodule stage2_mbox
  wire [63 : 0] stage2_mbox$req_v1, stage2_mbox$req_v2, stage2_mbox$word;
  wire [3 : 0] stage2_mbox$set_verbosity_verbosity;
  wire [2 : 0] stage2_mbox$req_f3;
  wire stage2_mbox$EN_req,
       stage2_mbox$EN_req_reset,
       stage2_mbox$EN_rsp_reset,
       stage2_mbox$EN_set_verbosity,
       stage2_mbox$req_is_OP_not_OP_32,
       stage2_mbox$valid;

  // ports of submodule stage3_f_reset_reqs
  wire stage3_f_reset_reqs$CLR,
       stage3_f_reset_reqs$DEQ,
       stage3_f_reset_reqs$EMPTY_N,
       stage3_f_reset_reqs$ENQ,
       stage3_f_reset_reqs$FULL_N;

  // ports of submodule stage3_f_reset_rsps
  wire stage3_f_reset_rsps$CLR,
       stage3_f_reset_rsps$DEQ,
       stage3_f_reset_rsps$EMPTY_N,
       stage3_f_reset_rsps$ENQ,
       stage3_f_reset_rsps$FULL_N;

  // ports of submodule stageD_f_reset_reqs
  wire stageD_f_reset_reqs$CLR,
       stageD_f_reset_reqs$DEQ,
       stageD_f_reset_reqs$EMPTY_N,
       stageD_f_reset_reqs$ENQ,
       stageD_f_reset_reqs$FULL_N;

  // ports of submodule stageD_f_reset_rsps
  wire stageD_f_reset_rsps$CLR,
       stageD_f_reset_rsps$DEQ,
       stageD_f_reset_rsps$EMPTY_N,
       stageD_f_reset_rsps$ENQ,
       stageD_f_reset_rsps$FULL_N;

  // ports of submodule stageF_branch_predictor
  reg [63 : 0] stageF_branch_predictor$predict_req_pc;
  wire [194 : 0] stageF_branch_predictor$bp_train_cf_info;
  wire [63 : 0] stageF_branch_predictor$bp_train_pc,
		stageF_branch_predictor$predict_rsp;
  wire [31 : 0] stageF_branch_predictor$bp_train_instr,
		stageF_branch_predictor$predict_rsp_instr;
  wire stageF_branch_predictor$EN_bp_train,
       stageF_branch_predictor$EN_predict_req,
       stageF_branch_predictor$EN_reset,
       stageF_branch_predictor$RDY_predict_req,
       stageF_branch_predictor$bp_train_is_i32_not_i16,
       stageF_branch_predictor$predict_rsp_is_i32_not_i16;

  // ports of submodule stageF_f_reset_reqs
  wire stageF_f_reset_reqs$CLR,
       stageF_f_reset_reqs$DEQ,
       stageF_f_reset_reqs$EMPTY_N,
       stageF_f_reset_reqs$ENQ,
       stageF_f_reset_reqs$FULL_N;

  // ports of submodule stageF_f_reset_rsps
  wire stageF_f_reset_rsps$CLR,
       stageF_f_reset_rsps$DEQ,
       stageF_f_reset_rsps$EMPTY_N,
       stageF_f_reset_rsps$ENQ,
       stageF_f_reset_rsps$FULL_N;

  // rule scheduling signals
  wire CAN_FIRE_RL_imem_rl_assert_fail,
       CAN_FIRE_RL_imem_rl_fetch_next_32b,
       CAN_FIRE_RL_rl_BREAK_cache_flush_finish,
       CAN_FIRE_RL_rl_WFI_resume,
       CAN_FIRE_RL_rl_debug_csr_access_busy,
       CAN_FIRE_RL_rl_debug_fpr_access_busy,
       CAN_FIRE_RL_rl_debug_gpr_access_busy,
       CAN_FIRE_RL_rl_debug_halt,
       CAN_FIRE_RL_rl_debug_halt_redundant,
       CAN_FIRE_RL_rl_debug_read_csr,
       CAN_FIRE_RL_rl_debug_read_fpr,
       CAN_FIRE_RL_rl_debug_read_gpr,
       CAN_FIRE_RL_rl_debug_run,
       CAN_FIRE_RL_rl_debug_run_redundant,
       CAN_FIRE_RL_rl_debug_write_csr,
       CAN_FIRE_RL_rl_debug_write_fpr,
       CAN_FIRE_RL_rl_debug_write_gpr,
       CAN_FIRE_RL_rl_finish_FENCE,
       CAN_FIRE_RL_rl_finish_FENCE_I,
       CAN_FIRE_RL_rl_finish_SFENCE_VMA,
       CAN_FIRE_RL_rl_pipe,
       CAN_FIRE_RL_rl_reset_complete,
       CAN_FIRE_RL_rl_reset_from_Debug_Module,
       CAN_FIRE_RL_rl_reset_from_WFI,
       CAN_FIRE_RL_rl_reset_start,
       CAN_FIRE_RL_rl_show_pipe,
       CAN_FIRE_RL_rl_stage1_CSRR_S_or_C,
       CAN_FIRE_RL_rl_stage1_CSRR_S_or_C_2,
       CAN_FIRE_RL_rl_stage1_CSRR_W,
       CAN_FIRE_RL_rl_stage1_CSRR_W_2,
       CAN_FIRE_RL_rl_stage1_FENCE,
       CAN_FIRE_RL_rl_stage1_FENCE_I,
       CAN_FIRE_RL_rl_stage1_SFENCE_VMA,
       CAN_FIRE_RL_rl_stage1_WFI,
       CAN_FIRE_RL_rl_stage1_interrupt,
       CAN_FIRE_RL_rl_stage1_mip_cmd,
       CAN_FIRE_RL_rl_stage1_restart_after_csrrx,
       CAN_FIRE_RL_rl_stage1_stop,
       CAN_FIRE_RL_rl_stage1_trap,
       CAN_FIRE_RL_rl_stage1_xRET,
       CAN_FIRE_RL_rl_stage2_nonpipe,
       CAN_FIRE_RL_rl_trap,
       CAN_FIRE_RL_rl_trap_BREAK_to_Debug_Mode,
       CAN_FIRE_RL_rl_trap_fetch,
       CAN_FIRE_RL_stage1_rl_reset,
       CAN_FIRE_RL_stage2_rl_reset_begin,
       CAN_FIRE_RL_stage2_rl_reset_end,
       CAN_FIRE_RL_stage3_rl_reset,
       CAN_FIRE_RL_stageD_rl_reset,
       CAN_FIRE_RL_stageF_rl_reset,
       CAN_FIRE_dma_server_m_arvalid,
       CAN_FIRE_dma_server_m_awvalid,
       CAN_FIRE_dma_server_m_bready,
       CAN_FIRE_dma_server_m_rready,
       CAN_FIRE_dma_server_m_wvalid,
       CAN_FIRE_hart0_csr_mem_server_request_put,
       CAN_FIRE_hart0_csr_mem_server_response_get,
       CAN_FIRE_hart0_fpr_mem_server_request_put,
       CAN_FIRE_hart0_fpr_mem_server_response_get,
       CAN_FIRE_hart0_gpr_mem_server_request_put,
       CAN_FIRE_hart0_gpr_mem_server_response_get,
       CAN_FIRE_hart0_put_other_req_put,
       CAN_FIRE_hart0_server_reset_request_put,
       CAN_FIRE_hart0_server_reset_response_get,
       CAN_FIRE_hart0_server_run_halt_request_put,
       CAN_FIRE_hart0_server_run_halt_response_get,
       CAN_FIRE_imem_master_m_arready,
       CAN_FIRE_imem_master_m_awready,
       CAN_FIRE_imem_master_m_bvalid,
       CAN_FIRE_imem_master_m_rvalid,
       CAN_FIRE_imem_master_m_wready,
       CAN_FIRE_m_external_interrupt_req,
       CAN_FIRE_ma_ddr4_ready,
       CAN_FIRE_mem_master_m_arready,
       CAN_FIRE_mem_master_m_awready,
       CAN_FIRE_mem_master_m_bvalid,
       CAN_FIRE_mem_master_m_rvalid,
       CAN_FIRE_mem_master_m_wready,
       CAN_FIRE_nmi_req,
       CAN_FIRE_s_external_interrupt_req,
       CAN_FIRE_set_verbosity,
       CAN_FIRE_software_interrupt_req,
       CAN_FIRE_timer_interrupt_req,
       CAN_FIRE_trace_data_out_get,
       WILL_FIRE_RL_imem_rl_assert_fail,
       WILL_FIRE_RL_imem_rl_fetch_next_32b,
       WILL_FIRE_RL_rl_BREAK_cache_flush_finish,
       WILL_FIRE_RL_rl_WFI_resume,
       WILL_FIRE_RL_rl_debug_csr_access_busy,
       WILL_FIRE_RL_rl_debug_fpr_access_busy,
       WILL_FIRE_RL_rl_debug_gpr_access_busy,
       WILL_FIRE_RL_rl_debug_halt,
       WILL_FIRE_RL_rl_debug_halt_redundant,
       WILL_FIRE_RL_rl_debug_read_csr,
       WILL_FIRE_RL_rl_debug_read_fpr,
       WILL_FIRE_RL_rl_debug_read_gpr,
       WILL_FIRE_RL_rl_debug_run,
       WILL_FIRE_RL_rl_debug_run_redundant,
       WILL_FIRE_RL_rl_debug_write_csr,
       WILL_FIRE_RL_rl_debug_write_fpr,
       WILL_FIRE_RL_rl_debug_write_gpr,
       WILL_FIRE_RL_rl_finish_FENCE,
       WILL_FIRE_RL_rl_finish_FENCE_I,
       WILL_FIRE_RL_rl_finish_SFENCE_VMA,
       WILL_FIRE_RL_rl_pipe,
       WILL_FIRE_RL_rl_reset_complete,
       WILL_FIRE_RL_rl_reset_from_Debug_Module,
       WILL_FIRE_RL_rl_reset_from_WFI,
       WILL_FIRE_RL_rl_reset_start,
       WILL_FIRE_RL_rl_show_pipe,
       WILL_FIRE_RL_rl_stage1_CSRR_S_or_C,
       WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2,
       WILL_FIRE_RL_rl_stage1_CSRR_W,
       WILL_FIRE_RL_rl_stage1_CSRR_W_2,
       WILL_FIRE_RL_rl_stage1_FENCE,
       WILL_FIRE_RL_rl_stage1_FENCE_I,
       WILL_FIRE_RL_rl_stage1_SFENCE_VMA,
       WILL_FIRE_RL_rl_stage1_WFI,
       WILL_FIRE_RL_rl_stage1_interrupt,
       WILL_FIRE_RL_rl_stage1_mip_cmd,
       WILL_FIRE_RL_rl_stage1_restart_after_csrrx,
       WILL_FIRE_RL_rl_stage1_stop,
       WILL_FIRE_RL_rl_stage1_trap,
       WILL_FIRE_RL_rl_stage1_xRET,
       WILL_FIRE_RL_rl_stage2_nonpipe,
       WILL_FIRE_RL_rl_trap,
       WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode,
       WILL_FIRE_RL_rl_trap_fetch,
       WILL_FIRE_RL_stage1_rl_reset,
       WILL_FIRE_RL_stage2_rl_reset_begin,
       WILL_FIRE_RL_stage2_rl_reset_end,
       WILL_FIRE_RL_stage3_rl_reset,
       WILL_FIRE_RL_stageD_rl_reset,
       WILL_FIRE_RL_stageF_rl_reset,
       WILL_FIRE_dma_server_m_arvalid,
       WILL_FIRE_dma_server_m_awvalid,
       WILL_FIRE_dma_server_m_bready,
       WILL_FIRE_dma_server_m_rready,
       WILL_FIRE_dma_server_m_wvalid,
       WILL_FIRE_hart0_csr_mem_server_request_put,
       WILL_FIRE_hart0_csr_mem_server_response_get,
       WILL_FIRE_hart0_fpr_mem_server_request_put,
       WILL_FIRE_hart0_fpr_mem_server_response_get,
       WILL_FIRE_hart0_gpr_mem_server_request_put,
       WILL_FIRE_hart0_gpr_mem_server_response_get,
       WILL_FIRE_hart0_put_other_req_put,
       WILL_FIRE_hart0_server_reset_request_put,
       WILL_FIRE_hart0_server_reset_response_get,
       WILL_FIRE_hart0_server_run_halt_request_put,
       WILL_FIRE_hart0_server_run_halt_response_get,
       WILL_FIRE_imem_master_m_arready,
       WILL_FIRE_imem_master_m_awready,
       WILL_FIRE_imem_master_m_bvalid,
       WILL_FIRE_imem_master_m_rvalid,
       WILL_FIRE_imem_master_m_wready,
       WILL_FIRE_m_external_interrupt_req,
       WILL_FIRE_ma_ddr4_ready,
       WILL_FIRE_mem_master_m_arready,
       WILL_FIRE_mem_master_m_awready,
       WILL_FIRE_mem_master_m_bvalid,
       WILL_FIRE_mem_master_m_rvalid,
       WILL_FIRE_mem_master_m_wready,
       WILL_FIRE_nmi_req,
       WILL_FIRE_s_external_interrupt_req,
       WILL_FIRE_set_verbosity,
       WILL_FIRE_software_interrupt_req,
       WILL_FIRE_timer_interrupt_req,
       WILL_FIRE_trace_data_out_get;

  // inputs to muxes for submodule ports
  reg [131 : 0] MUX_rg_trap_info$write_1__VAL_2;
  reg [63 : 0] MUX_csr_regfile$mav_csr_write_2__VAL_2;
  wire [426 : 0] MUX_f_trace_data$enq_1__VAL_1,
		 MUX_f_trace_data$enq_1__VAL_2,
		 MUX_f_trace_data$enq_1__VAL_3,
		 MUX_f_trace_data$enq_1__VAL_6,
		 MUX_f_trace_data$enq_1__VAL_7,
		 MUX_f_trace_data$enq_1__VAL_8,
		 MUX_rg_trap_trace_data$write_1__VAL_2;
  wire [131 : 0] MUX_rg_trap_info$write_1__VAL_1,
		 MUX_rg_trap_info$write_1__VAL_3,
		 MUX_rg_trap_info$write_1__VAL_4;
  wire [64 : 0] MUX_f_csr_rsps$enq_1__VAL_3,
		MUX_f_fpr_rsps$enq_1__VAL_3,
		MUX_f_gpr_rsps$enq_1__VAL_3;
  wire [63 : 0] MUX_imem_rg_tval$write_1__VAL_5,
		MUX_near_mem$imem_req_2__VAL_1,
		MUX_near_mem$imem_req_2__VAL_2,
		MUX_near_mem$imem_req_2__VAL_4,
		MUX_near_mem$imem_req_2__VAL_5;
  wire [31 : 0] MUX_rg_trap_instr$write_1__VAL_1;
  wire [3 : 0] MUX_rg_state$write_1__VAL_2,
	       MUX_rg_state$write_1__VAL_3,
	       MUX_rg_state$write_1__VAL_4;
  wire [2 : 0] MUX_csr_regfile$write_dcsr_cause_priv_1__VAL_2;
  wire MUX_csr_regfile$mav_csr_write_1__SEL_1,
       MUX_csr_regfile$mav_csr_write_1__SEL_2,
       MUX_csr_regfile$write_dcsr_cause_priv_1__SEL_1,
       MUX_csr_regfile$write_dpc_1__SEL_2,
       MUX_f_run_halt_rsps$enq_1__SEL_1,
       MUX_f_trace_data$enq_1__SEL_1,
       MUX_f_trace_data$enq_1__SEL_3,
       MUX_f_trace_data$enq_1__SEL_4,
       MUX_fpr_regfile$write_rd_1__SEL_1,
       MUX_gpr_regfile$write_rd_1__SEL_3,
       MUX_imem_rg_cache_addr$write_1__PSEL_1,
       MUX_imem_rg_cache_addr$write_1__SEL_3,
       MUX_imem_rg_f3$write_1__SEL_1,
       MUX_imem_rg_pc$write_1__SEL_3,
       MUX_rg_next_pc$write_1__SEL_1,
       MUX_rg_next_pc$write_1__SEL_4,
       MUX_rg_state$write_1__SEL_1,
       MUX_rg_state$write_1__SEL_10,
       MUX_rg_state$write_1__SEL_11,
       MUX_rg_state$write_1__SEL_2,
       MUX_rg_state$write_1__SEL_3,
       MUX_rg_state$write_1__SEL_4,
       MUX_rg_state$write_1__SEL_5,
       MUX_rg_step_count$write_1__SEL_4,
       MUX_rg_trap_info$write_1__SEL_1,
       MUX_rg_trap_instr$write_1__SEL_1,
       MUX_rg_trap_interrupt$write_1__SEL_1,
       MUX_rg_trap_trace_data$write_1__SEL_1,
       MUX_stage1_rg_full$write_1__VAL_2,
       MUX_stage2_rg_full$write_1__VAL_2,
       MUX_stageD_rg_full$write_1__VAL_2,
       MUX_stageF_rg_full$write_1__VAL_2;

  // declarations used by system tasks
  // synopsys translate_off
  reg [31 : 0] v__h2871;
  reg [31 : 0] v__h2865;
  // synopsys translate_on

  // remaining internal signals
  reg [127 : 0] CASE_stage2_rg_stage2_BITS_824_TO_822_0_stage2_ETC__q27;
  reg [63 : 0] CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q24,
	       CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q25,
	       CASE_stage2_rg_stage2_BITS_824_TO_822_2_stage2_ETC__q26,
	       IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d1305,
	       IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2373,
	       IF_stage2_rg_stage2_18_BITS_824_TO_822_19_EQ_0_ETC___d2223,
	       _theResult_____1_fst__h12309,
	       alu_outputs_trace_data_pc__h28334,
	       alu_outputs_trace_data_word1__h28338,
	       alu_outputs_trace_data_word2__h28339,
	       alu_outputs_trace_data_word3__h28340,
	       alu_outputs_trace_data_word4__h28341,
	       rd_val__h10798,
	       rs1_val__h35619,
	       value__h9553,
	       value__h9614,
	       x_out_bypass_rd_val__h9856,
	       x_out_cf_info_taken_PC__h14806,
	       x_out_data_to_stage2_addr__h10376,
	       x_out_data_to_stage2_val1__h10377,
	       x_out_data_to_stage3_frd_val__h9225,
	       x_out_data_to_stage3_rd_val__h9221,
	       x_out_fbypass_rd_val__h9984;
  reg [4 : 0] IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2345,
	      alu_outputs_trace_data_rd__h28337,
	      data_to_stage2_rd__h10357,
	      x_out_bypass_rd__h9855,
	      x_out_data_to_stage3_fpr_flags__h9224,
	      x_out_data_to_stage3_rd__h9220,
	      x_out_fbypass_rd__h9983;
  reg [3 : 0] CASE_rg_cur_priv_0b0_8_0b1_9_11__q16,
	      CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q18,
	      CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q19,
	      CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q17,
	      IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d1001,
	      IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d998,
	      IF_stage1_rg_stage_input_17_BITS_87_TO_76_53_E_ETC___d976,
	      alu_outputs_exc_code__h11522,
	      x_out_trap_info_exc_code__h9590;
  reg [2 : 0] CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q22,
	      CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q23;
  reg [1 : 0] CASE_stage2_rg_stage2_BITS_824_TO_822_0_2_1_IF_ETC__q4,
	      CASE_stage2_rg_stage2_BITS_824_TO_822_0_2_1_IF_ETC__q5,
	      CASE_stage2_rg_stage2_BITS_824_TO_822_1_IF_NOT_ETC__q6,
	      IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d1086;
  reg CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12,
      CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q13,
      CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14,
      CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q15,
      CASE_stage2_rg_stage2_BITS_824_TO_822_1_NOT_st_ETC__q29,
      CASE_stage2_rg_stage2_BITS_824_TO_822_1_stage2_ETC__q28,
      IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d407,
      IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d731,
      IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d714,
      IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d722,
      IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d907,
      IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d915,
      IF_stage2_rg_stage2_18_BITS_824_TO_822_19_EQ_1_ETC___d169,
      IF_stage2_rg_stage2_18_BITS_824_TO_822_19_EQ_1_ETC___d179;
  wire [426 : 0] IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2420;
  wire [255 : 0] IF_stage2_rg_stage2_18_BITS_824_TO_822_19_EQ_0_ETC___d2240;
  wire [191 : 0] rg_trap_info_626_BITS_131_TO_68_627_CONCAT_IF__ETC___d2650;
  wire [127 : 0] IF_stage2_rg_stage2_18_BIT_432_08_THEN_csr_reg_ETC___d2230,
		 csr_regfile_read_csr_mcycle__0_MINUS_rg_start__ETC___d2825;
  wire [63 : 0] IF_csr_regfile_read_csr_rg_trap_instr_654_BITS_ETC___d2714,
		IF_csr_regfilemav_csr_write_BIT_64_THEN_2_ELSE_0__q1,
		IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d1115,
		IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d1306,
		IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d1307,
		IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d1316,
		IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2374,
		SEXT_stage1_rg_stage_input_17_BITS_87_TO_76_53___d1114,
		_theResult_____1_fst__h12302,
		_theResult_____1_fst__h12337,
		_theResult____h10689,
		_theResult____h43947,
		_theResult___fst__h12446,
		_theResult___fst__h12453,
		_theResult___fst__h12552,
		_theResult___snd__h15154,
		_theResult___snd_fst_rd_val__h9975,
		addr_of_b32___1__h25679,
		addr_of_b32___1__h32842,
		addr_of_b32___1__h42989,
		addr_of_b32___1__h44948,
		addr_of_b32__h25567,
		addr_of_b32__h32730,
		addr_of_b32__h42877,
		addr_of_b32__h44836,
		alu_outputs___1_addr__h10542,
		alu_outputs___1_addr__h10941,
		alu_outputs___1_fval2__h10945,
		alu_outputs___1_trace_data_pc__h28288,
		alu_outputs___1_trace_data_word1__h28116,
		alu_outputs___1_trace_data_word2__h28117,
		alu_outputs___1_trace_data_word2__h28293,
		alu_outputs___1_trace_data_word5__h28120,
		alu_outputs___1_val1__h11228,
		alu_outputs___1_val1__h11257,
		alu_outputs_cf_info_fallthru_PC__h14797,
		alu_outputs_cf_info_taken_PC__h14798,
		branch_target__h10519,
		cpi__h43949,
		cpifrac__h43950,
		data_to_stage2_addr__h10358,
		delta_CPI_cycles__h43945,
		delta_CPI_instrs___1__h43982,
		delta_CPI_instrs__h43946,
		fall_through_pc__h10290,
		next_pc___1__h14317,
		next_pc__h10291,
		next_pc__h10557,
		next_pc__h10594,
		next_pc__h14314,
		output_stage2___1_data_to_stage3_frd_val__h9165,
		output_stage2___1_data_to_stage3_rd_val__h9194,
		output_stage2___1_data_to_stage3_trace_data_word1__h27021,
		output_stage2___1_data_to_stage3_trace_data_word1__h27042,
		output_stage2___1_data_to_stage3_trace_data_word5__h27046,
		rd_val___1__h12290,
		rd_val___1__h12298,
		rd_val___1__h12305,
		rd_val___1__h12312,
		rd_val___1__h12319,
		rd_val___1__h12326,
		rd_val___1__h15183,
		rd_val___1__h15214,
		rd_val___1__h15267,
		rd_val___1__h15296,
		rd_val___1__h15348,
		rd_val___1__h15396,
		rd_val___1__h15402,
		rd_val___1__h15447,
		rd_val__h10168,
		rd_val__h10193,
		rd_val__h10218,
		rd_val__h10241,
		rd_val__h10267,
		rd_val__h10736,
		rd_val__h10767,
		rd_val__h10823,
		rd_val__h10847,
		rd_val__h15051,
		rd_val__h15102,
		rd_val__h15124,
		rs1_val__h34674,
		rs1_val_bypassed__h5803,
		rs2_val__h10515,
		td_word1__h29016,
		trace_data___1_word2__h26793,
		trap_info_tval__h14555,
		val__h10170,
		val__h10195,
		value__h14669,
		x__h26853,
		x__h26867,
		x__h35109,
		x__h35168,
		x__h36096,
		x__h36155,
		x__h36158,
		x__h36164,
		x__h43948,
		x_out_cf_info_fallthru_PC__h14805,
		x_out_data_to_stage2_fval1__h10379,
		x_out_data_to_stage2_fval3__h10381,
		x_out_data_to_stage2_val2__h10378,
		x_out_next_pc__h10308,
		y__h35888;
  wire [31 : 0] IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem__ETC___d1883,
		IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1724,
		IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1725,
		IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1726,
		IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1727,
		IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1728,
		IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1729,
		IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1730,
		IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1732,
		IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1734,
		IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1736,
		IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1738,
		IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1739,
		IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1740,
		IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1742,
		IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1743,
		IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1744,
		IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1746,
		IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1748,
		IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1749,
		IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1751,
		IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1752,
		IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1753,
		IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1754,
		IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1755,
		IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1756,
		IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1757,
		IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1758,
		IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg_p_ETC___d1884,
		IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC__q21,
		_theResult____h6090,
		alu_outputs___1_trace_data_instr__h28290,
		d_instr__h23510,
		instr___1__h15927,
		instr__h16104,
		instr__h16249,
		instr__h16441,
		instr__h16636,
		instr__h16865,
		instr__h17318,
		instr__h17434,
		instr__h17499,
		instr__h17816,
		instr__h18154,
		instr__h18338,
		instr__h18467,
		instr__h18694,
		instr__h18949,
		instr__h19121,
		instr__h19290,
		instr__h19479,
		instr__h19668,
		instr__h19785,
		instr__h19963,
		instr__h20082,
		instr__h20177,
		instr__h20313,
		instr__h20449,
		instr__h20585,
		instr__h20723,
		instr__h20861,
		instr__h21019,
		instr__h21115,
		instr__h21268,
		instr__h21467,
		instr__h21618,
		instr__h21823,
		instr__h22631,
		instr__h22804,
		instr__h23003,
		instr__h23154,
		instr_out___1__h23512,
		instr_out___1__h23534,
		result___1__h29833,
		rs1_val_bypassed803_BITS_31_TO_0_MINUS_rs2_val_ETC__q11,
		rs1_val_bypassed803_BITS_31_TO_0_PLUS_rs2_val0_ETC__q10,
		rs1_val_bypassed803_BITS_31_TO_0_SRL_rs2_val05_ETC__q9,
		rs1_val_bypassed803_BITS_31_TO_0__q8,
		tmp__h15295,
		v32__h10821,
		x__h15217,
		x__h15270,
		x__h15405,
		x__h15450,
		x_out_data_to_stage1_instr__h15891;
  wire [20 : 0] SEXT_stageD_rg_data_461_BIT_76_478_CONCAT_stag_ETC___d1531,
		decoded_instr_imm21_UJ__h31424,
		stage1_rg_stage_input_BITS_30_TO_10__q3;
  wire [19 : 0] imm20__h18206;
  wire [12 : 0] SEXT_stageD_rg_data_461_BIT_76_478_CONCAT_stag_ETC___d1556,
		decoded_instr_imm13_SB__h31422,
		stage1_rg_stage_input_BITS_63_TO_51__q2;
  wire [11 : 0] decoded_instr_imm12_S__h31421,
		imm12__h16105,
		imm12__h16442,
		imm12__h18078,
		imm12__h18747,
		imm12__h18962,
		imm12__h19158,
		imm12__h19495,
		imm12__h21116,
		imm12__h21468,
		offset__h16812,
		stage1_rg_stage_input_BITS_75_TO_64__q7,
		stage1_rg_stage_input_BITS_87_TO_76__q20;
  wire [9 : 0] decoded_instr_funct10__h31419,
	       nzimm10__h18745,
	       nzimm10__h18960;
  wire [8 : 0] offset__h17443, offset__h21030;
  wire [7 : 0] offset__h15977, offset__h21402;
  wire [6 : 0] offset__h16384;
  wire [5 : 0] imm6__h18076, shamt__h10685;
  wire [4 : 0] IF_NOT_stage1_rg_stage_input_17_BITS_104_TO_98_ETC___d2336,
	       IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2334,
	       IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2335,
	       offset_BITS_4_TO_0___h16373,
	       offset_BITS_4_TO_0___h16804,
	       offset_BITS_4_TO_0___h21743,
	       rd__h16444,
	       rs1__h16443,
	       td1_rd__h37536,
	       x_out_data_to_stage2_rd__h10375,
	       x_rd__h34040;
  wire [3 : 0] IF_NOT_csr_regfile_read_mstatus__2_BITS_14_TO__ETC___d986,
	       IF_NOT_stage1_rg_stage_input_17_BITS_112_TO_11_ETC___d930,
	       IF_rg_cur_priv_1_EQ_0b11_45_OR_rg_cur_priv_1_E_ETC___d974,
	       IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d936,
	       IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d940,
	       IF_stage1_rg_stage_input_17_BITS_144_TO_140_43_ETC___d978,
	       IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004,
	       alu_outputs___1_exc_code__h11224,
	       cur_verbosity__h4054,
	       x_exc_code__h43682,
	       x_out_trap_info_exc_code__h14560;
  wire [2 : 0] IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153,
	       rm__h11387,
	       x_out_data_to_stage2_rounding_mode__h10385;
  wire [1 : 0] IF_NOT_near_mem_dmem_valid__41_63_OR_NOT_near__ETC___d276,
	       IF_NOT_near_mem_dmem_valid__41_63_OR_NOT_near__ETC___d296,
	       IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d301,
	       IF_near_mem_dmem_valid__41_THEN_IF_near_mem_dm_ETC___d144,
	       IF_stage2_fbox_valid__47_THEN_2_ELSE_1___d148,
	       IF_stage2_mbox_valid__45_THEN_2_ELSE_1___d146,
	       IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153,
	       IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d283,
	       new_epoch__h25078,
	       sxl__h8089,
	       uxl__h8090;
  wire IF_IF_stage1_rg_stage_input_17_BITS_151_TO_145_ETC___d1451,
       IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d2088,
       IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d2170,
       IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d326,
       IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d327,
       IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d330,
       IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d396,
       IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d398,
       IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d400,
       IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d725,
       IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d736,
       IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d918,
       IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d920,
       IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2132,
       IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2135,
       IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2487,
       IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2528,
       IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2535,
       IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2550,
       IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2574,
       IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d2105,
       IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d2260,
       IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d2262,
       IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d321,
       IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d323,
       IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333,
       IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923,
       NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53,
       NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d2082,
       NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357,
       NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2139,
       NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2604,
       NOT_csr_regfile_read_dpc__843_BITS_1_TO_0_844__ETC___d2852,
       NOT_csr_regfile_read_mstatus__2_BITS_14_TO_13__ETC___d903,
       NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1866,
       NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1880,
       NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1909,
       NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911,
       NOT_rg_cur_priv_1_EQ_0b11_45_433_AND_NOT_rg_cu_ETC___d1439,
       NOT_rg_next_pc_736_BITS_1_TO_0_737_EQ_0b0_738__ETC___d2745,
       NOT_soc_map_m_pc_reset_value__063_BITS_1_TO_0__ETC___d2078,
       NOT_stage1_rg_full_16_27_OR_stage1_rg_stage_in_ETC___d2163,
       NOT_stage1_rg_full_16_27_OR_stage1_rg_stage_in_ETC___d2165,
       NOT_stage1_rg_full_16_27_OR_stage1_rg_stage_in_ETC___d2167,
       NOT_stage1_rg_full_16_27_OR_stage1_rg_stage_in_ETC___d2168,
       NOT_stage1_rg_stage_input_17_BITS_112_TO_110_6_ETC___d443,
       NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d1077,
       NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d1089,
       NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d1093,
       NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d1099,
       NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2270,
       NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2272,
       NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2274,
       NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2537,
       NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2545,
       NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2548,
       NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2588,
       NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2805,
       NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2815,
       NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2820,
       NOT_stage1_rg_stage_input_17_BIT_332_58_44_AND_ETC___d2602,
       NOT_stageF_branch_predictor_predict_rsp_NOT_im_ETC___d2559,
       _dand1rg_step_count$EN_write,
       _dand2rg_step_count$EN_write,
       csr_regfile_RDY_server_reset_response_get__036_ETC___d2057,
       csr_regfile_csr_mip_read__092_EQ_rg_prev_mip_093___d2094,
       csr_regfile_interrupt_pending_rg_cur_priv_1_11_ETC___d2540,
       csr_regfile_interrupt_pending_rg_cur_priv_1_11_ETC___d2807,
       csr_regfile_read_misa__9_BIT_2_466_AND_stageD__ETC___d1541,
       csr_regfile_read_misa__9_BIT_2_466_AND_stageD__ETC___d1547,
       csr_regfile_read_mstatus__2_BITS_14_TO_13_4_EQ_ETC___d710,
       f_reset_reqs_i_notEmpty__013_AND_stageF_f_rese_ETC___d2025,
       f_reset_rsps_i_notFull__042_AND_NOT_rg_run_on__ETC___d2051,
       fpr_regfile_RDY_server_reset_request_put__010__ETC___d2028,
       imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1898,
       imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1902,
       imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1905,
       imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2047,
       imem_rg_pc_BITS_63_TO_2_0_EQ_imem_rg_cache_add_ETC___d1858,
       imem_rg_pc_BITS_63_TO_2_0_EQ_near_mem_imem_pc__ETC___d13,
       near_mem_imem_pc__1_EQ_imem_rg_pc_PLUS_2_860___d1861,
       near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d2007,
       rg_cur_priv_1_EQ_0b11_45_OR_rg_cur_priv_1_EQ_0_ETC___d1424,
       rg_cur_priv_1_EQ_0b11_45_OR_rg_cur_priv_1_EQ_0_ETC___d972,
       rg_state_4_EQ_13_7_AND_csr_regfile_wfi_resume__ETC___d2786,
       rg_state_4_EQ_4_081_AND_NOT_stage1_rg_stage_in_ETC___d2609,
       rg_state_4_EQ_4_081_AND_NOT_stage1_rg_stage_in_ETC___d2751,
       rg_state_4_EQ_4_081_AND_NOT_stage1_rg_stage_in_ETC___d2781,
       rg_state_4_EQ_4_081_AND_NOT_stage1_rg_stage_in_ETC___d2794,
       rg_state_4_EQ_4_081_AND_stage3_rg_full_01_OR_N_ETC___d2160,
       rg_state_4_EQ_5_623_AND_NOT_stageF_rg_full_888_ETC___d2624,
       rg_state_4_EQ_6_790_AND_NOT_stageF_rg_full_888_ETC___d2791,
       rg_state_4_EQ_9_733_AND_NOT_stageF_rg_full_888_ETC___d2734,
       stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d1186,
       stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d2085,
       stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d2562,
       stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d2576,
       stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d2580,
       stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d926,
       stage1_rg_stage_input_17_BITS_112_TO_110_61_EQ_ETC___d763,
       stage1_rg_stage_input_17_BITS_144_TO_140_43_EQ_ETC___d951,
       stage1_rg_stage_input_17_BITS_151_TO_145_59_EQ_ETC___d2328,
       stage1_rg_stage_input_17_BITS_151_TO_145_59_EQ_ETC___d756,
       stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d1393,
       stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2108,
       stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2115,
       stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2123,
       stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2128,
       stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2137,
       stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2142,
       stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2148,
       stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2283,
       stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2457,
       stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2484,
       stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319,
       stage3_rg_full_01_OR_NOT_IF_stage2_rg_full_17__ETC___d2158,
       stage3_rg_stage3_03_BITS_566_TO_562_12_EQ_stag_ETC___d382,
       stage3_rg_stage3_03_BITS_566_TO_562_12_EQ_stag_ETC___d390,
       stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1920,
       stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1926,
       stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1930,
       stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1934,
       stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1938,
       stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1942,
       stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1946,
       stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1950,
       stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1954,
       stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1958,
       stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1962,
       stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1966,
       stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1970,
       stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1974,
       stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1978;

  // action method hart0_server_reset_request_put
  assign RDY_hart0_server_reset_request_put = f_reset_reqs$FULL_N ;
  assign CAN_FIRE_hart0_server_reset_request_put = f_reset_reqs$FULL_N ;
  assign WILL_FIRE_hart0_server_reset_request_put =
	     EN_hart0_server_reset_request_put ;

  // actionvalue method hart0_server_reset_response_get
  assign hart0_server_reset_response_get = f_reset_rsps$D_OUT ;
  assign RDY_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ;
  assign CAN_FIRE_hart0_server_reset_response_get = f_reset_rsps$EMPTY_N ;
  assign WILL_FIRE_hart0_server_reset_response_get =
	     EN_hart0_server_reset_response_get ;

  // value method imem_master_m_awvalid
  assign imem_master_awvalid = near_mem$imem_master_awvalid ;

  // value method imem_master_m_awid
  assign imem_master_awid = near_mem$imem_master_awid ;

  // value method imem_master_m_awaddr
  assign imem_master_awaddr = near_mem$imem_master_awaddr ;

  // value method imem_master_m_awlen
  assign imem_master_awlen = near_mem$imem_master_awlen ;

  // value method imem_master_m_awsize
  assign imem_master_awsize = near_mem$imem_master_awsize ;

  // value method imem_master_m_awburst
  assign imem_master_awburst = near_mem$imem_master_awburst ;

  // value method imem_master_m_awlock
  assign imem_master_awlock = near_mem$imem_master_awlock ;

  // value method imem_master_m_awcache
  assign imem_master_awcache = near_mem$imem_master_awcache ;

  // value method imem_master_m_awprot
  assign imem_master_awprot = near_mem$imem_master_awprot ;

  // value method imem_master_m_awqos
  assign imem_master_awqos = near_mem$imem_master_awqos ;

  // value method imem_master_m_awregion
  assign imem_master_awregion = near_mem$imem_master_awregion ;

  // action method imem_master_m_awready
  assign CAN_FIRE_imem_master_m_awready = 1'd1 ;
  assign WILL_FIRE_imem_master_m_awready = 1'd1 ;

  // value method imem_master_m_wvalid
  assign imem_master_wvalid = near_mem$imem_master_wvalid ;

  // value method imem_master_m_wdata
  assign imem_master_wdata = near_mem$imem_master_wdata ;

  // value method imem_master_m_wstrb
  assign imem_master_wstrb = near_mem$imem_master_wstrb ;

  // value method imem_master_m_wlast
  assign imem_master_wlast = near_mem$imem_master_wlast ;

  // action method imem_master_m_wready
  assign CAN_FIRE_imem_master_m_wready = 1'd1 ;
  assign WILL_FIRE_imem_master_m_wready = 1'd1 ;

  // action method imem_master_m_bvalid
  assign CAN_FIRE_imem_master_m_bvalid = 1'd1 ;
  assign WILL_FIRE_imem_master_m_bvalid = 1'd1 ;

  // value method imem_master_m_bready
  assign imem_master_bready = near_mem$imem_master_bready ;

  // value method imem_master_m_arvalid
  assign imem_master_arvalid = near_mem$imem_master_arvalid ;

  // value method imem_master_m_arid
  assign imem_master_arid = near_mem$imem_master_arid ;

  // value method imem_master_m_araddr
  assign imem_master_araddr = near_mem$imem_master_araddr ;

  // value method imem_master_m_arlen
  assign imem_master_arlen = near_mem$imem_master_arlen ;

  // value method imem_master_m_arsize
  assign imem_master_arsize = near_mem$imem_master_arsize ;

  // value method imem_master_m_arburst
  assign imem_master_arburst = near_mem$imem_master_arburst ;

  // value method imem_master_m_arlock
  assign imem_master_arlock = near_mem$imem_master_arlock ;

  // value method imem_master_m_arcache
  assign imem_master_arcache = near_mem$imem_master_arcache ;

  // value method imem_master_m_arprot
  assign imem_master_arprot = near_mem$imem_master_arprot ;

  // value method imem_master_m_arqos
  assign imem_master_arqos = near_mem$imem_master_arqos ;

  // value method imem_master_m_arregion
  assign imem_master_arregion = near_mem$imem_master_arregion ;

  // action method imem_master_m_arready
  assign CAN_FIRE_imem_master_m_arready = 1'd1 ;
  assign WILL_FIRE_imem_master_m_arready = 1'd1 ;

  // action method imem_master_m_rvalid
  assign CAN_FIRE_imem_master_m_rvalid = 1'd1 ;
  assign WILL_FIRE_imem_master_m_rvalid = 1'd1 ;

  // value method imem_master_m_rready
  assign imem_master_rready = near_mem$imem_master_rready ;

  // value method mem_master_m_awvalid
  assign mem_master_awvalid = near_mem$mem_master_awvalid ;

  // value method mem_master_m_awid
  assign mem_master_awid = near_mem$mem_master_awid ;

  // value method mem_master_m_awaddr
  assign mem_master_awaddr = near_mem$mem_master_awaddr ;

  // value method mem_master_m_awlen
  assign mem_master_awlen = near_mem$mem_master_awlen ;

  // value method mem_master_m_awsize
  assign mem_master_awsize = near_mem$mem_master_awsize ;

  // value method mem_master_m_awburst
  assign mem_master_awburst = near_mem$mem_master_awburst ;

  // value method mem_master_m_awlock
  assign mem_master_awlock = near_mem$mem_master_awlock ;

  // value method mem_master_m_awcache
  assign mem_master_awcache = near_mem$mem_master_awcache ;

  // value method mem_master_m_awprot
  assign mem_master_awprot = near_mem$mem_master_awprot ;

  // value method mem_master_m_awqos
  assign mem_master_awqos = near_mem$mem_master_awqos ;

  // value method mem_master_m_awregion
  assign mem_master_awregion = near_mem$mem_master_awregion ;

  // action method mem_master_m_awready
  assign CAN_FIRE_mem_master_m_awready = 1'd1 ;
  assign WILL_FIRE_mem_master_m_awready = 1'd1 ;

  // value method mem_master_m_wvalid
  assign mem_master_wvalid = near_mem$mem_master_wvalid ;

  // value method mem_master_m_wdata
  assign mem_master_wdata = near_mem$mem_master_wdata ;

  // value method mem_master_m_wstrb
  assign mem_master_wstrb = near_mem$mem_master_wstrb ;

  // value method mem_master_m_wlast
  assign mem_master_wlast = near_mem$mem_master_wlast ;

  // action method mem_master_m_wready
  assign CAN_FIRE_mem_master_m_wready = 1'd1 ;
  assign WILL_FIRE_mem_master_m_wready = 1'd1 ;

  // action method mem_master_m_bvalid
  assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ;
  assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ;

  // value method mem_master_m_bready
  assign mem_master_bready = near_mem$mem_master_bready ;

  // value method mem_master_m_arvalid
  assign mem_master_arvalid = near_mem$mem_master_arvalid ;

  // value method mem_master_m_arid
  assign mem_master_arid = near_mem$mem_master_arid ;

  // value method mem_master_m_araddr
  assign mem_master_araddr = near_mem$mem_master_araddr ;

  // value method mem_master_m_arlen
  assign mem_master_arlen = near_mem$mem_master_arlen ;

  // value method mem_master_m_arsize
  assign mem_master_arsize = near_mem$mem_master_arsize ;

  // value method mem_master_m_arburst
  assign mem_master_arburst = near_mem$mem_master_arburst ;

  // value method mem_master_m_arlock
  assign mem_master_arlock = near_mem$mem_master_arlock ;

  // value method mem_master_m_arcache
  assign mem_master_arcache = near_mem$mem_master_arcache ;

  // value method mem_master_m_arprot
  assign mem_master_arprot = near_mem$mem_master_arprot ;

  // value method mem_master_m_arqos
  assign mem_master_arqos = near_mem$mem_master_arqos ;

  // value method mem_master_m_arregion
  assign mem_master_arregion = near_mem$mem_master_arregion ;

  // action method mem_master_m_arready
  assign CAN_FIRE_mem_master_m_arready = 1'd1 ;
  assign WILL_FIRE_mem_master_m_arready = 1'd1 ;

  // action method mem_master_m_rvalid
  assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ;
  assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ;

  // value method mem_master_m_rready
  assign mem_master_rready = near_mem$mem_master_rready ;

  // action method dma_server_m_awvalid
  assign CAN_FIRE_dma_server_m_awvalid = 1'd1 ;
  assign WILL_FIRE_dma_server_m_awvalid = 1'd1 ;

  // value method dma_server_m_awready
  assign dma_server_awready = near_mem$dma_server_awready ;

  // action method dma_server_m_wvalid
  assign CAN_FIRE_dma_server_m_wvalid = 1'd1 ;
  assign WILL_FIRE_dma_server_m_wvalid = 1'd1 ;

  // value method dma_server_m_wready
  assign dma_server_wready = near_mem$dma_server_wready ;

  // value method dma_server_m_bvalid
  assign dma_server_bvalid = near_mem$dma_server_bvalid ;

  // value method dma_server_m_bid
  assign dma_server_bid = near_mem$dma_server_bid ;

  // value method dma_server_m_bresp
  assign dma_server_bresp = near_mem$dma_server_bresp ;

  // action method dma_server_m_bready
  assign CAN_FIRE_dma_server_m_bready = 1'd1 ;
  assign WILL_FIRE_dma_server_m_bready = 1'd1 ;

  // action method dma_server_m_arvalid
  assign CAN_FIRE_dma_server_m_arvalid = 1'd1 ;
  assign WILL_FIRE_dma_server_m_arvalid = 1'd1 ;

  // value method dma_server_m_arready
  assign dma_server_arready = near_mem$dma_server_arready ;

  // value method dma_server_m_rvalid
  assign dma_server_rvalid = near_mem$dma_server_rvalid ;

  // value method dma_server_m_rid
  assign dma_server_rid = near_mem$dma_server_rid ;

  // value method dma_server_m_rdata
  assign dma_server_rdata = near_mem$dma_server_rdata ;

  // value method dma_server_m_rresp
  assign dma_server_rresp = near_mem$dma_server_rresp ;

  // value method dma_server_m_rlast
  assign dma_server_rlast = near_mem$dma_server_rlast ;

  // action method dma_server_m_rready
  assign CAN_FIRE_dma_server_m_rready = 1'd1 ;
  assign WILL_FIRE_dma_server_m_rready = 1'd1 ;

  // action method m_external_interrupt_req
  assign CAN_FIRE_m_external_interrupt_req = 1'd1 ;
  assign WILL_FIRE_m_external_interrupt_req = 1'd1 ;

  // action method s_external_interrupt_req
  assign CAN_FIRE_s_external_interrupt_req = 1'd1 ;
  assign WILL_FIRE_s_external_interrupt_req = 1'd1 ;

  // action method software_interrupt_req
  assign CAN_FIRE_software_interrupt_req = 1'd1 ;
  assign WILL_FIRE_software_interrupt_req = 1'd1 ;

  // action method timer_interrupt_req
  assign CAN_FIRE_timer_interrupt_req = 1'd1 ;
  assign WILL_FIRE_timer_interrupt_req = 1'd1 ;

  // action method nmi_req
  assign CAN_FIRE_nmi_req = 1'd1 ;
  assign WILL_FIRE_nmi_req = 1'd1 ;

  // actionvalue method trace_data_out_get
  assign trace_data_out_get = f_trace_data$D_OUT ;
  assign RDY_trace_data_out_get = f_trace_data$EMPTY_N ;
  assign CAN_FIRE_trace_data_out_get = f_trace_data$EMPTY_N ;
  assign WILL_FIRE_trace_data_out_get = EN_trace_data_out_get ;

  // action method hart0_server_run_halt_request_put
  assign RDY_hart0_server_run_halt_request_put = f_run_halt_reqs$FULL_N ;
  assign CAN_FIRE_hart0_server_run_halt_request_put = f_run_halt_reqs$FULL_N ;
  assign WILL_FIRE_hart0_server_run_halt_request_put =
	     EN_hart0_server_run_halt_request_put ;

  // actionvalue method hart0_server_run_halt_response_get
  assign hart0_server_run_halt_response_get = f_run_halt_rsps$D_OUT ;
  assign RDY_hart0_server_run_halt_response_get = f_run_halt_rsps$EMPTY_N ;
  assign CAN_FIRE_hart0_server_run_halt_response_get =
	     f_run_halt_rsps$EMPTY_N ;
  assign WILL_FIRE_hart0_server_run_halt_response_get =
	     EN_hart0_server_run_halt_response_get ;

  // action method hart0_put_other_req_put
  assign RDY_hart0_put_other_req_put = 1'd1 ;
  assign CAN_FIRE_hart0_put_other_req_put = 1'd1 ;
  assign WILL_FIRE_hart0_put_other_req_put = EN_hart0_put_other_req_put ;

  // action method hart0_gpr_mem_server_request_put
  assign RDY_hart0_gpr_mem_server_request_put = f_gpr_reqs$FULL_N ;
  assign CAN_FIRE_hart0_gpr_mem_server_request_put = f_gpr_reqs$FULL_N ;
  assign WILL_FIRE_hart0_gpr_mem_server_request_put =
	     EN_hart0_gpr_mem_server_request_put ;

  // actionvalue method hart0_gpr_mem_server_response_get
  assign hart0_gpr_mem_server_response_get = f_gpr_rsps$D_OUT ;
  assign RDY_hart0_gpr_mem_server_response_get = f_gpr_rsps$EMPTY_N ;
  assign CAN_FIRE_hart0_gpr_mem_server_response_get = f_gpr_rsps$EMPTY_N ;
  assign WILL_FIRE_hart0_gpr_mem_server_response_get =
	     EN_hart0_gpr_mem_server_response_get ;

  // action method hart0_fpr_mem_server_request_put
  assign RDY_hart0_fpr_mem_server_request_put = f_fpr_reqs$FULL_N ;
  assign CAN_FIRE_hart0_fpr_mem_server_request_put = f_fpr_reqs$FULL_N ;
  assign WILL_FIRE_hart0_fpr_mem_server_request_put =
	     EN_hart0_fpr_mem_server_request_put ;

  // actionvalue method hart0_fpr_mem_server_response_get
  assign hart0_fpr_mem_server_response_get = f_fpr_rsps$D_OUT ;
  assign RDY_hart0_fpr_mem_server_response_get = f_fpr_rsps$EMPTY_N ;
  assign CAN_FIRE_hart0_fpr_mem_server_response_get = f_fpr_rsps$EMPTY_N ;
  assign WILL_FIRE_hart0_fpr_mem_server_response_get =
	     EN_hart0_fpr_mem_server_response_get ;

  // action method hart0_csr_mem_server_request_put
  assign RDY_hart0_csr_mem_server_request_put = f_csr_reqs$FULL_N ;
  assign CAN_FIRE_hart0_csr_mem_server_request_put = f_csr_reqs$FULL_N ;
  assign WILL_FIRE_hart0_csr_mem_server_request_put =
	     EN_hart0_csr_mem_server_request_put ;

  // actionvalue method hart0_csr_mem_server_response_get
  assign hart0_csr_mem_server_response_get = f_csr_rsps$D_OUT ;
  assign RDY_hart0_csr_mem_server_response_get = f_csr_rsps$EMPTY_N ;
  assign CAN_FIRE_hart0_csr_mem_server_response_get = f_csr_rsps$EMPTY_N ;
  assign WILL_FIRE_hart0_csr_mem_server_response_get =
	     EN_hart0_csr_mem_server_response_get ;

  // action method set_verbosity
  assign RDY_set_verbosity = 1'd1 ;
  assign CAN_FIRE_set_verbosity = 1'd1 ;
  assign WILL_FIRE_set_verbosity = EN_set_verbosity ;

  // action method ma_ddr4_ready
  assign RDY_ma_ddr4_ready = 1'd1 ;
  assign CAN_FIRE_ma_ddr4_ready = 1'd1 ;
  assign WILL_FIRE_ma_ddr4_ready = EN_ma_ddr4_ready ;

  // value method mv_status
  assign mv_status = near_mem$mv_status ;

  // submodule csr_regfile
  mkCSR_RegFile csr_regfile(.CLK(CLK),
			    .RST_N(RST_N),
			    .access_permitted_1_csr_addr(csr_regfile$access_permitted_1_csr_addr),
			    .access_permitted_1_priv(csr_regfile$access_permitted_1_priv),
			    .access_permitted_1_read_not_write(csr_regfile$access_permitted_1_read_not_write),
			    .access_permitted_2_csr_addr(csr_regfile$access_permitted_2_csr_addr),
			    .access_permitted_2_priv(csr_regfile$access_permitted_2_priv),
			    .access_permitted_2_read_not_write(csr_regfile$access_permitted_2_read_not_write),
			    .csr_counter_read_fault_csr_addr(csr_regfile$csr_counter_read_fault_csr_addr),
			    .csr_counter_read_fault_priv(csr_regfile$csr_counter_read_fault_priv),
			    .csr_ret_actions_from_priv(csr_regfile$csr_ret_actions_from_priv),
			    .csr_trap_actions_exc_code(csr_regfile$csr_trap_actions_exc_code),
			    .csr_trap_actions_from_priv(csr_regfile$csr_trap_actions_from_priv),
			    .csr_trap_actions_interrupt(csr_regfile$csr_trap_actions_interrupt),
			    .csr_trap_actions_nmi(csr_regfile$csr_trap_actions_nmi),
			    .csr_trap_actions_pc(csr_regfile$csr_trap_actions_pc),
			    .csr_trap_actions_xtval(csr_regfile$csr_trap_actions_xtval),
			    .dcsr_break_enters_debug_cur_priv(csr_regfile$dcsr_break_enters_debug_cur_priv),
			    .interrupt_pending_cur_priv(csr_regfile$interrupt_pending_cur_priv),
			    .m_external_interrupt_req_set_not_clear(csr_regfile$m_external_interrupt_req_set_not_clear),
			    .ma_update_fcsr_fflags_flags(csr_regfile$ma_update_fcsr_fflags_flags),
			    .ma_update_mstatus_fs_fs(csr_regfile$ma_update_mstatus_fs_fs),
			    .mav_csr_write_csr_addr(csr_regfile$mav_csr_write_csr_addr),
			    .mav_csr_write_word(csr_regfile$mav_csr_write_word),
			    .mav_read_csr_csr_addr(csr_regfile$mav_read_csr_csr_addr),
			    .mv_update_fcsr_fflags_flags(csr_regfile$mv_update_fcsr_fflags_flags),
			    .mv_update_mstatus_fs_fs(csr_regfile$mv_update_mstatus_fs_fs),
			    .nmi_req_set_not_clear(csr_regfile$nmi_req_set_not_clear),
			    .read_csr_csr_addr(csr_regfile$read_csr_csr_addr),
			    .read_csr_port2_csr_addr(csr_regfile$read_csr_port2_csr_addr),
			    .s_external_interrupt_req_set_not_clear(csr_regfile$s_external_interrupt_req_set_not_clear),
			    .software_interrupt_req_set_not_clear(csr_regfile$software_interrupt_req_set_not_clear),
			    .timer_interrupt_req_set_not_clear(csr_regfile$timer_interrupt_req_set_not_clear),
			    .write_dcsr_cause_priv_cause(csr_regfile$write_dcsr_cause_priv_cause),
			    .write_dcsr_cause_priv_priv(csr_regfile$write_dcsr_cause_priv_priv),
			    .write_dpc_pc(csr_regfile$write_dpc_pc),
			    .EN_server_reset_request_put(csr_regfile$EN_server_reset_request_put),
			    .EN_server_reset_response_get(csr_regfile$EN_server_reset_response_get),
			    .EN_mav_read_csr(csr_regfile$EN_mav_read_csr),
			    .EN_mav_csr_write(csr_regfile$EN_mav_csr_write),
			    .EN_ma_update_fcsr_fflags(csr_regfile$EN_ma_update_fcsr_fflags),
			    .EN_ma_update_mstatus_fs(csr_regfile$EN_ma_update_mstatus_fs),
			    .EN_csr_trap_actions(csr_regfile$EN_csr_trap_actions),
			    .EN_csr_ret_actions(csr_regfile$EN_csr_ret_actions),
			    .EN_csr_minstret_incr(csr_regfile$EN_csr_minstret_incr),
			    .EN_write_dpc(csr_regfile$EN_write_dpc),
			    .EN_write_dcsr_cause_priv(csr_regfile$EN_write_dcsr_cause_priv),
			    .EN_debug(csr_regfile$EN_debug),
			    .RDY_server_reset_request_put(csr_regfile$RDY_server_reset_request_put),
			    .RDY_server_reset_response_get(csr_regfile$RDY_server_reset_response_get),
			    .read_csr(csr_regfile$read_csr),
			    .read_csr_port2(csr_regfile$read_csr_port2),
			    .mav_read_csr(),
			    .mav_csr_write(csr_regfile$mav_csr_write),
			    .read_frm(csr_regfile$read_frm),
			    .read_fflags(csr_regfile$read_fflags),
			    .mv_update_fcsr_fflags(csr_regfile$mv_update_fcsr_fflags),
			    .mv_update_mstatus_fs(csr_regfile$mv_update_mstatus_fs),
			    .read_misa(csr_regfile$read_misa),
			    .read_mstatus(csr_regfile$read_mstatus),
			    .read_sstatus(csr_regfile$read_sstatus),
			    .read_ustatus(),
			    .read_satp(csr_regfile$read_satp),
			    .csr_trap_actions(csr_regfile$csr_trap_actions),
			    .RDY_csr_trap_actions(),
			    .csr_ret_actions(csr_regfile$csr_ret_actions),
			    .RDY_csr_ret_actions(),
			    .read_csr_minstret(csr_regfile$read_csr_minstret),
			    .read_csr_mcycle(csr_regfile$read_csr_mcycle),
			    .read_csr_mtime(),
			    .access_permitted_1(csr_regfile$access_permitted_1),
			    .access_permitted_2(csr_regfile$access_permitted_2),
			    .csr_counter_read_fault(),
			    .csr_mip_read(csr_regfile$csr_mip_read),
			    .interrupt_pending(csr_regfile$interrupt_pending),
			    .wfi_resume(csr_regfile$wfi_resume),
			    .nmi_pending(csr_regfile$nmi_pending),
			    .read_dpc(csr_regfile$read_dpc),
			    .RDY_read_dpc(),
			    .RDY_write_dpc(),
			    .dcsr_break_enters_debug(csr_regfile$dcsr_break_enters_debug),
			    .RDY_dcsr_break_enters_debug(),
			    .read_dcsr_step(csr_regfile$read_dcsr_step),
			    .RDY_read_dcsr_step(),
			    .RDY_debug());

  // submodule f_csr_reqs
  FIFO2 #(.width(32'd77), .guarded(32'd1)) f_csr_reqs(.RST(RST_N),
						      .CLK(CLK),
						      .D_IN(f_csr_reqs$D_IN),
						      .ENQ(f_csr_reqs$ENQ),
						      .DEQ(f_csr_reqs$DEQ),
						      .CLR(f_csr_reqs$CLR),
						      .D_OUT(f_csr_reqs$D_OUT),
						      .FULL_N(f_csr_reqs$FULL_N),
						      .EMPTY_N(f_csr_reqs$EMPTY_N));

  // submodule f_csr_rsps
  FIFO2 #(.width(32'd65), .guarded(32'd1)) f_csr_rsps(.RST(RST_N),
						      .CLK(CLK),
						      .D_IN(f_csr_rsps$D_IN),
						      .ENQ(f_csr_rsps$ENQ),
						      .DEQ(f_csr_rsps$DEQ),
						      .CLR(f_csr_rsps$CLR),
						      .D_OUT(f_csr_rsps$D_OUT),
						      .FULL_N(f_csr_rsps$FULL_N),
						      .EMPTY_N(f_csr_rsps$EMPTY_N));

  // submodule f_fpr_reqs
  FIFO2 #(.width(32'd70), .guarded(32'd1)) f_fpr_reqs(.RST(RST_N),
						      .CLK(CLK),
						      .D_IN(f_fpr_reqs$D_IN),
						      .ENQ(f_fpr_reqs$ENQ),
						      .DEQ(f_fpr_reqs$DEQ),
						      .CLR(f_fpr_reqs$CLR),
						      .D_OUT(f_fpr_reqs$D_OUT),
						      .FULL_N(f_fpr_reqs$FULL_N),
						      .EMPTY_N(f_fpr_reqs$EMPTY_N));

  // submodule f_fpr_rsps
  FIFO2 #(.width(32'd65), .guarded(32'd1)) f_fpr_rsps(.RST(RST_N),
						      .CLK(CLK),
						      .D_IN(f_fpr_rsps$D_IN),
						      .ENQ(f_fpr_rsps$ENQ),
						      .DEQ(f_fpr_rsps$DEQ),
						      .CLR(f_fpr_rsps$CLR),
						      .D_OUT(f_fpr_rsps$D_OUT),
						      .FULL_N(f_fpr_rsps$FULL_N),
						      .EMPTY_N(f_fpr_rsps$EMPTY_N));

  // submodule f_gpr_reqs
  FIFO2 #(.width(32'd70), .guarded(32'd1)) f_gpr_reqs(.RST(RST_N),
						      .CLK(CLK),
						      .D_IN(f_gpr_reqs$D_IN),
						      .ENQ(f_gpr_reqs$ENQ),
						      .DEQ(f_gpr_reqs$DEQ),
						      .CLR(f_gpr_reqs$CLR),
						      .D_OUT(f_gpr_reqs$D_OUT),
						      .FULL_N(f_gpr_reqs$FULL_N),
						      .EMPTY_N(f_gpr_reqs$EMPTY_N));

  // submodule f_gpr_rsps
  FIFO2 #(.width(32'd65), .guarded(32'd1)) f_gpr_rsps(.RST(RST_N),
						      .CLK(CLK),
						      .D_IN(f_gpr_rsps$D_IN),
						      .ENQ(f_gpr_rsps$ENQ),
						      .DEQ(f_gpr_rsps$DEQ),
						      .CLR(f_gpr_rsps$CLR),
						      .D_OUT(f_gpr_rsps$D_OUT),
						      .FULL_N(f_gpr_rsps$FULL_N),
						      .EMPTY_N(f_gpr_rsps$EMPTY_N));

  // submodule f_reset_reqs
  FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N),
						       .CLK(CLK),
						       .D_IN(f_reset_reqs$D_IN),
						       .ENQ(f_reset_reqs$ENQ),
						       .DEQ(f_reset_reqs$DEQ),
						       .CLR(f_reset_reqs$CLR),
						       .D_OUT(f_reset_reqs$D_OUT),
						       .FULL_N(f_reset_reqs$FULL_N),
						       .EMPTY_N(f_reset_reqs$EMPTY_N));

  // submodule f_reset_rsps
  FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N),
						       .CLK(CLK),
						       .D_IN(f_reset_rsps$D_IN),
						       .ENQ(f_reset_rsps$ENQ),
						       .DEQ(f_reset_rsps$DEQ),
						       .CLR(f_reset_rsps$CLR),
						       .D_OUT(f_reset_rsps$D_OUT),
						       .FULL_N(f_reset_rsps$FULL_N),
						       .EMPTY_N(f_reset_rsps$EMPTY_N));

  // submodule f_run_halt_reqs
  FIFO2 #(.width(32'd1), .guarded(32'd1)) f_run_halt_reqs(.RST(RST_N),
							  .CLK(CLK),
							  .D_IN(f_run_halt_reqs$D_IN),
							  .ENQ(f_run_halt_reqs$ENQ),
							  .DEQ(f_run_halt_reqs$DEQ),
							  .CLR(f_run_halt_reqs$CLR),
							  .D_OUT(f_run_halt_reqs$D_OUT),
							  .FULL_N(f_run_halt_reqs$FULL_N),
							  .EMPTY_N(f_run_halt_reqs$EMPTY_N));

  // submodule f_run_halt_rsps
  FIFO2 #(.width(32'd1), .guarded(32'd1)) f_run_halt_rsps(.RST(RST_N),
							  .CLK(CLK),
							  .D_IN(f_run_halt_rsps$D_IN),
							  .ENQ(f_run_halt_rsps$ENQ),
							  .DEQ(f_run_halt_rsps$DEQ),
							  .CLR(f_run_halt_rsps$CLR),
							  .D_OUT(f_run_halt_rsps$D_OUT),
							  .FULL_N(f_run_halt_rsps$FULL_N),
							  .EMPTY_N(f_run_halt_rsps$EMPTY_N));

  // submodule f_trace_data
  FIFO2 #(.width(32'd427), .guarded(32'd1)) f_trace_data(.RST(RST_N),
							 .CLK(CLK),
							 .D_IN(f_trace_data$D_IN),
							 .ENQ(f_trace_data$ENQ),
							 .DEQ(f_trace_data$DEQ),
							 .CLR(f_trace_data$CLR),
							 .D_OUT(f_trace_data$D_OUT),
							 .FULL_N(f_trace_data$FULL_N),
							 .EMPTY_N(f_trace_data$EMPTY_N));

  // submodule fpr_regfile
  mkFPR_RegFile fpr_regfile(.CLK(CLK),
			    .RST_N(RST_N),
			    .read_rs1_port2_rs1(fpr_regfile$read_rs1_port2_rs1),
			    .read_rs1_rs1(fpr_regfile$read_rs1_rs1),
			    .read_rs2_rs2(fpr_regfile$read_rs2_rs2),
			    .read_rs3_rs3(fpr_regfile$read_rs3_rs3),
			    .write_rd_rd(fpr_regfile$write_rd_rd),
			    .write_rd_rd_val(fpr_regfile$write_rd_rd_val),
			    .EN_server_reset_request_put(fpr_regfile$EN_server_reset_request_put),
			    .EN_server_reset_response_get(fpr_regfile$EN_server_reset_response_get),
			    .EN_write_rd(fpr_regfile$EN_write_rd),
			    .RDY_server_reset_request_put(fpr_regfile$RDY_server_reset_request_put),
			    .RDY_server_reset_response_get(fpr_regfile$RDY_server_reset_response_get),
			    .read_rs1(fpr_regfile$read_rs1),
			    .read_rs1_port2(fpr_regfile$read_rs1_port2),
			    .read_rs2(fpr_regfile$read_rs2),
			    .read_rs3(fpr_regfile$read_rs3));

  // submodule gpr_regfile
  mkGPR_RegFile gpr_regfile(.CLK(CLK),
			    .RST_N(RST_N),
			    .read_rs1_port2_rs1(gpr_regfile$read_rs1_port2_rs1),
			    .read_rs1_rs1(gpr_regfile$read_rs1_rs1),
			    .read_rs2_rs2(gpr_regfile$read_rs2_rs2),
			    .write_rd_rd(gpr_regfile$write_rd_rd),
			    .write_rd_rd_val(gpr_regfile$write_rd_rd_val),
			    .EN_server_reset_request_put(gpr_regfile$EN_server_reset_request_put),
			    .EN_server_reset_response_get(gpr_regfile$EN_server_reset_response_get),
			    .EN_write_rd(gpr_regfile$EN_write_rd),
			    .RDY_server_reset_request_put(gpr_regfile$RDY_server_reset_request_put),
			    .RDY_server_reset_response_get(gpr_regfile$RDY_server_reset_response_get),
			    .read_rs1(gpr_regfile$read_rs1),
			    .read_rs1_port2(gpr_regfile$read_rs1_port2),
			    .read_rs2(gpr_regfile$read_rs2));

  // submodule near_mem
  mkNear_Mem near_mem(.CLK(CLK),
		      .RST_N(RST_N),
		      .dma_server_araddr(near_mem$dma_server_araddr),
		      .dma_server_arburst(near_mem$dma_server_arburst),
		      .dma_server_arcache(near_mem$dma_server_arcache),
		      .dma_server_arid(near_mem$dma_server_arid),
		      .dma_server_arlen(near_mem$dma_server_arlen),
		      .dma_server_arlock(near_mem$dma_server_arlock),
		      .dma_server_arprot(near_mem$dma_server_arprot),
		      .dma_server_arqos(near_mem$dma_server_arqos),
		      .dma_server_arregion(near_mem$dma_server_arregion),
		      .dma_server_arsize(near_mem$dma_server_arsize),
		      .dma_server_arvalid(near_mem$dma_server_arvalid),
		      .dma_server_awaddr(near_mem$dma_server_awaddr),
		      .dma_server_awburst(near_mem$dma_server_awburst),
		      .dma_server_awcache(near_mem$dma_server_awcache),
		      .dma_server_awid(near_mem$dma_server_awid),
		      .dma_server_awlen(near_mem$dma_server_awlen),
		      .dma_server_awlock(near_mem$dma_server_awlock),
		      .dma_server_awprot(near_mem$dma_server_awprot),
		      .dma_server_awqos(near_mem$dma_server_awqos),
		      .dma_server_awregion(near_mem$dma_server_awregion),
		      .dma_server_awsize(near_mem$dma_server_awsize),
		      .dma_server_awvalid(near_mem$dma_server_awvalid),
		      .dma_server_bready(near_mem$dma_server_bready),
		      .dma_server_rready(near_mem$dma_server_rready),
		      .dma_server_wdata(near_mem$dma_server_wdata),
		      .dma_server_wlast(near_mem$dma_server_wlast),
		      .dma_server_wstrb(near_mem$dma_server_wstrb),
		      .dma_server_wvalid(near_mem$dma_server_wvalid),
		      .dmem_req_addr(near_mem$dmem_req_addr),
		      .dmem_req_amo_funct7(near_mem$dmem_req_amo_funct7),
		      .dmem_req_f3(near_mem$dmem_req_f3),
		      .dmem_req_mstatus_MXR(near_mem$dmem_req_mstatus_MXR),
		      .dmem_req_op(near_mem$dmem_req_op),
		      .dmem_req_priv(near_mem$dmem_req_priv),
		      .dmem_req_satp(near_mem$dmem_req_satp),
		      .dmem_req_sstatus_SUM(near_mem$dmem_req_sstatus_SUM),
		      .dmem_req_store_value(near_mem$dmem_req_store_value),
		      .imem_master_arready(near_mem$imem_master_arready),
		      .imem_master_awready(near_mem$imem_master_awready),
		      .imem_master_bid(near_mem$imem_master_bid),
		      .imem_master_bresp(near_mem$imem_master_bresp),
		      .imem_master_bvalid(near_mem$imem_master_bvalid),
		      .imem_master_rdata(near_mem$imem_master_rdata),
		      .imem_master_rid(near_mem$imem_master_rid),
		      .imem_master_rlast(near_mem$imem_master_rlast),
		      .imem_master_rresp(near_mem$imem_master_rresp),
		      .imem_master_rvalid(near_mem$imem_master_rvalid),
		      .imem_master_wready(near_mem$imem_master_wready),
		      .imem_req_addr(near_mem$imem_req_addr),
		      .imem_req_f3(near_mem$imem_req_f3),
		      .imem_req_mstatus_MXR(near_mem$imem_req_mstatus_MXR),
		      .imem_req_priv(near_mem$imem_req_priv),
		      .imem_req_satp(near_mem$imem_req_satp),
		      .imem_req_sstatus_SUM(near_mem$imem_req_sstatus_SUM),
		      .mem_master_arready(near_mem$mem_master_arready),
		      .mem_master_awready(near_mem$mem_master_awready),
		      .mem_master_bid(near_mem$mem_master_bid),
		      .mem_master_bresp(near_mem$mem_master_bresp),
		      .mem_master_bvalid(near_mem$mem_master_bvalid),
		      .mem_master_rdata(near_mem$mem_master_rdata),
		      .mem_master_rid(near_mem$mem_master_rid),
		      .mem_master_rlast(near_mem$mem_master_rlast),
		      .mem_master_rresp(near_mem$mem_master_rresp),
		      .mem_master_rvalid(near_mem$mem_master_rvalid),
		      .mem_master_wready(near_mem$mem_master_wready),
		      .server_fence_request_put(near_mem$server_fence_request_put),
		      .EN_server_reset_request_put(near_mem$EN_server_reset_request_put),
		      .EN_server_reset_response_get(near_mem$EN_server_reset_response_get),
		      .EN_imem_req(near_mem$EN_imem_req),
		      .EN_dmem_req(near_mem$EN_dmem_req),
		      .EN_server_fence_i_request_put(near_mem$EN_server_fence_i_request_put),
		      .EN_server_fence_i_response_get(near_mem$EN_server_fence_i_response_get),
		      .EN_server_fence_request_put(near_mem$EN_server_fence_request_put),
		      .EN_server_fence_response_get(near_mem$EN_server_fence_response_get),
		      .EN_sfence_vma_server_request_put(near_mem$EN_sfence_vma_server_request_put),
		      .EN_sfence_vma_server_response_get(near_mem$EN_sfence_vma_server_response_get),
		      .EN_ma_ddr4_ready(near_mem$EN_ma_ddr4_ready),
		      .RDY_server_reset_request_put(near_mem$RDY_server_reset_request_put),
		      .RDY_server_reset_response_get(near_mem$RDY_server_reset_response_get),
		      .imem_valid(near_mem$imem_valid),
		      .imem_is_i32_not_i16(near_mem$imem_is_i32_not_i16),
		      .imem_pc(near_mem$imem_pc),
		      .imem_instr(near_mem$imem_instr),
		      .imem_exc(near_mem$imem_exc),
		      .imem_exc_code(near_mem$imem_exc_code),
		      .imem_tval(),
		      .imem_master_awvalid(near_mem$imem_master_awvalid),
		      .imem_master_awid(near_mem$imem_master_awid),
		      .imem_master_awaddr(near_mem$imem_master_awaddr),
		      .imem_master_awlen(near_mem$imem_master_awlen),
		      .imem_master_awsize(near_mem$imem_master_awsize),
		      .imem_master_awburst(near_mem$imem_master_awburst),
		      .imem_master_awlock(near_mem$imem_master_awlock),
		      .imem_master_awcache(near_mem$imem_master_awcache),
		      .imem_master_awprot(near_mem$imem_master_awprot),
		      .imem_master_awqos(near_mem$imem_master_awqos),
		      .imem_master_awregion(near_mem$imem_master_awregion),
		      .imem_master_wvalid(near_mem$imem_master_wvalid),
		      .imem_master_wdata(near_mem$imem_master_wdata),
		      .imem_master_wstrb(near_mem$imem_master_wstrb),
		      .imem_master_wlast(near_mem$imem_master_wlast),
		      .imem_master_bready(near_mem$imem_master_bready),
		      .imem_master_arvalid(near_mem$imem_master_arvalid),
		      .imem_master_arid(near_mem$imem_master_arid),
		      .imem_master_araddr(near_mem$imem_master_araddr),
		      .imem_master_arlen(near_mem$imem_master_arlen),
		      .imem_master_arsize(near_mem$imem_master_arsize),
		      .imem_master_arburst(near_mem$imem_master_arburst),
		      .imem_master_arlock(near_mem$imem_master_arlock),
		      .imem_master_arcache(near_mem$imem_master_arcache),
		      .imem_master_arprot(near_mem$imem_master_arprot),
		      .imem_master_arqos(near_mem$imem_master_arqos),
		      .imem_master_arregion(near_mem$imem_master_arregion),
		      .imem_master_rready(near_mem$imem_master_rready),
		      .dmem_valid(near_mem$dmem_valid),
		      .dmem_word64(near_mem$dmem_word64),
		      .dmem_st_amo_val(),
		      .dmem_exc(near_mem$dmem_exc),
		      .dmem_exc_code(near_mem$dmem_exc_code),
		      .mem_master_awvalid(near_mem$mem_master_awvalid),
		      .mem_master_awid(near_mem$mem_master_awid),
		      .mem_master_awaddr(near_mem$mem_master_awaddr),
		      .mem_master_awlen(near_mem$mem_master_awlen),
		      .mem_master_awsize(near_mem$mem_master_awsize),
		      .mem_master_awburst(near_mem$mem_master_awburst),
		      .mem_master_awlock(near_mem$mem_master_awlock),
		      .mem_master_awcache(near_mem$mem_master_awcache),
		      .mem_master_awprot(near_mem$mem_master_awprot),
		      .mem_master_awqos(near_mem$mem_master_awqos),
		      .mem_master_awregion(near_mem$mem_master_awregion),
		      .mem_master_wvalid(near_mem$mem_master_wvalid),
		      .mem_master_wdata(near_mem$mem_master_wdata),
		      .mem_master_wstrb(near_mem$mem_master_wstrb),
		      .mem_master_wlast(near_mem$mem_master_wlast),
		      .mem_master_bready(near_mem$mem_master_bready),
		      .mem_master_arvalid(near_mem$mem_master_arvalid),
		      .mem_master_arid(near_mem$mem_master_arid),
		      .mem_master_araddr(near_mem$mem_master_araddr),
		      .mem_master_arlen(near_mem$mem_master_arlen),
		      .mem_master_arsize(near_mem$mem_master_arsize),
		      .mem_master_arburst(near_mem$mem_master_arburst),
		      .mem_master_arlock(near_mem$mem_master_arlock),
		      .mem_master_arcache(near_mem$mem_master_arcache),
		      .mem_master_arprot(near_mem$mem_master_arprot),
		      .mem_master_arqos(near_mem$mem_master_arqos),
		      .mem_master_arregion(near_mem$mem_master_arregion),
		      .mem_master_rready(near_mem$mem_master_rready),
		      .RDY_server_fence_i_request_put(),
		      .RDY_server_fence_i_response_get(),
		      .RDY_server_fence_request_put(),
		      .RDY_server_fence_response_get(),
		      .RDY_sfence_vma_server_request_put(),
		      .RDY_sfence_vma_server_response_get(),
		      .dma_server_awready(near_mem$dma_server_awready),
		      .dma_server_wready(near_mem$dma_server_wready),
		      .dma_server_bvalid(near_mem$dma_server_bvalid),
		      .dma_server_bid(near_mem$dma_server_bid),
		      .dma_server_bresp(near_mem$dma_server_bresp),
		      .dma_server_arready(near_mem$dma_server_arready),
		      .dma_server_rvalid(near_mem$dma_server_rvalid),
		      .dma_server_rid(near_mem$dma_server_rid),
		      .dma_server_rdata(near_mem$dma_server_rdata),
		      .dma_server_rresp(near_mem$dma_server_rresp),
		      .dma_server_rlast(near_mem$dma_server_rlast),
		      .RDY_ma_ddr4_ready(),
		      .mv_status(near_mem$mv_status));

  // submodule soc_map
  mkSoC_Map soc_map(.CLK(CLK),
		    .RST_N(RST_N),
		    .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
		    .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
		    .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
		    .m_plic_addr_base(),
		    .m_plic_addr_size(),
		    .m_plic_addr_lim(),
		    .m_near_mem_io_addr_base(),
		    .m_near_mem_io_addr_size(),
		    .m_near_mem_io_addr_lim(),
		    .m_flash_mem_addr_base(),
		    .m_flash_mem_addr_size(),
		    .m_flash_mem_addr_lim(),
		    .m_ethernet_0_addr_base(),
		    .m_ethernet_0_addr_size(),
		    .m_ethernet_0_addr_lim(),
		    .m_dma_0_addr_base(),
		    .m_dma_0_addr_size(),
		    .m_dma_0_addr_lim(),
		    .m_uart16550_0_addr_base(),
		    .m_uart16550_0_addr_size(),
		    .m_uart16550_0_addr_lim(),
		    .m_gpio_0_addr_base(),
		    .m_gpio_0_addr_size(),
		    .m_gpio_0_addr_lim(),
		    .m_boot_rom_addr_base(),
		    .m_boot_rom_addr_size(),
		    .m_boot_rom_addr_lim(),
		    .m_ddr4_0_uncached_addr_base(),
		    .m_ddr4_0_uncached_addr_size(),
		    .m_ddr4_0_uncached_addr_lim(),
		    .m_ddr4_0_cached_addr_base(),
		    .m_ddr4_0_cached_addr_size(),
		    .m_ddr4_0_cached_addr_lim(),
		    .m_is_mem_addr(),
		    .m_is_IO_addr(),
		    .m_is_near_mem_IO_addr(),
		    .m_pc_reset_value(soc_map$m_pc_reset_value),
		    .m_mtvec_reset_value(),
		    .m_nmivec_reset_value());

  // submodule stage1_f_reset_reqs
  FIFO20 #(.guarded(32'd1)) stage1_f_reset_reqs(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stage1_f_reset_reqs$ENQ),
						.DEQ(stage1_f_reset_reqs$DEQ),
						.CLR(stage1_f_reset_reqs$CLR),
						.FULL_N(stage1_f_reset_reqs$FULL_N),
						.EMPTY_N(stage1_f_reset_reqs$EMPTY_N));

  // submodule stage1_f_reset_rsps
  FIFO20 #(.guarded(32'd1)) stage1_f_reset_rsps(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stage1_f_reset_rsps$ENQ),
						.DEQ(stage1_f_reset_rsps$DEQ),
						.CLR(stage1_f_reset_rsps$CLR),
						.FULL_N(stage1_f_reset_rsps$FULL_N),
						.EMPTY_N(stage1_f_reset_rsps$EMPTY_N));

  // submodule stage2_f_reset_reqs
  FIFO20 #(.guarded(32'd1)) stage2_f_reset_reqs(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stage2_f_reset_reqs$ENQ),
						.DEQ(stage2_f_reset_reqs$DEQ),
						.CLR(stage2_f_reset_reqs$CLR),
						.FULL_N(stage2_f_reset_reqs$FULL_N),
						.EMPTY_N(stage2_f_reset_reqs$EMPTY_N));

  // submodule stage2_f_reset_rsps
  FIFO20 #(.guarded(32'd1)) stage2_f_reset_rsps(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stage2_f_reset_rsps$ENQ),
						.DEQ(stage2_f_reset_rsps$DEQ),
						.CLR(stage2_f_reset_rsps$CLR),
						.FULL_N(stage2_f_reset_rsps$FULL_N),
						.EMPTY_N(stage2_f_reset_rsps$EMPTY_N));

  // submodule stage2_fbox
  mkFBox_Top stage2_fbox(.verbosity(4'd0),
			 .CLK(CLK),
			 .RST_N(RST_N),
			 .req_f7(stage2_fbox$req_f7),
			 .req_opcode(stage2_fbox$req_opcode),
			 .req_rm(stage2_fbox$req_rm),
			 .req_rs2(stage2_fbox$req_rs2),
			 .req_v1(stage2_fbox$req_v1),
			 .req_v2(stage2_fbox$req_v2),
			 .req_v3(stage2_fbox$req_v3),
			 .EN_server_reset_request_put(stage2_fbox$EN_server_reset_request_put),
			 .EN_server_reset_response_get(stage2_fbox$EN_server_reset_response_get),
			 .EN_req(stage2_fbox$EN_req),
			 .RDY_server_reset_request_put(stage2_fbox$RDY_server_reset_request_put),
			 .RDY_server_reset_response_get(stage2_fbox$RDY_server_reset_response_get),
			 .valid(stage2_fbox$valid),
			 .word_fst(stage2_fbox$word_fst),
			 .word_snd(stage2_fbox$word_snd));

  // submodule stage2_mbox
  mkRISCV_MBox stage2_mbox(.CLK(CLK),
			   .RST_N(RST_N),
			   .req_f3(stage2_mbox$req_f3),
			   .req_is_OP_not_OP_32(stage2_mbox$req_is_OP_not_OP_32),
			   .req_v1(stage2_mbox$req_v1),
			   .req_v2(stage2_mbox$req_v2),
			   .set_verbosity_verbosity(stage2_mbox$set_verbosity_verbosity),
			   .EN_set_verbosity(stage2_mbox$EN_set_verbosity),
			   .EN_req_reset(stage2_mbox$EN_req_reset),
			   .EN_rsp_reset(stage2_mbox$EN_rsp_reset),
			   .EN_req(stage2_mbox$EN_req),
			   .RDY_set_verbosity(),
			   .RDY_req_reset(),
			   .RDY_rsp_reset(),
			   .valid(stage2_mbox$valid),
			   .word(stage2_mbox$word));

  // submodule stage3_f_reset_reqs
  FIFO20 #(.guarded(32'd1)) stage3_f_reset_reqs(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stage3_f_reset_reqs$ENQ),
						.DEQ(stage3_f_reset_reqs$DEQ),
						.CLR(stage3_f_reset_reqs$CLR),
						.FULL_N(stage3_f_reset_reqs$FULL_N),
						.EMPTY_N(stage3_f_reset_reqs$EMPTY_N));

  // submodule stage3_f_reset_rsps
  FIFO20 #(.guarded(32'd1)) stage3_f_reset_rsps(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stage3_f_reset_rsps$ENQ),
						.DEQ(stage3_f_reset_rsps$DEQ),
						.CLR(stage3_f_reset_rsps$CLR),
						.FULL_N(stage3_f_reset_rsps$FULL_N),
						.EMPTY_N(stage3_f_reset_rsps$EMPTY_N));

  // submodule stageD_f_reset_reqs
  FIFO20 #(.guarded(32'd1)) stageD_f_reset_reqs(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stageD_f_reset_reqs$ENQ),
						.DEQ(stageD_f_reset_reqs$DEQ),
						.CLR(stageD_f_reset_reqs$CLR),
						.FULL_N(stageD_f_reset_reqs$FULL_N),
						.EMPTY_N(stageD_f_reset_reqs$EMPTY_N));

  // submodule stageD_f_reset_rsps
  FIFO20 #(.guarded(32'd1)) stageD_f_reset_rsps(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stageD_f_reset_rsps$ENQ),
						.DEQ(stageD_f_reset_rsps$DEQ),
						.CLR(stageD_f_reset_rsps$CLR),
						.FULL_N(stageD_f_reset_rsps$FULL_N),
						.EMPTY_N(stageD_f_reset_rsps$EMPTY_N));

  // submodule stageF_branch_predictor
  mkBranch_Predictor stageF_branch_predictor(.CLK(CLK),
					     .RST_N(RST_N),
					     .bp_train_cf_info(stageF_branch_predictor$bp_train_cf_info),
					     .bp_train_instr(stageF_branch_predictor$bp_train_instr),
					     .bp_train_is_i32_not_i16(stageF_branch_predictor$bp_train_is_i32_not_i16),
					     .bp_train_pc(stageF_branch_predictor$bp_train_pc),
					     .predict_req_pc(stageF_branch_predictor$predict_req_pc),
					     .predict_rsp_instr(stageF_branch_predictor$predict_rsp_instr),
					     .predict_rsp_is_i32_not_i16(stageF_branch_predictor$predict_rsp_is_i32_not_i16),
					     .EN_reset(stageF_branch_predictor$EN_reset),
					     .EN_predict_req(stageF_branch_predictor$EN_predict_req),
					     .EN_bp_train(stageF_branch_predictor$EN_bp_train),
					     .RDY_reset(),
					     .RDY_predict_req(stageF_branch_predictor$RDY_predict_req),
					     .predict_rsp(stageF_branch_predictor$predict_rsp),
					     .RDY_bp_train());

  // submodule stageF_f_reset_reqs
  FIFO20 #(.guarded(32'd1)) stageF_f_reset_reqs(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stageF_f_reset_reqs$ENQ),
						.DEQ(stageF_f_reset_reqs$DEQ),
						.CLR(stageF_f_reset_reqs$CLR),
						.FULL_N(stageF_f_reset_reqs$FULL_N),
						.EMPTY_N(stageF_f_reset_reqs$EMPTY_N));

  // submodule stageF_f_reset_rsps
  FIFO20 #(.guarded(32'd1)) stageF_f_reset_rsps(.RST(RST_N),
						.CLK(CLK),
						.ENQ(stageF_f_reset_rsps$ENQ),
						.DEQ(stageF_f_reset_rsps$DEQ),
						.CLR(stageF_f_reset_rsps$CLR),
						.FULL_N(stageF_f_reset_rsps$FULL_N),
						.EMPTY_N(stageF_f_reset_rsps$EMPTY_N));

  // rule RL_rl_show_pipe
  assign CAN_FIRE_RL_rl_show_pipe =
	     NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53 &&
	     rg_state != 4'd0 &&
	     rg_state != 4'd1 &&
	     rg_state != 4'd2 &&
	     rg_state != 4'd3 &&
	     rg_state != 4'd13 ;
  assign WILL_FIRE_RL_rl_show_pipe = CAN_FIRE_RL_rl_show_pipe ;

  // rule RL_rl_stage1_mip_cmd
  assign CAN_FIRE_RL_rl_stage1_mip_cmd =
	     f_trace_data$FULL_N && rg_state == 4'd4 &&
	     stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d2085 &&
	     IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d2088 &&
	     IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 ==
	     2'd0 &&
	     !stage3_rg_full &&
	     !csr_regfile_csr_mip_read__092_EQ_rg_prev_mip_093___d2094 ;
  assign WILL_FIRE_RL_rl_stage1_mip_cmd = CAN_FIRE_RL_rl_stage1_mip_cmd ;

  // rule RL_rl_debug_run_redundant
  assign CAN_FIRE_RL_rl_debug_run_redundant =
	     f_run_halt_rsps$FULL_N && f_run_halt_reqs$EMPTY_N &&
	     f_run_halt_reqs$D_OUT &&
	     rg_state != 4'd0 &&
	     rg_state != 4'd1 &&
	     rg_state != 4'd2 &&
	     rg_state != 4'd3 ;
  assign WILL_FIRE_RL_rl_debug_run_redundant =
	     CAN_FIRE_RL_rl_debug_run_redundant &&
	     !WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode ;

  // rule RL_rl_debug_halt
  assign CAN_FIRE_RL_rl_debug_halt =
	     f_run_halt_reqs$EMPTY_N && !f_run_halt_reqs$D_OUT &&
	     rg_state != 4'd0 &&
	     rg_state != 4'd1 &&
	     rg_state != 4'd2 &&
	     rg_state != 4'd3 ;
  assign WILL_FIRE_RL_rl_debug_halt =
	     CAN_FIRE_RL_rl_debug_halt && !WILL_FIRE_RL_rl_stage1_stop &&
	     !WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode &&
	     !WILL_FIRE_RL_rl_WFI_resume &&
	     !WILL_FIRE_RL_rl_stage1_WFI &&
	     !WILL_FIRE_RL_rl_stage1_SFENCE_VMA &&
	     !WILL_FIRE_RL_rl_stage1_FENCE &&
	     !WILL_FIRE_RL_rl_stage1_FENCE_I &&
	     !WILL_FIRE_RL_rl_stage1_xRET &&
	     !WILL_FIRE_RL_rl_stage1_CSRR_S_or_C &&
	     !WILL_FIRE_RL_rl_stage1_CSRR_W &&
	     !WILL_FIRE_RL_rl_stage1_trap ;

  // rule RL_rl_debug_halt_redundant
  assign CAN_FIRE_RL_rl_debug_halt_redundant =
	     f_run_halt_rsps$FULL_N && f_run_halt_reqs$EMPTY_N &&
	     !f_run_halt_reqs$D_OUT &&
	     (rg_state == 4'd0 || rg_state == 4'd1 || rg_state == 4'd2 ||
	      rg_state == 4'd3) ;
  assign WILL_FIRE_RL_rl_debug_halt_redundant =
	     CAN_FIRE_RL_rl_debug_halt_redundant &&
	     !WILL_FIRE_RL_rl_BREAK_cache_flush_finish ;

  // rule RL_rl_debug_read_gpr
  assign CAN_FIRE_RL_rl_debug_read_gpr =
	     f_gpr_reqs$EMPTY_N && f_gpr_rsps$FULL_N && rg_state == 4'd3 &&
	     !f_gpr_reqs$D_OUT[69] ;
  assign WILL_FIRE_RL_rl_debug_read_gpr = CAN_FIRE_RL_rl_debug_read_gpr ;

  // rule RL_rl_debug_write_gpr
  assign CAN_FIRE_RL_rl_debug_write_gpr =
	     f_gpr_reqs$EMPTY_N && f_gpr_rsps$FULL_N && rg_state == 4'd3 &&
	     f_gpr_reqs$D_OUT[69] ;
  assign WILL_FIRE_RL_rl_debug_write_gpr = CAN_FIRE_RL_rl_debug_write_gpr ;

  // rule RL_rl_debug_gpr_access_busy
  assign CAN_FIRE_RL_rl_debug_gpr_access_busy =
	     f_gpr_reqs$EMPTY_N && f_gpr_rsps$FULL_N && rg_state != 4'd3 ;
  assign WILL_FIRE_RL_rl_debug_gpr_access_busy =
	     CAN_FIRE_RL_rl_debug_gpr_access_busy ;

  // rule RL_rl_debug_read_fpr
  assign CAN_FIRE_RL_rl_debug_read_fpr =
	     f_fpr_reqs$EMPTY_N && f_fpr_rsps$FULL_N && rg_state == 4'd3 &&
	     !f_fpr_reqs$D_OUT[69] ;
  assign WILL_FIRE_RL_rl_debug_read_fpr = CAN_FIRE_RL_rl_debug_read_fpr ;

  // rule RL_rl_debug_write_fpr
  assign CAN_FIRE_RL_rl_debug_write_fpr =
	     f_fpr_reqs$EMPTY_N && f_fpr_rsps$FULL_N && rg_state == 4'd3 &&
	     f_fpr_reqs$D_OUT[69] ;
  assign WILL_FIRE_RL_rl_debug_write_fpr = CAN_FIRE_RL_rl_debug_write_fpr ;

  // rule RL_rl_debug_fpr_access_busy
  assign CAN_FIRE_RL_rl_debug_fpr_access_busy =
	     f_fpr_reqs$EMPTY_N && f_fpr_rsps$FULL_N && rg_state != 4'd3 ;
  assign WILL_FIRE_RL_rl_debug_fpr_access_busy =
	     CAN_FIRE_RL_rl_debug_fpr_access_busy ;

  // rule RL_rl_debug_read_csr
  assign CAN_FIRE_RL_rl_debug_read_csr =
	     f_csr_reqs$EMPTY_N && f_csr_rsps$FULL_N && rg_state == 4'd3 &&
	     !f_csr_reqs$D_OUT[76] ;
  assign WILL_FIRE_RL_rl_debug_read_csr = CAN_FIRE_RL_rl_debug_read_csr ;

  // rule RL_rl_debug_run
  assign CAN_FIRE_RL_rl_debug_run =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2047 &&
	     stageF_branch_predictor$RDY_predict_req &&
	     f_run_halt_rsps$FULL_N &&
	     f_run_halt_reqs$EMPTY_N &&
	     f_run_halt_reqs$D_OUT &&
	     rg_state == 4'd3 ;
  assign WILL_FIRE_RL_rl_debug_run =
	     CAN_FIRE_RL_rl_debug_run &&
	     !WILL_FIRE_RL_rl_reset_from_Debug_Module ;

  // rule RL_rl_debug_write_csr
  assign CAN_FIRE_RL_rl_debug_write_csr =
	     f_csr_reqs$EMPTY_N && f_csr_rsps$FULL_N && rg_state == 4'd3 &&
	     f_csr_reqs$D_OUT[76] ;
  assign WILL_FIRE_RL_rl_debug_write_csr =
	     CAN_FIRE_RL_rl_debug_write_csr && !WILL_FIRE_RL_rl_debug_run ;

  // rule RL_rl_debug_csr_access_busy
  assign CAN_FIRE_RL_rl_debug_csr_access_busy =
	     f_csr_reqs$EMPTY_N && f_csr_rsps$FULL_N && rg_state != 4'd3 ;
  assign WILL_FIRE_RL_rl_debug_csr_access_busy =
	     CAN_FIRE_RL_rl_debug_csr_access_busy ;

  // rule RL_rl_stage2_nonpipe
  assign CAN_FIRE_RL_rl_stage2_nonpipe =
	     rg_state == 4'd4 && !stage3_rg_full &&
	     IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 ==
	     2'd3 ;
  assign WILL_FIRE_RL_rl_stage2_nonpipe = CAN_FIRE_RL_rl_stage2_nonpipe ;

  // rule RL_rl_stage1_trap
  assign CAN_FIRE_RL_rl_stage1_trap =
	     rg_state_4_EQ_4_081_AND_NOT_stage1_rg_stage_in_ETC___d2609 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 ==
	     4'd12 &&
	     (x_out_trap_info_exc_code__h14560 != 4'd3 ||
	      !csr_regfile$dcsr_break_enters_debug) &&
	     (!stageF_rg_full ||
	      near_mem$imem_valid &&
	      NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911) ;
  assign WILL_FIRE_RL_rl_stage1_trap = CAN_FIRE_RL_rl_stage1_trap ;

  // rule RL_rl_trap
  assign CAN_FIRE_RL_rl_trap =
	     f_trace_data$FULL_N &&
	     rg_state_4_EQ_5_623_AND_NOT_stageF_rg_full_888_ETC___d2624 ;
  assign WILL_FIRE_RL_rl_trap = CAN_FIRE_RL_rl_trap ;

  // rule RL_rl_stage1_CSRR_W
  assign CAN_FIRE_RL_rl_stage1_CSRR_W =
	     rg_state_4_EQ_4_081_AND_NOT_stage1_rg_stage_in_ETC___d2609 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 ==
	     4'd3 ;
  assign WILL_FIRE_RL_rl_stage1_CSRR_W = CAN_FIRE_RL_rl_stage1_CSRR_W ;

  // rule RL_rl_stage1_CSRR_W_2
  assign CAN_FIRE_RL_rl_stage1_CSRR_W_2 = MUX_rg_state$write_1__SEL_3 ;
  assign WILL_FIRE_RL_rl_stage1_CSRR_W_2 = MUX_rg_state$write_1__SEL_3 ;

  // rule RL_rl_stage1_CSRR_S_or_C
  assign CAN_FIRE_RL_rl_stage1_CSRR_S_or_C =
	     rg_state_4_EQ_4_081_AND_NOT_stage1_rg_stage_in_ETC___d2609 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 ==
	     4'd4 ;
  assign WILL_FIRE_RL_rl_stage1_CSRR_S_or_C =
	     CAN_FIRE_RL_rl_stage1_CSRR_S_or_C ;

  // rule RL_rl_stage1_CSRR_S_or_C_2
  assign CAN_FIRE_RL_rl_stage1_CSRR_S_or_C_2 = MUX_rg_state$write_1__SEL_4 ;
  assign WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 = MUX_rg_state$write_1__SEL_4 ;

  // rule RL_rl_stage1_restart_after_csrrx
  assign CAN_FIRE_RL_rl_stage1_restart_after_csrrx =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2047 &&
	     stageF_branch_predictor$RDY_predict_req &&
	     rg_state_4_EQ_9_733_AND_NOT_stageF_rg_full_888_ETC___d2734 ;
  assign WILL_FIRE_RL_rl_stage1_restart_after_csrrx =
	     CAN_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // rule RL_rl_stage1_xRET
  assign CAN_FIRE_RL_rl_stage1_xRET =
	     f_trace_data$FULL_N &&
	     rg_state_4_EQ_4_081_AND_NOT_stage1_rg_stage_in_ETC___d2751 ;
  assign WILL_FIRE_RL_rl_stage1_xRET = CAN_FIRE_RL_rl_stage1_xRET ;

  // rule RL_rl_finish_FENCE_I
  assign CAN_FIRE_RL_rl_finish_FENCE_I =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2047 &&
	     stageF_branch_predictor$RDY_predict_req &&
	     f_trace_data$FULL_N &&
	     rg_state == 4'd10 ;
  assign WILL_FIRE_RL_rl_finish_FENCE_I = CAN_FIRE_RL_rl_finish_FENCE_I ;

  // rule RL_rl_stage1_FENCE_I
  assign CAN_FIRE_RL_rl_stage1_FENCE_I =
	     rg_state_4_EQ_4_081_AND_NOT_stage1_rg_stage_in_ETC___d2609 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 ==
	     4'd6 &&
	     (!stageF_rg_full ||
	      near_mem$imem_valid &&
	      NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911) ;
  assign WILL_FIRE_RL_rl_stage1_FENCE_I = CAN_FIRE_RL_rl_stage1_FENCE_I ;

  // rule RL_rl_stage1_FENCE
  assign CAN_FIRE_RL_rl_stage1_FENCE =
	     rg_state_4_EQ_4_081_AND_NOT_stage1_rg_stage_in_ETC___d2609 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 ==
	     4'd5 &&
	     (!stageF_rg_full ||
	      near_mem$imem_valid &&
	      NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911) ;
  assign WILL_FIRE_RL_rl_stage1_FENCE = CAN_FIRE_RL_rl_stage1_FENCE ;

  // rule RL_rl_finish_FENCE
  assign CAN_FIRE_RL_rl_finish_FENCE =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2047 &&
	     stageF_branch_predictor$RDY_predict_req &&
	     f_trace_data$FULL_N &&
	     rg_state == 4'd11 ;
  assign WILL_FIRE_RL_rl_finish_FENCE = CAN_FIRE_RL_rl_finish_FENCE ;

  // rule RL_rl_stage1_SFENCE_VMA
  assign CAN_FIRE_RL_rl_stage1_SFENCE_VMA =
	     rg_state_4_EQ_4_081_AND_NOT_stage1_rg_stage_in_ETC___d2609 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 ==
	     4'd7 &&
	     (!stageF_rg_full ||
	      near_mem$imem_valid &&
	      NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911) ;
  assign WILL_FIRE_RL_rl_stage1_SFENCE_VMA =
	     CAN_FIRE_RL_rl_stage1_SFENCE_VMA ;

  // rule RL_rl_finish_SFENCE_VMA
  assign CAN_FIRE_RL_rl_finish_SFENCE_VMA =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2047 &&
	     stageF_branch_predictor$RDY_predict_req &&
	     f_trace_data$FULL_N &&
	     rg_state == 4'd12 ;
  assign WILL_FIRE_RL_rl_finish_SFENCE_VMA =
	     CAN_FIRE_RL_rl_finish_SFENCE_VMA ;

  // rule RL_rl_stage1_WFI
  assign CAN_FIRE_RL_rl_stage1_WFI =
	     f_trace_data$FULL_N &&
	     rg_state_4_EQ_4_081_AND_NOT_stage1_rg_stage_in_ETC___d2781 ;
  assign WILL_FIRE_RL_rl_stage1_WFI = CAN_FIRE_RL_rl_stage1_WFI ;

  // rule RL_rl_WFI_resume
  assign CAN_FIRE_RL_rl_WFI_resume =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2047 &&
	     stageF_branch_predictor$RDY_predict_req &&
	     rg_state_4_EQ_13_7_AND_csr_regfile_wfi_resume__ETC___d2786 ;
  assign WILL_FIRE_RL_rl_WFI_resume = CAN_FIRE_RL_rl_WFI_resume ;

  // rule RL_rl_reset_from_WFI
  assign CAN_FIRE_RL_rl_reset_from_WFI =
	     rg_state == 4'd13 && f_reset_reqs$EMPTY_N ;
  assign WILL_FIRE_RL_rl_reset_from_WFI =
	     CAN_FIRE_RL_rl_reset_from_WFI && !WILL_FIRE_RL_rl_WFI_resume ;

  // rule RL_rl_trap_fetch
  assign CAN_FIRE_RL_rl_trap_fetch =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2047 &&
	     stageF_branch_predictor$RDY_predict_req &&
	     rg_state_4_EQ_6_790_AND_NOT_stageF_rg_full_888_ETC___d2791 ;
  assign WILL_FIRE_RL_rl_trap_fetch = CAN_FIRE_RL_rl_trap_fetch ;

  // rule RL_rl_trap_BREAK_to_Debug_Mode
  assign CAN_FIRE_RL_rl_trap_BREAK_to_Debug_Mode =
	     f_run_halt_rsps$FULL_N &&
	     rg_state_4_EQ_4_081_AND_NOT_stage1_rg_stage_in_ETC___d2794 &&
	     x_out_trap_info_exc_code__h14560 == 4'd3 &&
	     csr_regfile$dcsr_break_enters_debug ;
  assign WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode =
	     CAN_FIRE_RL_rl_trap_BREAK_to_Debug_Mode ;

  // rule RL_rl_reset_from_Debug_Module
  assign CAN_FIRE_RL_rl_reset_from_Debug_Module =
	     f_reset_reqs$EMPTY_N && rg_state != 4'd0 ;
  assign WILL_FIRE_RL_rl_reset_from_Debug_Module =
	     CAN_FIRE_RL_rl_reset_from_Debug_Module &&
	     !WILL_FIRE_RL_rl_BREAK_cache_flush_finish &&
	     !WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode &&
	     !WILL_FIRE_RL_rl_trap_fetch &&
	     !WILL_FIRE_RL_rl_reset_from_WFI &&
	     !WILL_FIRE_RL_rl_WFI_resume &&
	     !WILL_FIRE_RL_rl_stage1_WFI &&
	     !WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
	     !WILL_FIRE_RL_rl_stage1_SFENCE_VMA &&
	     !WILL_FIRE_RL_rl_finish_FENCE &&
	     !WILL_FIRE_RL_rl_stage1_FENCE &&
	     !WILL_FIRE_RL_rl_finish_FENCE_I &&
	     !WILL_FIRE_RL_rl_stage1_FENCE_I &&
	     !WILL_FIRE_RL_rl_stage1_xRET &&
	     !WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
	     !WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	     !WILL_FIRE_RL_rl_stage1_CSRR_S_or_C &&
	     !WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	     !WILL_FIRE_RL_rl_stage1_CSRR_W &&
	     !WILL_FIRE_RL_rl_trap &&
	     !WILL_FIRE_RL_rl_stage1_trap &&
	     !WILL_FIRE_RL_rl_stage2_nonpipe ;

  // rule RL_rl_BREAK_cache_flush_finish
  assign CAN_FIRE_RL_rl_BREAK_cache_flush_finish =
	     f_run_halt_rsps$FULL_N && rg_state == 4'd2 ;
  assign WILL_FIRE_RL_rl_BREAK_cache_flush_finish =
	     CAN_FIRE_RL_rl_BREAK_cache_flush_finish ;

  // rule RL_rl_stage1_interrupt
  assign CAN_FIRE_RL_rl_stage1_interrupt =
	     csr_regfile_interrupt_pending_rg_cur_priv_1_11_ETC___d2807 &&
	     (!stageF_rg_full ||
	      near_mem$imem_valid &&
	      NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911) ;
  assign WILL_FIRE_RL_rl_stage1_interrupt =
	     CAN_FIRE_RL_rl_stage1_interrupt &&
	     !WILL_FIRE_RL_rl_reset_from_Debug_Module ;

  // rule RL_rl_stage1_stop
  assign CAN_FIRE_RL_rl_stage1_stop =
	     rg_state == 4'd4 &&
	     NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2820 &&
	     (!stageF_rg_full ||
	      near_mem$imem_valid &&
	      NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911) ;
  assign WILL_FIRE_RL_rl_stage1_stop =
	     CAN_FIRE_RL_rl_stage1_stop &&
	     !WILL_FIRE_RL_rl_reset_from_Debug_Module ;

  // rule RL_imem_rl_assert_fail
  assign CAN_FIRE_RL_imem_rl_assert_fail = !near_mem$imem_is_i32_not_i16 ;
  assign WILL_FIRE_RL_imem_rl_assert_fail = CAN_FIRE_RL_imem_rl_assert_fail ;

  // rule RL_rl_reset_complete
  assign CAN_FIRE_RL_rl_reset_complete =
	     gpr_regfile$RDY_server_reset_response_get &&
	     fpr_regfile$RDY_server_reset_response_get &&
	     near_mem$RDY_server_reset_response_get &&
	     csr_regfile_RDY_server_reset_response_get__036_ETC___d2057 &&
	     rg_state == 4'd1 ;
  assign WILL_FIRE_RL_rl_reset_complete = MUX_rg_state$write_1__SEL_2 ;

  // rule RL_rl_pipe
  assign CAN_FIRE_RL_rl_pipe =
	     (!stage3_rg_full || f_trace_data$FULL_N) &&
	     (IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2135 ||
	      stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2148) &&
	     rg_state_4_EQ_4_081_AND_stage3_rg_full_01_OR_N_ETC___d2160 &&
	     (NOT_stage1_rg_full_16_27_OR_stage1_rg_stage_in_ETC___d2167 ||
	      NOT_stage1_rg_full_16_27_OR_stage1_rg_stage_in_ETC___d2168 ||
	      IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d2170 ||
	      IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 !=
	      2'd0 ||
	      stage3_rg_full) ;
  assign WILL_FIRE_RL_rl_pipe =
	     CAN_FIRE_RL_rl_pipe && !WILL_FIRE_RL_imem_rl_fetch_next_32b &&
	     !WILL_FIRE_RL_rl_debug_halt &&
	     !WILL_FIRE_RL_rl_reset_from_Debug_Module &&
	     !WILL_FIRE_RL_rl_stage1_mip_cmd ;

  // rule RL_rl_reset_start
  assign CAN_FIRE_RL_rl_reset_start =
	     gpr_regfile$RDY_server_reset_request_put &&
	     fpr_regfile_RDY_server_reset_request_put__010__ETC___d2028 &&
	     rg_state == 4'd0 ;
  assign WILL_FIRE_RL_rl_reset_start = CAN_FIRE_RL_rl_reset_start ;

  // rule RL_imem_rl_fetch_next_32b
  assign CAN_FIRE_RL_imem_rl_fetch_next_32b =
	     near_mem$imem_valid && imem_rg_pc[1:0] != 2'b0 &&
	     imem_rg_pc_BITS_63_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 &&
	     near_mem$imem_instr[17:16] == 2'b11 ;
  assign WILL_FIRE_RL_imem_rl_fetch_next_32b =
	     CAN_FIRE_RL_imem_rl_fetch_next_32b ;

  // rule RL_stage3_rl_reset
  assign CAN_FIRE_RL_stage3_rl_reset =
	     stage3_f_reset_reqs$EMPTY_N && stage3_f_reset_rsps$FULL_N ;
  assign WILL_FIRE_RL_stage3_rl_reset = CAN_FIRE_RL_stage3_rl_reset ;

  // rule RL_stage2_rl_reset_end
  assign CAN_FIRE_RL_stage2_rl_reset_end =
	     stage2_fbox$RDY_server_reset_response_get &&
	     stage2_f_reset_rsps$FULL_N &&
	     stage2_rg_resetting ;
  assign WILL_FIRE_RL_stage2_rl_reset_end = CAN_FIRE_RL_stage2_rl_reset_end ;

  // rule RL_stage2_rl_reset_begin
  assign CAN_FIRE_RL_stage2_rl_reset_begin =
	     stage2_fbox$RDY_server_reset_request_put &&
	     stage2_f_reset_reqs$EMPTY_N ;
  assign WILL_FIRE_RL_stage2_rl_reset_begin =
	     CAN_FIRE_RL_stage2_rl_reset_begin ;

  // rule RL_stage1_rl_reset
  assign CAN_FIRE_RL_stage1_rl_reset =
	     stage1_f_reset_reqs$EMPTY_N && stage1_f_reset_rsps$FULL_N ;
  assign WILL_FIRE_RL_stage1_rl_reset = CAN_FIRE_RL_stage1_rl_reset ;

  // rule RL_stageD_rl_reset
  assign CAN_FIRE_RL_stageD_rl_reset =
	     stageD_f_reset_reqs$EMPTY_N && stageD_f_reset_rsps$FULL_N ;
  assign WILL_FIRE_RL_stageD_rl_reset = CAN_FIRE_RL_stageD_rl_reset ;

  // rule RL_stageF_rl_reset
  assign CAN_FIRE_RL_stageF_rl_reset =
	     stageF_f_reset_reqs$EMPTY_N && stageF_f_reset_rsps$FULL_N ;
  assign WILL_FIRE_RL_stageF_rl_reset = CAN_FIRE_RL_stageF_rl_reset ;

  // inputs to muxes for submodule ports
  assign MUX_csr_regfile$mav_csr_write_1__SEL_1 =
	     WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	     csr_regfile$access_permitted_1 ;
  assign MUX_csr_regfile$mav_csr_write_1__SEL_2 =
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	     csr_regfile$access_permitted_2 &&
	     rg_trap_instr[19:15] != 5'd0 ;
  assign MUX_csr_regfile$write_dcsr_cause_priv_1__SEL_1 =
	     WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset ;
  assign MUX_csr_regfile$write_dpc_1__SEL_2 =
	     WILL_FIRE_RL_rl_stage1_stop ||
	     WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode ;
  assign MUX_f_run_halt_rsps$enq_1__SEL_1 =
	     WILL_FIRE_RL_rl_debug_halt_redundant ||
	     WILL_FIRE_RL_rl_BREAK_cache_flush_finish ||
	     WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode ;
  assign MUX_f_trace_data$enq_1__SEL_1 =
	     WILL_FIRE_RL_rl_pipe && stage3_rg_full ;
  assign MUX_f_trace_data$enq_1__SEL_3 =
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	     csr_regfile$access_permitted_2 ;
  assign MUX_f_trace_data$enq_1__SEL_4 =
	     WILL_FIRE_RL_rl_stage1_WFI ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ;
  assign MUX_fpr_regfile$write_rd_1__SEL_1 =
	     WILL_FIRE_RL_rl_pipe && stage3_rg_full &&
	     stage3_rg_stage3[567] &&
	     stage3_rg_stage3[496] ;
  assign MUX_gpr_regfile$write_rd_1__SEL_3 =
	     WILL_FIRE_RL_rl_pipe && stage3_rg_full &&
	     stage3_rg_stage3[567] &&
	     !stage3_rg_stage3[496] ;
  assign MUX_imem_rg_cache_addr$write_1__PSEL_1 =
	     WILL_FIRE_RL_rl_debug_run || WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
  assign MUX_imem_rg_cache_addr$write_1__SEL_3 =
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2550 ;
  assign MUX_imem_rg_f3$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ;
  assign MUX_imem_rg_pc$write_1__SEL_3 =
	     WILL_FIRE_RL_rl_trap_fetch || WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;
  assign MUX_rg_next_pc$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_pipe &&
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2484 ;
  assign MUX_rg_next_pc$write_1__SEL_4 =
	     WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_FENCE ||
	     WILL_FIRE_RL_rl_stage1_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage1_SFENCE_VMA ;
  assign MUX_rg_state$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2535 ;
  assign MUX_rg_state$write_1__SEL_2 =
	     CAN_FIRE_RL_rl_reset_complete &&
	     !WILL_FIRE_RL_imem_rl_fetch_next_32b &&
	     !WILL_FIRE_RL_rl_reset_from_Debug_Module ;
  assign MUX_rg_state$write_1__SEL_3 =
	     (!csr_regfile$access_permitted_1 || f_trace_data$FULL_N) &&
	     rg_state == 4'd7 ;
  assign MUX_rg_state$write_1__SEL_4 =
	     (!csr_regfile$access_permitted_2 || f_trace_data$FULL_N) &&
	     rg_state == 4'd8 ;
  assign MUX_rg_state$write_1__SEL_5 =
	     WILL_FIRE_RL_rl_reset_from_Debug_Module ||
	     WILL_FIRE_RL_rl_reset_from_WFI ;
  assign MUX_rg_state$write_1__SEL_10 =
	     WILL_FIRE_RL_rl_stage1_interrupt ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ;
  assign MUX_rg_state$write_1__SEL_11 =
	     WILL_FIRE_RL_rl_stage1_xRET || WILL_FIRE_RL_rl_trap ;
  assign MUX_rg_step_count$write_1__SEL_4 =
	     WILL_FIRE_RL_rl_stage1_stop || WILL_FIRE_RL_rl_reset_start ;
  assign MUX_rg_trap_info$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ;
  assign MUX_rg_trap_instr$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_stage1_interrupt ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage1_trap ;
  assign MUX_rg_trap_interrupt$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ;
  assign MUX_rg_trap_trace_data$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage1_trap ;
  always@(rg_trap_instr or
	  csr_regfile$read_csr or
	  y__h35888 or
	  IF_csr_regfile_read_csr_rg_trap_instr_654_BITS_ETC___d2714)
  begin
    case (rg_trap_instr[14:12])
      3'b010, 3'b110:
	  MUX_csr_regfile$mav_csr_write_2__VAL_2 =
	      IF_csr_regfile_read_csr_rg_trap_instr_654_BITS_ETC___d2714;
      default: MUX_csr_regfile$mav_csr_write_2__VAL_2 =
		   csr_regfile$read_csr[63:0] & y__h35888;
    endcase
  end
  assign MUX_csr_regfile$write_dcsr_cause_priv_1__VAL_2 =
	     rg_stop_req ? 3'd3 : 3'd4 ;
  assign MUX_f_csr_rsps$enq_1__VAL_3 =
	     { 1'd1, csr_regfile$read_csr_port2[63:0] } ;
  assign MUX_f_fpr_rsps$enq_1__VAL_3 = { 1'd1, fpr_regfile$read_rs1_port2 } ;
  assign MUX_f_gpr_rsps$enq_1__VAL_3 = { 1'd1, gpr_regfile$read_rs1_port2 } ;
  assign MUX_f_trace_data$enq_1__VAL_1 =
	     { stage3_rg_stage3[426:256],
	       x__h26853,
	       stage3_rg_stage3[191:128],
	       x__h26867,
	       stage3_rg_stage3[63:0] } ;
  assign MUX_f_trace_data$enq_1__VAL_2 =
	     { 5'd16,
	       rg_trap_trace_data[421:325],
	       rg_trap_instr[11:7],
	       csr_regfile$read_csr[63:0],
	       x__h35109,
	       x__h36155,
	       csr_regfile$mav_csr_write[128:65],
	       x__h35168 } ;
  assign MUX_f_trace_data$enq_1__VAL_3 =
	     { 5'd16,
	       rg_trap_trace_data[421:325],
	       rg_trap_instr[11:7],
	       csr_regfile$read_csr[63:0],
	       x__h36096,
	       x__h36155,
	       x__h36158,
	       x__h36164 } ;
  assign MUX_f_trace_data$enq_1__VAL_6 =
	     { 299'h0EAAAAAAAAAAAAAAA955555554AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA0000000000000344,
	       csr_regfile$csr_mip_read,
	       64'hAAAAAAAAAAAAAAAA } ;
  assign MUX_f_trace_data$enq_1__VAL_7 =
	     { rg_trap_interrupt ? 5'd17 : 5'd14,
	       csr_regfile$csr_trap_actions[193:130],
	       rg_trap_trace_data[357:325],
	       x_rd__h34040,
	       csr_regfile$csr_trap_actions[129:2],
	       rg_trap_info_626_BITS_131_TO_68_627_CONCAT_IF__ETC___d2650 } ;
  assign MUX_f_trace_data$enq_1__VAL_8 =
	     { 5'd15,
	       csr_regfile$csr_ret_actions[129:66],
	       stage1_rg_stage_input[333],
	       alu_outputs___1_trace_data_instr__h28290,
	       td1_rd__h37536,
	       csr_regfile$csr_ret_actions[63:0],
	       256'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA } ;
  assign MUX_imem_rg_tval$write_1__VAL_5 = near_mem$imem_pc + 64'd4 ;
  assign MUX_near_mem$imem_req_2__VAL_1 =
	     NOT_soc_map_m_pc_reset_value__063_BITS_1_TO_0__ETC___d2078 ?
	       addr_of_b32___1__h25679 :
	       addr_of_b32__h25567 ;
  assign MUX_near_mem$imem_req_2__VAL_2 =
	     NOT_stageF_branch_predictor_predict_rsp_NOT_im_ETC___d2559 ?
	       addr_of_b32___1__h32842 :
	       addr_of_b32__h32730 ;
  assign MUX_near_mem$imem_req_2__VAL_4 =
	     NOT_rg_next_pc_736_BITS_1_TO_0_737_EQ_0b0_738__ETC___d2745 ?
	       addr_of_b32___1__h42989 :
	       addr_of_b32__h42877 ;
  assign MUX_near_mem$imem_req_2__VAL_5 =
	     NOT_csr_regfile_read_dpc__843_BITS_1_TO_0_844__ETC___d2852 ?
	       addr_of_b32___1__h44948 :
	       addr_of_b32__h44836 ;
  assign MUX_rg_state$write_1__VAL_2 = rg_run_on_reset ? 4'd4 : 4'd3 ;
  assign MUX_rg_state$write_1__VAL_3 =
	     csr_regfile$access_permitted_1 ? 4'd9 : 4'd5 ;
  assign MUX_rg_state$write_1__VAL_4 =
	     csr_regfile$access_permitted_2 ? 4'd9 : 4'd5 ;
  assign MUX_rg_trap_info$write_1__VAL_1 =
	     { stage1_rg_stage_input[401:338], 4'd2, value__h14669 } ;
  always@(stage2_rg_stage2 or near_mem$dmem_exc_code)
  begin
    case (stage2_rg_stage2[824:822])
      3'd1, 3'd2, 3'd4:
	  MUX_rg_trap_info$write_1__VAL_2 =
	      { stage2_rg_stage2[920:857],
		near_mem$dmem_exc_code,
		stage2_rg_stage2[816:753] };
      default: MUX_rg_trap_info$write_1__VAL_2 =
		   { stage2_rg_stage2[920:857], 68'h20000000000000000 };
    endcase
  end
  assign MUX_rg_trap_info$write_1__VAL_3 =
	     { stage1_rg_stage_input[401:338],
	       stage1_rg_stage_input[332] ?
		 stage1_rg_stage_input[331:264] :
		 { alu_outputs_exc_code__h11522, trap_info_tval__h14555 } } ;
  assign MUX_rg_trap_info$write_1__VAL_4 =
	     { stage1_rg_stage_input[401:338], x_exc_code__h43682, 64'd0 } ;
  assign MUX_rg_trap_instr$write_1__VAL_1 = stage1_rg_stage_input[263:232] ;
  assign MUX_rg_trap_trace_data$write_1__VAL_2 =
	     { stage2_rg_stage2[426:320],
	       IF_stage2_rg_stage2_18_BITS_824_TO_822_19_EQ_0_ETC___d2223,
	       IF_stage2_rg_stage2_18_BITS_824_TO_822_19_EQ_0_ETC___d2240 } ;
  assign MUX_stage1_rg_full$write_1__VAL_2 =
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2487 &&
	     stageD_rg_full ||
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2574 ;
  assign MUX_stage2_rg_full$write_1__VAL_2 =
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2128 ?
	       IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	       4'd0 &&
	       IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d2088 :
	       IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 !=
	       2'd2 &&
	       IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 !=
	       2'd0 ;
  assign MUX_stageD_rg_full$write_1__VAL_2 =
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2528 ||
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2132 &&
	     stageD_rg_full ;
  assign MUX_stageF_rg_full$write_1__VAL_2 =
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2528 ?
	       NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2588 :
	       (IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2132 &&
		stageD_rg_full ||
		!near_mem$imem_valid ||
		imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1905) &&
	       stageF_rg_full ;

  // register cfg_logdelay
  assign cfg_logdelay$D_IN = set_verbosity_logdelay ;
  assign cfg_logdelay$EN = EN_set_verbosity ;

  // register cfg_verbosity
  assign cfg_verbosity$D_IN =
	     EN_set_verbosity ?
	       set_verbosity_verbosity :
	       hart0_put_other_req_put ;
  assign cfg_verbosity$EN = EN_set_verbosity || EN_hart0_put_other_req_put ;

  // register imem_rg_cache_addr
  assign imem_rg_cache_addr$D_IN = near_mem$imem_pc ;
  assign imem_rg_cache_addr$EN =
	     MUX_imem_rg_cache_addr$write_1__PSEL_1 && near_mem$imem_valid ||
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
	     near_mem$imem_valid ||
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2550 ||
	     WILL_FIRE_RL_imem_rl_fetch_next_32b ;

  // register imem_rg_cache_b16
  assign imem_rg_cache_b16$D_IN = near_mem$imem_instr[31:16] ;
  assign imem_rg_cache_b16$EN =
	     MUX_imem_rg_cache_addr$write_1__PSEL_1 && near_mem$imem_valid ||
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
	     near_mem$imem_valid ||
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2550 ||
	     WILL_FIRE_RL_imem_rl_fetch_next_32b ;

  // register imem_rg_f3
  assign imem_rg_f3$D_IN = 3'b010 ;
  assign imem_rg_f3$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2550 ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register imem_rg_mstatus_MXR
  assign imem_rg_mstatus_MXR$D_IN = csr_regfile$read_mstatus[19] ;
  assign imem_rg_mstatus_MXR$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2550 ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register imem_rg_pc
  always@(MUX_imem_rg_f3$write_1__SEL_1 or
	  soc_map$m_pc_reset_value or
	  MUX_imem_rg_cache_addr$write_1__SEL_3 or
	  stageF_branch_predictor$predict_rsp or
	  MUX_imem_rg_pc$write_1__SEL_3 or
	  rg_next_pc or WILL_FIRE_RL_rl_debug_run or csr_regfile$read_dpc)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_imem_rg_f3$write_1__SEL_1:
	  imem_rg_pc$D_IN = soc_map$m_pc_reset_value;
      MUX_imem_rg_cache_addr$write_1__SEL_3:
	  imem_rg_pc$D_IN = stageF_branch_predictor$predict_rsp;
      MUX_imem_rg_pc$write_1__SEL_3: imem_rg_pc$D_IN = rg_next_pc;
      WILL_FIRE_RL_rl_debug_run: imem_rg_pc$D_IN = csr_regfile$read_dpc;
      default: imem_rg_pc$D_IN =
		   64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign imem_rg_pc$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2550 ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_rl_debug_run ;

  // register imem_rg_priv
  assign imem_rg_priv$D_IN = rg_cur_priv ;
  assign imem_rg_priv$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2550 ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register imem_rg_satp
  assign imem_rg_satp$D_IN = csr_regfile$read_satp ;
  assign imem_rg_satp$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2550 ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register imem_rg_sstatus_SUM
  assign imem_rg_sstatus_SUM$D_IN = csr_regfile$read_sstatus[18] ;
  assign imem_rg_sstatus_SUM$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2550 ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register imem_rg_tval
  always@(MUX_imem_rg_f3$write_1__SEL_1 or
	  soc_map$m_pc_reset_value or
	  MUX_imem_rg_cache_addr$write_1__SEL_3 or
	  stageF_branch_predictor$predict_rsp or
	  MUX_imem_rg_pc$write_1__SEL_3 or
	  rg_next_pc or
	  WILL_FIRE_RL_rl_debug_run or
	  csr_regfile$read_dpc or
	  WILL_FIRE_RL_imem_rl_fetch_next_32b or
	  MUX_imem_rg_tval$write_1__VAL_5)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_imem_rg_f3$write_1__SEL_1:
	  imem_rg_tval$D_IN = soc_map$m_pc_reset_value;
      MUX_imem_rg_cache_addr$write_1__SEL_3:
	  imem_rg_tval$D_IN = stageF_branch_predictor$predict_rsp;
      MUX_imem_rg_pc$write_1__SEL_3: imem_rg_tval$D_IN = rg_next_pc;
      WILL_FIRE_RL_rl_debug_run: imem_rg_tval$D_IN = csr_regfile$read_dpc;
      WILL_FIRE_RL_imem_rl_fetch_next_32b:
	  imem_rg_tval$D_IN = MUX_imem_rg_tval$write_1__VAL_5;
      default: imem_rg_tval$D_IN =
		   64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign imem_rg_tval$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2550 ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_imem_rl_fetch_next_32b ;

  // register rg_csr_pc
  assign rg_csr_pc$D_IN = stage1_rg_stage_input[401:338] ;
  assign rg_csr_pc$EN = MUX_rg_trap_info$write_1__SEL_1 ;

  // register rg_csr_val1
  assign rg_csr_val1$D_IN = x_out_data_to_stage2_val1__h10377 ;
  assign rg_csr_val1$EN = MUX_rg_trap_info$write_1__SEL_1 ;

  // register rg_cur_priv
  always@(WILL_FIRE_RL_rl_trap or
	  csr_regfile$csr_trap_actions or
	  WILL_FIRE_RL_rl_stage1_xRET or
	  csr_regfile$csr_ret_actions or WILL_FIRE_RL_rl_reset_start)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_rl_trap:
	  rg_cur_priv$D_IN = csr_regfile$csr_trap_actions[1:0];
      WILL_FIRE_RL_rl_stage1_xRET:
	  rg_cur_priv$D_IN = csr_regfile$csr_ret_actions[65:64];
      WILL_FIRE_RL_rl_reset_start: rg_cur_priv$D_IN = 2'b11;
      default: rg_cur_priv$D_IN = 2'b10 /* unspecified value */ ;
    endcase
  end
  assign rg_cur_priv$EN =
	     WILL_FIRE_RL_rl_trap || WILL_FIRE_RL_rl_stage1_xRET ||
	     WILL_FIRE_RL_rl_reset_start ;

  // register rg_epoch
  always@(MUX_imem_rg_f3$write_1__SEL_1 or
	  new_epoch__h25078 or
	  MUX_imem_rg_cache_addr$write_1__PSEL_1 or
	  WILL_FIRE_RL_rl_reset_start)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_imem_rg_f3$write_1__SEL_1: rg_epoch$D_IN = new_epoch__h25078;
      MUX_imem_rg_cache_addr$write_1__PSEL_1:
	  rg_epoch$D_IN = new_epoch__h25078;
      WILL_FIRE_RL_rl_reset_start: rg_epoch$D_IN = 2'd0;
      default: rg_epoch$D_IN = 2'b10 /* unspecified value */ ;
    endcase
  end
  assign rg_epoch$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_rl_reset_start ;

  // register rg_mstatus_MXR
  assign rg_mstatus_MXR$D_IN = csr_regfile$read_mstatus[19] ;
  assign rg_mstatus_MXR$EN = MUX_rg_state$write_1__SEL_11 ;

  // register rg_next_pc
  always@(MUX_rg_next_pc$write_1__SEL_1 or
	  x_out_next_pc__h10308 or
	  WILL_FIRE_RL_rl_trap or
	  csr_regfile$csr_trap_actions or
	  WILL_FIRE_RL_rl_stage1_xRET or
	  csr_regfile$csr_ret_actions or MUX_rg_next_pc$write_1__SEL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_rg_next_pc$write_1__SEL_1: rg_next_pc$D_IN = x_out_next_pc__h10308;
      WILL_FIRE_RL_rl_trap:
	  rg_next_pc$D_IN = csr_regfile$csr_trap_actions[193:130];
      WILL_FIRE_RL_rl_stage1_xRET:
	  rg_next_pc$D_IN = csr_regfile$csr_ret_actions[129:66];
      MUX_rg_next_pc$write_1__SEL_4: rg_next_pc$D_IN = x_out_next_pc__h10308;
      default: rg_next_pc$D_IN =
		   64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign rg_next_pc$EN =
	     WILL_FIRE_RL_rl_pipe &&
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2484 ||
	     WILL_FIRE_RL_rl_trap ||
	     WILL_FIRE_RL_rl_stage1_xRET ||
	     WILL_FIRE_RL_rl_stage1_WFI ||
	     WILL_FIRE_RL_rl_stage1_FENCE ||
	     WILL_FIRE_RL_rl_stage1_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage1_SFENCE_VMA ;

  // register rg_prev_mip
  assign rg_prev_mip$D_IN =
	     WILL_FIRE_RL_rl_stage1_mip_cmd ?
	       csr_regfile$csr_mip_read :
	       64'd0 ;
  assign rg_prev_mip$EN =
	     WILL_FIRE_RL_rl_stage1_mip_cmd || WILL_FIRE_RL_rl_reset_start ;

  // register rg_run_on_reset
  assign rg_run_on_reset$D_IN = f_reset_reqs$D_OUT ;
  assign rg_run_on_reset$EN = CAN_FIRE_RL_rl_reset_start ;

  // register rg_sstatus_SUM
  assign rg_sstatus_SUM$D_IN = csr_regfile$read_sstatus[18] ;
  assign rg_sstatus_SUM$EN = MUX_rg_state$write_1__SEL_11 ;

  // register rg_start_CPI_cycles
  assign rg_start_CPI_cycles$D_IN = csr_regfile$read_csr_mcycle ;
  assign rg_start_CPI_cycles$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_debug_run ;

  // register rg_start_CPI_instrs
  assign rg_start_CPI_instrs$D_IN = csr_regfile$read_csr_minstret ;
  assign rg_start_CPI_instrs$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_debug_run ;

  // register rg_state
  always@(WILL_FIRE_RL_rl_reset_complete or
	  MUX_rg_state$write_1__VAL_2 or
	  WILL_FIRE_RL_rl_stage1_CSRR_W_2 or
	  MUX_rg_state$write_1__VAL_3 or
	  WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 or
	  MUX_rg_state$write_1__VAL_4 or
	  MUX_rg_state$write_1__SEL_5 or
	  WILL_FIRE_RL_rl_reset_start or
	  MUX_csr_regfile$write_dpc_1__SEL_2 or
	  WILL_FIRE_RL_rl_BREAK_cache_flush_finish or
	  MUX_imem_rg_cache_addr$write_1__PSEL_1 or
	  MUX_rg_state$write_1__SEL_10 or
	  MUX_rg_state$write_1__SEL_1 or
	  MUX_rg_state$write_1__SEL_11 or
	  WILL_FIRE_RL_rl_stage1_CSRR_W or
	  WILL_FIRE_RL_rl_stage1_CSRR_S_or_C or
	  WILL_FIRE_RL_rl_stage1_FENCE_I or
	  WILL_FIRE_RL_rl_stage1_FENCE or
	  WILL_FIRE_RL_rl_stage1_SFENCE_VMA or WILL_FIRE_RL_rl_stage1_WFI)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_rl_reset_complete:
	  rg_state$D_IN = MUX_rg_state$write_1__VAL_2;
      WILL_FIRE_RL_rl_stage1_CSRR_W_2:
	  rg_state$D_IN = MUX_rg_state$write_1__VAL_3;
      WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2:
	  rg_state$D_IN = MUX_rg_state$write_1__VAL_4;
      MUX_rg_state$write_1__SEL_5: rg_state$D_IN = 4'd0;
      WILL_FIRE_RL_rl_reset_start: rg_state$D_IN = 4'd1;
      MUX_csr_regfile$write_dpc_1__SEL_2: rg_state$D_IN = 4'd2;
      WILL_FIRE_RL_rl_BREAK_cache_flush_finish: rg_state$D_IN = 4'd3;
      MUX_imem_rg_cache_addr$write_1__PSEL_1: rg_state$D_IN = 4'd4;
      MUX_rg_state$write_1__SEL_10: rg_state$D_IN = 4'd5;
      MUX_rg_state$write_1__SEL_1 || MUX_rg_state$write_1__SEL_11:
	  rg_state$D_IN = 4'd6;
      WILL_FIRE_RL_rl_stage1_CSRR_W: rg_state$D_IN = 4'd7;
      WILL_FIRE_RL_rl_stage1_CSRR_S_or_C: rg_state$D_IN = 4'd8;
      WILL_FIRE_RL_rl_stage1_FENCE_I: rg_state$D_IN = 4'd10;
      WILL_FIRE_RL_rl_stage1_FENCE: rg_state$D_IN = 4'd11;
      WILL_FIRE_RL_rl_stage1_SFENCE_VMA: rg_state$D_IN = 4'd12;
      WILL_FIRE_RL_rl_stage1_WFI: rg_state$D_IN = 4'd13;
      default: rg_state$D_IN = 4'b1010 /* unspecified value */ ;
    endcase
  end
  assign rg_state$EN =
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2535 ||
	     WILL_FIRE_RL_rl_reset_complete ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W_2 ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 ||
	     WILL_FIRE_RL_rl_reset_from_Debug_Module ||
	     WILL_FIRE_RL_rl_reset_from_WFI ||
	     WILL_FIRE_RL_rl_reset_start ||
	     WILL_FIRE_RL_rl_stage1_stop ||
	     WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode ||
	     WILL_FIRE_RL_rl_BREAK_cache_flush_finish ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_rl_stage1_interrupt ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ||
	     WILL_FIRE_RL_rl_stage1_xRET ||
	     WILL_FIRE_RL_rl_trap ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_FENCE ||
	     WILL_FIRE_RL_rl_stage1_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_stage1_WFI ;

  // register rg_step_count
  assign rg_step_count$D_IN = !MUX_rg_step_count$write_1__SEL_4 ;
  assign rg_step_count$EN =
	     _dand1rg_step_count$EN_write || _dand2rg_step_count$EN_write ||
	     (WILL_FIRE_RL_rl_stage1_WFI || WILL_FIRE_RL_rl_stage1_xRET) &&
	     csr_regfile$read_dcsr_step &&
	     !rg_step_count ||
	     WILL_FIRE_RL_rl_stage1_stop ||
	     WILL_FIRE_RL_rl_reset_start ;

  // register rg_stop_req
  assign rg_stop_req$D_IN = !MUX_rg_step_count$write_1__SEL_4 ;
  assign rg_stop_req$EN =
	     WILL_FIRE_RL_rl_stage1_stop || WILL_FIRE_RL_rl_reset_start ||
	     WILL_FIRE_RL_rl_debug_halt ;

  // register rg_trap_info
  always@(MUX_rg_trap_info$write_1__SEL_1 or
	  MUX_rg_trap_info$write_1__VAL_1 or
	  WILL_FIRE_RL_rl_stage2_nonpipe or
	  MUX_rg_trap_info$write_1__VAL_2 or
	  WILL_FIRE_RL_rl_stage1_trap or
	  MUX_rg_trap_info$write_1__VAL_3 or
	  WILL_FIRE_RL_rl_stage1_interrupt or MUX_rg_trap_info$write_1__VAL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_rg_trap_info$write_1__SEL_1:
	  rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_1;
      WILL_FIRE_RL_rl_stage2_nonpipe:
	  rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_2;
      WILL_FIRE_RL_rl_stage1_trap:
	  rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_3;
      WILL_FIRE_RL_rl_stage1_interrupt:
	  rg_trap_info$D_IN = MUX_rg_trap_info$write_1__VAL_4;
      default: rg_trap_info$D_IN =
		   132'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign rg_trap_info$EN =
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage1_interrupt ;

  // register rg_trap_instr
  assign rg_trap_instr$D_IN =
	     MUX_rg_trap_instr$write_1__SEL_1 ?
	       stage1_rg_stage_input[263:232] :
	       stage2_rg_stage2[856:825] ;
  assign rg_trap_instr$EN =
	     WILL_FIRE_RL_rl_stage1_interrupt ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ;

  // register rg_trap_interrupt
  assign rg_trap_interrupt$D_IN = !MUX_rg_trap_interrupt$write_1__SEL_1 ;
  assign rg_trap_interrupt$EN =
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W ||
	     WILL_FIRE_RL_rl_stage1_trap ||
	     WILL_FIRE_RL_rl_stage2_nonpipe ||
	     WILL_FIRE_RL_rl_stage1_interrupt ;

  // register rg_trap_trace_data
  assign rg_trap_trace_data$D_IN =
	     MUX_rg_trap_trace_data$write_1__SEL_1 ?
	       IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2420 :
	       MUX_rg_trap_trace_data$write_1__VAL_2 ;
  assign rg_trap_trace_data$EN = MUX_rg_trap_interrupt$write_1__SEL_1 ;

  // register stage1_rg_full
  always@(WILL_FIRE_RL_stage1_rl_reset or
	  WILL_FIRE_RL_rl_pipe or
	  MUX_stage1_rg_full$write_1__VAL_2 or
	  MUX_imem_rg_f3$write_1__SEL_1 or
	  WILL_FIRE_RL_rl_stage1_WFI or
	  WILL_FIRE_RL_rl_finish_SFENCE_VMA or
	  WILL_FIRE_RL_rl_finish_FENCE or
	  WILL_FIRE_RL_rl_finish_FENCE_I or
	  WILL_FIRE_RL_rl_stage1_xRET or
	  WILL_FIRE_RL_rl_stage1_restart_after_csrrx or
	  WILL_FIRE_RL_rl_trap or WILL_FIRE_RL_rl_debug_run)
  case (1'b1)
    WILL_FIRE_RL_stage1_rl_reset: stage1_rg_full$D_IN = 1'd0;
    WILL_FIRE_RL_rl_pipe:
	stage1_rg_full$D_IN = MUX_stage1_rg_full$write_1__VAL_2;
    MUX_imem_rg_f3$write_1__SEL_1 || WILL_FIRE_RL_rl_stage1_WFI ||
    WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
    WILL_FIRE_RL_rl_finish_FENCE ||
    WILL_FIRE_RL_rl_finish_FENCE_I ||
    WILL_FIRE_RL_rl_stage1_xRET ||
    WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
    WILL_FIRE_RL_rl_trap ||
    WILL_FIRE_RL_rl_debug_run:
	stage1_rg_full$D_IN = 1'd0;
    default: stage1_rg_full$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign stage1_rg_full$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_rl_stage1_WFI ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_xRET ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_rl_trap ||
	     WILL_FIRE_RL_stage1_rl_reset ;

  // register stage1_rg_stage_input
  assign stage1_rg_stage_input$D_IN =
	     { stageD_rg_data[233:170],
	       stageD_rg_data[167:166],
	       stageD_rg_data[169:168],
	       stageD_rg_data[165:96],
	       _theResult____h6090,
	       stageD_rg_data[79:0],
	       _theResult____h6090[6:0],
	       _theResult____h6090[11:7],
	       _theResult____h6090[19:15],
	       _theResult____h6090[24:20],
	       _theResult____h6090[31:27],
	       _theResult____h6090[31:20],
	       _theResult____h6090[14:12],
	       _theResult____h6090[31:27],
	       _theResult____h6090[31:25],
	       decoded_instr_funct10__h31419,
	       _theResult____h6090[31:20],
	       decoded_instr_imm12_S__h31421,
	       decoded_instr_imm13_SB__h31422,
	       _theResult____h6090[31:12],
	       decoded_instr_imm21_UJ__h31424,
	       _theResult____h6090[27:20],
	       _theResult____h6090[26:25] } ;
  assign stage1_rg_stage_input$EN =
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2487 &&
	     stageD_rg_full ;

  // register stage2_rg_full
  always@(WILL_FIRE_RL_stage2_rl_reset_begin or
	  WILL_FIRE_RL_rl_pipe or
	  MUX_stage2_rg_full$write_1__VAL_2 or
	  MUX_imem_rg_f3$write_1__SEL_1 or
	  WILL_FIRE_RL_rl_trap or WILL_FIRE_RL_rl_debug_run)
  case (1'b1)
    WILL_FIRE_RL_stage2_rl_reset_begin: stage2_rg_full$D_IN = 1'd0;
    WILL_FIRE_RL_rl_pipe:
	stage2_rg_full$D_IN = MUX_stage2_rg_full$write_1__VAL_2;
    MUX_imem_rg_f3$write_1__SEL_1 || WILL_FIRE_RL_rl_trap ||
    WILL_FIRE_RL_rl_debug_run:
	stage2_rg_full$D_IN = 1'd0;
    default: stage2_rg_full$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign stage2_rg_full$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_rl_trap ||
	     WILL_FIRE_RL_stage2_rl_reset_begin ;

  // register stage2_rg_resetting
  assign stage2_rg_resetting$D_IN = WILL_FIRE_RL_stage2_rl_reset_begin ;
  assign stage2_rg_resetting$EN =
	     WILL_FIRE_RL_stage2_rl_reset_end ||
	     WILL_FIRE_RL_stage2_rl_reset_begin ;

  // register stage2_rg_stage2
  assign stage2_rg_stage2$D_IN =
	     { rg_cur_priv,
	       stage1_rg_stage_input[401:338],
	       stage1_rg_stage_input[263:232],
	       IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153,
	       x_out_data_to_stage2_rd__h10375,
	       x_out_data_to_stage2_addr__h10376,
	       x_out_data_to_stage2_val1__h10377,
	       x_out_data_to_stage2_val2__h10378,
	       x_out_data_to_stage2_fval1__h10379,
	       alu_outputs___1_fval2__h10945,
	       x_out_data_to_stage2_fval3__h10381,
	       stage1_rg_stage_input[151:145] == 7'b0000111 ||
	       (stage1_rg_stage_input[151:145] == 7'b1010011 ||
		stage1_rg_stage_input[151:145] == 7'b1000011 ||
		stage1_rg_stage_input[151:145] == 7'b1000111 ||
		stage1_rg_stage_input[151:145] == 7'b1001011 ||
		stage1_rg_stage_input[151:145] == 7'b1001111) &&
	       (stage1_rg_stage_input[104:98] != 7'h61 ||
		stage1_rg_stage_input[134:130] != 5'd0) &&
	       (stage1_rg_stage_input[104:98] != 7'h61 ||
		stage1_rg_stage_input[134:130] != 5'd1) &&
	       (stage1_rg_stage_input[104:98] != 7'h61 ||
		stage1_rg_stage_input[134:130] != 5'd2) &&
	       (stage1_rg_stage_input[104:98] != 7'h61 ||
		stage1_rg_stage_input[134:130] != 5'd3) &&
	       stage1_rg_stage_input[104:98] != 7'h71 &&
	       stage1_rg_stage_input[104:98] != 7'h51 &&
	       (stage1_rg_stage_input[104:98] != 7'h60 ||
		stage1_rg_stage_input[134:130] != 5'd2) &&
	       (stage1_rg_stage_input[104:98] != 7'h60 ||
		stage1_rg_stage_input[134:130] != 5'd3) &&
	       (stage1_rg_stage_input[104:98] != 7'h60 ||
		stage1_rg_stage_input[134:130] != 5'd0) &&
	       (stage1_rg_stage_input[104:98] != 7'h60 ||
		stage1_rg_stage_input[134:130] != 5'd1) &&
	       stage1_rg_stage_input[104:98] != 7'h70 &&
	       stage1_rg_stage_input[104:98] != 7'h50,
	       stage1_rg_stage_input[151:145] == 7'b0100111,
	       stage1_rg_stage_input_17_BITS_151_TO_145_59_EQ_ETC___d2328,
	       x_out_data_to_stage2_rounding_mode__h10385,
	       IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2420 } ;
  assign stage2_rg_stage2$EN =
	     WILL_FIRE_RL_rl_pipe &&
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2283 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd0 &&
	     IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d2088 ;

  // register stage3_rg_full
  always@(WILL_FIRE_RL_stage3_rl_reset or
	  WILL_FIRE_RL_rl_pipe or
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 or
	  MUX_imem_rg_f3$write_1__SEL_1 or WILL_FIRE_RL_rl_debug_run)
  case (1'b1)
    WILL_FIRE_RL_stage3_rl_reset: stage3_rg_full$D_IN = 1'd0;
    WILL_FIRE_RL_rl_pipe:
	stage3_rg_full$D_IN =
	    IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd2;
    MUX_imem_rg_f3$write_1__SEL_1 || WILL_FIRE_RL_rl_debug_run:
	stage3_rg_full$D_IN = 1'd0;
    default: stage3_rg_full$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign stage3_rg_full$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_stage3_rl_reset ;

  // register stage3_rg_stage3
  assign stage3_rg_stage3$D_IN =
	     { stage2_rg_stage2[920:825],
	       stage2_rg_stage2[922:921],
	       stage2_rg_stage2[824:822] == 3'd0 ||
	       IF_stage2_rg_stage2_18_BITS_824_TO_822_19_EQ_1_ETC___d179,
	       x_out_data_to_stage3_rd__h9220,
	       x_out_data_to_stage3_rd_val__h9221,
	       stage2_rg_stage2[824:822] != 3'd0 &&
	       stage2_rg_stage2[824:822] != 3'd1 &&
	       stage2_rg_stage2[824:822] != 3'd4 &&
	       stage2_rg_stage2[824:822] != 3'd2 &&
	       stage2_rg_stage2[824:822] != 3'd3,
	       stage2_rg_stage2[824:822] != 3'd0 &&
	       CASE_stage2_rg_stage2_BITS_824_TO_822_1_stage2_ETC__q28,
	       x_out_data_to_stage3_fpr_flags__h9224,
	       x_out_data_to_stage3_frd_val__h9225,
	       stage2_rg_stage2[426:320],
	       IF_stage2_rg_stage2_18_BITS_824_TO_822_19_EQ_0_ETC___d2223,
	       IF_stage2_rg_stage2_18_BITS_824_TO_822_19_EQ_0_ETC___d2240 } ;
  assign stage3_rg_stage3$EN =
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 ==
	     2'd2 ;

  // register stageD_rg_data
  assign stageD_rg_data$D_IN =
	     { imem_rg_pc,
	       stageF_rg_epoch,
	       stageF_rg_priv,
	       NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1909,
	       near_mem$imem_exc,
	       near_mem$imem_exc_code,
	       imem_rg_tval,
	       d_instr__h23510,
	       stageF_branch_predictor$predict_rsp } ;
  assign stageD_rg_data$EN =
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2528 ;

  // register stageD_rg_full
  always@(WILL_FIRE_RL_stageD_rl_reset or
	  WILL_FIRE_RL_rl_pipe or
	  MUX_stageD_rg_full$write_1__VAL_2 or
	  MUX_imem_rg_f3$write_1__SEL_1 or
	  WILL_FIRE_RL_rl_trap_fetch or
	  WILL_FIRE_RL_rl_WFI_resume or
	  WILL_FIRE_RL_rl_stage1_WFI or
	  WILL_FIRE_RL_rl_finish_SFENCE_VMA or
	  WILL_FIRE_RL_rl_finish_FENCE or
	  WILL_FIRE_RL_rl_finish_FENCE_I or
	  WILL_FIRE_RL_rl_stage1_xRET or
	  WILL_FIRE_RL_rl_stage1_restart_after_csrrx or
	  WILL_FIRE_RL_rl_trap or WILL_FIRE_RL_rl_debug_run)
  case (1'b1)
    WILL_FIRE_RL_stageD_rl_reset: stageD_rg_full$D_IN = 1'd0;
    WILL_FIRE_RL_rl_pipe:
	stageD_rg_full$D_IN = MUX_stageD_rg_full$write_1__VAL_2;
    MUX_imem_rg_f3$write_1__SEL_1 || WILL_FIRE_RL_rl_trap_fetch ||
    WILL_FIRE_RL_rl_WFI_resume ||
    WILL_FIRE_RL_rl_stage1_WFI ||
    WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
    WILL_FIRE_RL_rl_finish_FENCE ||
    WILL_FIRE_RL_rl_finish_FENCE_I ||
    WILL_FIRE_RL_rl_stage1_xRET ||
    WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
    WILL_FIRE_RL_rl_trap ||
    WILL_FIRE_RL_rl_debug_run:
	stageD_rg_full$D_IN = 1'd0;
    default: stageD_rg_full$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign stageD_rg_full$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_stage1_WFI ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_xRET ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_rl_trap ||
	     WILL_FIRE_RL_stageD_rl_reset ;

  // register stageF_rg_epoch
  always@(WILL_FIRE_RL_stageF_rl_reset or
	  MUX_imem_rg_cache_addr$write_1__SEL_3 or
	  stageF_rg_epoch or
	  MUX_imem_rg_f3$write_1__SEL_1 or
	  new_epoch__h25078 or
	  WILL_FIRE_RL_rl_trap_fetch or
	  WILL_FIRE_RL_rl_WFI_resume or
	  WILL_FIRE_RL_rl_finish_SFENCE_VMA or
	  WILL_FIRE_RL_rl_finish_FENCE or
	  WILL_FIRE_RL_rl_finish_FENCE_I or
	  WILL_FIRE_RL_rl_stage1_restart_after_csrrx or
	  WILL_FIRE_RL_rl_debug_run)
  case (1'b1)
    WILL_FIRE_RL_stageF_rl_reset: stageF_rg_epoch$D_IN = 2'd0;
    MUX_imem_rg_cache_addr$write_1__SEL_3:
	stageF_rg_epoch$D_IN = stageF_rg_epoch;
    MUX_imem_rg_f3$write_1__SEL_1: stageF_rg_epoch$D_IN = new_epoch__h25078;
    WILL_FIRE_RL_rl_trap_fetch: stageF_rg_epoch$D_IN = new_epoch__h25078;
    WILL_FIRE_RL_rl_WFI_resume: stageF_rg_epoch$D_IN = new_epoch__h25078;
    WILL_FIRE_RL_rl_finish_SFENCE_VMA:
	stageF_rg_epoch$D_IN = new_epoch__h25078;
    WILL_FIRE_RL_rl_finish_FENCE: stageF_rg_epoch$D_IN = new_epoch__h25078;
    WILL_FIRE_RL_rl_finish_FENCE_I: stageF_rg_epoch$D_IN = new_epoch__h25078;
    WILL_FIRE_RL_rl_stage1_restart_after_csrrx:
	stageF_rg_epoch$D_IN = new_epoch__h25078;
    WILL_FIRE_RL_rl_debug_run: stageF_rg_epoch$D_IN = new_epoch__h25078;
    default: stageF_rg_epoch$D_IN = 2'b10 /* unspecified value */ ;
  endcase
  assign stageF_rg_epoch$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2550 ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_stageF_rl_reset ;

  // register stageF_rg_full
  always@(WILL_FIRE_RL_stageF_rl_reset or
	  WILL_FIRE_RL_rl_pipe or
	  MUX_stageF_rg_full$write_1__VAL_2 or
	  MUX_imem_rg_f3$write_1__SEL_1 or
	  WILL_FIRE_RL_rl_trap_fetch or
	  WILL_FIRE_RL_rl_WFI_resume or
	  WILL_FIRE_RL_rl_finish_SFENCE_VMA or
	  WILL_FIRE_RL_rl_finish_FENCE or
	  WILL_FIRE_RL_rl_finish_FENCE_I or
	  WILL_FIRE_RL_rl_stage1_restart_after_csrrx or
	  WILL_FIRE_RL_rl_debug_run)
  case (1'b1)
    WILL_FIRE_RL_stageF_rl_reset: stageF_rg_full$D_IN = 1'd0;
    WILL_FIRE_RL_rl_pipe:
	stageF_rg_full$D_IN = MUX_stageF_rg_full$write_1__VAL_2;
    MUX_imem_rg_f3$write_1__SEL_1 || WILL_FIRE_RL_rl_trap_fetch ||
    WILL_FIRE_RL_rl_WFI_resume ||
    WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
    WILL_FIRE_RL_rl_finish_FENCE ||
    WILL_FIRE_RL_rl_finish_FENCE_I ||
    WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
    WILL_FIRE_RL_rl_debug_run:
	stageF_rg_full$D_IN = 1'd1;
    default: stageF_rg_full$D_IN = 1'b0 /* unspecified value */ ;
  endcase
  assign stageF_rg_full$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe ||
	     WILL_FIRE_RL_stageF_rl_reset ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // register stageF_rg_priv
  assign stageF_rg_priv$D_IN = rg_cur_priv ;
  assign stageF_rg_priv$EN =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2550 ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ;

  // submodule csr_regfile
  assign csr_regfile$access_permitted_1_csr_addr = rg_trap_instr[31:20] ;
  assign csr_regfile$access_permitted_1_priv = rg_cur_priv ;
  assign csr_regfile$access_permitted_1_read_not_write = 1'd0 ;
  assign csr_regfile$access_permitted_2_csr_addr = rg_trap_instr[31:20] ;
  assign csr_regfile$access_permitted_2_priv = rg_cur_priv ;
  assign csr_regfile$access_permitted_2_read_not_write =
	     rs1_val__h35619 == 64'd0 ;
  assign csr_regfile$csr_counter_read_fault_csr_addr = 12'h0 ;
  assign csr_regfile$csr_counter_read_fault_priv = 2'h0 ;
  always@(IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004)
  begin
    case (IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004)
      4'd8: csr_regfile$csr_ret_actions_from_priv = 2'b11;
      4'd9: csr_regfile$csr_ret_actions_from_priv = 2'b01;
      default: csr_regfile$csr_ret_actions_from_priv = 2'b0;
    endcase
  end
  assign csr_regfile$csr_trap_actions_exc_code = rg_trap_info[67:64] ;
  assign csr_regfile$csr_trap_actions_from_priv = rg_cur_priv ;
  assign csr_regfile$csr_trap_actions_interrupt =
	     rg_trap_interrupt && !csr_regfile$nmi_pending ;
  assign csr_regfile$csr_trap_actions_nmi =
	     rg_trap_interrupt && csr_regfile$nmi_pending ;
  assign csr_regfile$csr_trap_actions_pc = rg_trap_info[131:68] ;
  assign csr_regfile$csr_trap_actions_xtval = rg_trap_info[63:0] ;
  assign csr_regfile$dcsr_break_enters_debug_cur_priv = rg_cur_priv ;
  assign csr_regfile$interrupt_pending_cur_priv = rg_cur_priv ;
  assign csr_regfile$m_external_interrupt_req_set_not_clear =
	     m_external_interrupt_req_set_not_clear ;
  assign csr_regfile$ma_update_fcsr_fflags_flags = stage3_rg_stage3[495:491] ;
  assign csr_regfile$ma_update_mstatus_fs_fs = 2'h3 ;
  assign csr_regfile$mav_csr_write_csr_addr =
	     (MUX_csr_regfile$mav_csr_write_1__SEL_1 ||
	      MUX_csr_regfile$mav_csr_write_1__SEL_2) ?
	       rg_trap_instr[31:20] :
	       f_csr_reqs$D_OUT[75:64] ;
  always@(MUX_csr_regfile$mav_csr_write_1__SEL_1 or
	  rs1_val__h34674 or
	  MUX_csr_regfile$mav_csr_write_1__SEL_2 or
	  MUX_csr_regfile$mav_csr_write_2__VAL_2 or
	  WILL_FIRE_RL_rl_debug_write_csr or f_csr_reqs$D_OUT)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_csr_regfile$mav_csr_write_1__SEL_1:
	  csr_regfile$mav_csr_write_word = rs1_val__h34674;
      MUX_csr_regfile$mav_csr_write_1__SEL_2:
	  csr_regfile$mav_csr_write_word =
	      MUX_csr_regfile$mav_csr_write_2__VAL_2;
      WILL_FIRE_RL_rl_debug_write_csr:
	  csr_regfile$mav_csr_write_word = f_csr_reqs$D_OUT[63:0];
      default: csr_regfile$mav_csr_write_word =
		   64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign csr_regfile$mav_read_csr_csr_addr = 12'h0 ;
  assign csr_regfile$mv_update_fcsr_fflags_flags = stage3_rg_stage3[495:491] ;
  assign csr_regfile$mv_update_mstatus_fs_fs = 2'h3 ;
  assign csr_regfile$nmi_req_set_not_clear = nmi_req_set_not_clear ;
  assign csr_regfile$read_csr_csr_addr = rg_trap_instr[31:20] ;
  assign csr_regfile$read_csr_port2_csr_addr = f_csr_reqs$D_OUT[75:64] ;
  assign csr_regfile$s_external_interrupt_req_set_not_clear =
	     s_external_interrupt_req_set_not_clear ;
  assign csr_regfile$software_interrupt_req_set_not_clear =
	     software_interrupt_req_set_not_clear ;
  assign csr_regfile$timer_interrupt_req_set_not_clear =
	     timer_interrupt_req_set_not_clear ;
  always@(MUX_csr_regfile$write_dcsr_cause_priv_1__SEL_1 or
	  WILL_FIRE_RL_rl_stage1_stop or
	  MUX_csr_regfile$write_dcsr_cause_priv_1__VAL_2 or
	  WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_csr_regfile$write_dcsr_cause_priv_1__SEL_1:
	  csr_regfile$write_dcsr_cause_priv_cause = 3'd3;
      WILL_FIRE_RL_rl_stage1_stop:
	  csr_regfile$write_dcsr_cause_priv_cause =
	      MUX_csr_regfile$write_dcsr_cause_priv_1__VAL_2;
      WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode:
	  csr_regfile$write_dcsr_cause_priv_cause = 3'd1;
      default: csr_regfile$write_dcsr_cause_priv_cause =
		   3'b010 /* unspecified value */ ;
    endcase
  end
  assign csr_regfile$write_dcsr_cause_priv_priv =
	     (WILL_FIRE_RL_rl_stage1_stop ||
	      WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode) ?
	       rg_cur_priv :
	       2'b11 ;
  assign csr_regfile$write_dpc_pc =
	     MUX_csr_regfile$write_dcsr_cause_priv_1__SEL_1 ?
	       soc_map$m_pc_reset_value :
	       stage1_rg_stage_input[401:338] ;
  assign csr_regfile$EN_server_reset_request_put =
	     CAN_FIRE_RL_rl_reset_start ;
  assign csr_regfile$EN_server_reset_response_get =
	     MUX_rg_state$write_1__SEL_2 ;
  assign csr_regfile$EN_mav_read_csr = 1'b0 ;
  assign csr_regfile$EN_mav_csr_write =
	     WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	     csr_regfile$access_permitted_1 ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	     csr_regfile$access_permitted_2 &&
	     rg_trap_instr[19:15] != 5'd0 ||
	     WILL_FIRE_RL_rl_debug_write_csr ;
  assign csr_regfile$EN_ma_update_fcsr_fflags =
	     WILL_FIRE_RL_rl_pipe && stage3_rg_full &&
	     stage3_rg_stage3[567] &&
	     stage3_rg_stage3[497] ;
  assign csr_regfile$EN_ma_update_mstatus_fs =
	     WILL_FIRE_RL_rl_pipe && stage3_rg_full &&
	     stage3_rg_stage3[567] &&
	     (stage3_rg_stage3[497] || stage3_rg_stage3[496]) ;
  assign csr_regfile$EN_csr_trap_actions = CAN_FIRE_RL_rl_trap ;
  assign csr_regfile$EN_csr_ret_actions = CAN_FIRE_RL_rl_stage1_xRET ;
  assign csr_regfile$EN_csr_minstret_incr =
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 ==
	     2'd2 ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	     csr_regfile$access_permitted_1 ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	     csr_regfile$access_permitted_2 ||
	     WILL_FIRE_RL_rl_stage1_WFI ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_xRET ;
  assign csr_regfile$EN_write_dpc =
	     WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset ||
	     WILL_FIRE_RL_rl_stage1_stop ||
	     WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode ;
  assign csr_regfile$EN_write_dcsr_cause_priv =
	     WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset ||
	     WILL_FIRE_RL_rl_stage1_stop ||
	     WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode ;
  assign csr_regfile$EN_debug = 1'b0 ;

  // submodule f_csr_reqs
  assign f_csr_reqs$D_IN = hart0_csr_mem_server_request_put ;
  assign f_csr_reqs$ENQ = EN_hart0_csr_mem_server_request_put ;
  assign f_csr_reqs$DEQ =
	     WILL_FIRE_RL_rl_debug_csr_access_busy ||
	     WILL_FIRE_RL_rl_debug_write_csr ||
	     WILL_FIRE_RL_rl_debug_read_csr ;
  assign f_csr_reqs$CLR = 1'b0 ;

  // submodule f_csr_rsps
  always@(WILL_FIRE_RL_rl_debug_csr_access_busy or
	  WILL_FIRE_RL_rl_debug_write_csr or
	  WILL_FIRE_RL_rl_debug_read_csr or MUX_f_csr_rsps$enq_1__VAL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_rl_debug_csr_access_busy:
	  f_csr_rsps$D_IN = 65'h0AAAAAAAAAAAAAAAA;
      WILL_FIRE_RL_rl_debug_write_csr:
	  f_csr_rsps$D_IN = 65'h1AAAAAAAAAAAAAAAA;
      WILL_FIRE_RL_rl_debug_read_csr:
	  f_csr_rsps$D_IN = MUX_f_csr_rsps$enq_1__VAL_3;
      default: f_csr_rsps$D_IN =
		   65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign f_csr_rsps$ENQ =
	     WILL_FIRE_RL_rl_debug_csr_access_busy ||
	     WILL_FIRE_RL_rl_debug_write_csr ||
	     WILL_FIRE_RL_rl_debug_read_csr ;
  assign f_csr_rsps$DEQ = EN_hart0_csr_mem_server_response_get ;
  assign f_csr_rsps$CLR = 1'b0 ;

  // submodule f_fpr_reqs
  assign f_fpr_reqs$D_IN = hart0_fpr_mem_server_request_put ;
  assign f_fpr_reqs$ENQ = EN_hart0_fpr_mem_server_request_put ;
  assign f_fpr_reqs$DEQ =
	     WILL_FIRE_RL_rl_debug_fpr_access_busy ||
	     WILL_FIRE_RL_rl_debug_write_fpr ||
	     WILL_FIRE_RL_rl_debug_read_fpr ;
  assign f_fpr_reqs$CLR = 1'b0 ;

  // submodule f_fpr_rsps
  always@(WILL_FIRE_RL_rl_debug_fpr_access_busy or
	  WILL_FIRE_RL_rl_debug_write_fpr or
	  WILL_FIRE_RL_rl_debug_read_fpr or MUX_f_fpr_rsps$enq_1__VAL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_rl_debug_fpr_access_busy:
	  f_fpr_rsps$D_IN = 65'h0AAAAAAAAAAAAAAAA;
      WILL_FIRE_RL_rl_debug_write_fpr:
	  f_fpr_rsps$D_IN = 65'h1AAAAAAAAAAAAAAAA;
      WILL_FIRE_RL_rl_debug_read_fpr:
	  f_fpr_rsps$D_IN = MUX_f_fpr_rsps$enq_1__VAL_3;
      default: f_fpr_rsps$D_IN =
		   65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign f_fpr_rsps$ENQ =
	     WILL_FIRE_RL_rl_debug_fpr_access_busy ||
	     WILL_FIRE_RL_rl_debug_write_fpr ||
	     WILL_FIRE_RL_rl_debug_read_fpr ;
  assign f_fpr_rsps$DEQ = EN_hart0_fpr_mem_server_response_get ;
  assign f_fpr_rsps$CLR = 1'b0 ;

  // submodule f_gpr_reqs
  assign f_gpr_reqs$D_IN = hart0_gpr_mem_server_request_put ;
  assign f_gpr_reqs$ENQ = EN_hart0_gpr_mem_server_request_put ;
  assign f_gpr_reqs$DEQ =
	     WILL_FIRE_RL_rl_debug_gpr_access_busy ||
	     WILL_FIRE_RL_rl_debug_write_gpr ||
	     WILL_FIRE_RL_rl_debug_read_gpr ;
  assign f_gpr_reqs$CLR = 1'b0 ;

  // submodule f_gpr_rsps
  always@(WILL_FIRE_RL_rl_debug_gpr_access_busy or
	  WILL_FIRE_RL_rl_debug_write_gpr or
	  WILL_FIRE_RL_rl_debug_read_gpr or MUX_f_gpr_rsps$enq_1__VAL_3)
  begin
    case (1'b1) // synopsys parallel_case
      WILL_FIRE_RL_rl_debug_gpr_access_busy:
	  f_gpr_rsps$D_IN = 65'h0AAAAAAAAAAAAAAAA;
      WILL_FIRE_RL_rl_debug_write_gpr:
	  f_gpr_rsps$D_IN = 65'h1AAAAAAAAAAAAAAAA;
      WILL_FIRE_RL_rl_debug_read_gpr:
	  f_gpr_rsps$D_IN = MUX_f_gpr_rsps$enq_1__VAL_3;
      default: f_gpr_rsps$D_IN =
		   65'h0AAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign f_gpr_rsps$ENQ =
	     WILL_FIRE_RL_rl_debug_gpr_access_busy ||
	     WILL_FIRE_RL_rl_debug_write_gpr ||
	     WILL_FIRE_RL_rl_debug_read_gpr ;
  assign f_gpr_rsps$DEQ = EN_hart0_gpr_mem_server_response_get ;
  assign f_gpr_rsps$CLR = 1'b0 ;

  // submodule f_reset_reqs
  assign f_reset_reqs$D_IN = hart0_server_reset_request_put ;
  assign f_reset_reqs$ENQ = EN_hart0_server_reset_request_put ;
  assign f_reset_reqs$DEQ =
	     gpr_regfile$RDY_server_reset_request_put &&
	     fpr_regfile_RDY_server_reset_request_put__010__ETC___d2028 &&
	     rg_state == 4'd0 ;
  assign f_reset_reqs$CLR = 1'b0 ;

  // submodule f_reset_rsps
  assign f_reset_rsps$D_IN = rg_run_on_reset ;
  assign f_reset_rsps$ENQ = MUX_rg_state$write_1__SEL_2 ;
  assign f_reset_rsps$DEQ = EN_hart0_server_reset_response_get ;
  assign f_reset_rsps$CLR = 1'b0 ;

  // submodule f_run_halt_reqs
  assign f_run_halt_reqs$D_IN = hart0_server_run_halt_request_put ;
  assign f_run_halt_reqs$ENQ = EN_hart0_server_run_halt_request_put ;
  assign f_run_halt_reqs$DEQ =
	     WILL_FIRE_RL_rl_debug_halt_redundant ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_rl_debug_halt ||
	     WILL_FIRE_RL_rl_debug_run_redundant ;
  assign f_run_halt_reqs$CLR = 1'b0 ;

  // submodule f_run_halt_rsps
  assign f_run_halt_rsps$D_IN = !MUX_f_run_halt_rsps$enq_1__SEL_1 ;
  assign f_run_halt_rsps$ENQ =
	     WILL_FIRE_RL_rl_debug_halt_redundant ||
	     WILL_FIRE_RL_rl_BREAK_cache_flush_finish ||
	     WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode ||
	     WILL_FIRE_RL_rl_debug_run ||
	     WILL_FIRE_RL_rl_debug_run_redundant ;
  assign f_run_halt_rsps$DEQ = EN_hart0_server_run_halt_response_get ;
  assign f_run_halt_rsps$CLR = 1'b0 ;

  // submodule f_trace_data
  always@(MUX_f_trace_data$enq_1__SEL_1 or
	  MUX_f_trace_data$enq_1__VAL_1 or
	  MUX_csr_regfile$mav_csr_write_1__SEL_1 or
	  MUX_f_trace_data$enq_1__VAL_2 or
	  MUX_f_trace_data$enq_1__SEL_3 or
	  MUX_f_trace_data$enq_1__VAL_3 or
	  MUX_f_trace_data$enq_1__SEL_4 or
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2420 or
	  WILL_FIRE_RL_rl_reset_start or
	  WILL_FIRE_RL_rl_stage1_mip_cmd or
	  MUX_f_trace_data$enq_1__VAL_6 or
	  WILL_FIRE_RL_rl_trap or
	  MUX_f_trace_data$enq_1__VAL_7 or
	  WILL_FIRE_RL_rl_stage1_xRET or MUX_f_trace_data$enq_1__VAL_8)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_f_trace_data$enq_1__SEL_1:
	  f_trace_data$D_IN = MUX_f_trace_data$enq_1__VAL_1;
      MUX_csr_regfile$mav_csr_write_1__SEL_1:
	  f_trace_data$D_IN = MUX_f_trace_data$enq_1__VAL_2;
      MUX_f_trace_data$enq_1__SEL_3:
	  f_trace_data$D_IN = MUX_f_trace_data$enq_1__VAL_3;
      MUX_f_trace_data$enq_1__SEL_4:
	  f_trace_data$D_IN =
	      IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2420;
      WILL_FIRE_RL_rl_reset_start:
	  f_trace_data$D_IN =
	      427'h02AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
      WILL_FIRE_RL_rl_stage1_mip_cmd:
	  f_trace_data$D_IN = MUX_f_trace_data$enq_1__VAL_6;
      WILL_FIRE_RL_rl_trap: f_trace_data$D_IN = MUX_f_trace_data$enq_1__VAL_7;
      WILL_FIRE_RL_rl_stage1_xRET:
	  f_trace_data$D_IN = MUX_f_trace_data$enq_1__VAL_8;
      default: f_trace_data$D_IN =
		   427'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign f_trace_data$ENQ =
	     WILL_FIRE_RL_rl_pipe && stage3_rg_full ||
	     WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	     csr_regfile$access_permitted_1 ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	     csr_regfile$access_permitted_2 ||
	     WILL_FIRE_RL_rl_stage1_WFI ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_reset_start ||
	     WILL_FIRE_RL_rl_stage1_mip_cmd ||
	     WILL_FIRE_RL_rl_trap ||
	     WILL_FIRE_RL_rl_stage1_xRET ;
  assign f_trace_data$DEQ = EN_trace_data_out_get ;
  assign f_trace_data$CLR = 1'b0 ;

  // submodule fpr_regfile
  assign fpr_regfile$read_rs1_port2_rs1 = f_fpr_reqs$D_OUT[68:64] ;
  assign fpr_regfile$read_rs1_rs1 = stage1_rg_stage_input[139:135] ;
  assign fpr_regfile$read_rs2_rs2 = stage1_rg_stage_input[134:130] ;
  assign fpr_regfile$read_rs3_rs3 = stage1_rg_stage_input[129:125] ;
  assign fpr_regfile$write_rd_rd =
	     MUX_fpr_regfile$write_rd_1__SEL_1 ?
	       stage3_rg_stage3[566:562] :
	       f_fpr_reqs$D_OUT[68:64] ;
  assign fpr_regfile$write_rd_rd_val =
	     MUX_fpr_regfile$write_rd_1__SEL_1 ?
	       stage3_rg_stage3[490:427] :
	       f_fpr_reqs$D_OUT[63:0] ;
  assign fpr_regfile$EN_server_reset_request_put =
	     CAN_FIRE_RL_rl_reset_start ;
  assign fpr_regfile$EN_server_reset_response_get =
	     MUX_rg_state$write_1__SEL_2 ;
  assign fpr_regfile$EN_write_rd =
	     WILL_FIRE_RL_rl_pipe && stage3_rg_full &&
	     stage3_rg_stage3[567] &&
	     stage3_rg_stage3[496] ||
	     WILL_FIRE_RL_rl_debug_write_fpr ;

  // submodule gpr_regfile
  assign gpr_regfile$read_rs1_port2_rs1 = f_gpr_reqs$D_OUT[68:64] ;
  assign gpr_regfile$read_rs1_rs1 = stage1_rg_stage_input[139:135] ;
  assign gpr_regfile$read_rs2_rs2 = stage1_rg_stage_input[134:130] ;
  always@(MUX_csr_regfile$mav_csr_write_1__SEL_1 or
	  MUX_f_trace_data$enq_1__SEL_3 or
	  rg_trap_instr or
	  WILL_FIRE_RL_rl_debug_write_gpr or
	  f_gpr_reqs$D_OUT or
	  MUX_gpr_regfile$write_rd_1__SEL_3 or stage3_rg_stage3)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_csr_regfile$mav_csr_write_1__SEL_1 || MUX_f_trace_data$enq_1__SEL_3:
	  gpr_regfile$write_rd_rd = rg_trap_instr[11:7];
      WILL_FIRE_RL_rl_debug_write_gpr:
	  gpr_regfile$write_rd_rd = f_gpr_reqs$D_OUT[68:64];
      MUX_gpr_regfile$write_rd_1__SEL_3:
	  gpr_regfile$write_rd_rd = stage3_rg_stage3[566:562];
      default: gpr_regfile$write_rd_rd = 5'b01010 /* unspecified value */ ;
    endcase
  end
  always@(MUX_csr_regfile$mav_csr_write_1__SEL_1 or
	  MUX_f_trace_data$enq_1__SEL_3 or
	  csr_regfile$read_csr or
	  WILL_FIRE_RL_rl_debug_write_gpr or
	  f_gpr_reqs$D_OUT or
	  MUX_gpr_regfile$write_rd_1__SEL_3 or stage3_rg_stage3)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_csr_regfile$mav_csr_write_1__SEL_1 || MUX_f_trace_data$enq_1__SEL_3:
	  gpr_regfile$write_rd_rd_val = csr_regfile$read_csr[63:0];
      WILL_FIRE_RL_rl_debug_write_gpr:
	  gpr_regfile$write_rd_rd_val = f_gpr_reqs$D_OUT[63:0];
      MUX_gpr_regfile$write_rd_1__SEL_3:
	  gpr_regfile$write_rd_rd_val = stage3_rg_stage3[561:498];
      default: gpr_regfile$write_rd_rd_val =
		   64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign gpr_regfile$EN_server_reset_request_put =
	     CAN_FIRE_RL_rl_reset_start ;
  assign gpr_regfile$EN_server_reset_response_get =
	     MUX_rg_state$write_1__SEL_2 ;
  assign gpr_regfile$EN_write_rd =
	     WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	     csr_regfile$access_permitted_1 ||
	     WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	     csr_regfile$access_permitted_2 ||
	     WILL_FIRE_RL_rl_pipe && stage3_rg_full &&
	     stage3_rg_stage3[567] &&
	     !stage3_rg_stage3[496] ||
	     WILL_FIRE_RL_rl_debug_write_gpr ;

  // submodule near_mem
  assign near_mem$dma_server_araddr = dma_server_araddr ;
  assign near_mem$dma_server_arburst = dma_server_arburst ;
  assign near_mem$dma_server_arcache = dma_server_arcache ;
  assign near_mem$dma_server_arid = dma_server_arid ;
  assign near_mem$dma_server_arlen = dma_server_arlen ;
  assign near_mem$dma_server_arlock = dma_server_arlock ;
  assign near_mem$dma_server_arprot = dma_server_arprot ;
  assign near_mem$dma_server_arqos = dma_server_arqos ;
  assign near_mem$dma_server_arregion = dma_server_arregion ;
  assign near_mem$dma_server_arsize = dma_server_arsize ;
  assign near_mem$dma_server_arvalid = dma_server_arvalid ;
  assign near_mem$dma_server_awaddr = dma_server_awaddr ;
  assign near_mem$dma_server_awburst = dma_server_awburst ;
  assign near_mem$dma_server_awcache = dma_server_awcache ;
  assign near_mem$dma_server_awid = dma_server_awid ;
  assign near_mem$dma_server_awlen = dma_server_awlen ;
  assign near_mem$dma_server_awlock = dma_server_awlock ;
  assign near_mem$dma_server_awprot = dma_server_awprot ;
  assign near_mem$dma_server_awqos = dma_server_awqos ;
  assign near_mem$dma_server_awregion = dma_server_awregion ;
  assign near_mem$dma_server_awsize = dma_server_awsize ;
  assign near_mem$dma_server_awvalid = dma_server_awvalid ;
  assign near_mem$dma_server_bready = dma_server_bready ;
  assign near_mem$dma_server_rready = dma_server_rready ;
  assign near_mem$dma_server_wdata = dma_server_wdata ;
  assign near_mem$dma_server_wlast = dma_server_wlast ;
  assign near_mem$dma_server_wstrb = dma_server_wstrb ;
  assign near_mem$dma_server_wvalid = dma_server_wvalid ;
  assign near_mem$dmem_req_addr = x_out_data_to_stage2_addr__h10376 ;
  assign near_mem$dmem_req_amo_funct7 =
	     x_out_data_to_stage2_val1__h10377[6:0] ;
  assign near_mem$dmem_req_f3 = MUX_rg_trap_instr$write_1__VAL_1[14:12] ;
  assign near_mem$dmem_req_mstatus_MXR = csr_regfile$read_mstatus[19] ;
  always@(IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153)
  begin
    case (IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153)
      3'd1: near_mem$dmem_req_op = 2'd0;
      3'd2: near_mem$dmem_req_op = 2'd1;
      default: near_mem$dmem_req_op = 2'd2;
    endcase
  end
  assign near_mem$dmem_req_priv =
	     csr_regfile$read_mstatus[17] ?
	       csr_regfile$read_mstatus[12:11] :
	       rg_cur_priv ;
  assign near_mem$dmem_req_satp = csr_regfile$read_satp ;
  assign near_mem$dmem_req_sstatus_SUM = csr_regfile$read_sstatus[18] ;
  always@(stage1_rg_stage_input or
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d1316 or
	  alu_outputs___1_fval2__h10945 or branch_target__h10519)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0100111:
	  near_mem$dmem_req_store_value = alu_outputs___1_fval2__h10945;
      7'b1100011: near_mem$dmem_req_store_value = branch_target__h10519;
      default: near_mem$dmem_req_store_value =
		   IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d1316;
    endcase
  end
  assign near_mem$imem_master_arready = imem_master_arready ;
  assign near_mem$imem_master_awready = imem_master_awready ;
  assign near_mem$imem_master_bid = imem_master_bid ;
  assign near_mem$imem_master_bresp = imem_master_bresp ;
  assign near_mem$imem_master_bvalid = imem_master_bvalid ;
  assign near_mem$imem_master_rdata = imem_master_rdata ;
  assign near_mem$imem_master_rid = imem_master_rid ;
  assign near_mem$imem_master_rlast = imem_master_rlast ;
  assign near_mem$imem_master_rresp = imem_master_rresp ;
  assign near_mem$imem_master_rvalid = imem_master_rvalid ;
  assign near_mem$imem_master_wready = imem_master_wready ;
  always@(MUX_imem_rg_f3$write_1__SEL_1 or
	  MUX_near_mem$imem_req_2__VAL_1 or
	  MUX_imem_rg_cache_addr$write_1__SEL_3 or
	  MUX_near_mem$imem_req_2__VAL_2 or
	  WILL_FIRE_RL_imem_rl_fetch_next_32b or
	  MUX_imem_rg_tval$write_1__VAL_5 or
	  MUX_imem_rg_pc$write_1__SEL_3 or
	  MUX_near_mem$imem_req_2__VAL_4 or
	  WILL_FIRE_RL_rl_debug_run or MUX_near_mem$imem_req_2__VAL_5)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_imem_rg_f3$write_1__SEL_1:
	  near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_1;
      MUX_imem_rg_cache_addr$write_1__SEL_3:
	  near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_2;
      WILL_FIRE_RL_imem_rl_fetch_next_32b:
	  near_mem$imem_req_addr = MUX_imem_rg_tval$write_1__VAL_5;
      MUX_imem_rg_pc$write_1__SEL_3:
	  near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_4;
      WILL_FIRE_RL_rl_debug_run:
	  near_mem$imem_req_addr = MUX_near_mem$imem_req_2__VAL_5;
      default: near_mem$imem_req_addr =
		   64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign near_mem$imem_req_f3 =
	     WILL_FIRE_RL_imem_rl_fetch_next_32b ? imem_rg_f3 : 3'b010 ;
  assign near_mem$imem_req_mstatus_MXR =
	     (MUX_imem_rg_f3$write_1__SEL_1 ||
	      MUX_imem_rg_cache_addr$write_1__SEL_3 ||
	      MUX_imem_rg_pc$write_1__SEL_3 ||
	      WILL_FIRE_RL_rl_debug_run) ?
	       csr_regfile$read_mstatus[19] :
	       imem_rg_mstatus_MXR ;
  assign near_mem$imem_req_priv =
	     (MUX_imem_rg_f3$write_1__SEL_1 ||
	      MUX_imem_rg_cache_addr$write_1__SEL_3 ||
	      MUX_imem_rg_pc$write_1__SEL_3 ||
	      WILL_FIRE_RL_rl_debug_run) ?
	       rg_cur_priv :
	       imem_rg_priv ;
  assign near_mem$imem_req_satp =
	     WILL_FIRE_RL_imem_rl_fetch_next_32b ?
	       imem_rg_satp :
	       csr_regfile$read_satp ;
  assign near_mem$imem_req_sstatus_SUM =
	     (MUX_imem_rg_f3$write_1__SEL_1 ||
	      MUX_imem_rg_cache_addr$write_1__SEL_3 ||
	      MUX_imem_rg_pc$write_1__SEL_3 ||
	      WILL_FIRE_RL_rl_debug_run) ?
	       csr_regfile$read_sstatus[18] :
	       imem_rg_sstatus_SUM ;
  assign near_mem$mem_master_arready = mem_master_arready ;
  assign near_mem$mem_master_awready = mem_master_awready ;
  assign near_mem$mem_master_bid = mem_master_bid ;
  assign near_mem$mem_master_bresp = mem_master_bresp ;
  assign near_mem$mem_master_bvalid = mem_master_bvalid ;
  assign near_mem$mem_master_rdata = mem_master_rdata ;
  assign near_mem$mem_master_rid = mem_master_rid ;
  assign near_mem$mem_master_rlast = mem_master_rlast ;
  assign near_mem$mem_master_rresp = mem_master_rresp ;
  assign near_mem$mem_master_rvalid = mem_master_rvalid ;
  assign near_mem$mem_master_wready = mem_master_wready ;
  assign near_mem$server_fence_request_put =
	     8'b10101010 /* unspecified value */  ;
  assign near_mem$EN_server_reset_request_put = CAN_FIRE_RL_rl_reset_start ;
  assign near_mem$EN_server_reset_response_get = MUX_rg_state$write_1__SEL_2 ;
  assign near_mem$EN_imem_req =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2550 ||
	     WILL_FIRE_RL_imem_rl_fetch_next_32b ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_rl_debug_run ;
  assign near_mem$EN_dmem_req =
	     WILL_FIRE_RL_rl_pipe &&
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2283 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd0 &&
	     IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d2088 &&
	     (IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153 ==
	      3'd1 ||
	      IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153 ==
	      3'd2 ||
	      IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153 ==
	      3'd4) ;
  assign near_mem$EN_server_fence_i_request_put =
	     WILL_FIRE_RL_rl_stage1_stop ||
	     WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode ||
	     WILL_FIRE_RL_rl_stage1_FENCE_I ;
  assign near_mem$EN_server_fence_i_response_get =
	     WILL_FIRE_RL_rl_BREAK_cache_flush_finish ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ;
  assign near_mem$EN_server_fence_request_put = CAN_FIRE_RL_rl_stage1_FENCE ;
  assign near_mem$EN_server_fence_response_get = CAN_FIRE_RL_rl_finish_FENCE ;
  assign near_mem$EN_sfence_vma_server_request_put =
	     CAN_FIRE_RL_rl_stage1_SFENCE_VMA ;
  assign near_mem$EN_sfence_vma_server_response_get =
	     CAN_FIRE_RL_rl_finish_SFENCE_VMA ;
  assign near_mem$EN_ma_ddr4_ready = EN_ma_ddr4_ready ;

  // submodule soc_map
  assign soc_map$m_is_IO_addr_addr = 64'h0 ;
  assign soc_map$m_is_mem_addr_addr = 64'h0 ;
  assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;

  // submodule stage1_f_reset_reqs
  assign stage1_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
  assign stage1_f_reset_reqs$DEQ = CAN_FIRE_RL_stage1_rl_reset ;
  assign stage1_f_reset_reqs$CLR = 1'b0 ;

  // submodule stage1_f_reset_rsps
  assign stage1_f_reset_rsps$ENQ = CAN_FIRE_RL_stage1_rl_reset ;
  assign stage1_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
  assign stage1_f_reset_rsps$CLR = 1'b0 ;

  // submodule stage2_f_reset_reqs
  assign stage2_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
  assign stage2_f_reset_reqs$DEQ = CAN_FIRE_RL_stage2_rl_reset_begin ;
  assign stage2_f_reset_reqs$CLR = 1'b0 ;

  // submodule stage2_f_reset_rsps
  assign stage2_f_reset_rsps$ENQ = CAN_FIRE_RL_stage2_rl_reset_end ;
  assign stage2_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
  assign stage2_f_reset_rsps$CLR = 1'b0 ;

  // submodule stage2_fbox
  assign stage2_fbox$req_f7 = MUX_rg_trap_instr$write_1__VAL_1[31:25] ;
  assign stage2_fbox$req_opcode = MUX_rg_trap_instr$write_1__VAL_1[6:0] ;
  assign stage2_fbox$req_rm = x_out_data_to_stage2_rounding_mode__h10385 ;
  assign stage2_fbox$req_rs2 = MUX_rg_trap_instr$write_1__VAL_1[24:20] ;
  assign stage2_fbox$req_v1 =
	     stage1_rg_stage_input_17_BITS_151_TO_145_59_EQ_ETC___d2328 ?
	       x_out_data_to_stage2_val1__h10377 :
	       x_out_data_to_stage2_fval1__h10379 ;
  assign stage2_fbox$req_v2 = alu_outputs___1_fval2__h10945 ;
  assign stage2_fbox$req_v3 = x_out_data_to_stage2_fval3__h10381 ;
  assign stage2_fbox$EN_server_reset_request_put =
	     CAN_FIRE_RL_stage2_rl_reset_begin ;
  assign stage2_fbox$EN_server_reset_response_get =
	     CAN_FIRE_RL_stage2_rl_reset_end ;
  assign stage2_fbox$EN_req =
	     WILL_FIRE_RL_rl_pipe &&
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2283 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd0 &&
	     IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d2088 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153 ==
	     3'd5 ;

  // submodule stage2_mbox
  assign stage2_mbox$req_f3 = MUX_rg_trap_instr$write_1__VAL_1[14:12] ;
  assign stage2_mbox$req_is_OP_not_OP_32 =
	     !MUX_rg_trap_instr$write_1__VAL_1[3] ;
  assign stage2_mbox$req_v1 = x_out_data_to_stage2_val1__h10377 ;
  assign stage2_mbox$req_v2 = x_out_data_to_stage2_val2__h10378 ;
  assign stage2_mbox$set_verbosity_verbosity = 4'h0 ;
  assign stage2_mbox$EN_set_verbosity = 1'b0 ;
  assign stage2_mbox$EN_req_reset = 1'b0 ;
  assign stage2_mbox$EN_rsp_reset = 1'b0 ;
  assign stage2_mbox$EN_req =
	     WILL_FIRE_RL_rl_pipe &&
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2283 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd0 &&
	     IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d2088 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153 ==
	     3'd3 ;

  // submodule stage3_f_reset_reqs
  assign stage3_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
  assign stage3_f_reset_reqs$DEQ = CAN_FIRE_RL_stage3_rl_reset ;
  assign stage3_f_reset_reqs$CLR = 1'b0 ;

  // submodule stage3_f_reset_rsps
  assign stage3_f_reset_rsps$ENQ = CAN_FIRE_RL_stage3_rl_reset ;
  assign stage3_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
  assign stage3_f_reset_rsps$CLR = 1'b0 ;

  // submodule stageD_f_reset_reqs
  assign stageD_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
  assign stageD_f_reset_reqs$DEQ = CAN_FIRE_RL_stageD_rl_reset ;
  assign stageD_f_reset_reqs$CLR = 1'b0 ;

  // submodule stageD_f_reset_rsps
  assign stageD_f_reset_rsps$ENQ = CAN_FIRE_RL_stageD_rl_reset ;
  assign stageD_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
  assign stageD_f_reset_rsps$CLR = 1'b0 ;

  // submodule stageF_branch_predictor
  assign stageF_branch_predictor$bp_train_cf_info =
	     stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d2562 ?
	       { IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d1086,
		 stage1_rg_stage_input[401:338],
		 stage1_rg_stage_input[151:145] != 7'b1100011 ||
		 IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d407,
		 alu_outputs_cf_info_fallthru_PC__h14797,
		 alu_outputs_cf_info_taken_PC__h14798 } :
	       195'h6AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA ;
  assign stageF_branch_predictor$bp_train_instr = d_instr__h23510 ;
  assign stageF_branch_predictor$bp_train_is_i32_not_i16 =
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1909 ;
  assign stageF_branch_predictor$bp_train_pc = imem_rg_pc ;
  always@(MUX_imem_rg_f3$write_1__SEL_1 or
	  soc_map$m_pc_reset_value or
	  MUX_imem_rg_cache_addr$write_1__SEL_3 or
	  stageF_branch_predictor$predict_rsp or
	  MUX_imem_rg_pc$write_1__SEL_3 or
	  rg_next_pc or WILL_FIRE_RL_rl_debug_run or csr_regfile$read_dpc)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_imem_rg_f3$write_1__SEL_1:
	  stageF_branch_predictor$predict_req_pc = soc_map$m_pc_reset_value;
      MUX_imem_rg_cache_addr$write_1__SEL_3:
	  stageF_branch_predictor$predict_req_pc =
	      stageF_branch_predictor$predict_rsp;
      MUX_imem_rg_pc$write_1__SEL_3:
	  stageF_branch_predictor$predict_req_pc = rg_next_pc;
      WILL_FIRE_RL_rl_debug_run:
	  stageF_branch_predictor$predict_req_pc = csr_regfile$read_dpc;
      default: stageF_branch_predictor$predict_req_pc =
		   64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign stageF_branch_predictor$predict_rsp_instr = d_instr__h23510 ;
  assign stageF_branch_predictor$predict_rsp_is_i32_not_i16 =
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1909 ;
  assign stageF_branch_predictor$EN_reset = 1'b0 ;
  assign stageF_branch_predictor$EN_predict_req =
	     WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset ||
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2550 ||
	     WILL_FIRE_RL_rl_trap_fetch ||
	     WILL_FIRE_RL_rl_WFI_resume ||
	     WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	     WILL_FIRE_RL_rl_finish_FENCE ||
	     WILL_FIRE_RL_rl_finish_FENCE_I ||
	     WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	     WILL_FIRE_RL_rl_debug_run ;
  assign stageF_branch_predictor$EN_bp_train =
	     WILL_FIRE_RL_rl_pipe &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2528 ;

  // submodule stageF_f_reset_reqs
  assign stageF_f_reset_reqs$ENQ = CAN_FIRE_RL_rl_reset_start ;
  assign stageF_f_reset_reqs$DEQ = CAN_FIRE_RL_stageF_rl_reset ;
  assign stageF_f_reset_reqs$CLR = 1'b0 ;

  // submodule stageF_f_reset_rsps
  assign stageF_f_reset_rsps$ENQ = CAN_FIRE_RL_stageF_rl_reset ;
  assign stageF_f_reset_rsps$DEQ = MUX_rg_state$write_1__SEL_2 ;
  assign stageF_f_reset_rsps$CLR = 1'b0 ;

  // remaining internal signals
  assign IF_IF_stage1_rg_stage_input_17_BITS_151_TO_145_ETC___d1451 =
	     next_pc__h10291 == stage1_rg_stage_input[215:152] ;
  assign IF_NOT_csr_regfile_read_mstatus__2_BITS_14_TO__ETC___d986 =
	     NOT_csr_regfile_read_mstatus__2_BITS_14_TO_13__ETC___d903 ?
	       4'd1 :
	       4'd12 ;
  assign IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem__ETC___d1883 =
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1880 ?
	       { 16'b0,
		 imem_rg_pc_BITS_63_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 ?
		   near_mem$imem_instr[31:16] :
		   imem_rg_cache_b16 } :
	       near_mem$imem_instr ;
  assign IF_NOT_near_mem_dmem_valid__41_63_OR_NOT_near__ETC___d276 =
	     (!near_mem$dmem_valid || !near_mem$dmem_exc) ?
	       ((stage2_rg_stage2[821:817] == 5'd0) ? 2'd0 : 2'd1) :
	       2'd0 ;
  assign IF_NOT_near_mem_dmem_valid__41_63_OR_NOT_near__ETC___d296 =
	     (!near_mem$dmem_valid || !near_mem$dmem_exc) ?
	       (stage2_rg_stage2[432] ? 2'd1 : 2'd0) :
	       2'd0 ;
  assign IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d2088 =
	     IF_IF_stage1_rg_stage_input_17_BITS_151_TO_145_ETC___d1451 ||
	     !stageF_rg_full ||
	     near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911 ;
  assign IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d2170 =
	     !IF_IF_stage1_rg_stage_input_17_BITS_151_TO_145_ETC___d1451 &&
	     stageF_rg_full &&
	     (!near_mem$imem_valid ||
	      imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1905) ;
  assign IF_NOT_stage1_rg_stage_input_17_BITS_104_TO_98_ETC___d2336 =
	     ((stage1_rg_stage_input[104:98] != 7'h61 ||
	       stage1_rg_stage_input[134:130] != 5'd0) &&
	      (stage1_rg_stage_input[104:98] != 7'h61 ||
	       stage1_rg_stage_input[134:130] != 5'd1) &&
	      (stage1_rg_stage_input[104:98] != 7'h61 ||
	       stage1_rg_stage_input[134:130] != 5'd2) &&
	      (stage1_rg_stage_input[104:98] != 7'h61 ||
	       stage1_rg_stage_input[134:130] != 5'd3) &&
	      stage1_rg_stage_input[104:98] != 7'h71 &&
	      stage1_rg_stage_input[104:98] != 7'h51 &&
	      (stage1_rg_stage_input[104:98] != 7'h60 ||
	       stage1_rg_stage_input[134:130] != 5'd2) &&
	      (stage1_rg_stage_input[104:98] != 7'h60 ||
	       stage1_rg_stage_input[134:130] != 5'd3) &&
	      (stage1_rg_stage_input[104:98] != 7'h60 ||
	       stage1_rg_stage_input[134:130] != 5'd0) &&
	      (stage1_rg_stage_input[104:98] != 7'h60 ||
	       stage1_rg_stage_input[134:130] != 5'd1) &&
	      stage1_rg_stage_input[104:98] != 7'h70 &&
	      stage1_rg_stage_input[104:98] != 7'h50) ?
	       5'd8 :
	       5'd7 ;
  assign IF_NOT_stage1_rg_stage_input_17_BITS_112_TO_11_ETC___d930 =
	     NOT_stage1_rg_stage_input_17_BITS_112_TO_110_6_ETC___d443 ?
	       4'd12 :
	       4'd1 ;
  assign IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d301 =
	     (!stage2_rg_full || stage2_rg_stage2[824:822] == 3'd0) ?
	       2'd0 :
	       CASE_stage2_rg_stage2_BITS_824_TO_822_1_IF_NOT_ETC__q6 ;
  assign IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d326 =
	     x_out_fbypass_rd__h9983 == stage1_rg_stage_input[139:135] ;
  assign IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d327 =
	     x_out_fbypass_rd__h9983 == stage1_rg_stage_input[134:130] ;
  assign IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d330 =
	     x_out_fbypass_rd__h9983 == stage1_rg_stage_input[129:125] ;
  assign IF_csr_regfile_read_csr_rg_trap_instr_654_BITS_ETC___d2714 =
	     csr_regfile$read_csr[63:0] | rs1_val__h35619 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1724 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
	      stageD_rg_data[79:77] == 3'b001) ?
	       instr__h23003 :
	       ((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
		 stageD_rg_data[79:77] == 3'b101) ?
		  instr__h23154 :
		  32'h0) ;
  assign IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1725 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
	      stageD_rg_data[79:77] == 3'b101) ?
	       instr__h22804 :
	       IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1724 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1726 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
	      stageD_rg_data[79:77] == 3'b001 &&
	      csr_regfile$read_misa[3]) ?
	       instr__h22631 :
	       IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1725 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1727 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
	      stageD_rg_data[79:77] == 3'b011 &&
	      csr_regfile$read_misa[5]) ?
	       instr__h21823 :
	       IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1726 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1728 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
	      stageD_rg_data[79:77] == 3'b111) ?
	       instr__h21618 :
	       IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1727 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1729 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
	      stageD_rg_data[79:77] == 3'b011) ?
	       instr__h21467 :
	       IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1728 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1730 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
	      stageD_rg_data[79:77] == 3'b111) ?
	       instr__h21268 :
	       IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1729 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1732 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
	      stageD_rg_data[79:76] == 4'b1001 &&
	      stageD_rg_data[75:71] == 5'd0 &&
	      stageD_rg_data[70:66] == 5'd0) ?
	       instr__h21019 :
	       ((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
		 stageD_rg_data[75:71] != 5'd0 &&
		 stageD_rg_data[79:77] == 3'b011) ?
		  instr__h21115 :
		  IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1730) ;
  assign IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1734 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
	      stageD_rg_data[79:74] == 6'b100111 &&
	      stageD_rg_data[70:69] == 2'b01) ?
	       instr__h20723 :
	       ((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
		 stageD_rg_data[79:74] == 6'b100111 &&
		 stageD_rg_data[70:69] == 2'b0) ?
		  instr__h20861 :
		  IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1732) ;
  assign IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1736 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
	      stageD_rg_data[79:74] == 6'b100011 &&
	      stageD_rg_data[70:69] == 2'b01) ?
	       instr__h20449 :
	       ((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
		 stageD_rg_data[79:74] == 6'b100011 &&
		 stageD_rg_data[70:69] == 2'b0) ?
		  instr__h20585 :
		  IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1734) ;
  assign IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1738 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
	      stageD_rg_data[79:74] == 6'b100011 &&
	      stageD_rg_data[70:69] == 2'b11) ?
	       instr__h20177 :
	       ((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
		 stageD_rg_data[79:74] == 6'b100011 &&
		 stageD_rg_data[70:69] == 2'b10) ?
		  instr__h20313 :
		  IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1736) ;
  assign IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1739 =
	     (csr_regfile_read_misa__9_BIT_2_466_AND_stageD__ETC___d1547 &&
	      stageD_rg_data[70:66] != 5'd0) ?
	       instr__h20082 :
	       IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1738 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1740 =
	     (csr_regfile_read_misa__9_BIT_2_466_AND_stageD__ETC___d1541 &&
	      stageD_rg_data[70:66] != 5'd0) ?
	       instr__h19963 :
	       IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1739 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1742 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
	      stageD_rg_data[79:77] == 3'b100 &&
	      stageD_rg_data[75:74] == 2'b01 &&
	      imm6__h18076 != 6'd0) ?
	       instr__h19668 :
	       ((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
		 stageD_rg_data[79:77] == 3'b100 &&
		 stageD_rg_data[75:74] == 2'b10) ?
		  instr__h19785 :
		  IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1740) ;
  assign IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1743 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
	      stageD_rg_data[79:77] == 3'b100 &&
	      stageD_rg_data[75:74] == 2'b0 &&
	      imm6__h18076 != 6'd0) ?
	       instr__h19479 :
	       IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1742 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1744 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
	      stageD_rg_data[79:77] == 3'b0 &&
	      stageD_rg_data[75:71] != 5'd0 &&
	      imm6__h18076 != 6'd0) ?
	       instr__h19290 :
	       IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1743 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1746 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
	      stageD_rg_data[79:77] == 3'b011 &&
	      stageD_rg_data[75:71] == 5'd2 &&
	      nzimm10__h18745 != 10'd0) ?
	       instr__h18949 :
	       ((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
		 stageD_rg_data[79:77] == 3'b0 &&
		 nzimm10__h18960 != 10'd0) ?
		  instr__h19121 :
		  IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1744) ;
  assign IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1748 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
	      stageD_rg_data[79:77] == 3'b0 &&
	      stageD_rg_data[75:71] != 5'd0 &&
	      imm6__h18076 != 6'd0 ||
	      csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
	      stageD_rg_data[79:77] == 3'b0 &&
	      stageD_rg_data[75:71] == 5'd0 &&
	      imm6__h18076 == 6'd0) ?
	       instr__h18467 :
	       ((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
		 stageD_rg_data[79:77] == 3'b001 &&
		 stageD_rg_data[75:71] != 5'd0) ?
		  instr__h18694 :
		  IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1746) ;
  assign IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1749 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
	      stageD_rg_data[79:77] == 3'b011 &&
	      stageD_rg_data[75:71] != 5'd0 &&
	      stageD_rg_data[75:71] != 5'd2 &&
	      imm6__h18076 != 6'd0) ?
	       instr__h18338 :
	       IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1748 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1751 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
	      stageD_rg_data[79:77] == 3'b111) ?
	       instr__h17816 :
	       ((csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
		 stageD_rg_data[79:77] == 3'b010 &&
		 stageD_rg_data[75:71] != 5'd0) ?
		  instr__h18154 :
		  IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1749) ;
  assign IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1752 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
	      stageD_rg_data[79:77] == 3'b110) ?
	       instr__h17499 :
	       IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1751 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1753 =
	     (csr_regfile_read_misa__9_BIT_2_466_AND_stageD__ETC___d1547 &&
	      stageD_rg_data[70:66] == 5'd0) ?
	       instr__h17434 :
	       IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1752 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1754 =
	     (csr_regfile_read_misa__9_BIT_2_466_AND_stageD__ETC___d1541 &&
	      stageD_rg_data[70:66] == 5'd0) ?
	       instr__h17318 :
	       IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1753 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1755 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b01 &&
	      stageD_rg_data[79:77] == 3'b101) ?
	       instr__h16865 :
	       IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1754 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1756 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
	      stageD_rg_data[79:77] == 3'b110) ?
	       instr__h16636 :
	       IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1755 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1757 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b0 &&
	      stageD_rg_data[79:77] == 3'b010) ?
	       instr__h16441 :
	       IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1756 ;
  assign IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1758 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
	      stageD_rg_data[79:77] == 3'b110) ?
	       instr__h16249 :
	       IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1757 ;
  assign IF_csr_regfilemav_csr_write_BIT_64_THEN_2_ELSE_0__q1 =
	     csr_regfile$mav_csr_write[64] ? 64'd2 : 64'd0 ;
  assign IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg_p_ETC___d1884 =
	     (imem_rg_pc[1:0] == 2'b0 &&
	      imem_rg_pc_BITS_63_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 &&
	      near_mem$imem_instr[1:0] != 2'b11) ?
	       instr_out___1__h23534 :
	       IF_NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem__ETC___d1883 ;
  assign IF_near_mem_dmem_valid__41_THEN_IF_near_mem_dm_ETC___d144 =
	     near_mem$dmem_valid ? (near_mem$dmem_exc ? 2'd3 : 2'd2) : 2'd1 ;
  assign IF_rg_cur_priv_1_EQ_0b11_45_OR_rg_cur_priv_1_E_ETC___d974 =
	     ((rg_cur_priv == 2'b11 ||
	       rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[22]) &&
	      stage1_rg_stage_input[87:76] == 12'b000100000010) ?
	       4'd9 :
	       (rg_cur_priv_1_EQ_0b11_45_OR_rg_cur_priv_1_EQ_0_ETC___d972 ?
		  4'd11 :
		  4'd12) ;
  assign IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d936 =
	     ((stage1_rg_stage_input[112:110] == 3'b0 ||
	       stage1_rg_stage_input[112:110] == 3'b100 ||
	       stage1_rg_stage_input[112:110] == 3'b001 ||
	       stage1_rg_stage_input[112:110] == 3'b101 ||
	       stage1_rg_stage_input[112:110] == 3'b010 ||
	       stage1_rg_stage_input[112:110] == 3'b110 ||
	       stage1_rg_stage_input[112:110] == 3'b011) &&
	      (stage1_rg_stage_input[151:145] != 7'b0000111 ||
	       csr_regfile$read_mstatus[14:13] != 2'h0)) ?
	       4'd1 :
	       4'd12 ;
  assign IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d940 =
	     ((stage1_rg_stage_input[112:110] == 3'b0 ||
	       stage1_rg_stage_input[112:110] == 3'b001 ||
	       stage1_rg_stage_input[112:110] == 3'b010 ||
	       stage1_rg_stage_input[112:110] == 3'b011) &&
	      (stage1_rg_stage_input[151:145] != 7'b0100111 ||
	       csr_regfile$read_mstatus[14:13] != 2'h0)) ?
	       4'd1 :
	       4'd12 ;
  assign IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d1115 =
	     rs1_val_bypassed__h5803 +
	     SEXT_stage1_rg_stage_input_17_BITS_87_TO_76_53___d1114 ;
  assign IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d396 =
	     rs1_val_bypassed__h5803 == rs2_val__h10515 ;
  assign IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d398 =
	     (rs1_val_bypassed__h5803 ^ 64'h8000000000000000) <
	     (rs2_val__h10515 ^ 64'h8000000000000000) ;
  assign IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d400 =
	     rs1_val_bypassed__h5803 < rs2_val__h10515 ;
  assign IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC__q21 =
	     IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d1115[31:0] ;
  assign IF_stage1_rg_stage_input_17_BITS_144_TO_140_43_ETC___d978 =
	     stage1_rg_stage_input_17_BITS_144_TO_140_43_EQ_ETC___d951 ?
	       4'd7 :
	       ((stage1_rg_stage_input[144:140] == 5'd0 &&
		 stage1_rg_stage_input[139:135] == 5'd0) ?
		  IF_stage1_rg_stage_input_17_BITS_87_TO_76_53_E_ETC___d976 :
		  4'd12) ;
  assign IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d1306 =
	     ((stage1_rg_stage_input[151:145] == 7'b0010011 ||
	       stage1_rg_stage_input[151:145] == 7'b0110011) &&
	      (stage1_rg_stage_input[112:110] == 3'b001 ||
	       stage1_rg_stage_input[112:110] == 3'b101)) ?
	       _theResult____h10689 :
	       IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d1305 ;
  assign IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d1307 =
	     ((stage1_rg_stage_input[151:145] == 7'b0110011 ||
	       stage1_rg_stage_input[151:145] == 7'b0111011) &&
	      stage1_rg_stage_input[104:98] == 7'b0000001) ?
	       rs1_val_bypassed__h5803 :
	       IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d1306 ;
  assign IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d1316 =
	     ((stage1_rg_stage_input[151:145] == 7'b0110011 ||
	       stage1_rg_stage_input[151:145] == 7'b0111011) &&
	      stage1_rg_stage_input[104:98] == 7'b0000001) ?
	       rs2_val__h10515 :
	       CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q24 ;
  assign IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2334 =
	     (stage1_rg_stage_input[151:145] == 7'b0000111) ? 5'd10 : 5'd9 ;
  assign IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2335 =
	     (stage1_rg_stage_input[151:145] == 7'b0100111) ? 5'd12 : 5'd11 ;
  assign IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2374 =
	     ((stage1_rg_stage_input[151:145] == 7'b0010011 ||
	       stage1_rg_stage_input[151:145] == 7'b0110011) &&
	      (stage1_rg_stage_input[112:110] == 3'b001 ||
	       stage1_rg_stage_input[112:110] == 3'b101)) ?
	       _theResult____h10689 :
	       IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2373 ;
  assign IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d725 =
	     (stage1_rg_stage_input[151:145] == 7'b1100011) ?
	       stage1_rg_stage_input[112:110] != 3'b0 &&
	       stage1_rg_stage_input[112:110] != 3'b001 &&
	       stage1_rg_stage_input[112:110] != 3'b100 &&
	       stage1_rg_stage_input[112:110] != 3'b101 &&
	       stage1_rg_stage_input[112:110] != 3'b110 &&
	       stage1_rg_stage_input[112:110] != 3'b111 ||
	       IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d407 :
	       stage1_rg_stage_input[151:145] == 7'b1101111 ||
	       stage1_rg_stage_input[151:145] == 7'b1100111 ||
	       (stage1_rg_stage_input[151:145] != 7'b0110011 ||
		stage1_rg_stage_input[104:98] != 7'b0000001) &&
	       (stage1_rg_stage_input[151:145] != 7'b0111011 ||
		stage1_rg_stage_input[104:98] != 7'b0000001) &&
	       (stage1_rg_stage_input[151:145] != 7'b0010011 &&
		stage1_rg_stage_input[151:145] != 7'b0110011 ||
		stage1_rg_stage_input[112:110] != 3'b001 &&
		stage1_rg_stage_input[112:110] != 3'b101) &&
	       IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d722 ;
  assign IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d736 =
	     (stage1_rg_stage_input[151:145] == 7'b1100011) ?
	       stage1_rg_stage_input[112:110] != 3'b0 &&
	       stage1_rg_stage_input[112:110] != 3'b001 &&
	       stage1_rg_stage_input[112:110] != 3'b100 &&
	       stage1_rg_stage_input[112:110] != 3'b101 &&
	       stage1_rg_stage_input[112:110] != 3'b110 &&
	       stage1_rg_stage_input[112:110] != 3'b111 ||
	       IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d731 :
	       stage1_rg_stage_input[151:145] != 7'b1101111 &&
	       stage1_rg_stage_input[151:145] != 7'b1100111 ;
  assign IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d918 =
	     (stage1_rg_stage_input[151:145] == 7'b1100011) ?
	       (stage1_rg_stage_input[112:110] == 3'b0 ||
		stage1_rg_stage_input[112:110] == 3'b001 ||
		stage1_rg_stage_input[112:110] == 3'b100 ||
		stage1_rg_stage_input[112:110] == 3'b101 ||
		stage1_rg_stage_input[112:110] == 3'b110 ||
		stage1_rg_stage_input[112:110] == 3'b111) &&
	       IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d731 :
	       stage1_rg_stage_input[151:145] != 7'b1101111 &&
	       stage1_rg_stage_input[151:145] != 7'b1100111 &&
	       (stage1_rg_stage_input_17_BITS_151_TO_145_59_EQ_ETC___d756 ||
		IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d915) ;
  assign IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d920 =
	     (stage1_rg_stage_input[151:145] == 7'b1100011) ?
	       (stage1_rg_stage_input[112:110] == 3'b0 ||
		stage1_rg_stage_input[112:110] == 3'b001 ||
		stage1_rg_stage_input[112:110] == 3'b100 ||
		stage1_rg_stage_input[112:110] == 3'b101 ||
		stage1_rg_stage_input[112:110] == 3'b110 ||
		stage1_rg_stage_input[112:110] == 3'b111) &&
	       IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d407 :
	       stage1_rg_stage_input[151:145] == 7'b1101111 ||
	       stage1_rg_stage_input[151:145] == 7'b1100111 ;
  assign IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 =
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ?
	       (stage1_rg_stage_input[332] ?
		  4'd12 :
		  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d1001) :
	       4'd0 ;
  assign IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153 =
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ?
	       CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q23 :
	       3'd0 ;
  assign IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2132 =
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2128 ?
	       IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	       4'd0 &&
	       !IF_IF_stage1_rg_stage_input_17_BITS_151_TO_145_ETC___d1451 &&
	       stageF_rg_full &&
	       (!near_mem$imem_valid ||
		imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1905) :
	       stage1_rg_full ;
  assign IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2135 =
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2132 &&
	     stageD_rg_full ||
	     !stageF_rg_full ||
	     !near_mem$imem_valid ||
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1905 ;
  assign IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2420 =
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ?
	       { IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2345,
		 alu_outputs_trace_data_pc__h28334,
		 stage1_rg_stage_input[333],
		 alu_outputs___1_trace_data_instr__h28290,
		 alu_outputs_trace_data_rd__h28337,
		 alu_outputs_trace_data_word1__h28338,
		 alu_outputs_trace_data_word2__h28339,
		 alu_outputs_trace_data_word3__h28340,
		 alu_outputs_trace_data_word4__h28341,
		 alu_outputs___1_trace_data_word5__h28120 } :
	       { IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2345,
		 alu_outputs_trace_data_pc__h28334,
		 stage1_rg_stage_input[333],
		 alu_outputs___1_trace_data_instr__h28290,
		 alu_outputs_trace_data_rd__h28337,
		 alu_outputs_trace_data_word1__h28338,
		 alu_outputs_trace_data_word2__h28339,
		 alu_outputs_trace_data_word3__h28340,
		 alu_outputs_trace_data_word4__h28341,
		 alu_outputs___1_trace_data_word5__h28120 } ;
  assign IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2487 =
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2128 ?
	       IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 ==
	       4'd0 ||
	       IF_IF_stage1_rg_stage_input_17_BITS_151_TO_145_ETC___d1451 ||
	       !stageF_rg_full ||
	       near_mem$imem_valid &&
	       NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911 :
	       !stage1_rg_full ;
  assign IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2528 =
	     (IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2487 ||
	      !stageD_rg_full) &&
	     stageF_rg_full &&
	     near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911 ;
  assign IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2535 =
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2528 &&
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2142 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd0 &&
	     !IF_IF_stage1_rg_stage_input_17_BITS_151_TO_145_ETC___d1451 ;
  assign IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2550 =
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2528 &&
	     (NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2545 ||
	      IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 ==
	      4'd0 ||
	      IF_IF_stage1_rg_stage_input_17_BITS_151_TO_145_ETC___d1451) ;
  assign IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2574 =
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2128 ?
	       IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	       4'd0 &&
	       IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d2170 :
	       stage1_rg_full ;
  assign IF_stage2_fbox_valid__47_THEN_2_ELSE_1___d148 =
	     stage2_fbox$valid ? 2'd2 : 2'd1 ;
  assign IF_stage2_mbox_valid__45_THEN_2_ELSE_1___d146 =
	     stage2_mbox$valid ? 2'd2 : 2'd1 ;
  assign IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 =
	     stage2_rg_full ?
	       CASE_stage2_rg_stage2_BITS_824_TO_822_0_2_1_IF_ETC__q4 :
	       2'd0 ;
  assign IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d2105 =
	     IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333 ||
	     stage1_rg_stage_input[332] ||
	     IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d725 &&
	     IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d736 ;
  assign IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d2260 =
	     IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 ==
	     2'd2 &&
	     NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53 &&
	     stage2_rg_stage2[824:822] != 3'd0 &&
	     CASE_stage2_rg_stage2_BITS_824_TO_822_1_stage2_ETC__q28 ;
  assign IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d2262 =
	     IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 ==
	     2'd2 &&
	     NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53 &&
	     (stage2_rg_stage2[824:822] == 3'd0 ||
	      CASE_stage2_rg_stage2_BITS_824_TO_822_1_NOT_st_ETC__q29) ;
  assign IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d283 =
	     stage2_rg_full ?
	       CASE_stage2_rg_stage2_BITS_824_TO_822_0_2_1_IF_ETC__q5 :
	       2'd0 ;
  assign IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d321 =
	     x_out_bypass_rd__h9855 == stage1_rg_stage_input[139:135] ;
  assign IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d323 =
	     x_out_bypass_rd__h9855 == stage1_rg_stage_input[134:130] ;
  assign IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333 =
	     IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d283 ==
	     2'd1 &&
	     (IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d321 ||
	      IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d323) ||
	     IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d301 ==
	     2'd1 &&
	     (IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d326 ||
	      IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d327 ||
	      IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d330) ;
  assign IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923 =
	     IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333 ||
	     !stage1_rg_stage_input[332] &&
	     (IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d918 ||
	      IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d920) ;
  assign IF_stage2_rg_stage2_18_BITS_824_TO_822_19_EQ_0_ETC___d2240 =
	     { stage2_rg_stage2[255:128],
	       CASE_stage2_rg_stage2_BITS_824_TO_822_0_stage2_ETC__q27 } ;
  assign IF_stage2_rg_stage2_18_BIT_432_08_THEN_csr_reg_ETC___d2230 =
	     stage2_rg_stage2[432] ?
	       { csr_regfile$mv_update_mstatus_fs,
		 output_stage2___1_data_to_stage3_frd_val__h9165 } :
	       stage2_rg_stage2[127:0] ;
  assign NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53 =
	     cur_verbosity__h4054 > 4'd1 ;
  assign NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d2082 =
	     NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357 &&
	     !stage1_rg_stage_input[332] &&
	     (IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d918 ||
	      IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d920) ;
  assign NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357 =
	     (IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d283 !=
	      2'd1 ||
	      !IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d321 &&
	      !IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d323) &&
	     (IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d301 !=
	      2'd1 ||
	      !IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d326 &&
	      !IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d327 &&
	      !IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d330) ;
  assign NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739 =
	     NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357 &&
	     (stage1_rg_stage_input[332] ||
	      IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d725 &&
	      IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d736) ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2139 =
	     !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	     IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d2105 &&
	     IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923 ;
  assign NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2604 =
	     !csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	     !stage1_rg_stage_input[332] &&
	     (IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d918 ||
	      IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d920) ;
  assign NOT_csr_regfile_read_dpc__843_BITS_1_TO_0_844__ETC___d2852 =
	     csr_regfile$read_dpc[1:0] != 2'b0 && near_mem$imem_valid &&
	     addr_of_b32__h44836 == near_mem$imem_pc &&
	     near_mem$imem_instr[17:16] == 2'b11 ;
  assign NOT_csr_regfile_read_mstatus__2_BITS_14_TO_13__ETC___d903 =
	     csr_regfile$read_mstatus[14:13] != 2'h0 &&
	     CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14 &&
	     ((stage1_rg_stage_input[112:110] == 3'b111) ?
		csr_regfile$read_frm != 3'b101 &&
		csr_regfile$read_frm != 3'b110 &&
		csr_regfile$read_frm != 3'b111 :
		stage1_rg_stage_input[112:110] != 3'b101 &&
		stage1_rg_stage_input[112:110] != 3'b110) ;
  assign NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1866 =
	     imem_rg_pc[1:0] != 2'b0 &&
	     imem_rg_pc_BITS_63_TO_2_0_EQ_imem_rg_cache_add_ETC___d1858 &&
	     near_mem_imem_pc__1_EQ_imem_rg_pc_PLUS_2_860___d1861 &&
	     imem_rg_cache_b16[1:0] == 2'b11 ;
  assign NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1880 =
	     imem_rg_pc[1:0] != 2'b0 &&
	     (imem_rg_pc_BITS_63_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 &&
	      near_mem$imem_instr[17:16] != 2'b11 ||
	      imem_rg_pc_BITS_63_TO_2_0_EQ_imem_rg_cache_add_ETC___d1858 &&
	      imem_rg_cache_b16[1:0] != 2'b11) ;
  assign NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1909 =
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1866 ||
	     imem_rg_pc[1:0] == 2'b0 &&
	     imem_rg_pc_BITS_63_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 &&
	     near_mem$imem_instr[1:0] == 2'b11 ;
  assign NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911 =
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1909 ||
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1880 ||
	     imem_rg_pc[1:0] == 2'b0 &&
	     imem_rg_pc_BITS_63_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 &&
	     near_mem$imem_instr[1:0] != 2'b11 ;
  assign NOT_rg_cur_priv_1_EQ_0b11_45_433_AND_NOT_rg_cu_ETC___d1439 =
	     (rg_cur_priv != 2'b11 &&
	      (rg_cur_priv != 2'b01 || csr_regfile$read_mstatus[20]) ||
	      stage1_rg_stage_input[104:98] != 7'b0001001) &&
	     stage1_rg_stage_input[144:140] == 5'd0 &&
	     stage1_rg_stage_input[139:135] == 5'd0 &&
	     stage1_rg_stage_input[87:76] == 12'b000000000001 ;
  assign NOT_rg_next_pc_736_BITS_1_TO_0_737_EQ_0b0_738__ETC___d2745 =
	     rg_next_pc[1:0] != 2'b0 && near_mem$imem_valid &&
	     addr_of_b32__h42877 == near_mem$imem_pc &&
	     near_mem$imem_instr[17:16] == 2'b11 ;
  assign NOT_soc_map_m_pc_reset_value__063_BITS_1_TO_0__ETC___d2078 =
	     soc_map$m_pc_reset_value[1:0] != 2'b0 && near_mem$imem_valid &&
	     addr_of_b32__h25567 == near_mem$imem_pc &&
	     near_mem$imem_instr[17:16] == 2'b11 ;
  assign NOT_stage1_rg_full_16_27_OR_stage1_rg_stage_in_ETC___d2163 =
	     (!stage1_rg_full ||
	      stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	      IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d2105 ||
	      IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 ==
	      4'd0) &&
	     (!stage1_rg_full ||
	      !stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	      IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) ;
  assign NOT_stage1_rg_full_16_27_OR_stage1_rg_stage_in_ETC___d2165 =
	     (NOT_stage1_rg_full_16_27_OR_stage1_rg_stage_in_ETC___d2163 ||
	      !rg_stop_req && !rg_step_count) &&
	     csr_regfile_csr_mip_read__092_EQ_rg_prev_mip_093___d2094 ;
  assign NOT_stage1_rg_full_16_27_OR_stage1_rg_stage_in_ETC___d2167 =
	     NOT_stage1_rg_full_16_27_OR_stage1_rg_stage_in_ETC___d2165 &&
	     (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	      NOT_stage1_rg_full_16_27_OR_stage1_rg_stage_in_ETC___d2163) ;
  assign NOT_stage1_rg_full_16_27_OR_stage1_rg_stage_in_ETC___d2168 =
	     (!stage1_rg_full ||
	      stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	      IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d2105) &&
	     (!stage1_rg_full ||
	      !stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	      IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) ;
  assign NOT_stage1_rg_stage_input_17_BITS_112_TO_110_6_ETC___d443 =
	     (stage1_rg_stage_input[112:110] != 3'b0 ||
	      stage1_rg_stage_input[151:145] == 7'b0110011 &&
	      stage1_rg_stage_input[262]) &&
	     (stage1_rg_stage_input[112:110] != 3'b0 ||
	      stage1_rg_stage_input[151:145] != 7'b0110011 ||
	      !stage1_rg_stage_input[262]) &&
	     stage1_rg_stage_input[112:110] != 3'b010 &&
	     stage1_rg_stage_input[112:110] != 3'b011 &&
	     stage1_rg_stage_input[112:110] != 3'b100 &&
	     stage1_rg_stage_input[112:110] != 3'b110 &&
	     stage1_rg_stage_input[112:110] != 3'b111 ;
  assign NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d1077 =
	     (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	      IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd0 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd1 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd2 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd3 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd4 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd5 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd6 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd7 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd8 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd9 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd10 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd11 ;
  assign NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d1089 =
	     (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	      NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357) &&
	     (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	      IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) &&
	     IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d1086 ==
	     2'd3 ;
  assign NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d1093 =
	     (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	      NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357) &&
	     (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	      IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) &&
	     IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d1086 ==
	     2'd0 ;
  assign NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d1099 =
	     (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	      NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357) &&
	     (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	      IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) &&
	     IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d1086 !=
	     2'd3 &&
	     IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d1086 !=
	     2'd0 ;
  assign NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2270 =
	     (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	      IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923 ||
	      !rg_stop_req && !rg_step_count) &&
	     csr_regfile_csr_mip_read__092_EQ_rg_prev_mip_093___d2094 ;
  assign NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2272 =
	     NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2270 &&
	     (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	      !stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	      IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) ;
  assign NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2274 =
	     NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2272 &&
	     (IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 ==
	      2'd2 ||
	      IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 ==
	      2'd0) &&
	     stage1_rg_full &&
	     (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	      NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d2082) ;
  assign NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2537 =
	     (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	      NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d2082 ||
	      NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739) &&
	     (rg_stop_req || rg_step_count) ;
  assign NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2545 =
	     NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2537 ||
	     !csr_regfile_csr_mip_read__092_EQ_rg_prev_mip_093___d2094 ||
	     csr_regfile_interrupt_pending_rg_cur_priv_1_11_ETC___d2540 ||
	     IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 !=
	     2'd2 &&
	     IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 !=
	     2'd0 ||
	     !stage1_rg_full ||
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	     IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d2105 ;
  assign NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2548 =
	     (NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2545 ||
	      IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 ==
	      4'd0 ||
	      IF_IF_stage1_rg_stage_input_17_BITS_151_TO_145_ETC___d1451) &&
	     NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53 ;
  assign NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2588 =
	     NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2545 ||
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 ==
	     4'd0 ||
	     IF_IF_stage1_rg_stage_input_17_BITS_151_TO_145_ETC___d1451 ||
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2132 &&
	     stageD_rg_full ;
  assign NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2805 =
	     (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	      NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d2082) &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd0 ||
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	     NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739 ;
  assign NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2815 =
	     NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2805 &&
	     (rg_stop_req || rg_step_count) ||
	     (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
	     NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2805 ;
  assign NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2820 =
	     NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2815 &&
	     stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d2085 &&
	     IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 ==
	     2'd0 &&
	     !stage3_rg_full &&
	     csr_regfile_csr_mip_read__092_EQ_rg_prev_mip_093___d2094 &&
	     (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	      stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2108) ;
  assign NOT_stage1_rg_stage_input_17_BIT_332_58_44_AND_ETC___d2602 =
	     !stage1_rg_stage_input[332] &&
	     (IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d918 ||
	      IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d920) ||
	     !rg_stop_req && !rg_step_count ;
  assign NOT_stageF_branch_predictor_predict_rsp_NOT_im_ETC___d2559 =
	     stageF_branch_predictor$predict_rsp[1:0] != 2'b0 &&
	     near_mem$imem_valid &&
	     addr_of_b32__h32730 == near_mem$imem_pc &&
	     near_mem$imem_instr[17:16] == 2'b11 ;
  assign SEXT_stage1_rg_stage_input_17_BITS_87_TO_76_53___d1114 =
	     { {52{stage1_rg_stage_input_BITS_87_TO_76__q20[11]}},
	       stage1_rg_stage_input_BITS_87_TO_76__q20 } ;
  assign SEXT_stageD_rg_data_461_BIT_76_478_CONCAT_stag_ETC___d1531 =
	     { {9{offset__h16812[11]}}, offset__h16812 } ;
  assign SEXT_stageD_rg_data_461_BIT_76_478_CONCAT_stag_ETC___d1556 =
	     { {4{offset__h17443[8]}}, offset__h17443 } ;
  assign _dand1rg_step_count$EN_write =
	     (WILL_FIRE_RL_rl_finish_SFENCE_VMA ||
	      WILL_FIRE_RL_rl_finish_FENCE ||
	      WILL_FIRE_RL_rl_finish_FENCE_I ||
	      WILL_FIRE_RL_rl_pipe) &&
	     stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d2580 ;
  assign _dand2rg_step_count$EN_write =
	     (WILL_FIRE_RL_rl_stage1_restart_after_csrrx ||
	      WILL_FIRE_RL_rl_trap) &&
	     stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d2576 &&
	     csr_regfile$read_dcsr_step &&
	     !rg_step_count ;
  assign _theResult_____1_fst__h12302 =
	     (stage1_rg_stage_input[112:110] == 3'b0 &&
	      stage1_rg_stage_input[151:145] == 7'b0110011 &&
	      stage1_rg_stage_input[262]) ?
	       rd_val___1__h12298 :
	       _theResult_____1_fst__h12309 ;
  assign _theResult_____1_fst__h12337 =
	     rs1_val_bypassed__h5803 & _theResult___snd__h15154 ;
  assign _theResult____h10689 =
	     (stage1_rg_stage_input[112:110] == 3'b001) ?
	       rd_val__h15051 :
	       (stage1_rg_stage_input[262] ?
		  rd_val__h15124 :
		  rd_val__h15102) ;
  assign _theResult____h43947 =
	     (delta_CPI_instrs__h43946 == 64'd0) ?
	       delta_CPI_instrs___1__h43982 :
	       delta_CPI_instrs__h43946 ;
  assign _theResult____h6090 = x_out_data_to_stage1_instr__h15891 ;
  assign _theResult___fst__h12446 =
	     (stage1_rg_stage_input[112:110] == 3'b001 &&
	      !stage1_rg_stage_input[257]) ?
	       rd_val___1__h15214 :
	       _theResult___fst__h12453 ;
  assign _theResult___fst__h12453 =
	     stage1_rg_stage_input[262] ?
	       rd_val___1__h15296 :
	       rd_val___1__h15267 ;
  assign _theResult___fst__h12552 =
	     { {32{rs1_val_bypassed803_BITS_31_TO_0_SRL_rs2_val05_ETC__q9[31]}},
	       rs1_val_bypassed803_BITS_31_TO_0_SRL_rs2_val05_ETC__q9 } ;
  assign _theResult___snd__h15154 =
	     (stage1_rg_stage_input[151:145] == 7'b0010011) ?
	       SEXT_stage1_rg_stage_input_17_BITS_87_TO_76_53___d1114 :
	       rs2_val__h10515 ;
  assign _theResult___snd_fst_rd_val__h9975 =
	     stage2_rg_stage2[432] ?
	       stage2_fbox$word_fst :
	       stage2_rg_stage2[624:561] ;
  assign addr_of_b32___1__h25679 = addr_of_b32__h25567 + 64'd4 ;
  assign addr_of_b32___1__h32842 = addr_of_b32__h32730 + 64'd4 ;
  assign addr_of_b32___1__h42989 = addr_of_b32__h42877 + 64'd4 ;
  assign addr_of_b32___1__h44948 = addr_of_b32__h44836 + 64'd4 ;
  assign addr_of_b32__h25567 = { soc_map$m_pc_reset_value[63:2], 2'd0 } ;
  assign addr_of_b32__h32730 =
	     { stageF_branch_predictor$predict_rsp[63:2], 2'd0 } ;
  assign addr_of_b32__h42877 = { rg_next_pc[63:2], 2'd0 } ;
  assign addr_of_b32__h44836 = { csr_regfile$read_dpc[63:2], 2'd0 } ;
  assign alu_outputs___1_addr__h10542 =
	     IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d407 ?
	       branch_target__h10519 :
	       alu_outputs___1_trace_data_pc__h28288 ;
  assign alu_outputs___1_addr__h10941 =
	     rs1_val_bypassed__h5803 +
	     { {52{stage1_rg_stage_input_BITS_75_TO_64__q7[11]}},
	       stage1_rg_stage_input_BITS_75_TO_64__q7 } ;
  assign alu_outputs___1_exc_code__h11224 =
	     (stage1_rg_stage_input[112:110] == 3'b0) ?
	       (stage1_rg_stage_input_17_BITS_144_TO_140_43_EQ_ETC___d951 ?
		  4'd2 :
		  ((stage1_rg_stage_input[144:140] == 5'd0 &&
		    stage1_rg_stage_input[139:135] == 5'd0) ?
		     CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q17 :
		     4'd2)) :
	       4'd2 ;
  assign alu_outputs___1_fval2__h10945 =
	     (IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d301 ==
	      2'd2 &&
	      IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d327) ?
	       x_out_fbypass_rd_val__h9984 :
	       rd_val__h10241 ;
  assign alu_outputs___1_trace_data_instr__h28290 =
	     stage1_rg_stage_input[333] ?
	       stage1_rg_stage_input[263:232] :
	       result___1__h29833 ;
  assign alu_outputs___1_trace_data_pc__h28288 =
	     x_out_cf_info_fallthru_PC__h14805 ;
  assign alu_outputs___1_trace_data_word1__h28116 =
	     { 61'd0, stage1_rg_stage_input[112:110] } ;
  assign alu_outputs___1_trace_data_word2__h28117 = rs2_val__h10515 ;
  assign alu_outputs___1_trace_data_word2__h28293 =
	     { 59'd0, csr_regfile$read_fflags } ;
  assign alu_outputs___1_trace_data_word5__h28120 =
	     alu_outputs___1_fval2__h10945 ;
  assign alu_outputs___1_val1__h11228 =
	     stage1_rg_stage_input[112] ?
	       { 59'd0, stage1_rg_stage_input[139:135] } :
	       rs1_val_bypassed__h5803 ;
  assign alu_outputs___1_val1__h11257 =
	     { 57'd0, stage1_rg_stage_input[104:98] } ;
  assign alu_outputs_cf_info_fallthru_PC__h14797 =
	     x_out_cf_info_fallthru_PC__h14805 ;
  assign alu_outputs_cf_info_taken_PC__h14798 =
	     x_out_cf_info_taken_PC__h14806 ;
  assign branch_target__h10519 =
	     stage1_rg_stage_input[401:338] +
	     { {51{stage1_rg_stage_input_BITS_63_TO_51__q2[12]}},
	       stage1_rg_stage_input_BITS_63_TO_51__q2 } ;
  assign cpi__h43949 = x__h43948 / 64'd10 ;
  assign cpifrac__h43950 = x__h43948 % 64'd10 ;
  assign csr_regfile_RDY_server_reset_response_get__036_ETC___d2057 =
	     csr_regfile$RDY_server_reset_response_get &&
	     stageF_f_reset_rsps$EMPTY_N &&
	     stageD_f_reset_rsps$EMPTY_N &&
	     stage1_f_reset_rsps$EMPTY_N &&
	     stage2_f_reset_rsps$EMPTY_N &&
	     stage3_f_reset_rsps$EMPTY_N &&
	     f_reset_rsps_i_notFull__042_AND_NOT_rg_run_on__ETC___d2051 ;
  assign csr_regfile_csr_mip_read__092_EQ_rg_prev_mip_093___d2094 =
	     csr_regfile$csr_mip_read == rg_prev_mip ;
  assign csr_regfile_interrupt_pending_rg_cur_priv_1_11_ETC___d2540 =
	     (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
	     (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	      NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d2082 ||
	      NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739) ;
  assign csr_regfile_interrupt_pending_rg_cur_priv_1_11_ETC___d2807 =
	     (csr_regfile$interrupt_pending[4] || csr_regfile$nmi_pending) &&
	     rg_state == 4'd4 &&
	     stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d2085 &&
	     IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 ==
	     2'd0 &&
	     !stage3_rg_full &&
	     csr_regfile_csr_mip_read__092_EQ_rg_prev_mip_093___d2094 &&
	     NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2805 ;
  assign csr_regfile_read_csr_mcycle__0_MINUS_rg_start__ETC___d2825 =
	     delta_CPI_cycles__h43945 * 64'd10 ;
  assign csr_regfile_read_misa__9_BIT_2_466_AND_stageD__ETC___d1541 =
	     csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
	     stageD_rg_data[79:76] == 4'b1000 &&
	     stageD_rg_data[75:71] != 5'd0 ;
  assign csr_regfile_read_misa__9_BIT_2_466_AND_stageD__ETC___d1547 =
	     csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
	     stageD_rg_data[79:76] == 4'b1001 &&
	     stageD_rg_data[75:71] != 5'd0 ;
  assign csr_regfile_read_mstatus__2_BITS_14_TO_13_4_EQ_ETC___d710 =
	     csr_regfile$read_mstatus[14:13] == 2'h0 ||
	     CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12 ||
	     ((stage1_rg_stage_input[112:110] == 3'b111) ?
		csr_regfile$read_frm == 3'b101 ||
		csr_regfile$read_frm == 3'b110 ||
		csr_regfile$read_frm == 3'b111 :
		stage1_rg_stage_input[112:110] == 3'b101 ||
		stage1_rg_stage_input[112:110] == 3'b110) ;
  assign cur_verbosity__h4054 =
	     (csr_regfile$read_csr_minstret < cfg_logdelay) ?
	       4'd0 :
	       cfg_verbosity ;
  assign d_instr__h23510 =
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1866 ?
	       instr_out___1__h23512 :
	       IF_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg_p_ETC___d1884 ;
  assign data_to_stage2_addr__h10358 = x_out_data_to_stage2_addr__h10376 ;
  assign decoded_instr_funct10__h31419 =
	     { _theResult____h6090[31:25], _theResult____h6090[14:12] } ;
  assign decoded_instr_imm12_S__h31421 =
	     { _theResult____h6090[31:25], _theResult____h6090[11:7] } ;
  assign decoded_instr_imm13_SB__h31422 =
	     { _theResult____h6090[31],
	       _theResult____h6090[7],
	       _theResult____h6090[30:25],
	       _theResult____h6090[11:8],
	       1'b0 } ;
  assign decoded_instr_imm21_UJ__h31424 =
	     { _theResult____h6090[31],
	       _theResult____h6090[19:12],
	       _theResult____h6090[20],
	       _theResult____h6090[30:21],
	       1'b0 } ;
  assign delta_CPI_cycles__h43945 =
	     csr_regfile$read_csr_mcycle - rg_start_CPI_cycles ;
  assign delta_CPI_instrs___1__h43982 = delta_CPI_instrs__h43946 + 64'd1 ;
  assign delta_CPI_instrs__h43946 =
	     csr_regfile$read_csr_minstret - rg_start_CPI_instrs ;
  assign f_reset_reqs_i_notEmpty__013_AND_stageF_f_rese_ETC___d2025 =
	     f_reset_reqs$EMPTY_N && stageF_f_reset_reqs$FULL_N &&
	     stageD_f_reset_reqs$FULL_N &&
	     stage1_f_reset_reqs$FULL_N &&
	     stage2_f_reset_reqs$FULL_N &&
	     stage3_f_reset_reqs$FULL_N &&
	     f_trace_data$FULL_N ;
  assign f_reset_rsps_i_notFull__042_AND_NOT_rg_run_on__ETC___d2051 =
	     f_reset_rsps$FULL_N &&
	     (!rg_run_on_reset ||
	      imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2047 &&
	      stageF_branch_predictor$RDY_predict_req) ;
  assign fall_through_pc__h10290 =
	     stage1_rg_stage_input[401:338] +
	     (stage1_rg_stage_input[333] ? 64'd4 : 64'd2) ;
  assign fpr_regfile_RDY_server_reset_request_put__010__ETC___d2028 =
	     fpr_regfile$RDY_server_reset_request_put &&
	     near_mem$RDY_server_reset_request_put &&
	     csr_regfile$RDY_server_reset_request_put &&
	     f_reset_reqs_i_notEmpty__013_AND_stageF_f_rese_ETC___d2025 ;
  assign imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1898 =
	     (imem_rg_pc[1:0] == 2'b0 ||
	      !imem_rg_pc_BITS_63_TO_2_0_EQ_imem_rg_cache_add_ETC___d1858 ||
	      !near_mem_imem_pc__1_EQ_imem_rg_pc_PLUS_2_860___d1861 ||
	      imem_rg_cache_b16[1:0] != 2'b11) &&
	     (imem_rg_pc[1:0] != 2'b0 ||
	      !imem_rg_pc_BITS_63_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 ||
	      near_mem$imem_instr[1:0] != 2'b11) ;
  assign imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1902 =
	     imem_rg_pc[1:0] == 2'b0 ||
	     (!imem_rg_pc_BITS_63_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 ||
	      near_mem$imem_instr[17:16] == 2'b11) &&
	     (!imem_rg_pc_BITS_63_TO_2_0_EQ_imem_rg_cache_add_ETC___d1858 ||
	      imem_rg_cache_b16[1:0] == 2'b11) ;
  assign imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1905 =
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1898 &&
	     imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1902 &&
	     (imem_rg_pc[1:0] != 2'b0 ||
	      !imem_rg_pc_BITS_63_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 ||
	      near_mem$imem_instr[1:0] == 2'b11) ;
  assign imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_near_mem__ETC___d2047 =
	     imem_rg_pc[1:0] == 2'b0 || !near_mem$imem_valid ||
	     !imem_rg_pc_BITS_63_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 ||
	     near_mem$imem_instr[17:16] != 2'b11 ;
  assign imem_rg_pc_BITS_63_TO_2_0_EQ_imem_rg_cache_add_ETC___d1858 =
	     imem_rg_pc[63:2] == imem_rg_cache_addr[63:2] ;
  assign imem_rg_pc_BITS_63_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 =
	     imem_rg_pc[63:2] == near_mem$imem_pc[63:2] ;
  assign imm12__h16105 = { 4'd0, offset__h15977 } ;
  assign imm12__h16442 = { 5'd0, offset__h16384 } ;
  assign imm12__h18078 = { {6{imm6__h18076[5]}}, imm6__h18076 } ;
  assign imm12__h18747 = { {2{nzimm10__h18745[9]}}, nzimm10__h18745 } ;
  assign imm12__h18962 = { 2'd0, nzimm10__h18960 } ;
  assign imm12__h19158 = { 6'b0, imm6__h18076 } ;
  assign imm12__h19495 = { 6'b010000, imm6__h18076 } ;
  assign imm12__h21116 = { 3'd0, offset__h21030 } ;
  assign imm12__h21468 = { 4'd0, offset__h21402 } ;
  assign imm20__h18206 = { {14{imm6__h18076[5]}}, imm6__h18076 } ;
  assign imm6__h18076 = { stageD_rg_data[76], stageD_rg_data[70:66] } ;
  assign instr___1__h15927 =
	     (csr_regfile$read_misa[2] && stageD_rg_data[65:64] == 2'b10 &&
	      stageD_rg_data[75:71] != 5'd0 &&
	      stageD_rg_data[79:77] == 3'b010) ?
	       instr__h16104 :
	       IF_csr_regfile_read_misa__9_BIT_2_466_AND_stag_ETC___d1758 ;
  assign instr__h16104 =
	     { imm12__h16105, 8'd18, stageD_rg_data[75:71], 7'b0000011 } ;
  assign instr__h16249 =
	     { 4'd0,
	       stageD_rg_data[72:71],
	       stageD_rg_data[76],
	       stageD_rg_data[70:66],
	       8'd18,
	       offset_BITS_4_TO_0___h16373,
	       7'b0100011 } ;
  assign instr__h16441 =
	     { imm12__h16442, rs1__h16443, 3'b010, rd__h16444, 7'b0000011 } ;
  assign instr__h16636 =
	     { 5'd0,
	       stageD_rg_data[69],
	       stageD_rg_data[76],
	       rd__h16444,
	       rs1__h16443,
	       3'b010,
	       offset_BITS_4_TO_0___h16804,
	       7'b0100011 } ;
  assign instr__h16865 =
	     { SEXT_stageD_rg_data_461_BIT_76_478_CONCAT_stag_ETC___d1531[20],
	       SEXT_stageD_rg_data_461_BIT_76_478_CONCAT_stag_ETC___d1531[10:1],
	       SEXT_stageD_rg_data_461_BIT_76_478_CONCAT_stag_ETC___d1531[11],
	       SEXT_stageD_rg_data_461_BIT_76_478_CONCAT_stag_ETC___d1531[19:12],
	       12'd111 } ;
  assign instr__h17318 = { 12'd0, stageD_rg_data[75:71], 15'd103 } ;
  assign instr__h17434 = { 12'd0, stageD_rg_data[75:71], 15'd231 } ;
  assign instr__h17499 =
	     { SEXT_stageD_rg_data_461_BIT_76_478_CONCAT_stag_ETC___d1556[12],
	       SEXT_stageD_rg_data_461_BIT_76_478_CONCAT_stag_ETC___d1556[10:5],
	       5'd0,
	       rs1__h16443,
	       3'b0,
	       SEXT_stageD_rg_data_461_BIT_76_478_CONCAT_stag_ETC___d1556[4:1],
	       SEXT_stageD_rg_data_461_BIT_76_478_CONCAT_stag_ETC___d1556[11],
	       7'b1100011 } ;
  assign instr__h17816 =
	     { SEXT_stageD_rg_data_461_BIT_76_478_CONCAT_stag_ETC___d1556[12],
	       SEXT_stageD_rg_data_461_BIT_76_478_CONCAT_stag_ETC___d1556[10:5],
	       5'd0,
	       rs1__h16443,
	       3'b001,
	       SEXT_stageD_rg_data_461_BIT_76_478_CONCAT_stag_ETC___d1556[4:1],
	       SEXT_stageD_rg_data_461_BIT_76_478_CONCAT_stag_ETC___d1556[11],
	       7'b1100011 } ;
  assign instr__h18154 =
	     { imm12__h18078, 8'd0, stageD_rg_data[75:71], 7'b0010011 } ;
  assign instr__h18338 =
	     { imm20__h18206, stageD_rg_data[75:71], 7'b0110111 } ;
  assign instr__h18467 =
	     { imm12__h18078,
	       stageD_rg_data[75:71],
	       3'b0,
	       stageD_rg_data[75:71],
	       7'b0010011 } ;
  assign instr__h18694 =
	     { imm12__h18078,
	       stageD_rg_data[75:71],
	       3'b0,
	       stageD_rg_data[75:71],
	       7'b0011011 } ;
  assign instr__h18949 =
	     { imm12__h18747,
	       stageD_rg_data[75:71],
	       3'b0,
	       stageD_rg_data[75:71],
	       7'b0010011 } ;
  assign instr__h19121 = { imm12__h18962, 8'd16, rd__h16444, 7'b0010011 } ;
  assign instr__h19290 =
	     { imm12__h19158,
	       stageD_rg_data[75:71],
	       3'b001,
	       stageD_rg_data[75:71],
	       7'b0010011 } ;
  assign instr__h19479 =
	     { imm12__h19158, rs1__h16443, 3'b101, rs1__h16443, 7'b0010011 } ;
  assign instr__h19668 =
	     { imm12__h19495, rs1__h16443, 3'b101, rs1__h16443, 7'b0010011 } ;
  assign instr__h19785 =
	     { imm12__h18078, rs1__h16443, 3'b111, rs1__h16443, 7'b0010011 } ;
  assign instr__h19963 =
	     { 7'b0,
	       stageD_rg_data[70:66],
	       8'd0,
	       stageD_rg_data[75:71],
	       7'b0110011 } ;
  assign instr__h20082 =
	     { 7'b0,
	       stageD_rg_data[70:66],
	       stageD_rg_data[75:71],
	       3'b0,
	       stageD_rg_data[75:71],
	       7'b0110011 } ;
  assign instr__h20177 =
	     { 7'b0,
	       rd__h16444,
	       rs1__h16443,
	       3'b111,
	       rs1__h16443,
	       7'b0110011 } ;
  assign instr__h20313 =
	     { 7'b0,
	       rd__h16444,
	       rs1__h16443,
	       3'b110,
	       rs1__h16443,
	       7'b0110011 } ;
  assign instr__h20449 =
	     { 7'b0,
	       rd__h16444,
	       rs1__h16443,
	       3'b100,
	       rs1__h16443,
	       7'b0110011 } ;
  assign instr__h20585 =
	     { 7'b0100000,
	       rd__h16444,
	       rs1__h16443,
	       3'b0,
	       rs1__h16443,
	       7'b0110011 } ;
  assign instr__h20723 =
	     { 7'b0,
	       rd__h16444,
	       rs1__h16443,
	       3'b0,
	       rs1__h16443,
	       7'b0111011 } ;
  assign instr__h20861 =
	     { 7'b0100000,
	       rd__h16444,
	       rs1__h16443,
	       3'b0,
	       rs1__h16443,
	       7'b0111011 } ;
  assign instr__h21019 =
	     { 12'b000000000001,
	       stageD_rg_data[75:71],
	       3'b0,
	       stageD_rg_data[75:71],
	       7'b1110011 } ;
  assign instr__h21115 =
	     { imm12__h21116, 8'd19, stageD_rg_data[75:71], 7'b0000011 } ;
  assign instr__h21268 =
	     { 3'd0,
	       stageD_rg_data[73:71],
	       stageD_rg_data[76],
	       stageD_rg_data[70:66],
	       8'd19,
	       offset_BITS_4_TO_0___h21743,
	       7'b0100011 } ;
  assign instr__h21467 =
	     { imm12__h21468, rs1__h16443, 3'b011, rd__h16444, 7'b0000011 } ;
  assign instr__h21618 =
	     { 4'd0,
	       stageD_rg_data[70:69],
	       stageD_rg_data[76],
	       rd__h16444,
	       rs1__h16443,
	       3'b011,
	       offset_BITS_4_TO_0___h21743,
	       7'b0100011 } ;
  assign instr__h21823 =
	     { imm12__h16105, 8'd18, stageD_rg_data[75:71], 7'b0000111 } ;
  assign instr__h22631 =
	     { imm12__h21116, 8'd19, stageD_rg_data[75:71], 7'b0000111 } ;
  assign instr__h22804 =
	     { 3'd0,
	       stageD_rg_data[73:71],
	       stageD_rg_data[76],
	       stageD_rg_data[70:66],
	       8'd19,
	       offset_BITS_4_TO_0___h21743,
	       7'b0100111 } ;
  assign instr__h23003 =
	     { imm12__h21468, rs1__h16443, 3'b011, rd__h16444, 7'b0000111 } ;
  assign instr__h23154 =
	     { 4'd0,
	       stageD_rg_data[70:69],
	       stageD_rg_data[76],
	       rd__h16444,
	       rs1__h16443,
	       3'b011,
	       offset_BITS_4_TO_0___h21743,
	       7'b0100111 } ;
  assign instr_out___1__h23512 =
	     { near_mem$imem_instr[15:0], imem_rg_cache_b16 } ;
  assign instr_out___1__h23534 = { 16'b0, near_mem$imem_instr[15:0] } ;
  assign near_mem_imem_pc__1_EQ_imem_rg_pc_PLUS_2_860___d1861 =
	     near_mem$imem_pc == imem_rg_pc + 64'd2 ;
  assign near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d2007 =
	     near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code != 4'd0 &&
	     near_mem$imem_exc_code != 4'd1 &&
	     near_mem$imem_exc_code != 4'd2 &&
	     near_mem$imem_exc_code != 4'd3 &&
	     near_mem$imem_exc_code != 4'd4 &&
	     near_mem$imem_exc_code != 4'd5 &&
	     near_mem$imem_exc_code != 4'd6 &&
	     near_mem$imem_exc_code != 4'd7 &&
	     near_mem$imem_exc_code != 4'd8 &&
	     near_mem$imem_exc_code != 4'd9 &&
	     near_mem$imem_exc_code != 4'd11 &&
	     near_mem$imem_exc_code != 4'd12 &&
	     near_mem$imem_exc_code != 4'd13 &&
	     near_mem$imem_exc_code != 4'd15 ;
  assign new_epoch__h25078 = rg_epoch + 2'd1 ;
  assign next_pc___1__h14317 = stage1_rg_stage_input[401:338] + 64'd2 ;
  assign next_pc__h10291 = x_out_next_pc__h10308 ;
  assign next_pc__h10557 =
	     stage1_rg_stage_input[401:338] +
	     { {43{stage1_rg_stage_input_BITS_30_TO_10__q3[20]}},
	       stage1_rg_stage_input_BITS_30_TO_10__q3 } ;
  assign next_pc__h10594 =
	     { IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d1115[63:1],
	       1'd0 } ;
  assign next_pc__h14314 = stage1_rg_stage_input[401:338] + 64'd4 ;
  assign nzimm10__h18745 =
	     { stageD_rg_data[76],
	       stageD_rg_data[68:67],
	       stageD_rg_data[69],
	       stageD_rg_data[66],
	       stageD_rg_data[70],
	       4'b0 } ;
  assign nzimm10__h18960 =
	     { stageD_rg_data[74:71],
	       stageD_rg_data[76:75],
	       stageD_rg_data[69],
	       stageD_rg_data[70],
	       2'b0 } ;
  assign offset_BITS_4_TO_0___h16373 = { stageD_rg_data[75:73], 2'b0 } ;
  assign offset_BITS_4_TO_0___h16804 =
	     { stageD_rg_data[75:74], stageD_rg_data[70], 2'b0 } ;
  assign offset_BITS_4_TO_0___h21743 = { stageD_rg_data[75:74], 3'b0 } ;
  assign offset__h15977 =
	     { stageD_rg_data[67:66],
	       stageD_rg_data[76],
	       stageD_rg_data[70:68],
	       2'b0 } ;
  assign offset__h16384 =
	     { stageD_rg_data[69],
	       stageD_rg_data[76:74],
	       stageD_rg_data[70],
	       2'b0 } ;
  assign offset__h16812 =
	     { stageD_rg_data[76],
	       stageD_rg_data[72],
	       stageD_rg_data[74:73],
	       stageD_rg_data[70],
	       stageD_rg_data[71],
	       stageD_rg_data[66],
	       stageD_rg_data[75],
	       stageD_rg_data[69:67],
	       1'b0 } ;
  assign offset__h17443 =
	     { stageD_rg_data[76],
	       stageD_rg_data[70:69],
	       stageD_rg_data[66],
	       stageD_rg_data[75:74],
	       stageD_rg_data[68:67],
	       1'b0 } ;
  assign offset__h21030 =
	     { stageD_rg_data[68:66],
	       stageD_rg_data[76],
	       stageD_rg_data[70:69],
	       3'b0 } ;
  assign offset__h21402 =
	     { stageD_rg_data[70:69], stageD_rg_data[76:74], 3'b0 } ;
  assign output_stage2___1_data_to_stage3_frd_val__h9165 =
	     stage2_rg_stage2[432] ?
	       ((stage2_rg_stage2[839:837] == 3'b010) ?
		  { 32'hFFFFFFFF, near_mem$dmem_word64[31:0] } :
		  near_mem$dmem_word64) :
	       stage2_rg_stage2[624:561] ;
  assign output_stage2___1_data_to_stage3_rd_val__h9194 =
	     stage2_rg_stage2[432] ?
	       stage2_rg_stage2[752:689] :
	       stage2_fbox$word_fst ;
  assign output_stage2___1_data_to_stage3_trace_data_word1__h27021 =
	     stage2_rg_stage2[432] ?
	       stage2_rg_stage2[319:256] :
	       near_mem$dmem_word64 ;
  assign output_stage2___1_data_to_stage3_trace_data_word1__h27042 =
	     stage2_rg_stage2[432] ?
	       stage2_rg_stage2[319:256] :
	       output_stage2___1_data_to_stage3_rd_val__h9194 ;
  assign output_stage2___1_data_to_stage3_trace_data_word5__h27046 =
	     stage2_rg_stage2[432] ?
	       stage2_fbox$word_fst :
	       stage2_rg_stage2[63:0] ;
  assign rd__h16444 = { 2'b01, stageD_rg_data[68:66] } ;
  assign rd_val___1__h12290 =
	     rs1_val_bypassed__h5803 + _theResult___snd__h15154 ;
  assign rd_val___1__h12298 =
	     rs1_val_bypassed__h5803 - _theResult___snd__h15154 ;
  assign rd_val___1__h12305 =
	     ((rs1_val_bypassed__h5803 ^ 64'h8000000000000000) <
	      (_theResult___snd__h15154 ^ 64'h8000000000000000)) ?
	       64'd1 :
	       64'd0 ;
  assign rd_val___1__h12312 =
	     (rs1_val_bypassed__h5803 < _theResult___snd__h15154) ?
	       64'd1 :
	       64'd0 ;
  assign rd_val___1__h12319 =
	     rs1_val_bypassed__h5803 ^ _theResult___snd__h15154 ;
  assign rd_val___1__h12326 =
	     rs1_val_bypassed__h5803 | _theResult___snd__h15154 ;
  assign rd_val___1__h15183 =
	     { {32{IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC__q21[31]}},
	       IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC__q21 } ;
  assign rd_val___1__h15214 = { {32{x__h15217[31]}}, x__h15217 } ;
  assign rd_val___1__h15267 = { {32{x__h15270[31]}}, x__h15270 } ;
  assign rd_val___1__h15296 = { {32{tmp__h15295[31]}}, tmp__h15295 } ;
  assign rd_val___1__h15348 =
	     { {32{rs1_val_bypassed803_BITS_31_TO_0_PLUS_rs2_val0_ETC__q10[31]}},
	       rs1_val_bypassed803_BITS_31_TO_0_PLUS_rs2_val0_ETC__q10 } ;
  assign rd_val___1__h15396 =
	     { {32{rs1_val_bypassed803_BITS_31_TO_0_MINUS_rs2_val_ETC__q11[31]}},
	       rs1_val_bypassed803_BITS_31_TO_0_MINUS_rs2_val_ETC__q11 } ;
  assign rd_val___1__h15402 = { {32{x__h15405[31]}}, x__h15405 } ;
  assign rd_val___1__h15447 = { {32{x__h15450[31]}}, x__h15450 } ;
  assign rd_val__h10168 =
	     (!stage3_rg_stage3[496] && stage3_rg_full &&
	      stage3_rg_stage3[567] &&
	      stage3_rg_stage3_03_BITS_566_TO_562_12_EQ_stag_ETC___d382) ?
	       stage3_rg_stage3[561:498] :
	       gpr_regfile$read_rs1 ;
  assign rd_val__h10193 =
	     (!stage3_rg_stage3[496] && stage3_rg_full &&
	      stage3_rg_stage3[567] &&
	      stage3_rg_stage3_03_BITS_566_TO_562_12_EQ_stag_ETC___d390) ?
	       stage3_rg_stage3[561:498] :
	       gpr_regfile$read_rs2 ;
  assign rd_val__h10218 =
	     (stage3_rg_stage3[496] && stage3_rg_full &&
	      stage3_rg_stage3[567] &&
	      stage3_rg_stage3_03_BITS_566_TO_562_12_EQ_stag_ETC___d382) ?
	       stage3_rg_stage3[490:427] :
	       fpr_regfile$read_rs1 ;
  assign rd_val__h10241 =
	     (stage3_rg_stage3[496] && stage3_rg_full &&
	      stage3_rg_stage3[567] &&
	      stage3_rg_stage3_03_BITS_566_TO_562_12_EQ_stag_ETC___d390) ?
	       stage3_rg_stage3[490:427] :
	       fpr_regfile$read_rs2 ;
  assign rd_val__h10267 =
	     (stage3_rg_stage3[496] && stage3_rg_full &&
	      stage3_rg_stage3[567] &&
	      stage3_rg_stage3[566:562] == stage1_rg_stage_input[129:125]) ?
	       stage3_rg_stage3[490:427] :
	       fpr_regfile$read_rs3 ;
  assign rd_val__h10736 =
	     (stage1_rg_stage_input[112:110] == 3'b0 &&
	      (stage1_rg_stage_input[151:145] != 7'b0110011 ||
	       !stage1_rg_stage_input[262])) ?
	       rd_val___1__h12290 :
	       _theResult_____1_fst__h12302 ;
  assign rd_val__h10767 =
	     (stage1_rg_stage_input[112:110] == 3'b0) ?
	       rd_val___1__h15183 :
	       _theResult___fst__h12446 ;
  assign rd_val__h10823 = { {32{v32__h10821[31]}}, v32__h10821 } ;
  assign rd_val__h10847 = stage1_rg_stage_input[401:338] + rd_val__h10823 ;
  assign rd_val__h15051 = rs1_val_bypassed__h5803 << shamt__h10685 ;
  assign rd_val__h15102 = rs1_val_bypassed__h5803 >> shamt__h10685 ;
  assign rd_val__h15124 =
	     rs1_val_bypassed__h5803 >> shamt__h10685 |
	     ~(64'hFFFFFFFFFFFFFFFF >> shamt__h10685) &
	     {64{rs1_val_bypassed__h5803[63]}} ;
  assign result___1__h29833 = { 16'd0, stage1_rg_stage_input[231:216] } ;
  assign rg_cur_priv_1_EQ_0b11_45_OR_rg_cur_priv_1_EQ_0_ETC___d1424 =
	     (rg_cur_priv == 2'b11 ||
	      rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[20]) &&
	     stage1_rg_stage_input[104:98] == 7'b0001001 ||
	     stage1_rg_stage_input[144:140] != 5'd0 ||
	     stage1_rg_stage_input[139:135] != 5'd0 ||
	     stage1_rg_stage_input[87:76] != 12'b0 &&
	     stage1_rg_stage_input[87:76] != 12'b000000000001 ;
  assign rg_cur_priv_1_EQ_0b11_45_OR_rg_cur_priv_1_EQ_0_ETC___d972 =
	     (rg_cur_priv == 2'b11 ||
	      rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[21] ||
	      rg_cur_priv == 2'b0 && csr_regfile$read_misa[13]) &&
	     stage1_rg_stage_input[87:76] == 12'b000100000101 ;
  assign rg_state_4_EQ_13_7_AND_csr_regfile_wfi_resume__ETC___d2786 =
	     rg_state == 4'd13 &&
	     (csr_regfile$wfi_resume || rg_stop_req || rg_step_count) &&
	     (!stageF_rg_full ||
	      near_mem$imem_valid &&
	      NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911) ;
  assign rg_state_4_EQ_4_081_AND_NOT_stage1_rg_stage_in_ETC___d2609 =
	     rg_state == 4'd4 &&
	     NOT_stage1_rg_stage_input_17_BIT_332_58_44_AND_ETC___d2602 &&
	     csr_regfile_csr_mip_read__092_EQ_rg_prev_mip_093___d2094 &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2604 &&
	     !stage3_rg_full &&
	     IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 ==
	     2'd0 &&
	     stage1_rg_full &&
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	     NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739 ;
  assign rg_state_4_EQ_4_081_AND_NOT_stage1_rg_stage_in_ETC___d2751 =
	     rg_state_4_EQ_4_081_AND_NOT_stage1_rg_stage_in_ETC___d2609 &&
	     (IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 ==
	      4'd8 ||
	      IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 ==
	      4'd9 ||
	      IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 ==
	      4'd10) &&
	     (!stageF_rg_full ||
	      near_mem$imem_valid &&
	      NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911) ;
  assign rg_state_4_EQ_4_081_AND_NOT_stage1_rg_stage_in_ETC___d2781 =
	     rg_state_4_EQ_4_081_AND_NOT_stage1_rg_stage_in_ETC___d2609 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 ==
	     4'd11 &&
	     (!stageF_rg_full ||
	      near_mem$imem_valid &&
	      NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911) ;
  assign rg_state_4_EQ_4_081_AND_NOT_stage1_rg_stage_in_ETC___d2794 =
	     rg_state_4_EQ_4_081_AND_NOT_stage1_rg_stage_in_ETC___d2609 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 ==
	     4'd12 &&
	     (!stageF_rg_full ||
	      near_mem$imem_valid &&
	      NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911) ;
  assign rg_state_4_EQ_4_081_AND_stage3_rg_full_01_OR_N_ETC___d2160 =
	     rg_state == 4'd4 &&
	     (stage3_rg_full ||
	      IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 !=
	      2'd0 ||
	      stage1_rg_full ||
	      stageD_rg_full ||
	      stageF_rg_full) &&
	     (stage3_rg_full ||
	      IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 !=
	      2'd3) &&
	     stage3_rg_full_01_OR_NOT_IF_stage2_rg_full_17__ETC___d2158 ;
  assign rg_state_4_EQ_5_623_AND_NOT_stageF_rg_full_888_ETC___d2624 =
	     rg_state == 4'd5 &&
	     (!stageF_rg_full ||
	      near_mem$imem_valid &&
	      NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911) ;
  assign rg_state_4_EQ_6_790_AND_NOT_stageF_rg_full_888_ETC___d2791 =
	     rg_state == 4'd6 &&
	     (!stageF_rg_full ||
	      near_mem$imem_valid &&
	      NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911) ;
  assign rg_state_4_EQ_9_733_AND_NOT_stageF_rg_full_888_ETC___d2734 =
	     rg_state == 4'd9 &&
	     (!stageF_rg_full ||
	      near_mem$imem_valid &&
	      NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911) ;
  assign rg_trap_info_626_BITS_131_TO_68_627_CONCAT_IF__ETC___d2650 =
	     { rg_trap_info[131:68],
	       rg_trap_interrupt ?
		 128'h0000000000000000AAAAAAAAAAAAAAAA :
		 { rg_trap_info[63:0], rg_trap_trace_data[63:0] } } ;
  assign rm__h11387 = x_out_data_to_stage2_rounding_mode__h10385 ;
  assign rs1__h16443 = { 2'b01, stageD_rg_data[73:71] } ;
  assign rs1_val__h34674 =
	     (rg_trap_instr[14:12] == 3'b001) ?
	       rg_csr_val1 :
	       { 59'd0, rg_trap_instr[19:15] } ;
  assign rs1_val_bypassed803_BITS_31_TO_0_MINUS_rs2_val_ETC__q11 =
	     rs1_val_bypassed__h5803[31:0] - rs2_val__h10515[31:0] ;
  assign rs1_val_bypassed803_BITS_31_TO_0_PLUS_rs2_val0_ETC__q10 =
	     rs1_val_bypassed__h5803[31:0] + rs2_val__h10515[31:0] ;
  assign rs1_val_bypassed803_BITS_31_TO_0_SRL_rs2_val05_ETC__q9 =
	     rs1_val_bypassed__h5803[31:0] >> rs2_val__h10515[4:0] |
	     ~(32'hFFFFFFFF >> rs2_val__h10515[4:0]) &
	     {32{rs1_val_bypassed803_BITS_31_TO_0__q8[31]}} ;
  assign rs1_val_bypassed803_BITS_31_TO_0__q8 =
	     rs1_val_bypassed__h5803[31:0] ;
  assign rs1_val_bypassed__h5803 =
	     (stage1_rg_stage_input[139:135] == 5'd0) ? 64'd0 : val__h10170 ;
  assign rs2_val__h10515 =
	     (stage1_rg_stage_input[134:130] == 5'd0) ? 64'd0 : val__h10195 ;
  assign shamt__h10685 =
	     (stage1_rg_stage_input[151:145] == 7'b0010011) ?
	       stage1_rg_stage_input[81:76] :
	       rs2_val__h10515[5:0] ;
  assign stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d1186 =
	     stage1_rg_full &&
	     (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	      NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357) &&
	     (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	      IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153 !=
	     3'd0 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153 !=
	     3'd1 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153 !=
	     3'd2 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153 !=
	     3'd3 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153 !=
	     3'd4 ;
  assign stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d2085 =
	     stage1_rg_full &&
	     (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	      NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d2082 ||
	      NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739) ;
  assign stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d2562 =
	     stage1_rg_full &&
	     (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	      NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d2082) &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd0 ;
  assign stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d2576 =
	     stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d2562 ||
	     stage1_rg_full &&
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	     NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739 ;
  assign stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d2580 =
	     stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d2576 &&
	     IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d2088 &&
	     csr_regfile$read_dcsr_step &&
	     !rg_step_count ;
  assign stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d926 =
	     stage1_rg_full &&
	     (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	      NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357) &&
	     (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	      IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) ;
  assign stage1_rg_stage_input_17_BITS_112_TO_110_61_EQ_ETC___d763 =
	     stage1_rg_stage_input[112:110] == 3'b0 &&
	     (stage1_rg_stage_input[151:145] != 7'b0110011 ||
	      !stage1_rg_stage_input[262]) ||
	     stage1_rg_stage_input[112:110] == 3'b0 &&
	     stage1_rg_stage_input[151:145] == 7'b0110011 &&
	     stage1_rg_stage_input[262] ||
	     stage1_rg_stage_input[112:110] == 3'b010 ||
	     stage1_rg_stage_input[112:110] == 3'b011 ||
	     stage1_rg_stage_input[112:110] == 3'b100 ||
	     stage1_rg_stage_input[112:110] == 3'b110 ||
	     stage1_rg_stage_input[112:110] == 3'b111 ;
  assign stage1_rg_stage_input_17_BITS_144_TO_140_43_EQ_ETC___d951 =
	     stage1_rg_stage_input[144:140] == 5'd0 &&
	     (rg_cur_priv == 2'b11 ||
	      rg_cur_priv == 2'b01 && !csr_regfile$read_mstatus[20]) &&
	     stage1_rg_stage_input[104:98] == 7'b0001001 ;
  assign stage1_rg_stage_input_17_BITS_151_TO_145_59_EQ_ETC___d2328 =
	     stage1_rg_stage_input[151:145] == 7'b1010011 &&
	     (stage1_rg_stage_input[104:98] == 7'h69 &&
	      (stage1_rg_stage_input[134:130] == 5'd0 ||
	       stage1_rg_stage_input[134:130] == 5'd1 ||
	       stage1_rg_stage_input[134:130] == 5'd2 ||
	       stage1_rg_stage_input[134:130] == 5'd3) ||
	      stage1_rg_stage_input[104:98] == 7'h79 ||
	      stage1_rg_stage_input[104:98] == 7'h68 &&
	      (stage1_rg_stage_input[134:130] == 5'd0 ||
	       stage1_rg_stage_input[134:130] == 5'd1 ||
	       stage1_rg_stage_input[134:130] == 5'd2 ||
	       stage1_rg_stage_input[134:130] == 5'd3) ||
	      stage1_rg_stage_input[104:98] == 7'h78) ;
  assign stage1_rg_stage_input_17_BITS_151_TO_145_59_EQ_ETC___d756 =
	     stage1_rg_stage_input[151:145] == 7'b0110011 &&
	     stage1_rg_stage_input[104:98] == 7'b0000001 ||
	     stage1_rg_stage_input[151:145] == 7'b0111011 &&
	     stage1_rg_stage_input[104:98] == 7'b0000001 ||
	     (stage1_rg_stage_input[151:145] == 7'b0010011 ||
	      stage1_rg_stage_input[151:145] == 7'b0110011) &&
	     (stage1_rg_stage_input[112:110] == 3'b001 ||
	      stage1_rg_stage_input[112:110] == 3'b101) ;
  assign stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d1393 =
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	     NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd0 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd1 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd2 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd3 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd4 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd5 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd6 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd7 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd8 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd9 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd10 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd11 ;
  assign stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2108 =
	     (stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	      IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d2105 ||
	      IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 ==
	      4'd0) &&
	     (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	      IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) ;
  assign stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2115 =
	     (stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2108 ||
	      !rg_stop_req && !rg_step_count) &&
	     csr_regfile_csr_mip_read__092_EQ_rg_prev_mip_093___d2094 ;
  assign stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2123 =
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2115 &&
	     (!csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending ||
	      stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2108) ;
  assign stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2128 =
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2123 &&
	     (IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 ==
	      2'd2 ||
	      IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 ==
	      2'd0) &&
	     stage1_rg_full &&
	     (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	      NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d2082) ;
  assign stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2137 =
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	     IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d2105 &&
	     IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923 ||
	     !rg_stop_req && !rg_step_count ;
  assign stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2142 =
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2137 &&
	     csr_regfile_csr_mip_read__092_EQ_rg_prev_mip_093___d2094 &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2139 &&
	     (IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 ==
	      2'd2 ||
	      IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 ==
	      2'd0) &&
	     stage1_rg_full &&
	     (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	      NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d2082) ;
  assign stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2148 =
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2142 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd0 &&
	     !IF_IF_stage1_rg_stage_input_17_BITS_151_TO_145_ETC___d1451 ||
	     (imem_rg_pc[1:0] == 2'b0 ||
	      !imem_rg_pc_BITS_63_TO_2_0_EQ_near_mem_imem_pc__ETC___d13 ||
	      near_mem$imem_instr[17:16] != 2'b11) &&
	     stageF_branch_predictor$RDY_predict_req ;
  assign stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2283 =
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2137 &&
	     csr_regfile_csr_mip_read__092_EQ_rg_prev_mip_093___d2094 &&
	     NOT_csr_regfile_interrupt_pending_rg_cur_priv__ETC___d2139 &&
	     (IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 ==
	      2'd2 ||
	      IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 ==
	      2'd0) &&
	     stage1_rg_full &&
	     (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	      NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d2082) ;
  assign stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2457 =
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2283 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd0 &&
	     IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d2088 &&
	     NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53 ;
  assign stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2484 =
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2283 &&
	     IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	     4'd0 &&
	     IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d2088 &&
	     !IF_IF_stage1_rg_stage_input_17_BITS_151_TO_145_ETC___d1451 ;
  assign stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 =
	     stage1_rg_stage_input[335:334] == rg_epoch ;
  assign stage1_rg_stage_input_BITS_30_TO_10__q3 =
	     stage1_rg_stage_input[30:10] ;
  assign stage1_rg_stage_input_BITS_63_TO_51__q2 =
	     stage1_rg_stage_input[63:51] ;
  assign stage1_rg_stage_input_BITS_75_TO_64__q7 =
	     stage1_rg_stage_input[75:64] ;
  assign stage1_rg_stage_input_BITS_87_TO_76__q20 =
	     stage1_rg_stage_input[87:76] ;
  assign stage3_rg_full_01_OR_NOT_IF_stage2_rg_full_17__ETC___d2158 =
	     stage3_rg_full ||
	     IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 !=
	     2'd0 ||
	     !stage1_rg_full ||
	     !stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	     IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923 ;
  assign stage3_rg_stage3_03_BITS_566_TO_562_12_EQ_stag_ETC___d382 =
	     stage3_rg_stage3[566:562] == stage1_rg_stage_input[139:135] ;
  assign stage3_rg_stage3_03_BITS_566_TO_562_12_EQ_stag_ETC___d390 =
	     stage3_rg_stage3[566:562] == stage1_rg_stage_input[134:130] ;
  assign stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1920 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911 &&
	     !near_mem$imem_exc ;
  assign stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1926 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd0 ;
  assign stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1930 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd1 ;
  assign stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1934 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd2 ;
  assign stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1938 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd3 ;
  assign stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1942 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd4 ;
  assign stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1946 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd5 ;
  assign stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1950 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd6 ;
  assign stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1954 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd7 ;
  assign stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1958 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd8 ;
  assign stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1962 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd9 ;
  assign stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1966 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd11 ;
  assign stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1970 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd12 ;
  assign stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1974 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd13 ;
  assign stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1978 =
	     stageF_rg_full && near_mem$imem_valid &&
	     NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911 &&
	     near_mem$imem_exc &&
	     near_mem$imem_exc_code == 4'd15 ;
  assign sxl__h8089 =
	     (csr_regfile$read_misa[27:26] == 2'd2) ?
	       csr_regfile$read_mstatus[35:34] :
	       2'd0 ;
  assign td1_rd__h37536 = { 3'd0, csr_regfile$csr_ret_actions[65:64] } ;
  assign td_word1__h29016 = alu_outputs___1_trace_data_word1__h28116 ;
  assign tmp__h15295 =
	     rs1_val_bypassed__h5803[31:0] >> stage1_rg_stage_input[80:76] |
	     ~(32'hFFFFFFFF >> stage1_rg_stage_input[80:76]) &
	     {32{rs1_val_bypassed803_BITS_31_TO_0__q8[31]}} ;
  assign trace_data___1_word2__h26793 =
	     stage3_rg_stage3[255:192] |
	     { 59'd0, csr_regfile$mv_update_fcsr_fflags } ;
  assign trap_info_tval__h14555 =
	     (stage1_rg_stage_input[151:145] != 7'b1101111 &&
	      stage1_rg_stage_input[151:145] != 7'b1100111 &&
	      (stage1_rg_stage_input[151:145] != 7'b1110011 ||
	       stage1_rg_stage_input[112:110] != 3'b0 ||
	       rg_cur_priv_1_EQ_0b11_45_OR_rg_cur_priv_1_EQ_0_ETC___d1424)) ?
	       (stage1_rg_stage_input[333] ?
		  { 32'd0, stage1_rg_stage_input[263:232] } :
		  { 48'd0, stage1_rg_stage_input[231:216] }) :
	       CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q25 ;
  assign uxl__h8090 =
	     (csr_regfile$read_misa[27:26] == 2'd2) ?
	       csr_regfile$read_mstatus[33:32] :
	       2'd0 ;
  assign v32__h10821 = { stage1_rg_stage_input[50:31], 12'h0 } ;
  assign val__h10170 =
	     (IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d283 ==
	      2'd2 &&
	      IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d321) ?
	       x_out_bypass_rd_val__h9856 :
	       rd_val__h10168 ;
  assign val__h10195 =
	     (IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d283 ==
	      2'd2 &&
	      IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d323) ?
	       x_out_bypass_rd_val__h9856 :
	       rd_val__h10193 ;
  assign value__h14669 =
	     stage1_rg_stage_input[332] ?
	       stage1_rg_stage_input[327:264] :
	       trap_info_tval__h14555 ;
  assign x__h15217 =
	     rs1_val_bypassed__h5803[31:0] << stage1_rg_stage_input[80:76] ;
  assign x__h15270 =
	     rs1_val_bypassed__h5803[31:0] >> stage1_rg_stage_input[80:76] ;
  assign x__h15405 = rs1_val_bypassed__h5803[31:0] << rs2_val__h10515[4:0] ;
  assign x__h15450 = rs1_val_bypassed__h5803[31:0] >> rs2_val__h10515[4:0] ;
  assign x__h26853 =
	     stage3_rg_stage3[497] ?
	       trace_data___1_word2__h26793 :
	       stage3_rg_stage3[255:192] ;
  assign x__h26867 =
	     (stage3_rg_stage3[497] || stage3_rg_stage3[496]) ?
	       csr_regfile$mv_update_mstatus_fs :
	       stage3_rg_stage3[127:64] ;
  assign x__h35109 =
	     { IF_csr_regfilemav_csr_write_BIT_64_THEN_2_ELSE_0__q1[63:1],
	       1'd1 } ;
  assign x__h35168 =
	     csr_regfile$mav_csr_write[64] ?
	       csr_regfile$mav_csr_write[63:0] :
	       64'hAAAAAAAAAAAAAAAA ;
  assign x__h36096 =
	     ((rg_trap_instr[19:15] != 5'd0 &&
	       csr_regfile$mav_csr_write[64]) ?
		64'd2 :
		64'd0) |
	     ((rg_trap_instr[19:15] == 5'd0) ? 64'd0 : 64'd1) ;
  assign x__h36155 = { 52'd0, rg_trap_instr[31:20] } ;
  assign x__h36158 =
	     (rg_trap_instr[19:15] == 5'd0) ?
	       64'hAAAAAAAAAAAAAAAA :
	       csr_regfile$mav_csr_write[128:65] ;
  assign x__h36164 =
	     (rg_trap_instr[19:15] == 5'd0 ||
	      !csr_regfile$mav_csr_write[64]) ?
	       64'hAAAAAAAAAAAAAAAA :
	       csr_regfile$mav_csr_write[63:0] ;
  assign x__h43948 =
	     csr_regfile_read_csr_mcycle__0_MINUS_rg_start__ETC___d2825[63:0] /
	     _theResult____h43947 ;
  assign x_exc_code__h43682 =
	     (csr_regfile$interrupt_pending[4] && !csr_regfile$nmi_pending) ?
	       csr_regfile$interrupt_pending[3:0] :
	       4'd0 ;
  assign x_out_cf_info_fallthru_PC__h14805 =
	     stage1_rg_stage_input[333] ?
	       next_pc__h14314 :
	       next_pc___1__h14317 ;
  assign x_out_data_to_stage1_instr__h15891 =
	     stageD_rg_data[165] ? stageD_rg_data[95:64] : instr___1__h15927 ;
  assign x_out_data_to_stage2_fval1__h10379 =
	     (IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d301 ==
	      2'd2 &&
	      IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d326) ?
	       x_out_fbypass_rd_val__h9984 :
	       rd_val__h10218 ;
  assign x_out_data_to_stage2_fval3__h10381 =
	     (IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d301 ==
	      2'd2 &&
	      IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d330) ?
	       x_out_fbypass_rd_val__h9984 :
	       rd_val__h10267 ;
  assign x_out_data_to_stage2_rd__h10375 =
	     stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ?
	       data_to_stage2_rd__h10357 :
	       5'd0 ;
  assign x_out_data_to_stage2_rounding_mode__h10385 =
	     (stage1_rg_stage_input[112:110] == 3'b111) ?
	       csr_regfile$read_frm :
	       stage1_rg_stage_input[112:110] ;
  assign x_out_data_to_stage2_val2__h10378 =
	     (stage1_rg_stage_input[151:145] == 7'b1100011) ?
	       branch_target__h10519 :
	       IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d1316 ;
  assign x_out_next_pc__h10308 =
	     IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d920 ?
	       data_to_stage2_addr__h10358 :
	       fall_through_pc__h10290 ;
  assign x_out_trap_info_exc_code__h14560 =
	     stage1_rg_stage_input[332] ?
	       stage1_rg_stage_input[331:328] :
	       alu_outputs_exc_code__h11522 ;
  assign x_rd__h34040 = { 3'd0, csr_regfile$csr_trap_actions[1:0] } ;
  assign y__h35888 = ~rs1_val__h35619 ;
  always@(stage2_rg_stage2)
  begin
    case (stage2_rg_stage2[824:822])
      3'd1, 3'd2, 3'd4: value__h9553 = stage2_rg_stage2[920:857];
      default: value__h9553 = stage2_rg_stage2[920:857];
    endcase
  end
  always@(stage2_rg_stage2 or near_mem$dmem_exc_code)
  begin
    case (stage2_rg_stage2[824:822])
      3'd1, 3'd2, 3'd4:
	  x_out_trap_info_exc_code__h9590 = near_mem$dmem_exc_code;
      default: x_out_trap_info_exc_code__h9590 = 4'd2;
    endcase
  end
  always@(stage2_rg_stage2)
  begin
    case (stage2_rg_stage2[824:822])
      3'd1, 3'd2, 3'd4: value__h9614 = stage2_rg_stage2[816:753];
      default: value__h9614 = 64'd0;
    endcase
  end
  always@(stage2_rg_stage2 or stage2_fbox$word_snd)
  begin
    case (stage2_rg_stage2[824:822])
      3'd0, 3'd1, 3'd2, 3'd3, 3'd4:
	  x_out_data_to_stage3_fpr_flags__h9224 = 5'd0;
      default: x_out_data_to_stage3_fpr_flags__h9224 = stage2_fbox$word_snd;
    endcase
  end
  always@(stage2_rg_stage2)
  begin
    case (stage2_rg_stage2[824:822])
      3'd0, 3'd1, 3'd4:
	  x_out_data_to_stage3_rd__h9220 = stage2_rg_stage2[821:817];
      3'd2: x_out_data_to_stage3_rd__h9220 = 5'd0;
      default: x_out_data_to_stage3_rd__h9220 = stage2_rg_stage2[821:817];
    endcase
  end
  always@(stage2_rg_stage2)
  begin
    case (stage2_rg_stage2[824:822])
      3'd0, 3'd1, 3'd4: x_out_bypass_rd__h9855 = stage2_rg_stage2[821:817];
      default: x_out_bypass_rd__h9855 = stage2_rg_stage2[821:817];
    endcase
  end
  always@(stage2_rg_stage2)
  begin
    case (stage2_rg_stage2[824:822])
      3'd1, 3'd4: x_out_fbypass_rd__h9983 = stage2_rg_stage2[821:817];
      default: x_out_fbypass_rd__h9983 = stage2_rg_stage2[821:817];
    endcase
  end
  always@(rg_trap_instr or rg_csr_val1)
  begin
    case (rg_trap_instr[14:12])
      3'b010, 3'b011: rs1_val__h35619 = rg_csr_val1;
      default: rs1_val__h35619 = { 59'd0, rg_trap_instr[19:15] };
    endcase
  end
  always@(stage2_rg_stage2 or
	  stage2_fbox$word_fst or
	  output_stage2___1_data_to_stage3_frd_val__h9165)
  begin
    case (stage2_rg_stage2[824:822])
      3'd0, 3'd2, 3'd3:
	  x_out_data_to_stage3_frd_val__h9225 = stage2_rg_stage2[624:561];
      3'd1, 3'd4:
	  x_out_data_to_stage3_frd_val__h9225 =
	      output_stage2___1_data_to_stage3_frd_val__h9165;
      default: x_out_data_to_stage3_frd_val__h9225 = stage2_fbox$word_fst;
    endcase
  end
  always@(stage1_rg_stage_input)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0000011,
      7'b0000111,
      7'b0010011,
      7'b0010111,
      7'b0011011,
      7'b0110011,
      7'b0110111,
      7'b0111011,
      7'b1100111,
      7'b1101111:
	  data_to_stage2_rd__h10357 = stage1_rg_stage_input[144:140];
      7'b1100011: data_to_stage2_rd__h10357 = 5'd0;
      default: data_to_stage2_rd__h10357 = stage1_rg_stage_input[144:140];
    endcase
  end
  always@(stage2_rg_stage2 or
	  output_stage2___1_data_to_stage3_rd_val__h9194 or
	  near_mem$dmem_word64 or stage2_mbox$word)
  begin
    case (stage2_rg_stage2[824:822])
      3'd0, 3'd2:
	  x_out_data_to_stage3_rd_val__h9221 = stage2_rg_stage2[752:689];
      3'd1, 3'd4: x_out_data_to_stage3_rd_val__h9221 = near_mem$dmem_word64;
      3'd3: x_out_data_to_stage3_rd_val__h9221 = stage2_mbox$word;
      default: x_out_data_to_stage3_rd_val__h9221 =
		   output_stage2___1_data_to_stage3_rd_val__h9194;
    endcase
  end
  always@(stage2_rg_stage2 or
	  output_stage2___1_data_to_stage3_rd_val__h9194 or stage2_mbox$word)
  begin
    case (stage2_rg_stage2[824:822])
      3'd0, 3'd1, 3'd4:
	  x_out_bypass_rd_val__h9856 = stage2_rg_stage2[752:689];
      3'd3: x_out_bypass_rd_val__h9856 = stage2_mbox$word;
      default: x_out_bypass_rd_val__h9856 =
		   output_stage2___1_data_to_stage3_rd_val__h9194;
    endcase
  end
  always@(stage2_rg_stage2 or _theResult___snd_fst_rd_val__h9975)
  begin
    case (stage2_rg_stage2[824:822])
      3'd1, 3'd4: x_out_fbypass_rd_val__h9984 = stage2_rg_stage2[624:561];
      default: x_out_fbypass_rd_val__h9984 =
		   _theResult___snd_fst_rd_val__h9975;
    endcase
  end
  always@(stage1_rg_stage_input)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0000011,
      7'b0000111,
      7'b0010011,
      7'b0010111,
      7'b0011011,
      7'b0101111,
      7'b0110011,
      7'b0110111,
      7'b0111011,
      7'b1000011,
      7'b1000111,
      7'b1001011,
      7'b1001111,
      7'b1010011,
      7'b1100111,
      7'b1101111:
	  alu_outputs_trace_data_rd__h28337 = stage1_rg_stage_input[144:140];
      default: alu_outputs_trace_data_rd__h28337 = 5'd2;
    endcase
  end
  always@(stage1_rg_stage_input or
	  csr_regfile$read_mstatus or td_word1__h29016)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0000011, 7'b0000111:
	  alu_outputs_trace_data_word4__h28341 = csr_regfile$read_mstatus;
      7'b0101111: alu_outputs_trace_data_word4__h28341 = td_word1__h29016;
      default: alu_outputs_trace_data_word4__h28341 =
		   csr_regfile$read_mstatus;
    endcase
  end
  always@(stage2_rg_stage2 or
	  IF_stage2_fbox_valid__47_THEN_2_ELSE_1___d148 or
	  IF_near_mem_dmem_valid__41_THEN_IF_near_mem_dm_ETC___d144 or
	  IF_stage2_mbox_valid__45_THEN_2_ELSE_1___d146)
  begin
    case (stage2_rg_stage2[824:822])
      3'd0: CASE_stage2_rg_stage2_BITS_824_TO_822_0_2_1_IF_ETC__q4 = 2'd2;
      3'd1, 3'd2, 3'd4:
	  CASE_stage2_rg_stage2_BITS_824_TO_822_0_2_1_IF_ETC__q4 =
	      IF_near_mem_dmem_valid__41_THEN_IF_near_mem_dm_ETC___d144;
      3'd3:
	  CASE_stage2_rg_stage2_BITS_824_TO_822_0_2_1_IF_ETC__q4 =
	      IF_stage2_mbox_valid__45_THEN_2_ELSE_1___d146;
      default: CASE_stage2_rg_stage2_BITS_824_TO_822_0_2_1_IF_ETC__q4 =
		   IF_stage2_fbox_valid__47_THEN_2_ELSE_1___d148;
    endcase
  end
  always@(stage2_rg_stage2 or
	  stage2_fbox$valid or
	  near_mem$dmem_valid or near_mem$dmem_exc or stage2_mbox$valid)
  begin
    case (stage2_rg_stage2[824:822])
      3'd1, 3'd2, 3'd4:
	  IF_stage2_rg_stage2_18_BITS_824_TO_822_19_EQ_1_ETC___d169 =
	      !near_mem$dmem_valid || near_mem$dmem_exc;
      3'd3:
	  IF_stage2_rg_stage2_18_BITS_824_TO_822_19_EQ_1_ETC___d169 =
	      !stage2_mbox$valid;
      default: IF_stage2_rg_stage2_18_BITS_824_TO_822_19_EQ_1_ETC___d169 =
		   !stage2_fbox$valid;
    endcase
  end
  always@(stage2_rg_stage2 or
	  stage2_fbox$valid or
	  near_mem$dmem_valid or near_mem$dmem_exc or stage2_mbox$valid)
  begin
    case (stage2_rg_stage2[824:822])
      3'd1, 3'd2, 3'd4:
	  IF_stage2_rg_stage2_18_BITS_824_TO_822_19_EQ_1_ETC___d179 =
	      near_mem$dmem_valid && !near_mem$dmem_exc;
      3'd3:
	  IF_stage2_rg_stage2_18_BITS_824_TO_822_19_EQ_1_ETC___d179 =
	      stage2_mbox$valid;
      default: IF_stage2_rg_stage2_18_BITS_824_TO_822_19_EQ_1_ETC___d179 =
		   stage2_fbox$valid;
    endcase
  end
  always@(stage2_rg_stage2 or
	  IF_stage2_fbox_valid__47_THEN_2_ELSE_1___d148 or
	  IF_NOT_near_mem_dmem_valid__41_63_OR_NOT_near__ETC___d276 or
	  IF_stage2_mbox_valid__45_THEN_2_ELSE_1___d146)
  begin
    case (stage2_rg_stage2[824:822])
      3'd0: CASE_stage2_rg_stage2_BITS_824_TO_822_0_2_1_IF_ETC__q5 = 2'd2;
      3'd1, 3'd4:
	  CASE_stage2_rg_stage2_BITS_824_TO_822_0_2_1_IF_ETC__q5 =
	      IF_NOT_near_mem_dmem_valid__41_63_OR_NOT_near__ETC___d276;
      3'd2: CASE_stage2_rg_stage2_BITS_824_TO_822_0_2_1_IF_ETC__q5 = 2'd0;
      3'd3:
	  CASE_stage2_rg_stage2_BITS_824_TO_822_0_2_1_IF_ETC__q5 =
	      IF_stage2_mbox_valid__45_THEN_2_ELSE_1___d146;
      default: CASE_stage2_rg_stage2_BITS_824_TO_822_0_2_1_IF_ETC__q5 =
		   stage2_rg_stage2[432] ?
		     2'd0 :
		     IF_stage2_fbox_valid__47_THEN_2_ELSE_1___d148;
    endcase
  end
  always@(stage2_rg_stage2 or
	  IF_stage2_fbox_valid__47_THEN_2_ELSE_1___d148 or
	  IF_NOT_near_mem_dmem_valid__41_63_OR_NOT_near__ETC___d296)
  begin
    case (stage2_rg_stage2[824:822])
      3'd1, 3'd4:
	  CASE_stage2_rg_stage2_BITS_824_TO_822_1_IF_NOT_ETC__q6 =
	      IF_NOT_near_mem_dmem_valid__41_63_OR_NOT_near__ETC___d296;
      3'd2, 3'd3:
	  CASE_stage2_rg_stage2_BITS_824_TO_822_1_IF_NOT_ETC__q6 = 2'd0;
      default: CASE_stage2_rg_stage2_BITS_824_TO_822_1_IF_NOT_ETC__q6 =
		   stage2_rg_stage2[432] ?
		     IF_stage2_fbox_valid__47_THEN_2_ELSE_1___d148 :
		     2'd0;
    endcase
  end
  always@(stage1_rg_stage_input or
	  alu_outputs___1_trace_data_word2__h28293 or
	  alu_outputs___1_trace_data_word2__h28117 or rs2_val__h10515)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0100011, 7'b0100111:
	  alu_outputs_trace_data_word2__h28339 =
	      alu_outputs___1_trace_data_word2__h28117;
      7'b0101111: alu_outputs_trace_data_word2__h28339 = rs2_val__h10515;
      default: alu_outputs_trace_data_word2__h28339 =
		   alu_outputs___1_trace_data_word2__h28293;
    endcase
  end
  always@(stage1_rg_stage_input or
	  _theResult___fst__h12552 or
	  rd_val___1__h15348 or
	  rd_val___1__h15402 or rd_val___1__h15447 or rd_val___1__h15396)
  begin
    case (stage1_rg_stage_input[97:88])
      10'b0: rd_val__h10798 = rd_val___1__h15348;
      10'b0000000001: rd_val__h10798 = rd_val___1__h15402;
      10'b0000000101: rd_val__h10798 = rd_val___1__h15447;
      10'b0100000000: rd_val__h10798 = rd_val___1__h15396;
      default: rd_val__h10798 = _theResult___fst__h12552;
    endcase
  end
  always@(stage1_rg_stage_input or
	  IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d400 or
	  IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d396 or
	  IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d398)
  begin
    case (stage1_rg_stage_input[112:110])
      3'b0:
	  IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d731 =
	      !IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d396;
      3'b001:
	  IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d731 =
	      IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d396;
      3'b100:
	  IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d731 =
	      !IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d398;
      3'b101:
	  IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d731 =
	      IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d398;
      3'b110:
	  IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d731 =
	      !IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d400;
      default: IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d731 =
		   stage1_rg_stage_input[112:110] != 3'b111 ||
		   IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d400;
    endcase
  end
  always@(stage1_rg_stage_input or
	  IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d400 or
	  IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d396 or
	  IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d398)
  begin
    case (stage1_rg_stage_input[112:110])
      3'b0:
	  IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d407 =
	      IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d396;
      3'b001:
	  IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d407 =
	      !IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d396;
      3'b100:
	  IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d407 =
	      IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d398;
      3'b101:
	  IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d407 =
	      !IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d398;
      3'b110:
	  IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d407 =
	      IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d400;
      default: IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d407 =
		   stage1_rg_stage_input[112:110] == 3'b111 &&
		   !IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d400;
    endcase
  end
  always@(stage1_rg_stage_input or rm__h11387)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b1000011, 7'b1000111, 7'b1001011, 7'b1001111:
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12 =
	      stage1_rg_stage_input[99:98] != 2'b0 &&
	      stage1_rg_stage_input[99:98] != 2'b01;
      default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q12 =
		   stage1_rg_stage_input[104:98] != 7'h0 &&
		   stage1_rg_stage_input[104:98] != 7'h04 &&
		   stage1_rg_stage_input[104:98] != 7'h08 &&
		   stage1_rg_stage_input[104:98] != 7'h0C &&
		   stage1_rg_stage_input[104:98] != 7'h2C &&
		   (stage1_rg_stage_input[104:98] != 7'h10 ||
		    rm__h11387 != 3'd0) &&
		   (stage1_rg_stage_input[104:98] != 7'h10 ||
		    rm__h11387 != 3'd1) &&
		   (stage1_rg_stage_input[104:98] != 7'h10 ||
		    rm__h11387 != 3'd2) &&
		   (stage1_rg_stage_input[104:98] != 7'h60 ||
		    stage1_rg_stage_input[134:130] != 5'd0) &&
		   (stage1_rg_stage_input[104:98] != 7'h60 ||
		    stage1_rg_stage_input[134:130] != 5'd1) &&
		   (stage1_rg_stage_input[104:98] != 7'h60 ||
		    stage1_rg_stage_input[134:130] != 5'd2) &&
		   (stage1_rg_stage_input[104:98] != 7'h60 ||
		    stage1_rg_stage_input[134:130] != 5'd3) &&
		   (stage1_rg_stage_input[104:98] != 7'h68 ||
		    stage1_rg_stage_input[134:130] != 5'd0) &&
		   (stage1_rg_stage_input[104:98] != 7'h68 ||
		    stage1_rg_stage_input[134:130] != 5'd1) &&
		   (stage1_rg_stage_input[104:98] != 7'h68 ||
		    stage1_rg_stage_input[134:130] != 5'd2) &&
		   (stage1_rg_stage_input[104:98] != 7'h68 ||
		    stage1_rg_stage_input[134:130] != 5'd3) &&
		   (stage1_rg_stage_input[104:98] != 7'h14 ||
		    rm__h11387 != 3'd0) &&
		   (stage1_rg_stage_input[104:98] != 7'h14 ||
		    rm__h11387 != 3'd1) &&
		   (stage1_rg_stage_input[104:98] != 7'h50 ||
		    rm__h11387 != 3'd0) &&
		   (stage1_rg_stage_input[104:98] != 7'h50 ||
		    rm__h11387 != 3'd1) &&
		   (stage1_rg_stage_input[104:98] != 7'h50 ||
		    rm__h11387 != 3'd2) &&
		   (stage1_rg_stage_input[104:98] != 7'h70 ||
		    rm__h11387 != 3'd0) &&
		   (stage1_rg_stage_input[104:98] != 7'h78 ||
		    rm__h11387 != 3'd0) &&
		   (stage1_rg_stage_input[104:98] != 7'h70 ||
		    rm__h11387 != 3'd1) &&
		   stage1_rg_stage_input[104:98] != 7'b0000001 &&
		   stage1_rg_stage_input[104:98] != 7'h05 &&
		   stage1_rg_stage_input[104:98] != 7'b0001001 &&
		   stage1_rg_stage_input[104:98] != 7'h0D &&
		   stage1_rg_stage_input[104:98] != 7'h2D &&
		   (stage1_rg_stage_input[104:98] != 7'h11 ||
		    rm__h11387 != 3'd0) &&
		   (stage1_rg_stage_input[104:98] != 7'h11 ||
		    rm__h11387 != 3'd1) &&
		   (stage1_rg_stage_input[104:98] != 7'h11 ||
		    rm__h11387 != 3'd2) &&
		   (stage1_rg_stage_input[104:98] != 7'h61 ||
		    stage1_rg_stage_input[134:130] != 5'd0) &&
		   (stage1_rg_stage_input[104:98] != 7'h61 ||
		    stage1_rg_stage_input[134:130] != 5'd1) &&
		   (stage1_rg_stage_input[104:98] != 7'h61 ||
		    stage1_rg_stage_input[134:130] != 5'd2) &&
		   (stage1_rg_stage_input[104:98] != 7'h61 ||
		    stage1_rg_stage_input[134:130] != 5'd3) &&
		   (stage1_rg_stage_input[104:98] != 7'h69 ||
		    stage1_rg_stage_input[134:130] != 5'd0) &&
		   (stage1_rg_stage_input[104:98] != 7'h69 ||
		    stage1_rg_stage_input[134:130] != 5'd1) &&
		   (stage1_rg_stage_input[104:98] != 7'h69 ||
		    stage1_rg_stage_input[134:130] != 5'd2) &&
		   (stage1_rg_stage_input[104:98] != 7'h69 ||
		    stage1_rg_stage_input[134:130] != 5'd3) &&
		   (stage1_rg_stage_input[104:98] != 7'h21 ||
		    stage1_rg_stage_input[134:130] != 5'd0) &&
		   (stage1_rg_stage_input[104:98] != 7'h20 ||
		    stage1_rg_stage_input[134:130] != 5'd1) &&
		   (stage1_rg_stage_input[104:98] != 7'h15 ||
		    rm__h11387 != 3'd0) &&
		   (stage1_rg_stage_input[104:98] != 7'h15 ||
		    rm__h11387 != 3'd1) &&
		   (stage1_rg_stage_input[104:98] != 7'h51 ||
		    rm__h11387 != 3'd0) &&
		   (stage1_rg_stage_input[104:98] != 7'h51 ||
		    rm__h11387 != 3'd1) &&
		   (stage1_rg_stage_input[104:98] != 7'h51 ||
		    rm__h11387 != 3'd2) &&
		   (stage1_rg_stage_input[104:98] != 7'h71 ||
		    rm__h11387 != 3'd0) &&
		   (stage1_rg_stage_input[104:98] != 7'h79 ||
		    rm__h11387 != 3'd0) &&
		   (stage1_rg_stage_input[104:98] != 7'h71 ||
		    rm__h11387 != 3'd1);
    endcase
  end
  always@(stage1_rg_stage_input or
	  csr_regfile_read_mstatus__2_BITS_14_TO_13_4_EQ_ETC___d710 or
	  csr_regfile$read_mstatus)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0000111:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d714 =
	      stage1_rg_stage_input[112:110] != 3'b0 &&
	      stage1_rg_stage_input[112:110] != 3'b100 &&
	      stage1_rg_stage_input[112:110] != 3'b001 &&
	      stage1_rg_stage_input[112:110] != 3'b101 &&
	      stage1_rg_stage_input[112:110] != 3'b010 &&
	      stage1_rg_stage_input[112:110] != 3'b110 &&
	      stage1_rg_stage_input[112:110] != 3'b011 ||
	      csr_regfile$read_mstatus[14:13] == 2'h0;
      7'b0100111:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d714 =
	      stage1_rg_stage_input[112:110] != 3'b0 &&
	      stage1_rg_stage_input[112:110] != 3'b001 &&
	      stage1_rg_stage_input[112:110] != 3'b010 &&
	      stage1_rg_stage_input[112:110] != 3'b011 ||
	      csr_regfile$read_mstatus[14:13] == 2'h0;
      7'b0101111:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d714 =
	      stage1_rg_stage_input[109:105] != 5'b00010 &&
	      stage1_rg_stage_input[109:105] != 5'b00011 &&
	      stage1_rg_stage_input[109:105] != 5'b0 &&
	      stage1_rg_stage_input[109:105] != 5'b00001 &&
	      stage1_rg_stage_input[109:105] != 5'b01100 &&
	      stage1_rg_stage_input[109:105] != 5'b01000 &&
	      stage1_rg_stage_input[109:105] != 5'b00100 &&
	      stage1_rg_stage_input[109:105] != 5'b10000 &&
	      stage1_rg_stage_input[109:105] != 5'b11000 &&
	      stage1_rg_stage_input[109:105] != 5'b10100 &&
	      stage1_rg_stage_input[109:105] != 5'b11100 ||
	      stage1_rg_stage_input[112:110] != 3'b010 &&
	      stage1_rg_stage_input[112:110] != 3'b011;
      default: IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d714 =
		   stage1_rg_stage_input[151:145] != 7'b1010011 &&
		   stage1_rg_stage_input[151:145] != 7'b1000011 &&
		   stage1_rg_stage_input[151:145] != 7'b1000111 &&
		   stage1_rg_stage_input[151:145] != 7'b1001011 &&
		   stage1_rg_stage_input[151:145] != 7'b1001111 ||
		   csr_regfile_read_mstatus__2_BITS_14_TO_13_4_EQ_ETC___d710;
    endcase
  end
  always@(stage1_rg_stage_input or
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d714)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0000011:
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q13 =
	      stage1_rg_stage_input[112:110] != 3'b0 &&
	      stage1_rg_stage_input[112:110] != 3'b100 &&
	      stage1_rg_stage_input[112:110] != 3'b001 &&
	      stage1_rg_stage_input[112:110] != 3'b101 &&
	      stage1_rg_stage_input[112:110] != 3'b010 &&
	      stage1_rg_stage_input[112:110] != 3'b110 &&
	      stage1_rg_stage_input[112:110] != 3'b011;
      7'b0100011:
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q13 =
	      stage1_rg_stage_input[112:110] != 3'b0 &&
	      stage1_rg_stage_input[112:110] != 3'b001 &&
	      stage1_rg_stage_input[112:110] != 3'b010 &&
	      stage1_rg_stage_input[112:110] != 3'b011;
      default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q13 =
		   stage1_rg_stage_input[151:145] == 7'b0001111 ||
		   stage1_rg_stage_input[151:145] == 7'b1110011 ||
		   IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d714;
    endcase
  end
  always@(stage1_rg_stage_input or
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q13 or
	  NOT_stage1_rg_stage_input_17_BITS_112_TO_110_6_ETC___d443)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0010011, 7'b0110011:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d722 =
	      NOT_stage1_rg_stage_input_17_BITS_112_TO_110_6_ETC___d443;
      7'b0011011:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d722 =
	      stage1_rg_stage_input[112:110] != 3'b0 &&
	      (stage1_rg_stage_input[112:110] != 3'b001 ||
	       stage1_rg_stage_input[257]) &&
	      (stage1_rg_stage_input[112:110] != 3'b101 ||
	       stage1_rg_stage_input[257]);
      7'b0111011:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d722 =
	      stage1_rg_stage_input[97:88] != 10'b0 &&
	      stage1_rg_stage_input[97:88] != 10'b0100000000 &&
	      stage1_rg_stage_input[97:88] != 10'b0000000001 &&
	      stage1_rg_stage_input[97:88] != 10'b0000000101 &&
	      stage1_rg_stage_input[97:88] != 10'b0100000101;
      default: IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d722 =
		   stage1_rg_stage_input[151:145] != 7'b0110111 &&
		   stage1_rg_stage_input[151:145] != 7'b0010111 &&
		   CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q13;
    endcase
  end
  always@(stage1_rg_stage_input or rm__h11387)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b1000011, 7'b1000111, 7'b1001011, 7'b1001111:
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14 =
	      stage1_rg_stage_input[99:98] == 2'b0 ||
	      stage1_rg_stage_input[99:98] == 2'b01;
      default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q14 =
		   stage1_rg_stage_input[104:98] == 7'h0 ||
		   stage1_rg_stage_input[104:98] == 7'h04 ||
		   stage1_rg_stage_input[104:98] == 7'h08 ||
		   stage1_rg_stage_input[104:98] == 7'h0C ||
		   stage1_rg_stage_input[104:98] == 7'h2C ||
		   stage1_rg_stage_input[104:98] == 7'h10 &&
		   (rm__h11387 == 3'd0 || rm__h11387 == 3'd1 ||
		    rm__h11387 == 3'd2) ||
		   stage1_rg_stage_input[104:98] == 7'h60 &&
		   stage1_rg_stage_input[134:130] == 5'd0 ||
		   stage1_rg_stage_input[104:98] == 7'h60 &&
		   (stage1_rg_stage_input[134:130] == 5'd1 ||
		    stage1_rg_stage_input[134:130] == 5'd2 ||
		    stage1_rg_stage_input[134:130] == 5'd3) ||
		   stage1_rg_stage_input[104:98] == 7'h68 &&
		   (stage1_rg_stage_input[134:130] == 5'd0 ||
		    stage1_rg_stage_input[134:130] == 5'd1 ||
		    stage1_rg_stage_input[134:130] == 5'd2) ||
		   stage1_rg_stage_input[104:98] == 7'h68 &&
		   stage1_rg_stage_input[134:130] == 5'd3 ||
		   stage1_rg_stage_input[104:98] == 7'h14 &&
		   rm__h11387 == 3'd0 ||
		   stage1_rg_stage_input[104:98] == 7'h14 &&
		   rm__h11387 == 3'd1 ||
		   stage1_rg_stage_input[104:98] == 7'h50 &&
		   (rm__h11387 == 3'd0 || rm__h11387 == 3'd1) ||
		   stage1_rg_stage_input[104:98] == 7'h50 &&
		   rm__h11387 == 3'd2 ||
		   (stage1_rg_stage_input[104:98] == 7'h70 ||
		    stage1_rg_stage_input[104:98] == 7'h78) &&
		   rm__h11387 == 3'd0 ||
		   stage1_rg_stage_input[104:98] == 7'h70 &&
		   rm__h11387 == 3'd1 ||
		   stage1_rg_stage_input[104:98] == 7'b0000001 ||
		   stage1_rg_stage_input[104:98] == 7'h05 ||
		   stage1_rg_stage_input[104:98] == 7'b0001001 ||
		   stage1_rg_stage_input[104:98] == 7'h0D ||
		   stage1_rg_stage_input[104:98] == 7'h2D ||
		   stage1_rg_stage_input[104:98] == 7'h11 &&
		   rm__h11387 == 3'd0 ||
		   stage1_rg_stage_input[104:98] == 7'h11 &&
		   (rm__h11387 == 3'd1 || rm__h11387 == 3'd2) ||
		   stage1_rg_stage_input[104:98] == 7'h61 &&
		   stage1_rg_stage_input[134:130] == 5'd0 ||
		   stage1_rg_stage_input[104:98] == 7'h61 &&
		   (stage1_rg_stage_input[134:130] == 5'd1 ||
		    stage1_rg_stage_input[134:130] == 5'd2 ||
		    stage1_rg_stage_input[134:130] == 5'd3) ||
		   stage1_rg_stage_input[104:98] == 7'h69 &&
		   (stage1_rg_stage_input[134:130] == 5'd0 ||
		    stage1_rg_stage_input[134:130] == 5'd1 ||
		    stage1_rg_stage_input[134:130] == 5'd2) ||
		   stage1_rg_stage_input[104:98] == 7'h69 &&
		   stage1_rg_stage_input[134:130] == 5'd3 ||
		   stage1_rg_stage_input[104:98] == 7'h21 &&
		   stage1_rg_stage_input[134:130] == 5'd0 ||
		   stage1_rg_stage_input[104:98] == 7'h20 &&
		   stage1_rg_stage_input[134:130] == 5'd1 ||
		   stage1_rg_stage_input[104:98] == 7'h15 &&
		   (rm__h11387 == 3'd0 || rm__h11387 == 3'd1) ||
		   stage1_rg_stage_input[104:98] == 7'h51 &&
		   rm__h11387 == 3'd0 ||
		   stage1_rg_stage_input[104:98] == 7'h51 &&
		   (rm__h11387 == 3'd1 || rm__h11387 == 3'd2) ||
		   stage1_rg_stage_input[104:98] == 7'h71 &&
		   rm__h11387 == 3'd0 ||
		   stage1_rg_stage_input[104:98] == 7'h79 &&
		   rm__h11387 == 3'd0 ||
		   stage1_rg_stage_input[104:98] == 7'h71 &&
		   rm__h11387 == 3'd1;
    endcase
  end
  always@(stage1_rg_stage_input or
	  NOT_csr_regfile_read_mstatus__2_BITS_14_TO_13__ETC___d903 or
	  csr_regfile$read_mstatus)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0000111:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d907 =
	      (stage1_rg_stage_input[112:110] == 3'b0 ||
	       stage1_rg_stage_input[112:110] == 3'b100 ||
	       stage1_rg_stage_input[112:110] == 3'b001 ||
	       stage1_rg_stage_input[112:110] == 3'b101 ||
	       stage1_rg_stage_input[112:110] == 3'b010 ||
	       stage1_rg_stage_input[112:110] == 3'b110 ||
	       stage1_rg_stage_input[112:110] == 3'b011) &&
	      csr_regfile$read_mstatus[14:13] != 2'h0;
      7'b0100111:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d907 =
	      (stage1_rg_stage_input[112:110] == 3'b0 ||
	       stage1_rg_stage_input[112:110] == 3'b001 ||
	       stage1_rg_stage_input[112:110] == 3'b010 ||
	       stage1_rg_stage_input[112:110] == 3'b011) &&
	      csr_regfile$read_mstatus[14:13] != 2'h0;
      7'b0101111:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d907 =
	      (stage1_rg_stage_input[109:105] == 5'b00010 ||
	       stage1_rg_stage_input[109:105] == 5'b00011 ||
	       stage1_rg_stage_input[109:105] == 5'b0 ||
	       stage1_rg_stage_input[109:105] == 5'b00001 ||
	       stage1_rg_stage_input[109:105] == 5'b01100 ||
	       stage1_rg_stage_input[109:105] == 5'b01000 ||
	       stage1_rg_stage_input[109:105] == 5'b00100 ||
	       stage1_rg_stage_input[109:105] == 5'b10000 ||
	       stage1_rg_stage_input[109:105] == 5'b11000 ||
	       stage1_rg_stage_input[109:105] == 5'b10100 ||
	       stage1_rg_stage_input[109:105] == 5'b11100) &&
	      (stage1_rg_stage_input[112:110] == 3'b010 ||
	       stage1_rg_stage_input[112:110] == 3'b011);
      default: IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d907 =
		   (stage1_rg_stage_input[151:145] == 7'b1010011 ||
		    stage1_rg_stage_input[151:145] == 7'b1000011 ||
		    stage1_rg_stage_input[151:145] == 7'b1000111 ||
		    stage1_rg_stage_input[151:145] == 7'b1001011 ||
		    stage1_rg_stage_input[151:145] == 7'b1001111) &&
		   NOT_csr_regfile_read_mstatus__2_BITS_14_TO_13__ETC___d903;
    endcase
  end
  always@(stage1_rg_stage_input or
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d907)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0000011:
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q15 =
	      stage1_rg_stage_input[112:110] == 3'b0 ||
	      stage1_rg_stage_input[112:110] == 3'b100 ||
	      stage1_rg_stage_input[112:110] == 3'b001 ||
	      stage1_rg_stage_input[112:110] == 3'b101 ||
	      stage1_rg_stage_input[112:110] == 3'b010 ||
	      stage1_rg_stage_input[112:110] == 3'b110 ||
	      stage1_rg_stage_input[112:110] == 3'b011;
      7'b0100011:
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q15 =
	      stage1_rg_stage_input[112:110] == 3'b0 ||
	      stage1_rg_stage_input[112:110] == 3'b001 ||
	      stage1_rg_stage_input[112:110] == 3'b010 ||
	      stage1_rg_stage_input[112:110] == 3'b011;
      default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q15 =
		   stage1_rg_stage_input[151:145] != 7'b0001111 &&
		   stage1_rg_stage_input[151:145] != 7'b1110011 &&
		   IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d907;
    endcase
  end
  always@(stage1_rg_stage_input or
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q15 or
	  stage1_rg_stage_input_17_BITS_112_TO_110_61_EQ_ETC___d763)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0010011, 7'b0110011:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d915 =
	      stage1_rg_stage_input_17_BITS_112_TO_110_61_EQ_ETC___d763;
      7'b0011011:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d915 =
	      stage1_rg_stage_input[112:110] == 3'b0 ||
	      (stage1_rg_stage_input[112:110] == 3'b001 ||
	       stage1_rg_stage_input[112:110] == 3'b101) &&
	      !stage1_rg_stage_input[257];
      7'b0111011:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d915 =
	      stage1_rg_stage_input[97:88] == 10'b0 ||
	      stage1_rg_stage_input[97:88] == 10'b0100000000 ||
	      stage1_rg_stage_input[97:88] == 10'b0000000001 ||
	      stage1_rg_stage_input[97:88] == 10'b0000000101 ||
	      stage1_rg_stage_input[97:88] == 10'b0100000101;
      default: IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d915 =
		   stage1_rg_stage_input[151:145] == 7'b0110111 ||
		   stage1_rg_stage_input[151:145] == 7'b0010111 ||
		   CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q15;
    endcase
  end
  always@(rg_cur_priv)
  begin
    case (rg_cur_priv)
      2'b0: CASE_rg_cur_priv_0b0_8_0b1_9_11__q16 = 4'd8;
      2'b01: CASE_rg_cur_priv_0b0_8_0b1_9_11__q16 = 4'd9;
      default: CASE_rg_cur_priv_0b0_8_0b1_9_11__q16 = 4'd11;
    endcase
  end
  always@(stage1_rg_stage_input or CASE_rg_cur_priv_0b0_8_0b1_9_11__q16)
  begin
    case (stage1_rg_stage_input[87:76])
      12'b0:
	  CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q17 =
	      CASE_rg_cur_priv_0b0_8_0b1_9_11__q16;
      12'b000000000001:
	  CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q17 = 4'd3;
      default: CASE_stage1_rg_stage_input_BITS_87_TO_76_0b0_C_ETC__q17 = 4'd2;
    endcase
  end
  always@(stage1_rg_stage_input or alu_outputs___1_exc_code__h11224)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0000011,
      7'b0001111,
      7'b0010011,
      7'b0010111,
      7'b0011011,
      7'b0100011,
      7'b0110011,
      7'b0110111,
      7'b0111011,
      7'b1100011:
	  alu_outputs_exc_code__h11522 = 4'd2;
      7'b1100111, 7'b1101111: alu_outputs_exc_code__h11522 = 4'd0;
      7'b1110011:
	  alu_outputs_exc_code__h11522 = alu_outputs___1_exc_code__h11224;
      default: alu_outputs_exc_code__h11522 = 4'd2;
    endcase
  end
  always@(stage1_rg_stage_input or
	  rg_cur_priv or
	  IF_rg_cur_priv_1_EQ_0b11_45_OR_rg_cur_priv_1_E_ETC___d974)
  begin
    case (stage1_rg_stage_input[87:76])
      12'b0, 12'b000000000001:
	  IF_stage1_rg_stage_input_17_BITS_87_TO_76_53_E_ETC___d976 = 4'd12;
      default: IF_stage1_rg_stage_input_17_BITS_87_TO_76_53_E_ETC___d976 =
		   (rg_cur_priv == 2'b11 &&
		    stage1_rg_stage_input[87:76] == 12'b001100000010) ?
		     4'd8 :
		     IF_rg_cur_priv_1_EQ_0b11_45_OR_rg_cur_priv_1_E_ETC___d974;
    endcase
  end
  always@(stage1_rg_stage_input)
  begin
    case (stage1_rg_stage_input[112:110])
      3'b0: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q18 = 4'd5;
      3'b001: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q18 = 4'd6;
      default: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q18 =
		   4'd12;
    endcase
  end
  always@(stage1_rg_stage_input or
	  IF_stage1_rg_stage_input_17_BITS_144_TO_140_43_ETC___d978)
  begin
    case (stage1_rg_stage_input[112:110])
      3'b0:
	  CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q19 =
	      IF_stage1_rg_stage_input_17_BITS_144_TO_140_43_ETC___d978;
      3'b001, 3'b101:
	  CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q19 = 4'd3;
      3'b010, 3'b011, 3'b110, 3'b111:
	  CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q19 = 4'd4;
      3'd4: CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q19 = 4'd12;
    endcase
  end
  always@(stage1_rg_stage_input or
	  IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d936 or
	  CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q18 or
	  IF_NOT_stage1_rg_stage_input_17_BITS_112_TO_11_ETC___d930 or
	  IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d940 or
	  IF_NOT_csr_regfile_read_mstatus__2_BITS_14_TO__ETC___d986 or
	  CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q19)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0000011, 7'b0000111:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d998 =
	      IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d936;
      7'b0001111:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d998 =
	      CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q18;
      7'b0010011, 7'b0110011:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d998 =
	      IF_NOT_stage1_rg_stage_input_17_BITS_112_TO_11_ETC___d930;
      7'b0010111, 7'b0110111:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d998 = 4'd1;
      7'b0011011:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d998 =
	      (stage1_rg_stage_input[112:110] != 3'b0 &&
	       (stage1_rg_stage_input[112:110] != 3'b001 ||
		stage1_rg_stage_input[257]) &&
	       (stage1_rg_stage_input[112:110] != 3'b101 ||
		stage1_rg_stage_input[257])) ?
		4'd12 :
		4'd1;
      7'b0100011, 7'b0100111:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d998 =
	      IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d940;
      7'b0101111:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d998 =
	      ((stage1_rg_stage_input[109:105] == 5'b00010 ||
		stage1_rg_stage_input[109:105] == 5'b00011 ||
		stage1_rg_stage_input[109:105] == 5'b0 ||
		stage1_rg_stage_input[109:105] == 5'b00001 ||
		stage1_rg_stage_input[109:105] == 5'b01100 ||
		stage1_rg_stage_input[109:105] == 5'b01000 ||
		stage1_rg_stage_input[109:105] == 5'b00100 ||
		stage1_rg_stage_input[109:105] == 5'b10000 ||
		stage1_rg_stage_input[109:105] == 5'b11000 ||
		stage1_rg_stage_input[109:105] == 5'b10100 ||
		stage1_rg_stage_input[109:105] == 5'b11100) &&
	       (stage1_rg_stage_input[112:110] == 3'b010 ||
		stage1_rg_stage_input[112:110] == 3'b011)) ?
		4'd1 :
		4'd12;
      7'b0111011:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d998 =
	      (stage1_rg_stage_input[97:88] != 10'b0 &&
	       stage1_rg_stage_input[97:88] != 10'b0100000000 &&
	       stage1_rg_stage_input[97:88] != 10'b0000000001 &&
	       stage1_rg_stage_input[97:88] != 10'b0000000101 &&
	       stage1_rg_stage_input[97:88] != 10'b0100000101) ?
		4'd12 :
		4'd1;
      7'b1000011, 7'b1000111, 7'b1001011, 7'b1001111, 7'b1010011:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d998 =
	      IF_NOT_csr_regfile_read_mstatus__2_BITS_14_TO__ETC___d986;
      7'b1110011:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d998 =
	      CASE_stage1_rg_stage_input_BITS_112_TO_110_0b0_ETC__q19;
      default: IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d998 =
		   4'd12;
    endcase
  end
  always@(stage1_rg_stage_input or
	  stage1_rg_stage_input_17_BITS_151_TO_145_59_EQ_ETC___d756 or
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d998 or
	  IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d407)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b1100011:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d1001 =
	      (stage1_rg_stage_input[112:110] != 3'b0 &&
	       stage1_rg_stage_input[112:110] != 3'b001 &&
	       stage1_rg_stage_input[112:110] != 3'b100 &&
	       stage1_rg_stage_input[112:110] != 3'b101 &&
	       stage1_rg_stage_input[112:110] != 3'b110 &&
	       stage1_rg_stage_input[112:110] != 3'b111) ?
		4'd12 :
		(IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d407 ?
		   4'd2 :
		   4'd1);
      7'b1100111, 7'b1101111:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d1001 = 4'd2;
      default: IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d1001 =
		   stage1_rg_stage_input_17_BITS_151_TO_145_59_EQ_ETC___d756 ?
		     4'd1 :
		     IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d998;
    endcase
  end
  always@(stage1_rg_stage_input)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b1100011:
	  IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d1086 = 2'd0;
      7'b1100111:
	  IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d1086 = 2'd2;
      7'b1101111:
	  IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d1086 = 2'd1;
      default: IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d1086 =
		   2'd3;
    endcase
  end
  always@(stage1_rg_stage_input or
	  _theResult_____1_fst__h12337 or
	  rd_val___1__h12305 or
	  rd_val___1__h12312 or rd_val___1__h12319 or rd_val___1__h12326)
  begin
    case (stage1_rg_stage_input[112:110])
      3'b010: _theResult_____1_fst__h12309 = rd_val___1__h12305;
      3'b011: _theResult_____1_fst__h12309 = rd_val___1__h12312;
      3'b100: _theResult_____1_fst__h12309 = rd_val___1__h12319;
      3'b110: _theResult_____1_fst__h12309 = rd_val___1__h12326;
      default: _theResult_____1_fst__h12309 = _theResult_____1_fst__h12337;
    endcase
  end
  always@(stage1_rg_stage_input or
	  alu_outputs___1_addr__h10941 or
	  IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d1115 or
	  rs1_val_bypassed__h5803)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0000011, 7'b0000111:
	  alu_outputs_trace_data_word3__h28340 =
	      IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d1115;
      7'b0100011:
	  alu_outputs_trace_data_word3__h28340 = alu_outputs___1_addr__h10941;
      7'b0101111:
	  alu_outputs_trace_data_word3__h28340 = rs1_val_bypassed__h5803;
      default: alu_outputs_trace_data_word3__h28340 =
		   alu_outputs___1_addr__h10941;
    endcase
  end
  always@(stage1_rg_stage_input or
	  alu_outputs___1_addr__h10941 or
	  IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d1115 or
	  rs1_val_bypassed__h5803 or
	  alu_outputs___1_addr__h10542 or next_pc__h10594 or next_pc__h10557)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0000011, 7'b0000111:
	  x_out_data_to_stage2_addr__h10376 =
	      IF_stage1_rg_stage_input_17_BITS_139_TO_135_20_ETC___d1115;
      7'b0100011:
	  x_out_data_to_stage2_addr__h10376 = alu_outputs___1_addr__h10941;
      7'b0101111: x_out_data_to_stage2_addr__h10376 = rs1_val_bypassed__h5803;
      7'b1100011:
	  x_out_data_to_stage2_addr__h10376 = alu_outputs___1_addr__h10542;
      7'b1100111: x_out_data_to_stage2_addr__h10376 = next_pc__h10594;
      7'b1101111: x_out_data_to_stage2_addr__h10376 = next_pc__h10557;
      default: x_out_data_to_stage2_addr__h10376 =
		   alu_outputs___1_addr__h10941;
    endcase
  end
  always@(stage1_rg_stage_input or
	  next_pc__h10594 or branch_target__h10519 or next_pc__h10557)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b1100011: x_out_cf_info_taken_PC__h14806 = branch_target__h10519;
      7'b1101111: x_out_cf_info_taken_PC__h14806 = next_pc__h10557;
      default: x_out_cf_info_taken_PC__h14806 = next_pc__h10594;
    endcase
  end
  always@(stage1_rg_stage_input or
	  alu_outputs___1_trace_data_pc__h28288 or
	  alu_outputs___1_addr__h10542 or next_pc__h10594 or next_pc__h10557)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b1100011:
	  alu_outputs_trace_data_pc__h28334 = alu_outputs___1_addr__h10542;
      7'b1100111: alu_outputs_trace_data_pc__h28334 = next_pc__h10594;
      7'b1101111: alu_outputs_trace_data_pc__h28334 = next_pc__h10557;
      default: alu_outputs_trace_data_pc__h28334 =
		   alu_outputs___1_trace_data_pc__h28288;
    endcase
  end
  always@(stage1_rg_stage_input)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0000011, 7'b0000111:
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q22 = 3'd1;
      7'b0010011, 7'b0010111, 7'b0011011, 7'b0110011, 7'b0110111, 7'b0111011:
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q22 = 3'd0;
      7'b0100011, 7'b0100111:
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q22 = 3'd2;
      7'b0101111:
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q22 = 3'd4;
      default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q22 = 3'd5;
    endcase
  end
  always@(stage1_rg_stage_input or
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q22)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b1100011, 7'b1100111, 7'b1101111:
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q23 = 3'd0;
      default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q23 =
		   ((stage1_rg_stage_input[151:145] == 7'b0110011 ||
		     stage1_rg_stage_input[151:145] == 7'b0111011) &&
		    stage1_rg_stage_input[104:98] == 7'b0000001) ?
		     3'd3 :
		     CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q22;
    endcase
  end
  always@(stage1_rg_stage_input or rs2_val__h10515)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0100011, 7'b0101111:
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q24 =
	      rs2_val__h10515;
      default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q24 =
		   rs2_val__h10515;
    endcase
  end
  always@(stage1_rg_stage_input or
	  NOT_rg_cur_priv_1_EQ_0b11_45_433_AND_NOT_rg_cu_ETC___d1439 or
	  data_to_stage2_addr__h10358)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b1100111, 7'b1101111:
	  CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q25 =
	      data_to_stage2_addr__h10358;
      default: CASE_stage1_rg_stage_input_BITS_151_TO_145_0b1_ETC__q25 =
		   (stage1_rg_stage_input[151:145] == 7'b1110011 &&
		    stage1_rg_stage_input[112:110] == 3'b0 &&
		    NOT_rg_cur_priv_1_EQ_0b11_45_433_AND_NOT_rg_cu_ETC___d1439) ?
		     stage1_rg_stage_input[401:338] :
		     64'd0;
    endcase
  end
  always@(stage1_rg_stage_input or
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2334 or
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2335 or
	  IF_NOT_stage1_rg_stage_input_17_BITS_104_TO_98_ETC___d2336)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0000011, 7'b0000111:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2345 =
	      IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2334;
      7'b0001111, 7'b1100011, 7'b1110011:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2345 = 5'd5;
      7'b0010011,
      7'b0010111,
      7'b0011011,
      7'b0110011,
      7'b0110111,
      7'b0111011,
      7'b1100111,
      7'b1101111:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2345 = 5'd6;
      7'b0100011, 7'b0100111:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2345 =
	      IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2335;
      7'b0101111:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2345 = 5'd13;
      7'b1000011, 7'b1000111, 7'b1001011, 7'b1001111, 7'b1010011:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2345 =
	      IF_NOT_stage1_rg_stage_input_17_BITS_104_TO_98_ETC___d2336;
      default: IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2345 =
		   5'd14;
    endcase
  end
  always@(stage1_rg_stage_input or
	  alu_outputs___1_trace_data_word1__h28116 or
	  rd_val__h10736 or
	  rd_val__h10847 or
	  rd_val__h10767 or rd_val__h10823 or rd_val__h10798)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0010011, 7'b0110011:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2373 =
	      rd_val__h10736;
      7'b0010111:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2373 =
	      rd_val__h10847;
      7'b0011011:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2373 =
	      rd_val__h10767;
      7'b0100011:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2373 =
	      alu_outputs___1_trace_data_word1__h28116;
      7'b0110111:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2373 =
	      rd_val__h10823;
      7'b0111011:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2373 =
	      rd_val__h10798;
      default: IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2373 =
		   alu_outputs___1_trace_data_word1__h28116;
    endcase
  end
  always@(stage1_rg_stage_input or
	  rs1_val_bypassed__h5803 or
	  rd_val__h10736 or
	  rd_val__h10847 or
	  rd_val__h10767 or
	  alu_outputs___1_val1__h11257 or
	  rd_val__h10823 or rd_val__h10798 or alu_outputs___1_val1__h11228)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b0010011, 7'b0110011:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d1305 =
	      rd_val__h10736;
      7'b0010111:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d1305 =
	      rd_val__h10847;
      7'b0011011:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d1305 =
	      rd_val__h10767;
      7'b0101111:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d1305 =
	      alu_outputs___1_val1__h11257;
      7'b0110111:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d1305 =
	      rd_val__h10823;
      7'b0111011:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d1305 =
	      rd_val__h10798;
      7'b1110011:
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d1305 =
	      alu_outputs___1_val1__h11228;
      default: IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d1305 =
		   rs1_val_bypassed__h5803;
    endcase
  end
  always@(stage1_rg_stage_input or
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2374 or
	  alu_outputs___1_trace_data_pc__h28288)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b1100111, 7'b1101111:
	  alu_outputs_trace_data_word1__h28338 =
	      alu_outputs___1_trace_data_pc__h28288;
      default: alu_outputs_trace_data_word1__h28338 =
		   IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d2374;
    endcase
  end
  always@(stage1_rg_stage_input or
	  IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d1307 or
	  alu_outputs___1_trace_data_pc__h28288)
  begin
    case (stage1_rg_stage_input[151:145])
      7'b1100111, 7'b1101111:
	  x_out_data_to_stage2_val1__h10377 =
	      alu_outputs___1_trace_data_pc__h28288;
      default: x_out_data_to_stage2_val1__h10377 =
		   IF_stage1_rg_stage_input_17_BITS_151_TO_145_59_ETC___d1307;
    endcase
  end
  always@(stage2_rg_stage2 or
	  output_stage2___1_data_to_stage3_trace_data_word1__h27042 or
	  output_stage2___1_data_to_stage3_trace_data_word1__h27021 or
	  stage2_mbox$word)
  begin
    case (stage2_rg_stage2[824:822])
      3'd0, 3'd2:
	  IF_stage2_rg_stage2_18_BITS_824_TO_822_19_EQ_0_ETC___d2223 =
	      stage2_rg_stage2[319:256];
      3'd1, 3'd4:
	  IF_stage2_rg_stage2_18_BITS_824_TO_822_19_EQ_0_ETC___d2223 =
	      output_stage2___1_data_to_stage3_trace_data_word1__h27021;
      3'd3:
	  IF_stage2_rg_stage2_18_BITS_824_TO_822_19_EQ_0_ETC___d2223 =
	      stage2_mbox$word;
      default: IF_stage2_rg_stage2_18_BITS_824_TO_822_19_EQ_0_ETC___d2223 =
		   output_stage2___1_data_to_stage3_trace_data_word1__h27042;
    endcase
  end
  always@(stage2_rg_stage2 or
	  output_stage2___1_data_to_stage3_trace_data_word5__h27046)
  begin
    case (stage2_rg_stage2[824:822])
      3'd2, 3'd3:
	  CASE_stage2_rg_stage2_BITS_824_TO_822_2_stage2_ETC__q26 =
	      stage2_rg_stage2[63:0];
      default: CASE_stage2_rg_stage2_BITS_824_TO_822_2_stage2_ETC__q26 =
		   output_stage2___1_data_to_stage3_trace_data_word5__h27046;
    endcase
  end
  always@(stage2_rg_stage2 or
	  CASE_stage2_rg_stage2_BITS_824_TO_822_2_stage2_ETC__q26 or
	  IF_stage2_rg_stage2_18_BIT_432_08_THEN_csr_reg_ETC___d2230)
  begin
    case (stage2_rg_stage2[824:822])
      3'd0:
	  CASE_stage2_rg_stage2_BITS_824_TO_822_0_stage2_ETC__q27 =
	      stage2_rg_stage2[127:0];
      3'd1, 3'd4:
	  CASE_stage2_rg_stage2_BITS_824_TO_822_0_stage2_ETC__q27 =
	      IF_stage2_rg_stage2_18_BIT_432_08_THEN_csr_reg_ETC___d2230;
      default: CASE_stage2_rg_stage2_BITS_824_TO_822_0_stage2_ETC__q27 =
		   { stage2_rg_stage2[127:64],
		     CASE_stage2_rg_stage2_BITS_824_TO_822_2_stage2_ETC__q26 };
    endcase
  end
  always@(stage2_rg_stage2)
  begin
    case (stage2_rg_stage2[824:822])
      3'd1, 3'd4:
	  CASE_stage2_rg_stage2_BITS_824_TO_822_1_stage2_ETC__q28 =
	      stage2_rg_stage2[432];
      default: CASE_stage2_rg_stage2_BITS_824_TO_822_1_stage2_ETC__q28 =
		   stage2_rg_stage2[824:822] != 3'd2 &&
		   stage2_rg_stage2[824:822] != 3'd3 &&
		   stage2_rg_stage2[432];
    endcase
  end
  always@(stage2_rg_stage2)
  begin
    case (stage2_rg_stage2[824:822])
      3'd1, 3'd4:
	  CASE_stage2_rg_stage2_BITS_824_TO_822_1_NOT_st_ETC__q29 =
	      !stage2_rg_stage2[432];
      default: CASE_stage2_rg_stage2_BITS_824_TO_822_1_NOT_st_ETC__q29 =
		   stage2_rg_stage2[824:822] == 3'd2 ||
		   stage2_rg_stage2[824:822] == 3'd3 ||
		   !stage2_rg_stage2[432];
    endcase
  end

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        cfg_logdelay <= `BSV_ASSIGNMENT_DELAY 64'd0;
	cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
	imem_rg_cache_addr <= `BSV_ASSIGNMENT_DELAY 64'hFFFFFFFFFFFFFFFF;
	rg_cur_priv <= `BSV_ASSIGNMENT_DELAY 2'b11;
	rg_prev_mip <= `BSV_ASSIGNMENT_DELAY 64'd0;
	rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY 1'd0;
	rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0;
	rg_step_count <= `BSV_ASSIGNMENT_DELAY 1'd0;
	rg_stop_req <= `BSV_ASSIGNMENT_DELAY 1'd0;
	stage1_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	stage2_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY 1'd0;
	stage3_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	stageD_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	stageF_rg_epoch <= `BSV_ASSIGNMENT_DELAY 2'd0;
	stageF_rg_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
      end
    else
      begin
        if (cfg_logdelay$EN)
	  cfg_logdelay <= `BSV_ASSIGNMENT_DELAY cfg_logdelay$D_IN;
	if (cfg_verbosity$EN)
	  cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
	if (imem_rg_cache_addr$EN)
	  imem_rg_cache_addr <= `BSV_ASSIGNMENT_DELAY imem_rg_cache_addr$D_IN;
	if (rg_cur_priv$EN)
	  rg_cur_priv <= `BSV_ASSIGNMENT_DELAY rg_cur_priv$D_IN;
	if (rg_prev_mip$EN)
	  rg_prev_mip <= `BSV_ASSIGNMENT_DELAY rg_prev_mip$D_IN;
	if (rg_run_on_reset$EN)
	  rg_run_on_reset <= `BSV_ASSIGNMENT_DELAY rg_run_on_reset$D_IN;
	if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
	if (rg_step_count$EN)
	  rg_step_count <= `BSV_ASSIGNMENT_DELAY rg_step_count$D_IN;
	if (rg_stop_req$EN)
	  rg_stop_req <= `BSV_ASSIGNMENT_DELAY rg_stop_req$D_IN;
	if (stage1_rg_full$EN)
	  stage1_rg_full <= `BSV_ASSIGNMENT_DELAY stage1_rg_full$D_IN;
	if (stage2_rg_full$EN)
	  stage2_rg_full <= `BSV_ASSIGNMENT_DELAY stage2_rg_full$D_IN;
	if (stage2_rg_resetting$EN)
	  stage2_rg_resetting <= `BSV_ASSIGNMENT_DELAY
	      stage2_rg_resetting$D_IN;
	if (stage3_rg_full$EN)
	  stage3_rg_full <= `BSV_ASSIGNMENT_DELAY stage3_rg_full$D_IN;
	if (stageD_rg_full$EN)
	  stageD_rg_full <= `BSV_ASSIGNMENT_DELAY stageD_rg_full$D_IN;
	if (stageF_rg_epoch$EN)
	  stageF_rg_epoch <= `BSV_ASSIGNMENT_DELAY stageF_rg_epoch$D_IN;
	if (stageF_rg_full$EN)
	  stageF_rg_full <= `BSV_ASSIGNMENT_DELAY stageF_rg_full$D_IN;
      end
    if (imem_rg_cache_b16$EN)
      imem_rg_cache_b16 <= `BSV_ASSIGNMENT_DELAY imem_rg_cache_b16$D_IN;
    if (imem_rg_f3$EN) imem_rg_f3 <= `BSV_ASSIGNMENT_DELAY imem_rg_f3$D_IN;
    if (imem_rg_mstatus_MXR$EN)
      imem_rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY imem_rg_mstatus_MXR$D_IN;
    if (imem_rg_pc$EN) imem_rg_pc <= `BSV_ASSIGNMENT_DELAY imem_rg_pc$D_IN;
    if (imem_rg_priv$EN)
      imem_rg_priv <= `BSV_ASSIGNMENT_DELAY imem_rg_priv$D_IN;
    if (imem_rg_satp$EN)
      imem_rg_satp <= `BSV_ASSIGNMENT_DELAY imem_rg_satp$D_IN;
    if (imem_rg_sstatus_SUM$EN)
      imem_rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY imem_rg_sstatus_SUM$D_IN;
    if (imem_rg_tval$EN)
      imem_rg_tval <= `BSV_ASSIGNMENT_DELAY imem_rg_tval$D_IN;
    if (rg_csr_pc$EN) rg_csr_pc <= `BSV_ASSIGNMENT_DELAY rg_csr_pc$D_IN;
    if (rg_csr_val1$EN) rg_csr_val1 <= `BSV_ASSIGNMENT_DELAY rg_csr_val1$D_IN;
    if (rg_epoch$EN) rg_epoch <= `BSV_ASSIGNMENT_DELAY rg_epoch$D_IN;
    if (rg_mstatus_MXR$EN)
      rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY rg_mstatus_MXR$D_IN;
    if (rg_next_pc$EN) rg_next_pc <= `BSV_ASSIGNMENT_DELAY rg_next_pc$D_IN;
    if (rg_sstatus_SUM$EN)
      rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY rg_sstatus_SUM$D_IN;
    if (rg_start_CPI_cycles$EN)
      rg_start_CPI_cycles <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_cycles$D_IN;
    if (rg_start_CPI_instrs$EN)
      rg_start_CPI_instrs <= `BSV_ASSIGNMENT_DELAY rg_start_CPI_instrs$D_IN;
    if (rg_trap_info$EN)
      rg_trap_info <= `BSV_ASSIGNMENT_DELAY rg_trap_info$D_IN;
    if (rg_trap_instr$EN)
      rg_trap_instr <= `BSV_ASSIGNMENT_DELAY rg_trap_instr$D_IN;
    if (rg_trap_interrupt$EN)
      rg_trap_interrupt <= `BSV_ASSIGNMENT_DELAY rg_trap_interrupt$D_IN;
    if (rg_trap_trace_data$EN)
      rg_trap_trace_data <= `BSV_ASSIGNMENT_DELAY rg_trap_trace_data$D_IN;
    if (stage1_rg_stage_input$EN)
      stage1_rg_stage_input <= `BSV_ASSIGNMENT_DELAY
	  stage1_rg_stage_input$D_IN;
    if (stage2_rg_stage2$EN)
      stage2_rg_stage2 <= `BSV_ASSIGNMENT_DELAY stage2_rg_stage2$D_IN;
    if (stage3_rg_stage3$EN)
      stage3_rg_stage3 <= `BSV_ASSIGNMENT_DELAY stage3_rg_stage3$D_IN;
    if (stageD_rg_data$EN)
      stageD_rg_data <= `BSV_ASSIGNMENT_DELAY stageD_rg_data$D_IN;
    if (stageF_rg_priv$EN)
      stageF_rg_priv <= `BSV_ASSIGNMENT_DELAY stageF_rg_priv$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    cfg_logdelay = 64'hAAAAAAAAAAAAAAAA;
    cfg_verbosity = 4'hA;
    imem_rg_cache_addr = 64'hAAAAAAAAAAAAAAAA;
    imem_rg_cache_b16 = 16'hAAAA;
    imem_rg_f3 = 3'h2;
    imem_rg_mstatus_MXR = 1'h0;
    imem_rg_pc = 64'hAAAAAAAAAAAAAAAA;
    imem_rg_priv = 2'h2;
    imem_rg_satp = 64'hAAAAAAAAAAAAAAAA;
    imem_rg_sstatus_SUM = 1'h0;
    imem_rg_tval = 64'hAAAAAAAAAAAAAAAA;
    rg_csr_pc = 64'hAAAAAAAAAAAAAAAA;
    rg_csr_val1 = 64'hAAAAAAAAAAAAAAAA;
    rg_cur_priv = 2'h2;
    rg_epoch = 2'h2;
    rg_mstatus_MXR = 1'h0;
    rg_next_pc = 64'hAAAAAAAAAAAAAAAA;
    rg_prev_mip = 64'hAAAAAAAAAAAAAAAA;
    rg_run_on_reset = 1'h0;
    rg_sstatus_SUM = 1'h0;
    rg_start_CPI_cycles = 64'hAAAAAAAAAAAAAAAA;
    rg_start_CPI_instrs = 64'hAAAAAAAAAAAAAAAA;
    rg_state = 4'hA;
    rg_step_count = 1'h0;
    rg_stop_req = 1'h0;
    rg_trap_info = 132'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    rg_trap_instr = 32'hAAAAAAAA;
    rg_trap_interrupt = 1'h0;
    rg_trap_trace_data =
	427'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    stage1_rg_full = 1'h0;
    stage1_rg_stage_input =
	402'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    stage2_rg_full = 1'h0;
    stage2_rg_resetting = 1'h0;
    stage2_rg_stage2 =
	923'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    stage3_rg_full = 1'h0;
    stage3_rg_stage3 =
	666'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    stageD_rg_data =
	234'h2AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA;
    stageD_rg_full = 1'h0;
    stageF_rg_epoch = 2'h2;
    stageF_rg_full = 1'h0;
    stageF_rg_priv = 2'h2;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$display("================================================================");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$display("%0d: Pipeline State:  minstret:%0d  cur_priv:%0d  mstatus:%0x  epoch:%0d",
		 csr_regfile$read_csr_mcycle,
		 csr_regfile$read_csr_minstret,
		 rg_cur_priv,
		 csr_regfile$read_mstatus,
		 rg_epoch);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write("MStatus{",
	       "sd:%0d",
	       csr_regfile$read_mstatus[14:13] == 2'h3 ||
	       csr_regfile$read_mstatus[16:15] == 2'h3);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] == 2'd2)
	$write(" sxl:%0d uxl:%0d", sxl__h8089, uxl__h8090);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && csr_regfile$read_misa[27:26] != 2'd2)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" tsr:%0d", csr_regfile$read_mstatus[22]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" tw:%0d", csr_regfile$read_mstatus[21]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" tvm:%0d", csr_regfile$read_mstatus[20]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" mxr:%0d", csr_regfile$read_mstatus[19]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" sum:%0d", csr_regfile$read_mstatus[18]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" mprv:%0d", csr_regfile$read_mstatus[17]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" xs:%0d", csr_regfile$read_mstatus[16:15]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" fs:%0d", csr_regfile$read_mstatus[14:13]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" mpp:%0d", csr_regfile$read_mstatus[12:11]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" spp:%0d", csr_regfile$read_mstatus[8]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" pies:%0d_%0d%0d",
	       csr_regfile$read_mstatus[7],
	       csr_regfile$read_mstatus[5],
	       csr_regfile$read_mstatus[4]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$write(" ies:%0d_%0d%0d",
	       csr_regfile$read_mstatus[3],
	       csr_regfile$read_mstatus[1],
	       csr_regfile$read_mstatus[0]);
    if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("    Stage3: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("Output_Stage3");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_full) $write(" PIPE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_full) $write(" EMPTY");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("        Bypass  to Stage1: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  (stage3_rg_stage3[496] || !stage3_rg_full ||
	   !stage3_rg_stage3[567]))
	$write("Rd -");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_stage3[496] &&
	  stage3_rg_full &&
	  stage3_rg_stage3[567])
	$write("Rd %0d ", stage3_rg_stage3[566:562]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  (stage3_rg_stage3[496] || !stage3_rg_full ||
	   !stage3_rg_stage3[567]))
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage3_rg_stage3[496] &&
	  stage3_rg_full &&
	  stage3_rg_stage3[567])
	$write("rd_val:%h", stage3_rg_stage3[561:498]);
    if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("        FBypass to Stage1: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("FBypass {");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  (!stage3_rg_stage3[496] || !stage3_rg_full ||
	   !stage3_rg_stage3[567]))
	$write("FRd -");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_stage3[496] &&
	  stage3_rg_full &&
	  stage3_rg_stage3[567])
	$write("FRd %0d ", stage3_rg_stage3[566:562]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  (!stage3_rg_stage3[496] || !stage3_rg_full ||
	   !stage3_rg_stage3[567]))
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage3_rg_stage3[496] &&
	  stage3_rg_full &&
	  stage3_rg_stage3[567])
	$write("frd_val:%h", stage3_rg_stage3[490:427]);
    if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$display("    Stage2: pc 0x%08h instr 0x%08h priv %0d",
		 stage2_rg_stage2[920:857],
		 stage2_rg_stage2[856:825],
		 stage2_rg_stage2[922:921]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("        ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd0)
	$write("Output_Stage2", " EMPTY");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd1)
	$write("Output_Stage2", " BUSY: pc:%0h", stage2_rg_stage2[920:857]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd3)
	$write("Output_Stage2", " NONPIPE: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd0 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd1 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd3)
	$write("Output_Stage2", " PIPE: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd0 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd1 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd3)
	$write("data_to_Stage3 {pc:%h  instr:%h  priv:%0d\n",
	       stage2_rg_stage2[920:857],
	       stage2_rg_stage2[856:825],
	       stage2_rg_stage2[922:921]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd0 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd1 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd3)
	$write("        rd_valid:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd0 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd1 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd3 &&
	  stage2_rg_stage2[824:822] != 3'd0 &&
	  IF_stage2_rg_stage2_18_BITS_824_TO_822_19_EQ_1_ETC___d169)
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd0 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd1 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd3 &&
	  (stage2_rg_stage2[824:822] == 3'd0 ||
	   IF_stage2_rg_stage2_18_BITS_824_TO_822_19_EQ_1_ETC___d179))
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd0 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd1 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd3 &&
	  stage2_rg_stage2[824:822] != 3'd0 &&
	  stage2_rg_stage2[824:822] != 3'd1 &&
	  stage2_rg_stage2[824:822] != 3'd4 &&
	  stage2_rg_stage2[824:822] != 3'd2 &&
	  stage2_rg_stage2[824:822] != 3'd3)
	$write("  fflags: %05b",
	       "'h%h",
	       x_out_data_to_stage3_fpr_flags__h9224);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd0 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd1 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd3 &&
	  (stage2_rg_stage2[824:822] == 3'd0 ||
	   stage2_rg_stage2[824:822] == 3'd1 ||
	   stage2_rg_stage2[824:822] == 3'd4 ||
	   stage2_rg_stage2[824:822] == 3'd2 ||
	   stage2_rg_stage2[824:822] == 3'd3))
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd0 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd1 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd3 &&
	  stage2_rg_stage2[824:822] != 3'd0 &&
	  CASE_stage2_rg_stage2_BITS_824_TO_822_1_stage2_ETC__q28)
	$write("  frd:%0d  rd_val:%h\n",
	       x_out_data_to_stage3_rd__h9220,
	       x_out_data_to_stage3_frd_val__h9225);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd0 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd1 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd3 &&
	  (stage2_rg_stage2[824:822] == 3'd0 ||
	   CASE_stage2_rg_stage2_BITS_824_TO_822_1_NOT_st_ETC__q29))
	$write("  grd:%0d  rd_val:%h\n",
	       x_out_data_to_stage3_rd__h9220,
	       x_out_data_to_stage3_rd_val__h9221);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd3)
	$write("Trap_Info { ", "epc: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd0 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd1 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd3)
	$write("'h%h", value__h9553);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd0 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd1 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd3)
	$write(", ", "exc_code: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd0 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd1 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd3)
	$write("'h%h", x_out_trap_info_exc_code__h9590);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd0 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd1 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd3)
	$write(", ", "tval: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd0 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd1 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd3)
	$write("'h%h", value__h9614, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd0 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd1 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd3)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd0 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd1 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd3)
	$write("Trap_Info { ", "epc: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd0 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd1 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd3)
	$write("'h%h", value__h9553);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd0 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd1 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd3)
	$write(", ", "exc_code: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd0 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd1 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd3)
	$write("'h%h", x_out_trap_info_exc_code__h9590);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd0 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd1 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd3)
	$write(", ", "tval: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd0 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd1 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd1)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd3)
	$write("'h%h", value__h9614, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd0 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd1 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 != 2'd3)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("        Bypass  to Stage1: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("Bypass {");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d283 == 2'd0)
	$write("Rd -");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d283 != 2'd0)
	$write("Rd %0d ", x_out_bypass_rd__h9855);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d283 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d283 == 2'd1)
	$write("-");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d283 != 2'd0 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d283 != 2'd1)
	$write("rd_val:%h", x_out_bypass_rd_val__h9856);
    if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("        FBypass to Stage1: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("FBypass {");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d301 == 2'd0)
	$write("FRd -");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d301 != 2'd0)
	$write("FRd %0d ", x_out_fbypass_rd__h9983);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d301 == 2'd0)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d301 == 2'd1)
	$write("-");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d301 != 2'd0 &&
	  IF_NOT_stage2_rg_full_17_57_OR_stage2_rg_stage_ETC___d301 != 2'd1)
	$write("frd_val:%h", x_out_fbypass_rd_val__h9984);
    if (RST_N != `BSV_RESET_VALUE) if (WILL_FIRE_RL_rl_show_pipe) $write("}");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$display("    Stage1: pc 0x%08h instr 0x%08h priv %0d",
		 stage1_rg_stage_input[401:338],
		 stage1_rg_stage_input[263:232],
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("        ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333)
	$write("Output_Stage1",
	       " BUSY pc:%h",
	       stage1_rg_stage_input[401:338]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739)
	$write("Output_Stage1",
	       " NONPIPE: pc:%h",
	       stage1_rg_stage_input[401:338]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d926)
	$write("Output_Stage1");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full)
	$write("Output_Stage1", " EMPTY");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d926)
	$write(" PIPE: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357) &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 == 4'd0)
	$write("CONTROL_DISCARD");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357) &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 == 4'd1)
	$write("CONTROL_STRAIGHT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357) &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 == 4'd2)
	$write("CONTROL_BRANCH");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357) &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 == 4'd3)
	$write("CONTROL_CSRR_W");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357) &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 == 4'd4)
	$write("CONTROL_CSRR_S_or_C");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357) &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 == 4'd5)
	$write("CONTROL_FENCE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357) &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 == 4'd6)
	$write("CONTROL_FENCE_I");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357) &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 == 4'd7)
	$write("CONTROL_SFENCE_VMA");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357) &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 == 4'd8)
	$write("CONTROL_MRET");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357) &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 == 4'd9)
	$write("CONTROL_SRET");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357) &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 == 4'd10)
	$write("CONTROL_URET");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357) &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 == 4'd11)
	$write("CONTROL_WFI");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357) &&
	  NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d1077)
	$write("CONTROL_TRAP");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d926)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d1089)
	$write("{", "CF_None");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d1093)
	$write("{", "BR ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d1099)
	$write("{");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d1089)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d1093)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357) &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) &&
	  IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d1086 == 2'd1)
	$write("JAL [%h->%h/%h]",
	       stage1_rg_stage_input[401:338],
	       x_out_cf_info_taken_PC__h14806,
	       x_out_cf_info_fallthru_PC__h14805);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357) &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) &&
	  IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d1086 == 2'd2)
	$write("JALR [%h->%h/%h]",
	       stage1_rg_stage_input[401:338],
	       x_out_cf_info_taken_PC__h14806,
	       x_out_cf_info_fallthru_PC__h14805);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d1089)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d1093)
	if (stage1_rg_stage_input[151:145] != 7'b1100011 ||
	    IF_stage1_rg_stage_input_17_BITS_112_TO_110_61_ETC___d407)
	  $write("taken ");
	else
	  $write("fallthru ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d1099)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d1089)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d1093)
	$write("[%h->%h %h]",
	       stage1_rg_stage_input[401:338],
	       x_out_cf_info_fallthru_PC__h14805,
	       x_out_cf_info_taken_PC__h14806);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d1099)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d926)
	$write("}");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d926)
	$write("data_to_Stage 2 {pc:%h  instr:%h  priv:%0d\n",
	       stage1_rg_stage_input[401:338],
	       stage1_rg_stage_input[263:232],
	       rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d926)
	$write("            op_stage2:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357) &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153 == 3'd0)
	$write("OP_Stage2_ALU");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357) &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153 == 3'd1)
	$write("OP_Stage2_LD");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357) &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153 == 3'd2)
	$write("OP_Stage2_ST");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357) &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153 == 3'd3)
	$write("OP_Stage2_M");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357) &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d923) &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153 == 3'd4)
	$write("OP_Stage2_AMO");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d1186)
	$write("OP_Stage2_FD");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d926)
	$write("  rd:%0d\n", x_out_data_to_stage2_rd__h10375);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d926)
	$write("            addr:%h  val1:%h  val2:%h}",
	       x_out_data_to_stage2_addr__h10376,
	       x_out_data_to_stage2_val1__h10377,
	       x_out_data_to_stage2_val2__h10378);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d926)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d926)
	$write("            fval1:%h  fval2:%h  fval3:%h}",
	       x_out_data_to_stage2_fval1__h10379,
	       alu_outputs___1_fval2__h10945,
	       x_out_data_to_stage2_fval3__h10381);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d926)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 == 4'd0)
	$write("CONTROL_DISCARD");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 == 4'd1)
	$write("CONTROL_STRAIGHT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 == 4'd2)
	$write("CONTROL_BRANCH");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 == 4'd3)
	$write("CONTROL_CSRR_W");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 == 4'd4)
	$write("CONTROL_CSRR_S_or_C");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 == 4'd5)
	$write("CONTROL_FENCE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 == 4'd6)
	$write("CONTROL_FENCE_I");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 == 4'd7)
	$write("CONTROL_SFENCE_VMA");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 == 4'd8)
	$write("CONTROL_MRET");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 == 4'd9)
	$write("CONTROL_SRET");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 == 4'd10)
	$write("CONTROL_URET");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 == 4'd11)
	$write("CONTROL_WFI");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d1393)
	$write("CONTROL_TRAP");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d926)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739)
	$write(" ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d926)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739)
	$write("Trap_Info { ", "epc: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d926)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739)
	$write("'h%h", stage1_rg_stage_input[401:338]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d926)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739)
	$write(", ", "exc_code: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d926)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739)
	$write("'h%h", x_out_trap_info_exc_code__h14560);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d926)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739)
	$write(", ", "tval: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d926)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d739)
	$write("'h%h", value__h14669, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stage1_rg_full_16_AND_NOT_stage1_rg_stage_inpu_ETC___d926)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d333)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357) &&
	  !IF_IF_stage1_rg_stage_input_17_BITS_151_TO_145_ETC___d1451)
	$write("\n        redirect next_pc:%h", x_out_next_pc__h10308);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stage1_rg_full &&
	  (!stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d319 ||
	   NOT_IF_stage2_rg_full_17_THEN_IF_stage2_rg_sta_ETC___d357) &&
	  IF_IF_stage1_rg_stage_input_17_BITS_151_TO_145_ETC___d1451)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stage1_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$display("    StageD: pc 0x%08h instr 0x%08h priv %0d epoch %0d",
		 stageD_rg_data[233:170],
		 x_out_data_to_stage1_instr__h15891,
		 stageD_rg_data[167:166],
		 stageD_rg_data[169:168]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("        ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("Output_StageD");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full) $write(" PIPE: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write(" EMPTY");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[164])
	$write("data_to_Stage1 {pc:%0h  priv:%0d  epoch:%0d",
	       stageD_rg_data[233:170],
	       stageD_rg_data[167:166],
	       stageD_rg_data[169:168]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[164])
	$write("data_to_Stage1 {pc:%0h  priv:%0d  epoch:%0d",
	       stageD_rg_data[233:170],
	       stageD_rg_data[167:166],
	       stageD_rg_data[169:168]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[164])
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  !stageD_rg_data[164] &&
	  stageD_rg_data[165])
	$write("  instr_C:%0h", stageD_rg_data[79:64]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  !stageD_rg_data[164] &&
	  !stageD_rg_data[165])
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[164])
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[164])
	$write("  instr:%0h  pred_pc:%0h",
	       x_out_data_to_stage1_instr__h15891,
	       stageD_rg_data[63:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[164])
	$write("  ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[164])
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[164] &&
	  stageD_rg_data[163:160] == 4'd0)
	$write("INSTRUCTION_ADDR_MISALIGNED");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[164] &&
	  stageD_rg_data[163:160] == 4'd1)
	$write("INSTRUCTION_ACCESS_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[164] &&
	  stageD_rg_data[163:160] == 4'd2)
	$write("ILLEGAL_INSTRUCTION");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[164] &&
	  stageD_rg_data[163:160] == 4'd3)
	$write("BREAKPOINT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[164] &&
	  stageD_rg_data[163:160] == 4'd4)
	$write("LOAD_ADDR_MISALIGNED");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[164] &&
	  stageD_rg_data[163:160] == 4'd5)
	$write("LOAD_ACCESS_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[164] &&
	  stageD_rg_data[163:160] == 4'd6)
	$write("STORE_AMO_ADDR_MISALIGNED");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[164] &&
	  stageD_rg_data[163:160] == 4'd7)
	$write("STORE_AMO_ACCESS_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[164] &&
	  stageD_rg_data[163:160] == 4'd8)
	$write("ECALL_FROM_U");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[164] &&
	  stageD_rg_data[163:160] == 4'd9)
	$write("ECALL_FROM_S");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[164] &&
	  stageD_rg_data[163:160] == 4'd11)
	$write("ECALL_FROM_M");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[164] &&
	  stageD_rg_data[163:160] == 4'd12)
	$write("INSTRUCTION_PAGE_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[164] &&
	  stageD_rg_data[163:160] == 4'd13)
	$write("LOAD_PAGE_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[164] &&
	  stageD_rg_data[163:160] == 4'd15)
	$write("STORE_AMO_PAGE_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full &&
	  stageD_rg_data[164] &&
	  stageD_rg_data[163:160] != 4'd0 &&
	  stageD_rg_data[163:160] != 4'd1 &&
	  stageD_rg_data[163:160] != 4'd2 &&
	  stageD_rg_data[163:160] != 4'd3 &&
	  stageD_rg_data[163:160] != 4'd4 &&
	  stageD_rg_data[163:160] != 4'd5 &&
	  stageD_rg_data[163:160] != 4'd6 &&
	  stageD_rg_data[163:160] != 4'd7 &&
	  stageD_rg_data[163:160] != 4'd8 &&
	  stageD_rg_data[163:160] != 4'd9 &&
	  stageD_rg_data[163:160] != 4'd11 &&
	  stageD_rg_data[163:160] != 4'd12 &&
	  stageD_rg_data[163:160] != 4'd13 &&
	  stageD_rg_data[163:160] != 4'd15)
	$write("unknown trap Exc_Code %d", stageD_rg_data[163:160]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[164])
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && stageD_rg_data[164])
	$write(" tval %0h", stageD_rg_data[159:96]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full && !stageD_rg_data[164])
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageD_rg_full) $write("}");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stageD_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe)
	$display("    StageF: pc 0x%08h instr 0x%08h priv %0d epoch %0d",
		 imem_rg_pc,
		 d_instr__h23510,
		 stageF_rg_priv,
		 stageF_rg_epoch);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("        ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("Output_StageF");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
	  (!near_mem$imem_valid ||
	   imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1905))
	$write(" BUSY: pc:%h", imem_rg_pc);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
	  near_mem$imem_valid &&
	  NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911)
	$write(" PIPE: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write(" EMPTY");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
	  (!near_mem$imem_valid ||
	   imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1905))
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
	  near_mem$imem_valid &&
	  NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911)
	$write("data_to_StageD {pc:%h  priv:%0d  epoch:%0d",
	       imem_rg_pc,
	       stageF_rg_priv,
	       stageF_rg_epoch);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
	  (!near_mem$imem_valid ||
	   imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1905))
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
	  near_mem$imem_valid &&
	  NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911 &&
	  near_mem$imem_exc)
	$write("  ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1920)
	$write("  instr:%h  pred_pc:%h",
	       d_instr__h23510,
	       stageF_branch_predictor$predict_rsp);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
	  (!near_mem$imem_valid ||
	   imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1905))
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1926)
	$write("INSTRUCTION_ADDR_MISALIGNED");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1930)
	$write("INSTRUCTION_ACCESS_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1934)
	$write("ILLEGAL_INSTRUCTION");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1938)
	$write("BREAKPOINT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1942)
	$write("LOAD_ADDR_MISALIGNED");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1946)
	$write("LOAD_ACCESS_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1950)
	$write("STORE_AMO_ADDR_MISALIGNED");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1954)
	$write("STORE_AMO_ACCESS_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1958)
	$write("ECALL_FROM_U");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1962)
	$write("ECALL_FROM_S");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1966)
	$write("ECALL_FROM_M");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1970)
	$write("INSTRUCTION_PAGE_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1974)
	$write("LOAD_PAGE_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1978)
	$write("STORE_AMO_PAGE_FAULT");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
	  near_mem_imem_valid_AND_NOT_imem_rg_pc_BITS_1__ETC___d2007)
	$write("unknown trap Exc_Code %d", near_mem$imem_exc_code);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe &&
	  stageF_rg_full_888_AND_near_mem_imem_valid_AND_ETC___d1920)
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
	  (!near_mem$imem_valid ||
	   imem_rg_pc_BITS_1_TO_0_EQ_0b0_OR_NOT_imem_rg_p_ETC___d1905))
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && stageF_rg_full &&
	  near_mem$imem_valid &&
	  NOT_imem_rg_pc_BITS_1_TO_0_EQ_0b0_AND_imem_rg__ETC___d1911)
	$write("}");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe && !stageF_rg_full) $write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_show_pipe) $display("----------------");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_mip_cmd &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_stage1_mip_cmd: MIP new 0x%0h, old 0x%0h",
		 csr_regfile$read_csr_mcycle,
		 csr_regfile$csr_mip_read,
		 rg_prev_mip);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_run_redundant &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_debug_run_redundant",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_run_redundant)
	$display("%0d: %m.debug_run_redundant: CPU already running.",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_debug_halt", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_debug_halt", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_debug_halt_redundant",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant)
	$display("%0d: %m.rl_debug_halt_redundant: CPU already halted.",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant) $write("    state = ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd0)
	$write("CPU_RESET1");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd1)
	$write("CPU_RESET2");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd2)
	$write("CPU_GDB_PAUSING");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd3)
	$write("CPU_DEBUG_MODE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd4)
	$write("CPU_RUNNING");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd5)
	$write("CPU_TRAP");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd6)
	$write("CPU_START_TRAP_HANDLER");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd7)
	$write("CPU_CSRRW_2");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd8)
	$write("CPU_CSRR_S_or_C_2");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd9)
	$write("CPU_CSRRX_RESTART");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd10)
	$write("CPU_FENCE_I");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd11)
	$write("CPU_FENCE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state == 4'd12)
	$write("CPU_SFENCE_VMA");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant && rg_state != 4'd0 &&
	  rg_state != 4'd1 &&
	  rg_state != 4'd2 &&
	  rg_state != 4'd3 &&
	  rg_state != 4'd4 &&
	  rg_state != 4'd5 &&
	  rg_state != 4'd6 &&
	  rg_state != 4'd7 &&
	  rg_state != 4'd8 &&
	  rg_state != 4'd9 &&
	  rg_state != 4'd10 &&
	  rg_state != 4'd11 &&
	  rg_state != 4'd12)
	$write("CPU_WFI_PAUSED");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_halt_redundant) $write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_read_gpr &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_debug_read_gpr: reg %0d => 0x%0h",
		 csr_regfile$read_csr_mcycle,
		 f_gpr_reqs$D_OUT[68:64],
		 gpr_regfile$read_rs1_port2);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_write_gpr &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_debug_write_gpr: reg %0d <= 0x%0h",
		 csr_regfile$read_csr_mcycle,
		 f_gpr_reqs$D_OUT[68:64],
		 f_gpr_reqs$D_OUT[63:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_gpr_access_busy &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_debug_gpr_access_busy",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_read_fpr &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_debug_read_fpr: reg %0d => 0x%0h",
		 csr_regfile$read_csr_mcycle,
		 f_fpr_reqs$D_OUT[68:64],
		 fpr_regfile$read_rs1_port2);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_write_fpr &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_debug_write_fpr: reg %0d <= 0x%0h",
		 csr_regfile$read_csr_mcycle,
		 f_fpr_reqs$D_OUT[68:64],
		 f_fpr_reqs$D_OUT[63:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_fpr_access_busy &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_debug_fpr_access_busy",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_read_csr &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_debug_read_csr: csr %0d => 0x%0h",
		 csr_regfile$read_csr_mcycle,
		 f_csr_reqs$D_OUT[75:64],
		 csr_regfile$read_csr_port2[63:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_run &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_debug_run", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_run &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$write("    %m.enq:  pc:0x%0h  epoch:%0d  priv:%0d",
	       csr_regfile$read_dpc,
	       new_epoch__h25078,
	       rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_run &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$write("  sstatus_SUM:%0d  mstatus_MXR:%0d  satp:0x%0h",
	       csr_regfile$read_sstatus[18],
	       csr_regfile$read_mstatus[19],
	       csr_regfile$read_satp);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_run &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_run &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("    fa_stageF_redirect: minstret:%0d  new_pc:%0x  cur_priv:%0d, epoch %0d->%0d",
		 csr_regfile$read_csr_minstret,
		 csr_regfile$read_dpc,
		 rg_cur_priv,
		 rg_epoch,
		 new_epoch__h25078);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_write_csr &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_debug_write_csr: csr 0x%0h 0x%0h <= 0x%0h",
		 csr_regfile$read_csr_mcycle,
		 f_csr_reqs$D_OUT[75:64],
		 f_csr_reqs$D_OUT[63:0],
		 { csr_regfile$mav_csr_write[128:64], x__h35168 });
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_debug_csr_access_busy &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_debug_csr_access_busy",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage2_nonpipe &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_stage2_nonpipe", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_trap &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_stage1_trap", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap &&
	  (cur_verbosity__h4054 != 4'd0 ||
	   csr_regfile$read_csr_minstret[19:0] == 20'd0))
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 rg_trap_info[131:68],
		 rg_trap_instr,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap && cur_verbosity__h4054 != 4'd0)
	$display("    mcause:0x%0h  epc 0x%0h  tval:0x%0h  next_pc 0x%0h, new_priv %0d new_mstatus 0x%0h",
		 csr_regfile$csr_trap_actions[65:2],
		 rg_trap_info[131:68],
		 rg_trap_info[63:0],
		 csr_regfile$csr_trap_actions[193:130],
		 csr_regfile$csr_trap_actions[1:0],
		 csr_regfile$csr_trap_actions[129:66]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_W &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_stage1_CSRR_W", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_stage1_CSRR_W_2", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 && csr_regfile$access_permitted_1 &&
	  (cur_verbosity__h4054 != 4'd0 ||
	   csr_regfile$read_csr_minstret[19:0] == 20'd0))
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 rg_csr_pc,
		 rg_trap_instr,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 && csr_regfile$access_permitted_1 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("    S1: write CSRRW/CSRRWI Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d",
		 rg_trap_instr[19:15],
		 rs1_val__h34674,
		 rg_trap_instr[31:20],
		 csr_regfile$read_csr[63:0],
		 rg_trap_instr[11:7]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_W_2 &&
	  !csr_regfile$access_permitted_1 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("    Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d",
		 rg_trap_instr[19:15],
		 rs1_val__h34674,
		 rg_trap_instr[31:20],
		 rg_trap_instr[11:7]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_stage1_CSRR_S_or_C",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_stage1_CSRR_S_or_C_2",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	  csr_regfile$access_permitted_2 &&
	  (cur_verbosity__h4054 != 4'd0 ||
	   csr_regfile$read_csr_minstret[19:0] == 20'd0))
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 rg_csr_pc,
		 rg_trap_instr,
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	  csr_regfile$access_permitted_2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("    S1: write CSRR_S_or_C: Rs1 %0d Rs1_val 0x%0h csr 0x%0h csr_val 0x%0h Rd %0d",
		 rg_trap_instr[19:15],
		 rs1_val__h35619,
		 rg_trap_instr[31:20],
		 csr_regfile$read_csr[63:0],
		 rg_trap_instr[11:7]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_CSRR_S_or_C_2 &&
	  !csr_regfile$access_permitted_2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("    Trap on CSR permissions: Rs1 %0d Rs1_val 0x%0h csr 0x%0h Rd %0d",
		 rg_trap_instr[19:15],
		 rs1_val__h35619,
		 rg_trap_instr[31:20],
		 rg_trap_instr[11:7]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_stage1_restart_after_csrrx",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$write("    %m.enq:  pc:0x%0h  epoch:%0d  priv:%0d",
	       rg_next_pc,
	       new_epoch__h25078,
	       rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$write("  sstatus_SUM:%0d  mstatus_MXR:%0d  satp:0x%0h",
	       csr_regfile$read_sstatus[18],
	       csr_regfile$read_mstatus[19],
	       csr_regfile$read_satp);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_restart_after_csrrx &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("    fa_stageF_redirect: minstret:%0d  new_pc:%0x  cur_priv:%0d, epoch %0d->%0d",
		 csr_regfile$read_csr_minstret,
		 rg_next_pc,
		 rg_cur_priv,
		 rg_epoch,
		 new_epoch__h25078);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_xRET &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_stage1_xRET", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_xRET &&
	  (cur_verbosity__h4054 != 4'd0 ||
	   csr_regfile$read_csr_minstret[19:0] == 20'd0))
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 stage1_rg_stage_input[401:338],
		 stage1_rg_stage_input[263:232],
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_xRET && cur_verbosity__h4054 != 4'd0)
	$display("    xRET: next_pc:0x%0h  new mstatus:0x%0h  new priv:%0d",
		 csr_regfile$csr_ret_actions[129:66],
		 csr_regfile$csr_ret_actions[63:0],
		 csr_regfile$csr_ret_actions[65:64]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_finish_FENCE_I", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE_I &&
	  (cur_verbosity__h4054 != 4'd0 ||
	   csr_regfile$read_csr_minstret[19:0] == 20'd0))
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 stage1_rg_stage_input[401:338],
		 stage1_rg_stage_input[263:232],
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$write("    %m.enq:  pc:0x%0h  epoch:%0d  priv:%0d",
	       rg_next_pc,
	       new_epoch__h25078,
	       rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$write("  sstatus_SUM:%0d  mstatus_MXR:%0d  satp:0x%0h",
	       csr_regfile$read_sstatus[18],
	       csr_regfile$read_mstatus[19],
	       csr_regfile$read_satp);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("    fa_stageF_redirect: minstret:%0d  new_pc:%0x  cur_priv:%0d, epoch %0d->%0d",
		 csr_regfile$read_csr_minstret,
		 rg_next_pc,
		 rg_cur_priv,
		 rg_epoch,
		 new_epoch__h25078);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_FENCE_I &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_stage1_FENCE_I", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_stage1_FENCE", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_finish_FENCE", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE &&
	  (cur_verbosity__h4054 != 4'd0 ||
	   csr_regfile$read_csr_minstret[19:0] == 20'd0))
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 stage1_rg_stage_input[401:338],
		 stage1_rg_stage_input[263:232],
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$write("    %m.enq:  pc:0x%0h  epoch:%0d  priv:%0d",
	       rg_next_pc,
	       new_epoch__h25078,
	       rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$write("  sstatus_SUM:%0d  mstatus_MXR:%0d  satp:0x%0h",
	       csr_regfile$read_sstatus[18],
	       csr_regfile$read_mstatus[19],
	       csr_regfile$read_satp);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_FENCE &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("    fa_stageF_redirect: minstret:%0d  new_pc:%0x  cur_priv:%0d, epoch %0d->%0d",
		 csr_regfile$read_csr_minstret,
		 rg_next_pc,
		 rg_cur_priv,
		 rg_epoch,
		 new_epoch__h25078);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_SFENCE_VMA &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_stage1_SFENCE_VMA", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_finish_SFENCE_VMA", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
	  (cur_verbosity__h4054 != 4'd0 ||
	   csr_regfile$read_csr_minstret[19:0] == 20'd0))
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 stage1_rg_stage_input[401:338],
		 stage1_rg_stage_input[263:232],
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$write("    %m.enq:  pc:0x%0h  epoch:%0d  priv:%0d",
	       rg_next_pc,
	       new_epoch__h25078,
	       rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$write("  sstatus_SUM:%0d  mstatus_MXR:%0d  satp:0x%0h",
	       csr_regfile$read_sstatus[18],
	       csr_regfile$read_mstatus[19],
	       csr_regfile$read_satp);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_finish_SFENCE_VMA &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("    fa_stageF_redirect: minstret:%0d  new_pc:%0x  cur_priv:%0d, epoch %0d->%0d",
		 csr_regfile$read_csr_minstret,
		 rg_next_pc,
		 rg_cur_priv,
		 rg_epoch,
		 new_epoch__h25078);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_WFI &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_stage1_WFI", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_WFI &&
	  (cur_verbosity__h4054 != 4'd0 ||
	   csr_regfile$read_csr_minstret[19:0] == 20'd0))
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 stage1_rg_stage_input[401:338],
		 stage1_rg_stage_input[263:232],
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_WFI &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("    CPU.rl_stage1_WFI");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_WFI_resume &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_WFI_resume", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_WFI_resume &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$write("    %m.enq:  pc:0x%0h  epoch:%0d  priv:%0d",
	       rg_next_pc,
	       new_epoch__h25078,
	       rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_WFI_resume &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$write("  sstatus_SUM:%0d  mstatus_MXR:%0d  satp:0x%0h",
	       csr_regfile$read_sstatus[18],
	       csr_regfile$read_mstatus[19],
	       csr_regfile$read_satp);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_WFI_resume &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_WFI_resume &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("    fa_stageF_redirect: minstret:%0d  new_pc:%0x  cur_priv:%0d, epoch %0d->%0d",
		 csr_regfile$read_csr_minstret,
		 rg_next_pc,
		 rg_cur_priv,
		 rg_epoch,
		 new_epoch__h25078);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_from_WFI &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_reset_from_WFI", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap_fetch &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$write("    %m.enq:  pc:0x%0h  epoch:%0d  priv:%0d",
	       rg_next_pc,
	       new_epoch__h25078,
	       rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap_fetch &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$write("  sstatus_SUM:%0d  mstatus_MXR:%0d  satp:0x%0h",
	       csr_regfile$read_sstatus[18],
	       csr_regfile$read_mstatus[19],
	       csr_regfile$read_satp);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap_fetch &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap_fetch &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("    fa_stageF_redirect: minstret:%0d  new_pc:%0x  cur_priv:%0d, epoch %0d->%0d",
		 csr_regfile$read_csr_minstret,
		 rg_next_pc,
		 rg_cur_priv,
		 rg_epoch,
		 new_epoch__h25078);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_trap_BREAK_to_Debug_Mode",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode)
	$display("%0d: %m.rl_trap_BREAK_to_Debug_Mode: PC 0x%08h instr 0x%08h",
		 csr_regfile$read_csr_mcycle,
		 stage1_rg_stage_input[401:338],
		 stage1_rg_stage_input[263:232]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_trap_BREAK_to_Debug_Mode &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("    Flushing caches");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_from_Debug_Module)
	$display("%0d: %m.rl_reset_from_Debug_Module",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_BREAK_cache_flush_finish &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_BREAK_cache_flush_finish",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_interrupt &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_stage1_interrupt", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_stop &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_stage1_stop", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_stop && rg_stop_req)
	$display("%0d: %m.rl_stage1_stop: Stop for debugger. minstret %0d priv %0d PC 0x%0h instr 0x%0h",
		 csr_regfile$read_csr_mcycle,
		 csr_regfile$read_csr_minstret,
		 rg_cur_priv,
		 stage1_rg_stage_input[401:338],
		 stage1_rg_stage_input[263:232]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_stop && rg_stop_req)
	$display("CPI: %0d.%0d = (%0d/%0d) since last 'continue'",
		 cpi__h43949,
		 cpifrac__h43950,
		 delta_CPI_cycles__h43945,
		 _theResult____h43947);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_stage1_stop && !rg_stop_req)
	$display("%0d: %m.rl_stage1_stop: Stop after single-step. PC = 0x%08h",
		 csr_regfile$read_csr_mcycle,
		 stage1_rg_stage_input[401:338]);
    if (WILL_FIRE_RL_imem_rl_assert_fail)
      begin
        v__h2871 = $stime;
	#0;
      end
    v__h2865 = v__h2871 / 32'd10;
    if (WILL_FIRE_RL_imem_rl_assert_fail)
      $display("%0d: ERROR: CPU_Fetch_C: imem32.is_i32_not_i16 is False",
	       v__h2865);
    if (WILL_FIRE_RL_imem_rl_assert_fail) $finish(32'd1);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset)
	$display("%0d: %m.rl_reset_complete: restart at PC = 0x%0h",
		 csr_regfile$read_csr_mcycle,
		 soc_map$m_pc_reset_value);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$write("    %m.enq:  pc:0x%0h  epoch:%0d  priv:%0d",
	       soc_map$m_pc_reset_value,
	       new_epoch__h25078,
	       rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$write("  sstatus_SUM:%0d  mstatus_MXR:%0d  satp:0x%0h",
	       csr_regfile$read_sstatus[18],
	       csr_regfile$read_mstatus[19],
	       csr_regfile$read_satp);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_complete && rg_run_on_reset &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("    fa_stageF_redirect: minstret:%0d  new_pc:%0x  cur_priv:%0d, epoch %0d->%0d",
		 csr_regfile$read_csr_minstret,
		 soc_map$m_pc_reset_value,
		 rg_cur_priv,
		 rg_epoch,
		 new_epoch__h25078);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_complete && !rg_run_on_reset)
	$display("%0d: %m.rl_reset_complete: entering DEBUG_MODE",
		 csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("%0d: %m.rl_pipe", csr_regfile$read_csr_mcycle);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[567] &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53 &&
	  stage3_rg_stage3[496])
	$display("    S3.fa_deq: write FRd 0x%0h, rd_val 0x%0h",
		 stage3_rg_stage3[566:562],
		 stage3_rg_stage3[490:427]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe && stage3_rg_full && stage3_rg_stage3[567] &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53 &&
	  !stage3_rg_stage3[496])
	$display("    S3.fa_deq: write GRd 0x%0h, rd_val 0x%0h",
		 stage3_rg_stage3[566:562],
		 stage3_rg_stage3[561:498]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$write("    S3.enq: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$write("data_to_Stage3 {pc:%h  instr:%h  priv:%0d\n",
	       stage2_rg_stage2[920:857],
	       stage2_rg_stage2[856:825],
	       stage2_rg_stage2[922:921]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$write("        rd_valid:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53 &&
	  stage2_rg_stage2[824:822] != 3'd0 &&
	  IF_stage2_rg_stage2_18_BITS_824_TO_822_19_EQ_1_ETC___d169)
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53 &&
	  (stage2_rg_stage2[824:822] == 3'd0 ||
	   IF_stage2_rg_stage2_18_BITS_824_TO_822_19_EQ_1_ETC___d179))
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53 &&
	  stage2_rg_stage2[824:822] != 3'd0 &&
	  stage2_rg_stage2[824:822] != 3'd1 &&
	  stage2_rg_stage2[824:822] != 3'd4 &&
	  stage2_rg_stage2[824:822] != 3'd2 &&
	  stage2_rg_stage2[824:822] != 3'd3)
	$write("  fflags: %05b",
	       "'h%h",
	       x_out_data_to_stage3_fpr_flags__h9224);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53 &&
	  (stage2_rg_stage2[824:822] == 3'd0 ||
	   stage2_rg_stage2[824:822] == 3'd1 ||
	   stage2_rg_stage2[824:822] == 3'd4 ||
	   stage2_rg_stage2[824:822] == 3'd2 ||
	   stage2_rg_stage2[824:822] == 3'd3))
	$write("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d2260)
	$write("  frd:%0d  rd_val:%h\n",
	       x_out_data_to_stage3_rd__h9220,
	       x_out_data_to_stage3_frd_val__h9225);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d2262)
	$write("  grd:%0d  rd_val:%h\n",
	       x_out_data_to_stage3_rd__h9220,
	       x_out_data_to_stage3_rd_val__h9221);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd2 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage2_rg_full_17_THEN_IF_stage2_rg_stage2__ETC___d153 == 2'd2 &&
	  (cur_verbosity__h4054 != 4'd0 ||
	   csr_regfile$read_csr_minstret[19:0] == 20'd0))
	$display("instret:%0d  PC:0x%0h  instr:0x%0h  priv:%0d",
		 csr_regfile$read_csr_minstret,
		 stage2_rg_stage2[920:857],
		 stage2_rg_stage2[856:825],
		 rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2274 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 ==
	  4'd0 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("    rl_pipe: Discarding stage1 due to redirection");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2457)
	$write("    CPU_Stage2.enq (Data_Stage1_to_Stage2) ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2457)
	$write("data_to_Stage 2 {pc:%h  instr:%h  priv:%0d\n",
	       stage1_rg_stage_input[401:338],
	       stage1_rg_stage_input[263:232],
	       rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2457)
	$write("            op_stage2:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2283 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	  4'd0 &&
	  IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d2088 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153 == 3'd0)
	$write("OP_Stage2_ALU");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2283 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	  4'd0 &&
	  IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d2088 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153 == 3'd1)
	$write("OP_Stage2_LD");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2283 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	  4'd0 &&
	  IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d2088 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153 == 3'd2)
	$write("OP_Stage2_ST");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2283 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	  4'd0 &&
	  IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d2088 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153 == 3'd3)
	$write("OP_Stage2_M");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2283 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	  4'd0 &&
	  IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d2088 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153 == 3'd4)
	$write("OP_Stage2_AMO");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2283 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1004 !=
	  4'd0 &&
	  IF_NOT_stage1_rg_full_16_27_OR_NOT_stage1_rg_s_ETC___d2088 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153 !=
	  3'd0 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153 !=
	  3'd1 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153 !=
	  3'd2 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153 !=
	  3'd3 &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d1153 != 3'd4)
	$write("OP_Stage2_FD");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2457)
	$write("  rd:%0d\n", x_out_data_to_stage2_rd__h10375);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2457)
	$write("            addr:%h  val1:%h  val2:%h}",
	       x_out_data_to_stage2_addr__h10376,
	       x_out_data_to_stage2_val1__h10377,
	       x_out_data_to_stage2_val2__h10378);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2457)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2457)
	$write("            fval1:%h  fval2:%h  fval3:%h}",
	       x_out_data_to_stage2_fval1__h10379,
	       alu_outputs___1_fval2__h10945,
	       x_out_data_to_stage2_fval3__h10381);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  stage1_rg_stage_input_17_BITS_335_TO_334_18_EQ_ETC___d2457)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2487 &&
	  stageD_rg_full &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("    CPU_Stage1.enq: 0x%08h", stageD_rg_data[233:170]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2528 &&
	  NOT_IF_csr_regfile_read_csr_minstret__7_ULT_cf_ETC___d53)
	$display("    CPU_StageD.enq (Data_StageF_to_StageD)");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2528 &&
	  NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2548)
	$write("    %m.enq:  pc:0x%0h  epoch:%0d  priv:%0d",
	       stageF_branch_predictor$predict_rsp,
	       stageF_rg_epoch,
	       rg_cur_priv);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2528 &&
	  NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2548)
	$write("  sstatus_SUM:%0d  mstatus_MXR:%0d  satp:0x%0h",
	       csr_regfile$read_sstatus[18],
	       csr_regfile$read_mstatus[19],
	       csr_regfile$read_satp);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_pipe &&
	  IF_stage1_rg_stage_input_17_BITS_335_TO_334_18_ETC___d2528 &&
	  NOT_stage1_rg_stage_input_17_BITS_335_TO_334_1_ETC___d2548)
	$display("");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start)
	$display("================================================================");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start)
	$write("CPU: Bluespec  RISC-V  Flute  v3.0");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start) $display(" (RV64)");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start)
	$display("Copyright (c) 2016-2020 Bluespec, Inc. All Rights Reserved.");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset_start)
	$display("================================================================");
  end
  // synopsys translate_on
endmodule  // mkCPU

