//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name                         I/O  size props
// RDY_set_verbosity              O     1 const
// RDY_server_reset_request_put   O     1 reg
// RDY_server_reset_response_get  O     1
// valid                          O     1
// addr                           O    32 reg
// cword                          O    64
// st_amo_val                     O    64
// exc                            O     1
// exc_code                       O     4 reg
// RDY_server_flush_request_put   O     1 reg
// RDY_server_flush_response_get  O     1
// RDY_tlb_flush                  O     1 const
// mem_master_awvalid             O     1 reg
// mem_master_awid                O     4 reg
// mem_master_awaddr              O    64 reg
// mem_master_awlen               O     8 reg
// mem_master_awsize              O     3 reg
// mem_master_awburst             O     2 reg
// mem_master_awlock              O     1 reg
// mem_master_awcache             O     4 reg
// mem_master_awprot              O     3 reg
// mem_master_awqos               O     4 reg
// mem_master_awregion            O     4 reg
// mem_master_wvalid              O     1 reg
// mem_master_wdata               O    64 reg
// mem_master_wstrb               O     8 reg
// mem_master_wlast               O     1 reg
// mem_master_bready              O     1 reg
// mem_master_arvalid             O     1 reg
// mem_master_arid                O     4 reg
// mem_master_araddr              O    64 reg
// mem_master_arlen               O     8 reg
// mem_master_arsize              O     3 reg
// mem_master_arburst             O     2 reg
// mem_master_arlock              O     1 reg
// mem_master_arcache             O     4 reg
// mem_master_arprot              O     3 reg
// mem_master_arqos               O     4 reg
// mem_master_arregion            O     4 reg
// mem_master_rready              O     1 reg
// RDY_set_watch_tohost           O     1 const
// mv_tohost_value                O    64 reg
// RDY_mv_tohost_value            O     1 const
// RDY_ma_ddr4_ready              O     1 const
// mv_status                      O     8
// CLK                            I     1 clock
// RST_N                          I     1 reset
// set_verbosity_verbosity        I     4 reg
// req_op                         I     2
// req_f3                         I     3
// req_amo_funct7                 I     7 reg
// req_addr                       I    32
// req_st_value                   I    64
// req_priv                       I     2 reg
// req_sstatus_SUM                I     1 reg
// req_mstatus_MXR                I     1 reg
// req_satp                       I    32 reg
// mem_master_awready             I     1
// mem_master_wready              I     1
// mem_master_bvalid              I     1
// mem_master_bid                 I     4 reg
// mem_master_bresp               I     2 reg
// mem_master_arready             I     1
// mem_master_rvalid              I     1
// mem_master_rid                 I     4 reg
// mem_master_rdata               I    64 reg
// mem_master_rresp               I     2 reg
// mem_master_rlast               I     1 reg
// set_watch_tohost_watch_tohost  I     1 reg
// set_watch_tohost_tohost_addr   I    64 reg
// EN_set_verbosity               I     1
// EN_server_reset_request_put    I     1
// EN_server_reset_response_get   I     1
// EN_req                         I     1
// EN_server_flush_request_put    I     1
// EN_server_flush_response_get   I     1
// EN_tlb_flush                   I     1
// EN_set_watch_tohost            I     1
// EN_ma_ddr4_ready               I     1
//
// No combinational paths from inputs to outputs
//
//

`ifdef BSV_ASSIGNMENT_DELAY
`else
  `define BSV_ASSIGNMENT_DELAY
`endif

`ifdef BSV_POSITIVE_RESET
  `define BSV_RESET_VALUE 1'b1
  `define BSV_RESET_EDGE posedge
`else
  `define BSV_RESET_VALUE 1'b0
  `define BSV_RESET_EDGE negedge
`endif

module mkMMU_Cache(CLK,
		   RST_N,

		   set_verbosity_verbosity,
		   EN_set_verbosity,
		   RDY_set_verbosity,

		   EN_server_reset_request_put,
		   RDY_server_reset_request_put,

		   EN_server_reset_response_get,
		   RDY_server_reset_response_get,

		   req_op,
		   req_f3,
		   req_amo_funct7,
		   req_addr,
		   req_st_value,
		   req_priv,
		   req_sstatus_SUM,
		   req_mstatus_MXR,
		   req_satp,
		   EN_req,

		   valid,

		   addr,

		   cword,

		   st_amo_val,

		   exc,

		   exc_code,

		   EN_server_flush_request_put,
		   RDY_server_flush_request_put,

		   EN_server_flush_response_get,
		   RDY_server_flush_response_get,

		   EN_tlb_flush,
		   RDY_tlb_flush,

		   mem_master_awvalid,

		   mem_master_awid,

		   mem_master_awaddr,

		   mem_master_awlen,

		   mem_master_awsize,

		   mem_master_awburst,

		   mem_master_awlock,

		   mem_master_awcache,

		   mem_master_awprot,

		   mem_master_awqos,

		   mem_master_awregion,

		   mem_master_awready,

		   mem_master_wvalid,

		   mem_master_wdata,

		   mem_master_wstrb,

		   mem_master_wlast,

		   mem_master_wready,

		   mem_master_bvalid,
		   mem_master_bid,
		   mem_master_bresp,

		   mem_master_bready,

		   mem_master_arvalid,

		   mem_master_arid,

		   mem_master_araddr,

		   mem_master_arlen,

		   mem_master_arsize,

		   mem_master_arburst,

		   mem_master_arlock,

		   mem_master_arcache,

		   mem_master_arprot,

		   mem_master_arqos,

		   mem_master_arregion,

		   mem_master_arready,

		   mem_master_rvalid,
		   mem_master_rid,
		   mem_master_rdata,
		   mem_master_rresp,
		   mem_master_rlast,

		   mem_master_rready,

		   set_watch_tohost_watch_tohost,
		   set_watch_tohost_tohost_addr,
		   EN_set_watch_tohost,
		   RDY_set_watch_tohost,

		   mv_tohost_value,
		   RDY_mv_tohost_value,

		   EN_ma_ddr4_ready,
		   RDY_ma_ddr4_ready,

		   mv_status);
  parameter [0 : 0] dmem_not_imem = 1'b0;
  input  CLK;
  input  RST_N;

  // action method set_verbosity
  input  [3 : 0] set_verbosity_verbosity;
  input  EN_set_verbosity;
  output RDY_set_verbosity;

  // action method server_reset_request_put
  input  EN_server_reset_request_put;
  output RDY_server_reset_request_put;

  // action method server_reset_response_get
  input  EN_server_reset_response_get;
  output RDY_server_reset_response_get;

  // action method req
  input  [1 : 0] req_op;
  input  [2 : 0] req_f3;
  input  [6 : 0] req_amo_funct7;
  input  [31 : 0] req_addr;
  input  [63 : 0] req_st_value;
  input  [1 : 0] req_priv;
  input  req_sstatus_SUM;
  input  req_mstatus_MXR;
  input  [31 : 0] req_satp;
  input  EN_req;

  // value method valid
  output valid;

  // value method addr
  output [31 : 0] addr;

  // value method cword
  output [63 : 0] cword;

  // value method st_amo_val
  output [63 : 0] st_amo_val;

  // value method exc
  output exc;

  // value method exc_code
  output [3 : 0] exc_code;

  // action method server_flush_request_put
  input  EN_server_flush_request_put;
  output RDY_server_flush_request_put;

  // action method server_flush_response_get
  input  EN_server_flush_response_get;
  output RDY_server_flush_response_get;

  // action method tlb_flush
  input  EN_tlb_flush;
  output RDY_tlb_flush;

  // value method mem_master_m_awvalid
  output mem_master_awvalid;

  // value method mem_master_m_awid
  output [3 : 0] mem_master_awid;

  // value method mem_master_m_awaddr
  output [63 : 0] mem_master_awaddr;

  // value method mem_master_m_awlen
  output [7 : 0] mem_master_awlen;

  // value method mem_master_m_awsize
  output [2 : 0] mem_master_awsize;

  // value method mem_master_m_awburst
  output [1 : 0] mem_master_awburst;

  // value method mem_master_m_awlock
  output mem_master_awlock;

  // value method mem_master_m_awcache
  output [3 : 0] mem_master_awcache;

  // value method mem_master_m_awprot
  output [2 : 0] mem_master_awprot;

  // value method mem_master_m_awqos
  output [3 : 0] mem_master_awqos;

  // value method mem_master_m_awregion
  output [3 : 0] mem_master_awregion;

  // value method mem_master_m_awuser

  // action method mem_master_m_awready
  input  mem_master_awready;

  // value method mem_master_m_wvalid
  output mem_master_wvalid;

  // value method mem_master_m_wdata
  output [63 : 0] mem_master_wdata;

  // value method mem_master_m_wstrb
  output [7 : 0] mem_master_wstrb;

  // value method mem_master_m_wlast
  output mem_master_wlast;

  // value method mem_master_m_wuser

  // action method mem_master_m_wready
  input  mem_master_wready;

  // action method mem_master_m_bvalid
  input  mem_master_bvalid;
  input  [3 : 0] mem_master_bid;
  input  [1 : 0] mem_master_bresp;

  // value method mem_master_m_bready
  output mem_master_bready;

  // value method mem_master_m_arvalid
  output mem_master_arvalid;

  // value method mem_master_m_arid
  output [3 : 0] mem_master_arid;

  // value method mem_master_m_araddr
  output [63 : 0] mem_master_araddr;

  // value method mem_master_m_arlen
  output [7 : 0] mem_master_arlen;

  // value method mem_master_m_arsize
  output [2 : 0] mem_master_arsize;

  // value method mem_master_m_arburst
  output [1 : 0] mem_master_arburst;

  // value method mem_master_m_arlock
  output mem_master_arlock;

  // value method mem_master_m_arcache
  output [3 : 0] mem_master_arcache;

  // value method mem_master_m_arprot
  output [2 : 0] mem_master_arprot;

  // value method mem_master_m_arqos
  output [3 : 0] mem_master_arqos;

  // value method mem_master_m_arregion
  output [3 : 0] mem_master_arregion;

  // value method mem_master_m_aruser

  // action method mem_master_m_arready
  input  mem_master_arready;

  // action method mem_master_m_rvalid
  input  mem_master_rvalid;
  input  [3 : 0] mem_master_rid;
  input  [63 : 0] mem_master_rdata;
  input  [1 : 0] mem_master_rresp;
  input  mem_master_rlast;

  // value method mem_master_m_rready
  output mem_master_rready;

  // action method set_watch_tohost
  input  set_watch_tohost_watch_tohost;
  input  [63 : 0] set_watch_tohost_tohost_addr;
  input  EN_set_watch_tohost;
  output RDY_set_watch_tohost;

  // value method mv_tohost_value
  output [63 : 0] mv_tohost_value;
  output RDY_mv_tohost_value;

  // action method ma_ddr4_ready
  input  EN_ma_ddr4_ready;
  output RDY_ma_ddr4_ready;

  // value method mv_status
  output [7 : 0] mv_status;

  // signals for module outputs
  reg [63 : 0] cword;
  wire [63 : 0] mem_master_araddr,
		mem_master_awaddr,
		mem_master_wdata,
		mv_tohost_value,
		st_amo_val;
  wire [31 : 0] addr;
  wire [7 : 0] mem_master_arlen,
	       mem_master_awlen,
	       mem_master_wstrb,
	       mv_status;
  wire [3 : 0] exc_code,
	       mem_master_arcache,
	       mem_master_arid,
	       mem_master_arqos,
	       mem_master_arregion,
	       mem_master_awcache,
	       mem_master_awid,
	       mem_master_awqos,
	       mem_master_awregion;
  wire [2 : 0] mem_master_arprot,
	       mem_master_arsize,
	       mem_master_awprot,
	       mem_master_awsize;
  wire [1 : 0] mem_master_arburst, mem_master_awburst;
  wire RDY_ma_ddr4_ready,
       RDY_mv_tohost_value,
       RDY_server_flush_request_put,
       RDY_server_flush_response_get,
       RDY_server_reset_request_put,
       RDY_server_reset_response_get,
       RDY_set_verbosity,
       RDY_set_watch_tohost,
       RDY_tlb_flush,
       exc,
       mem_master_arlock,
       mem_master_arvalid,
       mem_master_awlock,
       mem_master_awvalid,
       mem_master_bready,
       mem_master_rready,
       mem_master_wlast,
       mem_master_wvalid,
       valid;

  // inlined wires
  wire [3 : 0] ctr_wr_rsps_pending_crg$port0__write_1,
	       ctr_wr_rsps_pending_crg$port1__write_1,
	       ctr_wr_rsps_pending_crg$port2__read,
	       ctr_wr_rsps_pending_crg$port3__read;
  wire ctr_wr_rsps_pending_crg$EN_port2__write, dw_valid$whas;

  // register cfg_verbosity
  reg [3 : 0] cfg_verbosity;
  wire [3 : 0] cfg_verbosity$D_IN;
  wire cfg_verbosity$EN;

  // register ctr_wr_rsps_pending_crg
  reg [3 : 0] ctr_wr_rsps_pending_crg;
  wire [3 : 0] ctr_wr_rsps_pending_crg$D_IN;
  wire ctr_wr_rsps_pending_crg$EN;

  // register rg_addr
  reg [31 : 0] rg_addr;
  wire [31 : 0] rg_addr$D_IN;
  wire rg_addr$EN;

  // register rg_amo_funct7
  reg [6 : 0] rg_amo_funct7;
  wire [6 : 0] rg_amo_funct7$D_IN;
  wire rg_amo_funct7$EN;

  // register rg_cset_cword_in_cache
  reg [8 : 0] rg_cset_cword_in_cache;
  wire [8 : 0] rg_cset_cword_in_cache$D_IN;
  wire rg_cset_cword_in_cache$EN;

  // register rg_cset_in_cache
  reg [5 : 0] rg_cset_in_cache;
  wire [5 : 0] rg_cset_in_cache$D_IN;
  wire rg_cset_in_cache$EN;

  // register rg_ddr4_ready
  reg rg_ddr4_ready;
  wire rg_ddr4_ready$D_IN, rg_ddr4_ready$EN;

  // register rg_error_during_refill
  reg rg_error_during_refill;
  wire rg_error_during_refill$D_IN, rg_error_during_refill$EN;

  // register rg_exc_code
  reg [3 : 0] rg_exc_code;
  reg [3 : 0] rg_exc_code$D_IN;
  wire rg_exc_code$EN;

  // register rg_f3
  reg [2 : 0] rg_f3;
  wire [2 : 0] rg_f3$D_IN;
  wire rg_f3$EN;

  // register rg_ld_val
  reg [63 : 0] rg_ld_val;
  reg [63 : 0] rg_ld_val$D_IN;
  wire rg_ld_val$EN;

  // register rg_lower_word32
  reg [31 : 0] rg_lower_word32;
  wire [31 : 0] rg_lower_word32$D_IN;
  wire rg_lower_word32$EN;

  // register rg_lower_word32_full
  reg rg_lower_word32_full;
  wire rg_lower_word32_full$D_IN, rg_lower_word32_full$EN;

  // register rg_lrsc_pa
  reg [33 : 0] rg_lrsc_pa;
  wire [33 : 0] rg_lrsc_pa$D_IN;
  wire rg_lrsc_pa$EN;

  // register rg_lrsc_valid
  reg rg_lrsc_valid;
  wire rg_lrsc_valid$D_IN, rg_lrsc_valid$EN;

  // register rg_mstatus_MXR
  reg rg_mstatus_MXR;
  wire rg_mstatus_MXR$D_IN, rg_mstatus_MXR$EN;

  // register rg_op
  reg [1 : 0] rg_op;
  wire [1 : 0] rg_op$D_IN;
  wire rg_op$EN;

  // register rg_pa
  reg [33 : 0] rg_pa;
  wire [33 : 0] rg_pa$D_IN;
  wire rg_pa$EN;

  // register rg_priv
  reg [1 : 0] rg_priv;
  wire [1 : 0] rg_priv$D_IN;
  wire rg_priv$EN;

  // register rg_pte_pa
  reg [33 : 0] rg_pte_pa;
  wire [33 : 0] rg_pte_pa$D_IN;
  wire rg_pte_pa$EN;

  // register rg_satp
  reg [31 : 0] rg_satp;
  wire [31 : 0] rg_satp$D_IN;
  wire rg_satp$EN;

  // register rg_sstatus_SUM
  reg rg_sstatus_SUM;
  wire rg_sstatus_SUM$D_IN, rg_sstatus_SUM$EN;

  // register rg_st_amo_val
  reg [63 : 0] rg_st_amo_val;
  wire [63 : 0] rg_st_amo_val$D_IN;
  wire rg_st_amo_val$EN;

  // register rg_state
  reg [3 : 0] rg_state;
  reg [3 : 0] rg_state$D_IN;
  wire rg_state$EN;

  // register rg_tohost_addr
  reg [63 : 0] rg_tohost_addr;
  wire [63 : 0] rg_tohost_addr$D_IN;
  wire rg_tohost_addr$EN;

  // register rg_tohost_value
  reg [63 : 0] rg_tohost_value;
  wire [63 : 0] rg_tohost_value$D_IN;
  wire rg_tohost_value$EN;

  // register rg_victim_way
  reg rg_victim_way;
  wire rg_victim_way$D_IN, rg_victim_way$EN;

  // register rg_watch_tohost
  reg rg_watch_tohost;
  wire rg_watch_tohost$D_IN, rg_watch_tohost$EN;

  // register rg_wr_rsp_err
  reg rg_wr_rsp_err;
  wire rg_wr_rsp_err$D_IN, rg_wr_rsp_err$EN;

  // ports of submodule f_fabric_write_reqs
  reg [100 : 0] f_fabric_write_reqs$D_IN;
  wire [100 : 0] f_fabric_write_reqs$D_OUT;
  wire f_fabric_write_reqs$CLR,
       f_fabric_write_reqs$DEQ,
       f_fabric_write_reqs$EMPTY_N,
       f_fabric_write_reqs$ENQ,
       f_fabric_write_reqs$FULL_N;

  // ports of submodule f_pte_writebacks
  wire [65 : 0] f_pte_writebacks$D_IN, f_pte_writebacks$D_OUT;
  wire f_pte_writebacks$CLR,
       f_pte_writebacks$DEQ,
       f_pte_writebacks$EMPTY_N,
       f_pte_writebacks$ENQ,
       f_pte_writebacks$FULL_N;

  // ports of submodule f_reset_reqs
  wire f_reset_reqs$CLR,
       f_reset_reqs$DEQ,
       f_reset_reqs$D_IN,
       f_reset_reqs$D_OUT,
       f_reset_reqs$EMPTY_N,
       f_reset_reqs$ENQ,
       f_reset_reqs$FULL_N;

  // ports of submodule f_reset_rsps
  wire f_reset_rsps$CLR,
       f_reset_rsps$DEQ,
       f_reset_rsps$D_IN,
       f_reset_rsps$D_OUT,
       f_reset_rsps$EMPTY_N,
       f_reset_rsps$ENQ,
       f_reset_rsps$FULL_N;

  // ports of submodule master_xactor_f_rd_addr
  reg [96 : 0] master_xactor_f_rd_addr$D_IN;
  wire [96 : 0] master_xactor_f_rd_addr$D_OUT;
  wire master_xactor_f_rd_addr$CLR,
       master_xactor_f_rd_addr$DEQ,
       master_xactor_f_rd_addr$EMPTY_N,
       master_xactor_f_rd_addr$ENQ,
       master_xactor_f_rd_addr$FULL_N;

  // ports of submodule master_xactor_f_rd_data
  wire [70 : 0] master_xactor_f_rd_data$D_IN, master_xactor_f_rd_data$D_OUT;
  wire master_xactor_f_rd_data$CLR,
       master_xactor_f_rd_data$DEQ,
       master_xactor_f_rd_data$EMPTY_N,
       master_xactor_f_rd_data$ENQ,
       master_xactor_f_rd_data$FULL_N;

  // ports of submodule master_xactor_f_wr_addr
  wire [96 : 0] master_xactor_f_wr_addr$D_IN, master_xactor_f_wr_addr$D_OUT;
  wire master_xactor_f_wr_addr$CLR,
       master_xactor_f_wr_addr$DEQ,
       master_xactor_f_wr_addr$EMPTY_N,
       master_xactor_f_wr_addr$ENQ,
       master_xactor_f_wr_addr$FULL_N;

  // ports of submodule master_xactor_f_wr_data
  wire [72 : 0] master_xactor_f_wr_data$D_IN, master_xactor_f_wr_data$D_OUT;
  wire master_xactor_f_wr_data$CLR,
       master_xactor_f_wr_data$DEQ,
       master_xactor_f_wr_data$EMPTY_N,
       master_xactor_f_wr_data$ENQ,
       master_xactor_f_wr_data$FULL_N;

  // ports of submodule master_xactor_f_wr_resp
  wire [5 : 0] master_xactor_f_wr_resp$D_IN, master_xactor_f_wr_resp$D_OUT;
  wire master_xactor_f_wr_resp$CLR,
       master_xactor_f_wr_resp$DEQ,
       master_xactor_f_wr_resp$EMPTY_N,
       master_xactor_f_wr_resp$ENQ,
       master_xactor_f_wr_resp$FULL_N;

  // ports of submodule ram_cword_set
  reg [127 : 0] ram_cword_set$DIB;
  reg [8 : 0] ram_cword_set$ADDRB;
  wire [127 : 0] ram_cword_set$DIA, ram_cword_set$DOB;
  wire [8 : 0] ram_cword_set$ADDRA;
  wire ram_cword_set$ENA,
       ram_cword_set$ENB,
       ram_cword_set$WEA,
       ram_cword_set$WEB;

  // ports of submodule ram_state_and_ctag_cset
  wire [45 : 0] ram_state_and_ctag_cset$DIA,
		ram_state_and_ctag_cset$DIB,
		ram_state_and_ctag_cset$DOB;
  wire [5 : 0] ram_state_and_ctag_cset$ADDRA, ram_state_and_ctag_cset$ADDRB;
  wire ram_state_and_ctag_cset$ENA,
       ram_state_and_ctag_cset$ENB,
       ram_state_and_ctag_cset$WEA,
       ram_state_and_ctag_cset$WEB;

  // ports of submodule soc_map
  wire [63 : 0] soc_map$m_is_IO_addr_addr,
		soc_map$m_is_mem_addr_addr,
		soc_map$m_is_near_mem_IO_addr_addr;
  wire soc_map$m_is_mem_addr;

  // ports of submodule tlb
  reg [31 : 0] tlb$insert_pte;
  reg [1 : 0] tlb$insert_level;
  wire [68 : 0] tlb$lookup;
  wire [33 : 0] tlb$insert_pte_pa;
  wire [19 : 0] tlb$insert_vpn, tlb$lookup_vpn;
  wire [8 : 0] tlb$insert_asid, tlb$lookup_asid;
  wire tlb$EN_flush, tlb$EN_insert, tlb$RDY_insert, tlb$RDY_lookup;

  // rule scheduling signals
  wire CAN_FIRE_RL_rl_ST_AMO_response,
       CAN_FIRE_RL_rl_cache_refill_rsps_loop,
       CAN_FIRE_RL_rl_discard_write_rsp,
       CAN_FIRE_RL_rl_drive_exception_rsp,
       CAN_FIRE_RL_rl_fabric_send_write_req,
       CAN_FIRE_RL_rl_io_AMO_SC_req,
       CAN_FIRE_RL_rl_io_AMO_op_req,
       CAN_FIRE_RL_rl_io_AMO_read_rsp,
       CAN_FIRE_RL_rl_io_read_req,
       CAN_FIRE_RL_rl_io_read_rsp,
       CAN_FIRE_RL_rl_io_write_req,
       CAN_FIRE_RL_rl_maintain_io_read_rsp,
       CAN_FIRE_RL_rl_probe_and_immed_rsp,
       CAN_FIRE_RL_rl_ptw_level_0,
       CAN_FIRE_RL_rl_ptw_level_1,
       CAN_FIRE_RL_rl_rereq,
       CAN_FIRE_RL_rl_reset,
       CAN_FIRE_RL_rl_start_cache_refill,
       CAN_FIRE_RL_rl_start_reset,
       CAN_FIRE_RL_rl_start_tlb_refill,
       CAN_FIRE_RL_rl_writeback_updated_PTE,
       CAN_FIRE_ma_ddr4_ready,
       CAN_FIRE_mem_master_m_arready,
       CAN_FIRE_mem_master_m_awready,
       CAN_FIRE_mem_master_m_bvalid,
       CAN_FIRE_mem_master_m_rvalid,
       CAN_FIRE_mem_master_m_wready,
       CAN_FIRE_req,
       CAN_FIRE_server_flush_request_put,
       CAN_FIRE_server_flush_response_get,
       CAN_FIRE_server_reset_request_put,
       CAN_FIRE_server_reset_response_get,
       CAN_FIRE_set_verbosity,
       CAN_FIRE_set_watch_tohost,
       CAN_FIRE_tlb_flush,
       WILL_FIRE_RL_rl_ST_AMO_response,
       WILL_FIRE_RL_rl_cache_refill_rsps_loop,
       WILL_FIRE_RL_rl_discard_write_rsp,
       WILL_FIRE_RL_rl_drive_exception_rsp,
       WILL_FIRE_RL_rl_fabric_send_write_req,
       WILL_FIRE_RL_rl_io_AMO_SC_req,
       WILL_FIRE_RL_rl_io_AMO_op_req,
       WILL_FIRE_RL_rl_io_AMO_read_rsp,
       WILL_FIRE_RL_rl_io_read_req,
       WILL_FIRE_RL_rl_io_read_rsp,
       WILL_FIRE_RL_rl_io_write_req,
       WILL_FIRE_RL_rl_maintain_io_read_rsp,
       WILL_FIRE_RL_rl_probe_and_immed_rsp,
       WILL_FIRE_RL_rl_ptw_level_0,
       WILL_FIRE_RL_rl_ptw_level_1,
       WILL_FIRE_RL_rl_rereq,
       WILL_FIRE_RL_rl_reset,
       WILL_FIRE_RL_rl_start_cache_refill,
       WILL_FIRE_RL_rl_start_reset,
       WILL_FIRE_RL_rl_start_tlb_refill,
       WILL_FIRE_RL_rl_writeback_updated_PTE,
       WILL_FIRE_ma_ddr4_ready,
       WILL_FIRE_mem_master_m_arready,
       WILL_FIRE_mem_master_m_awready,
       WILL_FIRE_mem_master_m_bvalid,
       WILL_FIRE_mem_master_m_rvalid,
       WILL_FIRE_mem_master_m_wready,
       WILL_FIRE_req,
       WILL_FIRE_server_flush_request_put,
       WILL_FIRE_server_flush_response_get,
       WILL_FIRE_server_reset_request_put,
       WILL_FIRE_server_reset_response_get,
       WILL_FIRE_set_verbosity,
       WILL_FIRE_set_watch_tohost,
       WILL_FIRE_tlb_flush;

  // inputs to muxes for submodule ports
  wire [127 : 0] MUX_ram_cword_set$a_put_3__VAL_1,
		 MUX_ram_cword_set$a_put_3__VAL_2;
  wire [100 : 0] MUX_f_fabric_write_reqs$enq_1__VAL_1,
		 MUX_f_fabric_write_reqs$enq_1__VAL_2,
		 MUX_f_fabric_write_reqs$enq_1__VAL_3,
		 MUX_f_fabric_write_reqs$enq_1__VAL_4;
  wire [96 : 0] MUX_master_xactor_f_rd_addr$enq_1__VAL_1,
		MUX_master_xactor_f_rd_addr$enq_1__VAL_2,
		MUX_master_xactor_f_rd_addr$enq_1__VAL_3,
		MUX_master_xactor_f_rd_addr$enq_1__VAL_4;
  wire [63 : 0] MUX_dw_output_ld_val$wset_1__VAL_3,
		MUX_rg_ld_val$write_1__VAL_2;
  wire [45 : 0] MUX_ram_state_and_ctag_cset$a_put_3__VAL_1;
  wire [33 : 0] MUX_rg_pa$write_1__VAL_1;
  wire [8 : 0] MUX_ram_cword_set$b_put_2__VAL_2,
	       MUX_ram_cword_set$b_put_2__VAL_4;
  wire [5 : 0] MUX_rg_cset_in_cache$write_1__VAL_1;
  wire [3 : 0] MUX_rg_exc_code$write_1__VAL_1,
	       MUX_rg_exc_code$write_1__VAL_5,
	       MUX_rg_state$write_1__VAL_11,
	       MUX_rg_state$write_1__VAL_13,
	       MUX_rg_state$write_1__VAL_14,
	       MUX_rg_state$write_1__VAL_16,
	       MUX_rg_state$write_1__VAL_2,
	       MUX_rg_state$write_1__VAL_4;
  wire MUX_dw_output_ld_val$wset_1__SEL_1,
       MUX_dw_output_ld_val$wset_1__SEL_2,
       MUX_dw_output_ld_val$wset_1__SEL_4,
       MUX_dw_valid$wset_1__SEL_2,
       MUX_f_fabric_write_reqs$enq_1__SEL_2,
       MUX_master_xactor_f_rd_addr$enq_1__SEL_1,
       MUX_master_xactor_f_rd_addr$enq_1__SEL_2,
       MUX_ram_cword_set$a_put_1__SEL_1,
       MUX_ram_cword_set$b_put_1__SEL_1,
       MUX_ram_cword_set$b_put_1__SEL_2,
       MUX_ram_state_and_ctag_cset$a_put_1__SEL_1,
       MUX_rg_error_during_refill$write_1__SEL_1,
       MUX_rg_exc_code$write_1__SEL_1,
       MUX_rg_exc_code$write_1__SEL_2,
       MUX_rg_exc_code$write_1__SEL_3,
       MUX_rg_exc_code$write_1__SEL_5,
       MUX_rg_exc_code$write_1__SEL_6,
       MUX_rg_exc_code$write_1__SEL_7,
       MUX_rg_ld_val$write_1__SEL_2,
       MUX_rg_lrsc_valid$write_1__SEL_2,
       MUX_rg_state$write_1__SEL_11,
       MUX_rg_state$write_1__SEL_16,
       MUX_rg_state$write_1__SEL_17,
       MUX_rg_state$write_1__SEL_3,
       MUX_tlb$insert_1__SEL_1,
       MUX_tlb$insert_1__SEL_2,
       MUX_tlb$insert_1__SEL_3;

  // declarations used by system tasks
  // synopsys translate_off
  reg [31 : 0] v__h4706;
  reg [31 : 0] v__h4805;
  reg [31 : 0] v__h4955;
  reg [31 : 0] v__h21391;
  reg [31 : 0] v__h25107;
  reg [31 : 0] v__h41747;
  reg [31 : 0] v__h28618;
  reg [31 : 0] v__h29551;
  reg [31 : 0] v__h29309;
  reg [31 : 0] v__h29949;
  reg [31 : 0] v__h29837;
  reg [31 : 0] v__h29480;
  reg [31 : 0] v__h30488;
  reg [31 : 0] v__h30559;
  reg [31 : 0] v__h30641;
  reg [31 : 0] v__h30417;
  reg [31 : 0] v__h30766;
  reg [31 : 0] v__h31457;
  reg [31 : 0] v__h31679;
  reg [31 : 0] v__h41679;
  reg [31 : 0] v__h34148;
  reg [31 : 0] v__h34498;
  reg [31 : 0] v__h35598;
  reg [31 : 0] v__h35705;
  reg [31 : 0] v__h35810;
  reg [31 : 0] v__h35890;
  reg [31 : 0] v__h36100;
  reg [31 : 0] v__h36218;
  reg [31 : 0] v__h36512;
  reg [31 : 0] v__h36687;
  reg [31 : 0] v__h38946;
  reg [31 : 0] v__h36783;
  reg [31 : 0] v__h39524;
  reg [31 : 0] v__h39566;
  reg [31 : 0] v__h4238;
  reg [31 : 0] v__h39935;
  reg [31 : 0] v__h41310;
  reg [31 : 0] v__h4232;
  reg [31 : 0] v__h4700;
  reg [31 : 0] v__h4799;
  reg [31 : 0] v__h4949;
  reg [31 : 0] v__h21385;
  reg [31 : 0] v__h25101;
  reg [31 : 0] v__h28612;
  reg [31 : 0] v__h29303;
  reg [31 : 0] v__h29474;
  reg [31 : 0] v__h29545;
  reg [31 : 0] v__h29831;
  reg [31 : 0] v__h29943;
  reg [31 : 0] v__h30411;
  reg [31 : 0] v__h30482;
  reg [31 : 0] v__h30553;
  reg [31 : 0] v__h30635;
  reg [31 : 0] v__h30760;
  reg [31 : 0] v__h31451;
  reg [31 : 0] v__h31673;
  reg [31 : 0] v__h34142;
  reg [31 : 0] v__h34492;
  reg [31 : 0] v__h35592;
  reg [31 : 0] v__h35699;
  reg [31 : 0] v__h35804;
  reg [31 : 0] v__h35884;
  reg [31 : 0] v__h36094;
  reg [31 : 0] v__h36212;
  reg [31 : 0] v__h36506;
  reg [31 : 0] v__h36681;
  reg [31 : 0] v__h36777;
  reg [31 : 0] v__h38940;
  reg [31 : 0] v__h39518;
  reg [31 : 0] v__h39560;
  reg [31 : 0] v__h39929;
  reg [31 : 0] v__h41304;
  reg [31 : 0] v__h41673;
  reg [31 : 0] v__h41741;
  // synopsys translate_on

  // remaining internal signals
  reg [63 : 0] CASE_rg_addr_BITS_2_TO_0_0x0_result1213_0x4_re_ETC__q30,
	       CASE_rg_addr_BITS_2_TO_0_0x0_result5378_0x4_re_ETC__q35,
	       CASE_rg_addr_BITS_2_TO_0_0x0_result5443_0x4_re_ETC__q36,
	       CASE_rg_addr_BITS_2_TO_0_0x0_result8654_0x4_re_ETC__q51,
	       CASE_rg_f3_0b0_IF_rg_addr_01_BITS_2_TO_0_19_EQ_ETC__q53,
	       CASE_x1_avValue_pa220_BITS_2_TO_0_0x0_old_cwor_ETC__q31,
	       CASE_x1_avValue_pa220_BITS_2_TO_0_0x0_old_cwor_ETC__q34,
	       IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d754,
	       IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d763,
	       IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d822,
	       IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d831,
	       IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1169,
	       IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1189,
	       IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1276,
	       IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1296,
	       IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1306,
	       IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d611,
	       IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d631,
	       IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d641,
	       IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1153,
	       IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1181,
	       IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1260,
	       IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1288,
	       IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d595,
	       IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d623,
	       IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_01_BITS__ETC___d649,
	       IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_IF_rg_f3_15_E_ETC___d710,
	       _theResult_____2__h25629,
	       _theResult_____2__h36859,
	       ld_val__h34607,
	       mem_req_wr_data_wdata__h3204,
	       n__h22557,
	       n__h25491,
	       new_ld_val__h36813,
	       old_cword__h22546,
	       w1__h25621,
	       w1__h36847,
	       w1__h36851;
  reg [33 : 0] _theResult___fst__h6721;
  reg [7 : 0] mem_req_wr_data_wstrb__h3205;
  reg [2 : 0] value__h36399, x__h3025;
  reg CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_15_ETC__q29,
      IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d322,
      IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d328,
      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_OR_rg_a_ETC___d239,
      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_OR_rg_a_ETC___d247,
      IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b100_17__ETC___d261,
      IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b1_40_OR_ETC___d277,
      IF_rg_f3_15_EQ_0b0_16_THEN_NOT_rg_priv_1_ULE_0_ETC___d337;
  wire [63 : 0] IF_NOT_ram_state_and_ctag_cset_b_read__98_BIT__ETC___d774,
		IF_NOT_ram_state_and_ctag_cset_b_read__98_BIT__ETC___d842,
		IF_ram_state_and_ctag_cset_b_read__98_BIT_45_0_ETC___d773,
		IF_ram_state_and_ctag_cset_b_read__98_BIT_45_0_ETC___d841,
		IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_1__ETC___d657,
		IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_IF_ETC___d1307,
		IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_ra_ETC___d642,
		IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_rg_st_amo_val_ETC___d779,
		IF_rg_op_17_EQ_1_64_OR_rg_op_17_EQ_2_20_AND_rg_ETC___d851,
		_theResult___snd_fst__h3212,
		cline_fabric_addr__h30819,
		fabric_addr__h36270,
		lev_0_pte_pa_w64_fa__h29585,
		lev_1_pte_pa_w64_fa__h28673,
		mem_req_wr_addr_awaddr__h2978,
		new_st_val__h25327,
		new_st_val__h25633,
		new_st_val__h25724,
		new_st_val__h26704,
		new_st_val__h26708,
		new_st_val__h26712,
		new_st_val__h26716,
		new_st_val__h26721,
		new_st_val__h26727,
		new_st_val__h26732,
		new_st_val__h36863,
		new_st_val__h36954,
		new_st_val__h38814,
		new_st_val__h38818,
		new_st_val__h38822,
		new_st_val__h38826,
		new_st_val__h38831,
		new_st_val__h38837,
		new_st_val__h38842,
		new_value__h24197,
		new_value__h7772,
		result__h20481,
		result__h20509,
		result__h20537,
		result__h20565,
		result__h20593,
		result__h20621,
		result__h20649,
		result__h20677,
		result__h20722,
		result__h20750,
		result__h20778,
		result__h20806,
		result__h20834,
		result__h20862,
		result__h20890,
		result__h20918,
		result__h20963,
		result__h20991,
		result__h21019,
		result__h21047,
		result__h21088,
		result__h21116,
		result__h21144,
		result__h21172,
		result__h21213,
		result__h21241,
		result__h21280,
		result__h21308,
		result__h34667,
		result__h34697,
		result__h34724,
		result__h34751,
		result__h34778,
		result__h34805,
		result__h34832,
		result__h34859,
		result__h34903,
		result__h34930,
		result__h34957,
		result__h34984,
		result__h35011,
		result__h35038,
		result__h35065,
		result__h35092,
		result__h35136,
		result__h35163,
		result__h35190,
		result__h35217,
		result__h35257,
		result__h35284,
		result__h35311,
		result__h35338,
		result__h35378,
		result__h35405,
		result__h35443,
		result__h35470,
		result__h37042,
		result__h37950,
		result__h37978,
		result__h38006,
		result__h38034,
		result__h38062,
		result__h38090,
		result__h38118,
		result__h38163,
		result__h38191,
		result__h38219,
		result__h38247,
		result__h38275,
		result__h38303,
		result__h38331,
		result__h38359,
		result__h38404,
		result__h38432,
		result__h38460,
		result__h38488,
		result__h38529,
		result__h38557,
		result__h38585,
		result__h38613,
		result__h38654,
		result__h38682,
		result__h38721,
		result__h38749,
		w1___1__h25692,
		w1___1__h36922,
		w2___1__h36923,
		w2__h36853,
		word64__h7644,
		x__h21778,
		x__h36842,
		x__h3849,
		x__h7795,
		y__h14125,
		y__h7796,
		y__h7810;
  wire [33 : 0] _theResult___fst__h6308,
		_theResult___fst__h6380,
		cline_addr__h30818,
		lev_0_PTN_pa__h29581,
		lev_0_pte_pa__h29583,
		lev_0_pte_pa_w64__h29584,
		lev_1_pte_pa__h28671,
		lev_1_pte_pa_w64__h28672,
		pa___1__h6727,
		pa___1__h6776,
		pa__h6208,
		satp_pa__h1960,
		vpn_0_pa__h29582,
		vpn_1_pa__h28670,
		x1_avValue_pa__h6220;
  wire [31 : 0] IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_01_BITS__ETC__q32,
		_theResult____h28937,
		_theResult___snd_fst__h6310,
		_theResult___snd_fst__h6382,
		_theResult___snd_fst__h6859,
		ld_val4607_BITS_31_TO_0__q39,
		ld_val4607_BITS_63_TO_32__q46,
		master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3,
		master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10,
		pte___1__h6908,
		pte___1__h6936,
		pte___2__h6719,
		rg_st_amo_val_BITS_31_TO_0__q33,
		w16847_BITS_31_TO_0__q52,
		word64644_BITS_31_TO_0__q17,
		word64644_BITS_63_TO_32__q24,
		x1_avValue_pte__h6223;
  wire [15 : 0] ld_val4607_BITS_15_TO_0__q38,
		ld_val4607_BITS_31_TO_16__q42,
		ld_val4607_BITS_47_TO_32__q45,
		ld_val4607_BITS_63_TO_48__q49,
		master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2,
		master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q6,
		master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9,
		master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13,
		word64644_BITS_15_TO_0__q16,
		word64644_BITS_31_TO_16__q20,
		word64644_BITS_47_TO_32__q23,
		word64644_BITS_63_TO_48__q27;
  wire [7 : 0] ld_val4607_BITS_15_TO_8__q40,
	       ld_val4607_BITS_23_TO_16__q41,
	       ld_val4607_BITS_31_TO_24__q43,
	       ld_val4607_BITS_39_TO_32__q44,
	       ld_val4607_BITS_47_TO_40__q47,
	       ld_val4607_BITS_55_TO_48__q48,
	       ld_val4607_BITS_63_TO_56__q50,
	       ld_val4607_BITS_7_TO_0__q37,
	       master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1,
	       master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4,
	       master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q5,
	       master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q7,
	       master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q8,
	       master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11,
	       master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12,
	       master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14,
	       strobe64__h3142,
	       strobe64__h3144,
	       strobe64__h3146,
	       word64644_BITS_15_TO_8__q18,
	       word64644_BITS_23_TO_16__q19,
	       word64644_BITS_31_TO_24__q21,
	       word64644_BITS_39_TO_32__q22,
	       word64644_BITS_47_TO_40__q25,
	       word64644_BITS_55_TO_48__q26,
	       word64644_BITS_63_TO_56__q28,
	       word64644_BITS_7_TO_0__q15;
  wire [5 : 0] shift_bits__h2992;
  wire [3 : 0] IF_NOT_ram_state_and_ctag_cset_b_read__98_BIT__ETC___d436,
	       IF_rg_op_17_EQ_0_18_OR_rg_op_17_EQ_2_20_AND_rg_ETC___d438,
	       IF_rg_op_17_EQ_1_64_OR_rg_op_17_EQ_2_20_AND_rg_ETC___d437,
	       IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5__ETC___d440,
	       access_exc_code__h2760,
	       b__h28572,
	       exc_code___1__h6621,
	       x1_avValue_exc_code__h6221;
  wire [1 : 0] tmp__h30958, tmp__h30959;
  wire IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d332,
       IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_NO_ETC___d253,
       IF_rg_op_17_EQ_0_18_OR_rg_op_17_EQ_2_20_AND_rg_ETC___d346,
       IF_rg_op_17_EQ_1_64_OR_rg_op_17_EQ_2_20_AND_rg_ETC___d345,
       IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5__ETC___d480,
       NOT_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_3_ETC___d321,
       NOT_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_3_ETC___d327,
       NOT_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_3_ETC___d331,
       NOT_IF_rg_pte_pa_40_BIT_2_41_THEN_master_xacto_ETC___d968,
       NOT_cfg_verbosity_read__2_ULE_2_058___d1059,
       NOT_cfg_verbosity_read__2_ULT_2_44___d445,
       NOT_dmem_not_imem_32_AND_rg_op_17_EQ_0_18_OR_r_ETC___d380,
       NOT_dmem_not_imem_32_OR_NOT_rg_op_17_EQ_0_18_1_ETC___d139,
       NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d474,
       NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d670,
       NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d682,
       NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d687,
       NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d695,
       NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d704,
       NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d717,
       NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d854,
       NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d872,
       NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d918,
       NOT_master_xactor_f_rd_data_first__36_BITS_2_T_ETC___d961,
       NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d233,
       NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d263,
       NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d283,
       NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d344,
       NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d482,
       NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d685,
       NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d692,
       NOT_ram_state_and_ctag_cset_b_read__98_BIT_45__ETC___d234,
       NOT_req_f3_BITS_1_TO_0_393_EQ_0b0_394_395_AND__ETC___d1414,
       NOT_rg_op_17_EQ_0_18_19_AND_NOT_rg_op_17_EQ_2__ETC___d431,
       NOT_rg_op_17_EQ_1_64_88_AND_NOT_rg_op_17_EQ_2__ETC___d714,
       NOT_rg_op_17_EQ_1_64_88_AND_ram_state_and_ctag_ETC___d701,
       NOT_rg_op_17_EQ_2_20_21_OR_NOT_rg_amo_funct7_2_ETC___d712,
       NOT_rg_op_17_EQ_2_20_21_OR_NOT_rg_amo_funct7_2_ETC___d875,
       NOT_rg_op_17_EQ_2_20_21_OR_NOT_rg_amo_funct7_2_ETC___d881,
       NOT_rg_op_17_EQ_2_20_21_OR_NOT_rg_amo_funct7_2_ETC___d887,
       NOT_rg_priv_1_EQ_0b0_07_73_OR_tlb_lookup_rg_sa_ETC___d387,
       NOT_rg_priv_1_EQ_0b0_07_73_OR_tlb_lookup_rg_sa_ETC___d410,
       NOT_rg_priv_1_EQ_0b0_07_73_OR_tlb_lookup_rg_sa_ETC___d448,
       NOT_rg_priv_1_EQ_0b0_07_73_OR_tlb_lookup_rg_sa_ETC___d664,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d173,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d348,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d392,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d407,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d459,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d460,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d467,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d470,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d476,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d497,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d503,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d504,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d667,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d672,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d678,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d684,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d689,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d697,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d700,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d706,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d719,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d849,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d850,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d856,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d862,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d868,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d874,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d879,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d880,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d885,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d891,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d892,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d897,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d898,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d904,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d909,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d910,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d915,
       NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d920,
       NOT_tlb_lookup_rg_satp_4_BITS_30_TO_22_00_rg_a_ETC___d154,
       NOT_tlb_lookup_rg_satp_4_BITS_30_TO_22_00_rg_a_ETC___d170,
       cfg_verbosity_read__2_ULE_1___d43,
       dmem_not_imem_AND_rg_op_17_EQ_0_18_OR_rg_op_17_ETC___d382,
       dmem_not_imem_OR_NOT_rg_op_17_EQ_0_18_19_AND_N_ETC___d131,
       lrsc_result__h21768,
       master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d1000,
       master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d1004,
       master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d1010,
       master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d1036,
       master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d977,
       master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985,
       ram_state_and_ctag_cset_b_read__98_BITS_21_TO__ETC___d203,
       ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209,
       ram_state_and_ctag_cset_b_read__98_BIT_22_99_A_ETC___d479,
       ram_state_and_ctag_cset_b_read__98_BIT_22_99_A_ETC___d490,
       ram_state_and_ctag_cset_b_read__98_BIT_22_99_A_ETC___d668,
       ram_state_and_ctag_cset_b_read__98_BIT_22_99_A_ETC___d911,
       req_f3_BITS_1_TO_0_393_EQ_0b0_394_OR_req_f3_BI_ETC___d1423,
       rg_amo_funct7_22_BITS_6_TO_2_23_EQ_0b10_24_AND_ETC___d675,
       rg_amo_funct7_22_BITS_6_TO_2_23_EQ_0b1_86_OR_I_ETC___d342,
       rg_lrsc_pa_68_EQ_IF_rg_priv_1_ULE_0b1_2_AND_rg_ETC___d269,
       rg_op_17_EQ_0_18_OR_rg_op_17_EQ_2_20_AND_rg_am_ETC___d426,
       rg_op_17_EQ_0_18_OR_rg_op_17_EQ_2_20_AND_rg_am_ETC___d463,
       rg_op_17_EQ_0_18_OR_rg_op_17_EQ_2_20_AND_rg_am_ETC___d484,
       rg_op_17_EQ_0_18_OR_rg_op_17_EQ_2_20_AND_rg_am_ETC___d494,
       rg_op_17_EQ_0_18_OR_rg_op_17_EQ_2_20_AND_rg_am_ETC___d498,
       rg_op_17_EQ_1_64_OR_rg_op_17_EQ_2_20_AND_rg_am_ETC___d492,
       rg_op_17_EQ_1_64_OR_rg_op_17_EQ_2_20_AND_rg_am_ETC___d715,
       rg_op_17_EQ_1_64_OR_rg_op_17_EQ_2_20_AND_rg_am_ETC___d845,
       rg_op_17_EQ_2_20_AND_rg_amo_funct7_22_BITS_6_T_ETC___d285,
       rg_priv_1_EQ_0b0_07_AND_NOT_tlb_lookup_rg_satp_ETC___d148,
       rg_priv_1_EQ_0b0_07_AND_NOT_tlb_lookup_rg_satp_ETC___d161,
       rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d157,
       rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d350,
       rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d395,
       rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d417,
       rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d434,
       rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d435,
       rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d453,
       rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d456,
       rg_priv_1_ULE_0b1___d92,
       rg_state_5_EQ_12_109_AND_rg_op_17_EQ_0_18_OR_r_ETC___d1111,
       tlb_lookup_rg_satp_4_BITS_30_TO_22_00_rg_addr__ETC___d137,
       tlb_lookup_rg_satp_4_BITS_30_TO_22_00_rg_addr__ETC___d389,
       y__h6547;

  // action method set_verbosity
  assign RDY_set_verbosity = 1'd1 ;
  assign CAN_FIRE_set_verbosity = 1'd1 ;
  assign WILL_FIRE_set_verbosity = EN_set_verbosity ;

  // action method server_reset_request_put
  assign RDY_server_reset_request_put = f_reset_reqs$FULL_N ;
  assign CAN_FIRE_server_reset_request_put = f_reset_reqs$FULL_N ;
  assign WILL_FIRE_server_reset_request_put = EN_server_reset_request_put ;

  // action method server_reset_response_get
  assign RDY_server_reset_response_get =
	     !f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
  assign CAN_FIRE_server_reset_response_get =
	     !f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
  assign WILL_FIRE_server_reset_response_get = EN_server_reset_response_get ;

  // action method req
  assign CAN_FIRE_req = 1'd1 ;
  assign WILL_FIRE_req = EN_req ;

  // value method valid
  assign valid = dw_valid$whas ;

  // value method addr
  assign addr = rg_addr ;

  // value method cword
  always@(MUX_dw_output_ld_val$wset_1__SEL_1 or
	  ld_val__h34607 or
	  MUX_dw_output_ld_val$wset_1__SEL_2 or
	  new_ld_val__h36813 or
	  MUX_dw_valid$wset_1__SEL_2 or
	  MUX_dw_output_ld_val$wset_1__VAL_3 or
	  MUX_dw_output_ld_val$wset_1__SEL_4 or rg_ld_val)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_dw_output_ld_val$wset_1__SEL_1: cword = ld_val__h34607;
      MUX_dw_output_ld_val$wset_1__SEL_2: cword = new_ld_val__h36813;
      MUX_dw_valid$wset_1__SEL_2: cword = MUX_dw_output_ld_val$wset_1__VAL_3;
      MUX_dw_output_ld_val$wset_1__SEL_4: cword = rg_ld_val;
      default: cword = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end

  // value method st_amo_val
  assign st_amo_val = MUX_dw_valid$wset_1__SEL_2 ? 64'd0 : rg_st_amo_val ;

  // value method exc
  assign exc = rg_state == 4'd4 ;

  // value method exc_code
  assign exc_code = rg_exc_code ;

  // action method server_flush_request_put
  assign RDY_server_flush_request_put = f_reset_reqs$FULL_N ;
  assign CAN_FIRE_server_flush_request_put = f_reset_reqs$FULL_N ;
  assign WILL_FIRE_server_flush_request_put = EN_server_flush_request_put ;

  // action method server_flush_response_get
  assign RDY_server_flush_response_get =
	     f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
  assign CAN_FIRE_server_flush_response_get =
	     f_reset_rsps$D_OUT && f_reset_rsps$EMPTY_N ;
  assign WILL_FIRE_server_flush_response_get = EN_server_flush_response_get ;

  // action method tlb_flush
  assign RDY_tlb_flush = 1'd1 ;
  assign CAN_FIRE_tlb_flush = 1'd1 ;
  assign WILL_FIRE_tlb_flush = EN_tlb_flush ;

  // value method mem_master_m_awvalid
  assign mem_master_awvalid = master_xactor_f_wr_addr$EMPTY_N ;

  // value method mem_master_m_awid
  assign mem_master_awid = master_xactor_f_wr_addr$D_OUT[96:93] ;

  // value method mem_master_m_awaddr
  assign mem_master_awaddr = master_xactor_f_wr_addr$D_OUT[92:29] ;

  // value method mem_master_m_awlen
  assign mem_master_awlen = master_xactor_f_wr_addr$D_OUT[28:21] ;

  // value method mem_master_m_awsize
  assign mem_master_awsize = master_xactor_f_wr_addr$D_OUT[20:18] ;

  // value method mem_master_m_awburst
  assign mem_master_awburst = master_xactor_f_wr_addr$D_OUT[17:16] ;

  // value method mem_master_m_awlock
  assign mem_master_awlock = master_xactor_f_wr_addr$D_OUT[15] ;

  // value method mem_master_m_awcache
  assign mem_master_awcache = master_xactor_f_wr_addr$D_OUT[14:11] ;

  // value method mem_master_m_awprot
  assign mem_master_awprot = master_xactor_f_wr_addr$D_OUT[10:8] ;

  // value method mem_master_m_awqos
  assign mem_master_awqos = master_xactor_f_wr_addr$D_OUT[7:4] ;

  // value method mem_master_m_awregion
  assign mem_master_awregion = master_xactor_f_wr_addr$D_OUT[3:0] ;

  // action method mem_master_m_awready
  assign CAN_FIRE_mem_master_m_awready = 1'd1 ;
  assign WILL_FIRE_mem_master_m_awready = 1'd1 ;

  // value method mem_master_m_wvalid
  assign mem_master_wvalid = master_xactor_f_wr_data$EMPTY_N ;

  // value method mem_master_m_wdata
  assign mem_master_wdata = master_xactor_f_wr_data$D_OUT[72:9] ;

  // value method mem_master_m_wstrb
  assign mem_master_wstrb = master_xactor_f_wr_data$D_OUT[8:1] ;

  // value method mem_master_m_wlast
  assign mem_master_wlast = master_xactor_f_wr_data$D_OUT[0] ;

  // action method mem_master_m_wready
  assign CAN_FIRE_mem_master_m_wready = 1'd1 ;
  assign WILL_FIRE_mem_master_m_wready = 1'd1 ;

  // action method mem_master_m_bvalid
  assign CAN_FIRE_mem_master_m_bvalid = 1'd1 ;
  assign WILL_FIRE_mem_master_m_bvalid = 1'd1 ;

  // value method mem_master_m_bready
  assign mem_master_bready = master_xactor_f_wr_resp$FULL_N ;

  // value method mem_master_m_arvalid
  assign mem_master_arvalid = master_xactor_f_rd_addr$EMPTY_N ;

  // value method mem_master_m_arid
  assign mem_master_arid = master_xactor_f_rd_addr$D_OUT[96:93] ;

  // value method mem_master_m_araddr
  assign mem_master_araddr = master_xactor_f_rd_addr$D_OUT[92:29] ;

  // value method mem_master_m_arlen
  assign mem_master_arlen = master_xactor_f_rd_addr$D_OUT[28:21] ;

  // value method mem_master_m_arsize
  assign mem_master_arsize = master_xactor_f_rd_addr$D_OUT[20:18] ;

  // value method mem_master_m_arburst
  assign mem_master_arburst = master_xactor_f_rd_addr$D_OUT[17:16] ;

  // value method mem_master_m_arlock
  assign mem_master_arlock = master_xactor_f_rd_addr$D_OUT[15] ;

  // value method mem_master_m_arcache
  assign mem_master_arcache = master_xactor_f_rd_addr$D_OUT[14:11] ;

  // value method mem_master_m_arprot
  assign mem_master_arprot = master_xactor_f_rd_addr$D_OUT[10:8] ;

  // value method mem_master_m_arqos
  assign mem_master_arqos = master_xactor_f_rd_addr$D_OUT[7:4] ;

  // value method mem_master_m_arregion
  assign mem_master_arregion = master_xactor_f_rd_addr$D_OUT[3:0] ;

  // action method mem_master_m_arready
  assign CAN_FIRE_mem_master_m_arready = 1'd1 ;
  assign WILL_FIRE_mem_master_m_arready = 1'd1 ;

  // action method mem_master_m_rvalid
  assign CAN_FIRE_mem_master_m_rvalid = 1'd1 ;
  assign WILL_FIRE_mem_master_m_rvalid = 1'd1 ;

  // value method mem_master_m_rready
  assign mem_master_rready = master_xactor_f_rd_data$FULL_N ;

  // action method set_watch_tohost
  assign RDY_set_watch_tohost = 1'd1 ;
  assign CAN_FIRE_set_watch_tohost = 1'd1 ;
  assign WILL_FIRE_set_watch_tohost = EN_set_watch_tohost ;

  // value method mv_tohost_value
  assign mv_tohost_value = rg_tohost_value ;
  assign RDY_mv_tohost_value = 1'd1 ;

  // action method ma_ddr4_ready
  assign RDY_ma_ddr4_ready = 1'd1 ;
  assign CAN_FIRE_ma_ddr4_ready = 1'd1 ;
  assign WILL_FIRE_ma_ddr4_ready = EN_ma_ddr4_ready ;

  // value method mv_status
  assign mv_status = rg_wr_rsp_err ? 8'd1 : 8'd0 ;

  // submodule f_fabric_write_reqs
  FIFO2 #(.width(32'd101), .guarded(32'd1)) f_fabric_write_reqs(.RST(RST_N),
								.CLK(CLK),
								.D_IN(f_fabric_write_reqs$D_IN),
								.ENQ(f_fabric_write_reqs$ENQ),
								.DEQ(f_fabric_write_reqs$DEQ),
								.CLR(f_fabric_write_reqs$CLR),
								.D_OUT(f_fabric_write_reqs$D_OUT),
								.FULL_N(f_fabric_write_reqs$FULL_N),
								.EMPTY_N(f_fabric_write_reqs$EMPTY_N));

  // submodule f_pte_writebacks
  FIFO2 #(.width(32'd66), .guarded(32'd1)) f_pte_writebacks(.RST(RST_N),
							    .CLK(CLK),
							    .D_IN(f_pte_writebacks$D_IN),
							    .ENQ(f_pte_writebacks$ENQ),
							    .DEQ(f_pte_writebacks$DEQ),
							    .CLR(f_pte_writebacks$CLR),
							    .D_OUT(f_pte_writebacks$D_OUT),
							    .FULL_N(f_pte_writebacks$FULL_N),
							    .EMPTY_N(f_pte_writebacks$EMPTY_N));

  // submodule f_reset_reqs
  FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_reqs(.RST(RST_N),
						       .CLK(CLK),
						       .D_IN(f_reset_reqs$D_IN),
						       .ENQ(f_reset_reqs$ENQ),
						       .DEQ(f_reset_reqs$DEQ),
						       .CLR(f_reset_reqs$CLR),
						       .D_OUT(f_reset_reqs$D_OUT),
						       .FULL_N(f_reset_reqs$FULL_N),
						       .EMPTY_N(f_reset_reqs$EMPTY_N));

  // submodule f_reset_rsps
  FIFO2 #(.width(32'd1), .guarded(32'd1)) f_reset_rsps(.RST(RST_N),
						       .CLK(CLK),
						       .D_IN(f_reset_rsps$D_IN),
						       .ENQ(f_reset_rsps$ENQ),
						       .DEQ(f_reset_rsps$DEQ),
						       .CLR(f_reset_rsps$CLR),
						       .D_OUT(f_reset_rsps$D_OUT),
						       .FULL_N(f_reset_rsps$FULL_N),
						       .EMPTY_N(f_reset_rsps$EMPTY_N));

  // submodule master_xactor_f_rd_addr
  FIFO2 #(.width(32'd97),
	  .guarded(32'd1)) master_xactor_f_rd_addr(.RST(RST_N),
						   .CLK(CLK),
						   .D_IN(master_xactor_f_rd_addr$D_IN),
						   .ENQ(master_xactor_f_rd_addr$ENQ),
						   .DEQ(master_xactor_f_rd_addr$DEQ),
						   .CLR(master_xactor_f_rd_addr$CLR),
						   .D_OUT(master_xactor_f_rd_addr$D_OUT),
						   .FULL_N(master_xactor_f_rd_addr$FULL_N),
						   .EMPTY_N(master_xactor_f_rd_addr$EMPTY_N));

  // submodule master_xactor_f_rd_data
  FIFO2 #(.width(32'd71),
	  .guarded(32'd1)) master_xactor_f_rd_data(.RST(RST_N),
						   .CLK(CLK),
						   .D_IN(master_xactor_f_rd_data$D_IN),
						   .ENQ(master_xactor_f_rd_data$ENQ),
						   .DEQ(master_xactor_f_rd_data$DEQ),
						   .CLR(master_xactor_f_rd_data$CLR),
						   .D_OUT(master_xactor_f_rd_data$D_OUT),
						   .FULL_N(master_xactor_f_rd_data$FULL_N),
						   .EMPTY_N(master_xactor_f_rd_data$EMPTY_N));

  // submodule master_xactor_f_wr_addr
  FIFO2 #(.width(32'd97),
	  .guarded(32'd1)) master_xactor_f_wr_addr(.RST(RST_N),
						   .CLK(CLK),
						   .D_IN(master_xactor_f_wr_addr$D_IN),
						   .ENQ(master_xactor_f_wr_addr$ENQ),
						   .DEQ(master_xactor_f_wr_addr$DEQ),
						   .CLR(master_xactor_f_wr_addr$CLR),
						   .D_OUT(master_xactor_f_wr_addr$D_OUT),
						   .FULL_N(master_xactor_f_wr_addr$FULL_N),
						   .EMPTY_N(master_xactor_f_wr_addr$EMPTY_N));

  // submodule master_xactor_f_wr_data
  FIFO2 #(.width(32'd73),
	  .guarded(32'd1)) master_xactor_f_wr_data(.RST(RST_N),
						   .CLK(CLK),
						   .D_IN(master_xactor_f_wr_data$D_IN),
						   .ENQ(master_xactor_f_wr_data$ENQ),
						   .DEQ(master_xactor_f_wr_data$DEQ),
						   .CLR(master_xactor_f_wr_data$CLR),
						   .D_OUT(master_xactor_f_wr_data$D_OUT),
						   .FULL_N(master_xactor_f_wr_data$FULL_N),
						   .EMPTY_N(master_xactor_f_wr_data$EMPTY_N));

  // submodule master_xactor_f_wr_resp
  FIFO2 #(.width(32'd6), .guarded(32'd1)) master_xactor_f_wr_resp(.RST(RST_N),
								  .CLK(CLK),
								  .D_IN(master_xactor_f_wr_resp$D_IN),
								  .ENQ(master_xactor_f_wr_resp$ENQ),
								  .DEQ(master_xactor_f_wr_resp$DEQ),
								  .CLR(master_xactor_f_wr_resp$CLR),
								  .D_OUT(master_xactor_f_wr_resp$D_OUT),
								  .FULL_N(master_xactor_f_wr_resp$FULL_N),
								  .EMPTY_N(master_xactor_f_wr_resp$EMPTY_N));

  // submodule ram_cword_set
  BRAM2 #(.PIPELINED(1'd0),
	  .ADDR_WIDTH(32'd9),
	  .DATA_WIDTH(32'd128),
	  .MEMSIZE(10'd512)) ram_cword_set(.CLKA(CLK),
					   .CLKB(CLK),
					   .ADDRA(ram_cword_set$ADDRA),
					   .ADDRB(ram_cword_set$ADDRB),
					   .DIA(ram_cword_set$DIA),
					   .DIB(ram_cword_set$DIB),
					   .WEA(ram_cword_set$WEA),
					   .WEB(ram_cword_set$WEB),
					   .ENA(ram_cword_set$ENA),
					   .ENB(ram_cword_set$ENB),
					   .DOA(),
					   .DOB(ram_cword_set$DOB));

  // submodule ram_state_and_ctag_cset
  BRAM2 #(.PIPELINED(1'd0),
	  .ADDR_WIDTH(32'd6),
	  .DATA_WIDTH(32'd46),
	  .MEMSIZE(7'd64)) ram_state_and_ctag_cset(.CLKA(CLK),
						   .CLKB(CLK),
						   .ADDRA(ram_state_and_ctag_cset$ADDRA),
						   .ADDRB(ram_state_and_ctag_cset$ADDRB),
						   .DIA(ram_state_and_ctag_cset$DIA),
						   .DIB(ram_state_and_ctag_cset$DIB),
						   .WEA(ram_state_and_ctag_cset$WEA),
						   .WEB(ram_state_and_ctag_cset$WEB),
						   .ENA(ram_state_and_ctag_cset$ENA),
						   .ENB(ram_state_and_ctag_cset$ENB),
						   .DOA(),
						   .DOB(ram_state_and_ctag_cset$DOB));

  // submodule soc_map
  mkSoC_Map soc_map(.CLK(CLK),
		    .RST_N(RST_N),
		    .m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
		    .m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
		    .m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
		    .m_near_mem_io_addr_base(),
		    .m_near_mem_io_addr_size(),
		    .m_near_mem_io_addr_lim(),
		    .m_plic_addr_base(),
		    .m_plic_addr_size(),
		    .m_plic_addr_lim(),
		    .m_uart0_addr_base(),
		    .m_uart0_addr_size(),
		    .m_uart0_addr_lim(),
		    .m_boot_rom_addr_base(),
		    .m_boot_rom_addr_size(),
		    .m_boot_rom_addr_lim(),
		    .m_mem0_controller_addr_base(),
		    .m_mem0_controller_addr_size(),
		    .m_mem0_controller_addr_lim(),
		    .m_tcm_addr_base(),
		    .m_tcm_addr_size(),
		    .m_tcm_addr_lim(),
		    .m_is_mem_addr(soc_map$m_is_mem_addr),
		    .m_is_IO_addr(),
		    .m_is_near_mem_IO_addr(),
		    .m_pc_reset_value(),
		    .m_mtvec_reset_value(),
		    .m_nmivec_reset_value());

  // submodule tlb
  mkTLB #(.dmem_not_imem(dmem_not_imem)) tlb(.CLK(CLK),
					     .RST_N(RST_N),
					     .insert_asid(tlb$insert_asid),
					     .insert_level(tlb$insert_level),
					     .insert_pte(tlb$insert_pte),
					     .insert_pte_pa(tlb$insert_pte_pa),
					     .insert_vpn(tlb$insert_vpn),
					     .lookup_asid(tlb$lookup_asid),
					     .lookup_vpn(tlb$lookup_vpn),
					     .EN_flush(tlb$EN_flush),
					     .EN_insert(tlb$EN_insert),
					     .RDY_flush(),
					     .lookup(tlb$lookup),
					     .RDY_lookup(tlb$RDY_lookup),
					     .RDY_insert(tlb$RDY_insert));

  // rule RL_rl_fabric_send_write_req
  assign CAN_FIRE_RL_rl_fabric_send_write_req =
	     ctr_wr_rsps_pending_crg != 4'd15 &&
	     f_fabric_write_reqs$EMPTY_N &&
	     master_xactor_f_wr_addr$FULL_N &&
	     master_xactor_f_wr_data$FULL_N &&
	     rg_ddr4_ready ;
  assign WILL_FIRE_RL_rl_fabric_send_write_req =
	     CAN_FIRE_RL_rl_fabric_send_write_req ;

  // rule RL_rl_reset
  assign CAN_FIRE_RL_rl_reset =
	     (rg_cset_in_cache != 6'd63 ||
	      f_reset_reqs$EMPTY_N && f_reset_rsps$FULL_N) &&
	     rg_state == 4'd1 ;
  assign WILL_FIRE_RL_rl_reset = CAN_FIRE_RL_rl_reset ;

  // rule RL_rl_probe_and_immed_rsp
  assign CAN_FIRE_RL_rl_probe_and_immed_rsp =
	     (cfg_verbosity_read__2_ULE_1___d43 || tlb$RDY_lookup) &&
	     (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$RDY_lookup) &&
	     rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d350 &&
	     rg_ddr4_ready &&
	     rg_state == 4'd3 ;
  assign WILL_FIRE_RL_rl_probe_and_immed_rsp =
	     CAN_FIRE_RL_rl_probe_and_immed_rsp &&
	     !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_start_tlb_refill
  assign CAN_FIRE_RL_rl_start_tlb_refill =
	     master_xactor_f_rd_addr$FULL_N && rg_state == 4'd5 &&
	     b__h28572 == 4'd0 ;
  assign WILL_FIRE_RL_rl_start_tlb_refill =
	     CAN_FIRE_RL_rl_start_tlb_refill && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_ptw_level_1
  assign CAN_FIRE_RL_rl_ptw_level_1 =
	     master_xactor_f_rd_data$EMPTY_N &&
	     NOT_master_xactor_f_rd_data_first__36_BITS_2_T_ETC___d961 &&
	     rg_state == 4'd6 ;
  assign WILL_FIRE_RL_rl_ptw_level_1 =
	     CAN_FIRE_RL_rl_ptw_level_1 && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_ptw_level_0
  assign CAN_FIRE_RL_rl_ptw_level_0 =
	     master_xactor_f_rd_data$EMPTY_N &&
	     (master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	      !_theResult____h28937[0] ||
	      !_theResult____h28937[1] && _theResult____h28937[2] ||
	      !_theResult____h28937[3] && !_theResult____h28937[1] ||
	      tlb$RDY_insert) &&
	     rg_state == 4'd7 ;
  assign WILL_FIRE_RL_rl_ptw_level_0 =
	     CAN_FIRE_RL_rl_ptw_level_0 && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_start_cache_refill
  assign CAN_FIRE_RL_rl_start_cache_refill =
	     master_xactor_f_rd_addr$FULL_N && rg_state == 4'd8 &&
	     b__h28572 == 4'd0 ;
  assign WILL_FIRE_RL_rl_start_cache_refill =
	     CAN_FIRE_RL_rl_start_cache_refill &&
	     !WILL_FIRE_RL_rl_start_reset &&
	     !EN_req ;

  // rule RL_rl_cache_refill_rsps_loop
  assign CAN_FIRE_RL_rl_cache_refill_rsps_loop =
	     master_xactor_f_rd_data$EMPTY_N && rg_state == 4'd9 ;
  assign WILL_FIRE_RL_rl_cache_refill_rsps_loop =
	     CAN_FIRE_RL_rl_cache_refill_rsps_loop &&
	     !WILL_FIRE_RL_rl_start_reset &&
	     !EN_req ;

  // rule RL_rl_rereq
  assign CAN_FIRE_RL_rl_rereq = rg_state == 4'd10 ;
  assign WILL_FIRE_RL_rl_rereq =
	     CAN_FIRE_RL_rl_rereq && !WILL_FIRE_RL_rl_start_reset && !EN_req ;

  // rule RL_rl_ST_AMO_response
  assign CAN_FIRE_RL_rl_ST_AMO_response = rg_state == 4'd11 ;
  assign WILL_FIRE_RL_rl_ST_AMO_response = CAN_FIRE_RL_rl_ST_AMO_response ;

  // rule RL_rl_io_read_req
  assign CAN_FIRE_RL_rl_io_read_req =
	     master_xactor_f_rd_addr$FULL_N &&
	     rg_state_5_EQ_12_109_AND_rg_op_17_EQ_0_18_OR_r_ETC___d1111 ;
  assign WILL_FIRE_RL_rl_io_read_req =
	     CAN_FIRE_RL_rl_io_read_req && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_io_read_rsp
  assign CAN_FIRE_RL_rl_io_read_rsp =
	     master_xactor_f_rd_data$EMPTY_N && rg_state == 4'd13 ;
  assign WILL_FIRE_RL_rl_io_read_rsp =
	     CAN_FIRE_RL_rl_io_read_rsp && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_maintain_io_read_rsp
  assign CAN_FIRE_RL_rl_maintain_io_read_rsp = rg_state == 4'd14 ;
  assign WILL_FIRE_RL_rl_maintain_io_read_rsp =
	     CAN_FIRE_RL_rl_maintain_io_read_rsp ;

  // rule RL_rl_io_write_req
  assign CAN_FIRE_RL_rl_io_write_req =
	     f_fabric_write_reqs$FULL_N && rg_state == 4'd12 &&
	     rg_op == 2'd1 ;
  assign WILL_FIRE_RL_rl_io_write_req =
	     CAN_FIRE_RL_rl_io_write_req && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_io_AMO_SC_req
  assign CAN_FIRE_RL_rl_io_AMO_SC_req =
	     rg_state == 4'd12 && rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00011 ;
  assign WILL_FIRE_RL_rl_io_AMO_SC_req =
	     CAN_FIRE_RL_rl_io_AMO_SC_req && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_io_AMO_op_req
  assign CAN_FIRE_RL_rl_io_AMO_op_req =
	     master_xactor_f_rd_addr$FULL_N && rg_state == 4'd12 &&
	     rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] != 5'b00010 &&
	     rg_amo_funct7[6:2] != 5'b00011 ;
  assign WILL_FIRE_RL_rl_io_AMO_op_req =
	     CAN_FIRE_RL_rl_io_AMO_op_req && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_writeback_updated_PTE
  assign CAN_FIRE_RL_rl_writeback_updated_PTE =
	     f_pte_writebacks$EMPTY_N && f_fabric_write_reqs$FULL_N ;
  assign WILL_FIRE_RL_rl_writeback_updated_PTE =
	     CAN_FIRE_RL_rl_writeback_updated_PTE &&
	     !WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	     !WILL_FIRE_RL_rl_io_write_req &&
	     !WILL_FIRE_RL_rl_probe_and_immed_rsp ;

  // rule RL_rl_io_AMO_read_rsp
  assign CAN_FIRE_RL_rl_io_AMO_read_rsp =
	     master_xactor_f_rd_data$EMPTY_N &&
	     (master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	      f_fabric_write_reqs$FULL_N) &&
	     rg_state == 4'd15 ;
  assign WILL_FIRE_RL_rl_io_AMO_read_rsp =
	     CAN_FIRE_RL_rl_io_AMO_read_rsp && !WILL_FIRE_RL_rl_start_reset ;

  // rule RL_rl_discard_write_rsp
  assign CAN_FIRE_RL_rl_discard_write_rsp =
	     b__h28572 != 4'd0 && master_xactor_f_wr_resp$EMPTY_N ;
  assign WILL_FIRE_RL_rl_discard_write_rsp =
	     CAN_FIRE_RL_rl_discard_write_rsp ;

  // rule RL_rl_drive_exception_rsp
  assign CAN_FIRE_RL_rl_drive_exception_rsp = rg_state == 4'd4 ;
  assign WILL_FIRE_RL_rl_drive_exception_rsp = rg_state == 4'd4 ;

  // rule RL_rl_start_reset
  assign CAN_FIRE_RL_rl_start_reset = MUX_rg_state$write_1__SEL_3 ;
  assign WILL_FIRE_RL_rl_start_reset = MUX_rg_state$write_1__SEL_3 ;

  // inputs to muxes for submodule ports
  assign MUX_dw_output_ld_val$wset_1__SEL_1 =
	     WILL_FIRE_RL_rl_io_read_rsp &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
  assign MUX_dw_output_ld_val$wset_1__SEL_2 =
	     WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
  assign MUX_dw_output_ld_val$wset_1__SEL_4 =
	     WILL_FIRE_RL_rl_maintain_io_read_rsp ||
	     WILL_FIRE_RL_rl_ST_AMO_response ;
  assign MUX_dw_valid$wset_1__SEL_2 =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d504 ;
  assign MUX_f_fabric_write_reqs$enq_1__SEL_2 =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d850 ;
  assign MUX_master_xactor_f_rd_addr$enq_1__SEL_1 =
	     WILL_FIRE_RL_rl_ptw_level_1 &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     _theResult____h28937[0] &&
	     !_theResult____h28937[2] &&
	     !_theResult____h28937[3] &&
	     !_theResult____h28937[1] ;
  assign MUX_master_xactor_f_rd_addr$enq_1__SEL_2 =
	     WILL_FIRE_RL_rl_io_AMO_op_req || WILL_FIRE_RL_rl_io_read_req ;
  assign MUX_ram_cword_set$a_put_1__SEL_1 =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
  assign MUX_ram_cword_set$b_put_1__SEL_1 =
	     EN_req &&
	     req_f3_BITS_1_TO_0_393_EQ_0b0_394_OR_req_f3_BI_ETC___d1423 ;
  assign MUX_ram_cword_set$b_put_1__SEL_2 =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     rg_cset_cword_in_cache[2:0] != 3'd7 ;
  assign MUX_ram_state_and_ctag_cset$a_put_1__SEL_1 =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     rg_cset_cword_in_cache[2:0] == 3'd0 &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ;
  assign MUX_rg_error_during_refill$write_1__SEL_1 =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
  assign MUX_rg_exc_code$write_1__SEL_1 =
	     EN_req &&
	     NOT_req_f3_BITS_1_TO_0_393_EQ_0b0_394_395_AND__ETC___d1414 ;
  assign MUX_rg_exc_code$write_1__SEL_2 =
	     WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
  assign MUX_rg_exc_code$write_1__SEL_3 =
	     WILL_FIRE_RL_rl_io_read_rsp &&
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
  assign MUX_rg_exc_code$write_1__SEL_5 =
	     WILL_FIRE_RL_rl_ptw_level_0 &&
	     (!_theResult____h28937[0] ||
	      !_theResult____h28937[1] && _theResult____h28937[2] ||
	      !_theResult____h28937[3] && !_theResult____h28937[1] ||
	      master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) ;
  assign MUX_rg_exc_code$write_1__SEL_6 =
	     WILL_FIRE_RL_rl_ptw_level_1 &&
	     NOT_IF_rg_pte_pa_40_BIT_2_41_THEN_master_xacto_ETC___d968 ;
  assign MUX_rg_exc_code$write_1__SEL_7 =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d157 ;
  assign MUX_rg_ld_val$write_1__SEL_2 =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d706 ;
  assign MUX_rg_lrsc_valid$write_1__SEL_2 =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d497 ;
  assign MUX_rg_state$write_1__SEL_3 =
	     f_reset_reqs$EMPTY_N && rg_state != 4'd1 ;
  assign MUX_rg_state$write_1__SEL_11 =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     rg_cset_cword_in_cache[2:0] == 3'd7 ;
  assign MUX_rg_state$write_1__SEL_16 =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d435 ;
  assign MUX_rg_state$write_1__SEL_17 =
	     WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ;
  assign MUX_tlb$insert_1__SEL_1 =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d417 ;
  assign MUX_tlb$insert_1__SEL_2 =
	     WILL_FIRE_RL_rl_ptw_level_1 &&
	     master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d1000 ;
  assign MUX_tlb$insert_1__SEL_3 =
	     WILL_FIRE_RL_rl_ptw_level_0 &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     _theResult____h28937[0] &&
	     (_theResult____h28937[1] || !_theResult____h28937[2]) &&
	     (_theResult____h28937[3] || _theResult____h28937[1]) ;
  assign MUX_dw_output_ld_val$wset_1__VAL_3 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
	       new_value__h7772 :
	       new_value__h24197 ;
  assign MUX_f_fabric_write_reqs$enq_1__VAL_1 = { rg_f3, rg_pa, x__h36842 } ;
  assign MUX_f_fabric_write_reqs$enq_1__VAL_2 =
	     { rg_f3,
	       x1_avValue_pa__h6220,
	       IF_rg_op_17_EQ_1_64_OR_rg_op_17_EQ_2_20_AND_rg_ETC___d851 } ;
  assign MUX_f_fabric_write_reqs$enq_1__VAL_3 =
	     { 3'b010, f_pte_writebacks$D_OUT[65:32], x__h3849 } ;
  assign MUX_f_fabric_write_reqs$enq_1__VAL_4 =
	     { rg_f3, rg_pa, rg_st_amo_val } ;
  assign MUX_master_xactor_f_rd_addr$enq_1__VAL_1 =
	     { 4'd0, lev_0_pte_pa_w64_fa__h29585, 29'd589824 } ;
  assign MUX_master_xactor_f_rd_addr$enq_1__VAL_2 =
	     { 4'd0, fabric_addr__h36270, 8'd0, value__h36399, 18'd65536 } ;
  assign MUX_master_xactor_f_rd_addr$enq_1__VAL_3 =
	     { 4'd0, lev_1_pte_pa_w64_fa__h28673, 29'd589824 } ;
  assign MUX_master_xactor_f_rd_addr$enq_1__VAL_4 =
	     { 4'd0, cline_fabric_addr__h30819, 29'd15532032 } ;
  assign MUX_ram_cword_set$a_put_3__VAL_1 =
	     rg_victim_way ?
	       { master_xactor_f_rd_data$D_OUT[66:3],
		 ram_cword_set$DOB[63:0] } :
	       { ram_cword_set$DOB[127:64],
		 master_xactor_f_rd_data$D_OUT[66:3] } ;
  assign MUX_ram_cword_set$a_put_3__VAL_2 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
	       { IF_ram_state_and_ctag_cset_b_read__98_BIT_45_0_ETC___d773,
		 IF_NOT_ram_state_and_ctag_cset_b_read__98_BIT__ETC___d774 } :
	       { IF_ram_state_and_ctag_cset_b_read__98_BIT_45_0_ETC___d841,
		 IF_NOT_ram_state_and_ctag_cset_b_read__98_BIT__ETC___d842 } ;
  assign MUX_ram_cword_set$b_put_2__VAL_2 = rg_cset_cword_in_cache + 9'd1 ;
  assign MUX_ram_cword_set$b_put_2__VAL_4 = { rg_addr[11:6], 3'd0 } ;
  assign MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 =
	     { rg_victim_way || ram_state_and_ctag_cset$DOB[45],
	       rg_victim_way ?
		 rg_pa[33:12] :
		 ram_state_and_ctag_cset$DOB[44:23],
	       !rg_victim_way || ram_state_and_ctag_cset$DOB[22],
	       rg_victim_way ?
		 ram_state_and_ctag_cset$DOB[21:0] :
		 rg_pa[33:12] } ;
  assign MUX_rg_cset_in_cache$write_1__VAL_1 = rg_cset_in_cache + 6'd1 ;
  assign MUX_rg_exc_code$write_1__VAL_1 = (req_op == 2'd0) ? 4'd4 : 4'd6 ;
  assign MUX_rg_exc_code$write_1__VAL_5 =
	     (master_xactor_f_rd_data$D_OUT[2:1] == 2'b0) ?
	       exc_code___1__h6621 :
	       access_exc_code__h2760 ;
  assign MUX_rg_ld_val$write_1__VAL_2 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
	       x__h21778 :
	       IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_IF_rg_f3_15_E_ETC___d710 ;
  assign MUX_rg_pa$write_1__VAL_1 = { 2'd0, req_addr } ;
  assign MUX_rg_state$write_1__VAL_2 =
	     NOT_req_f3_BITS_1_TO_0_393_EQ_0b0_394_395_AND__ETC___d1414 ?
	       4'd4 :
	       4'd3 ;
  assign MUX_rg_state$write_1__VAL_4 =
	     (master_xactor_f_rd_data$D_OUT[2:1] == 2'b0) ? 4'd14 : 4'd4 ;
  assign MUX_rg_state$write_1__VAL_11 =
	     (master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	      rg_error_during_refill) ?
	       4'd4 :
	       4'd10 ;
  assign MUX_rg_state$write_1__VAL_13 =
	     (master_xactor_f_rd_data$D_OUT[2:1] == 2'b0) ?
	       ((!_theResult____h28937[0] ||
		 !_theResult____h28937[1] && _theResult____h28937[2] ||
		 !_theResult____h28937[3] && !_theResult____h28937[1]) ?
		  4'd4 :
		  4'd10) :
	       4'd4 ;
  assign MUX_rg_state$write_1__VAL_14 =
	     (master_xactor_f_rd_data$D_OUT[2:1] == 2'b0) ?
	       ((!_theResult____h28937[0] ||
		 !_theResult____h28937[1] && _theResult____h28937[2]) ?
		  4'd4 :
		  ((!_theResult____h28937[3] && !_theResult____h28937[1]) ?
		     4'd7 :
		     ((_theResult____h28937[19:10] == 10'd0) ?
			4'd10 :
			4'd4))) :
	       4'd4 ;
  assign MUX_rg_state$write_1__VAL_16 =
	     (rg_priv_1_ULE_0b1___d92 && rg_satp[31] && !tlb$lookup[68]) ?
	       4'd5 :
	       IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5__ETC___d440 ;

  // inlined wires
  assign dw_valid$whas =
	     (WILL_FIRE_RL_rl_io_read_rsp ||
	      WILL_FIRE_RL_rl_io_AMO_read_rsp) &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d504 ||
	     WILL_FIRE_RL_rl_drive_exception_rsp ||
	     WILL_FIRE_RL_rl_maintain_io_read_rsp ||
	     WILL_FIRE_RL_rl_ST_AMO_response ;
  assign ctr_wr_rsps_pending_crg$port0__write_1 =
	     ctr_wr_rsps_pending_crg + 4'd1 ;
  assign ctr_wr_rsps_pending_crg$port1__write_1 = b__h28572 - 4'd1 ;
  assign ctr_wr_rsps_pending_crg$port2__read =
	     CAN_FIRE_RL_rl_discard_write_rsp ?
	       ctr_wr_rsps_pending_crg$port1__write_1 :
	       b__h28572 ;
  assign ctr_wr_rsps_pending_crg$EN_port2__write =
	     WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;
  assign ctr_wr_rsps_pending_crg$port3__read =
	     ctr_wr_rsps_pending_crg$EN_port2__write ?
	       4'd0 :
	       ctr_wr_rsps_pending_crg$port2__read ;

  // register cfg_verbosity
  assign cfg_verbosity$D_IN = set_verbosity_verbosity ;
  assign cfg_verbosity$EN = EN_set_verbosity ;

  // register ctr_wr_rsps_pending_crg
  assign ctr_wr_rsps_pending_crg$D_IN = ctr_wr_rsps_pending_crg$port3__read ;
  assign ctr_wr_rsps_pending_crg$EN = 1'b1 ;

  // register rg_addr
  assign rg_addr$D_IN = req_addr ;
  assign rg_addr$EN = EN_req ;

  // register rg_amo_funct7
  assign rg_amo_funct7$D_IN = req_amo_funct7 ;
  assign rg_amo_funct7$EN = EN_req ;

  // register rg_cset_cword_in_cache
  assign rg_cset_cword_in_cache$D_IN =
	     MUX_ram_cword_set$b_put_1__SEL_2 ?
	       MUX_ram_cword_set$b_put_2__VAL_2 :
	       MUX_ram_cword_set$b_put_2__VAL_4 ;
  assign rg_cset_cword_in_cache$EN =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     rg_cset_cword_in_cache[2:0] != 3'd7 ||
	     WILL_FIRE_RL_rl_start_cache_refill ;

  // register rg_cset_in_cache
  assign rg_cset_in_cache$D_IN =
	     WILL_FIRE_RL_rl_reset ?
	       MUX_rg_cset_in_cache$write_1__VAL_1 :
	       6'd0 ;
  assign rg_cset_in_cache$EN =
	     WILL_FIRE_RL_rl_reset || WILL_FIRE_RL_rl_start_reset ;

  // register rg_ddr4_ready
  assign rg_ddr4_ready$D_IN = 1'd1 ;
  assign rg_ddr4_ready$EN = EN_ma_ddr4_ready ;

  // register rg_error_during_refill
  assign rg_error_during_refill$D_IN =
	     MUX_rg_error_during_refill$write_1__SEL_1 ;
  assign rg_error_during_refill$EN =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	     WILL_FIRE_RL_rl_start_cache_refill ;

  // register rg_exc_code
  always@(MUX_rg_exc_code$write_1__SEL_1 or
	  MUX_rg_exc_code$write_1__VAL_1 or
	  MUX_rg_exc_code$write_1__SEL_2 or
	  MUX_rg_exc_code$write_1__SEL_3 or
	  MUX_rg_error_during_refill$write_1__SEL_1 or
	  access_exc_code__h2760 or
	  MUX_rg_exc_code$write_1__SEL_5 or
	  MUX_rg_exc_code$write_1__VAL_5 or
	  MUX_rg_exc_code$write_1__SEL_6 or
	  MUX_rg_exc_code$write_1__SEL_7 or x1_avValue_exc_code__h6221)
  case (1'b1)
    MUX_rg_exc_code$write_1__SEL_1:
	rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_1;
    MUX_rg_exc_code$write_1__SEL_2: rg_exc_code$D_IN = 4'd7;
    MUX_rg_exc_code$write_1__SEL_3: rg_exc_code$D_IN = 4'd5;
    MUX_rg_error_during_refill$write_1__SEL_1:
	rg_exc_code$D_IN = access_exc_code__h2760;
    MUX_rg_exc_code$write_1__SEL_5:
	rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_5;
    MUX_rg_exc_code$write_1__SEL_6:
	rg_exc_code$D_IN = MUX_rg_exc_code$write_1__VAL_5;
    MUX_rg_exc_code$write_1__SEL_7:
	rg_exc_code$D_IN = x1_avValue_exc_code__h6221;
    default: rg_exc_code$D_IN = 4'b1010 /* unspecified value */ ;
  endcase
  assign rg_exc_code$EN =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d157 ||
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	     WILL_FIRE_RL_rl_io_read_rsp &&
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	     WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	     EN_req &&
	     NOT_req_f3_BITS_1_TO_0_393_EQ_0b0_394_395_AND__ETC___d1414 ||
	     WILL_FIRE_RL_rl_ptw_level_1 &&
	     NOT_IF_rg_pte_pa_40_BIT_2_41_THEN_master_xacto_ETC___d968 ||
	     WILL_FIRE_RL_rl_ptw_level_0 &&
	     (!_theResult____h28937[0] ||
	      !_theResult____h28937[1] && _theResult____h28937[2] ||
	      !_theResult____h28937[3] && !_theResult____h28937[1] ||
	      master_xactor_f_rd_data$D_OUT[2:1] != 2'b0) ;

  // register rg_f3
  assign rg_f3$D_IN = req_f3 ;
  assign rg_f3$EN = EN_req ;

  // register rg_ld_val
  always@(MUX_dw_output_ld_val$wset_1__SEL_2 or
	  new_ld_val__h36813 or
	  MUX_rg_ld_val$write_1__SEL_2 or
	  MUX_rg_ld_val$write_1__VAL_2 or
	  WILL_FIRE_RL_rl_io_read_rsp or
	  ld_val__h34607 or WILL_FIRE_RL_rl_io_AMO_SC_req)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_dw_output_ld_val$wset_1__SEL_2: rg_ld_val$D_IN = new_ld_val__h36813;
      MUX_rg_ld_val$write_1__SEL_2:
	  rg_ld_val$D_IN = MUX_rg_ld_val$write_1__VAL_2;
      WILL_FIRE_RL_rl_io_read_rsp: rg_ld_val$D_IN = ld_val__h34607;
      WILL_FIRE_RL_rl_io_AMO_SC_req: rg_ld_val$D_IN = 64'd1;
      default: rg_ld_val$D_IN = 64'hAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign rg_ld_val$EN =
	     WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d706 ||
	     WILL_FIRE_RL_rl_io_read_rsp ||
	     WILL_FIRE_RL_rl_io_AMO_SC_req ;

  // register rg_lower_word32
  assign rg_lower_word32$D_IN = 32'h0 ;
  assign rg_lower_word32$EN = 1'b0 ;

  // register rg_lower_word32_full
  assign rg_lower_word32_full$D_IN = 1'd0 ;
  assign rg_lower_word32_full$EN =
	     WILL_FIRE_RL_rl_start_cache_refill ||
	     WILL_FIRE_RL_rl_start_reset ;

  // register rg_lrsc_pa
  assign rg_lrsc_pa$D_IN = x1_avValue_pa__h6220 ;
  assign rg_lrsc_pa$EN =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$lookup[68]) &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d678 ;

  // register rg_lrsc_valid
  assign rg_lrsc_valid$D_IN =
	     MUX_rg_lrsc_valid$write_1__SEL_2 &&
	     rg_op_17_EQ_0_18_OR_rg_op_17_EQ_2_20_AND_rg_am_ETC___d498 ;
  assign rg_lrsc_valid$EN =
	     WILL_FIRE_RL_rl_io_read_req && rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00010 ||
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d497 ||
	     WILL_FIRE_RL_rl_start_reset ;

  // register rg_mstatus_MXR
  assign rg_mstatus_MXR$D_IN = req_mstatus_MXR ;
  assign rg_mstatus_MXR$EN = EN_req ;

  // register rg_op
  assign rg_op$D_IN = req_op ;
  assign rg_op$EN = EN_req ;

  // register rg_pa
  assign rg_pa$D_IN =
	     EN_req ? MUX_rg_pa$write_1__VAL_1 : x1_avValue_pa__h6220 ;
  assign rg_pa$EN =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d460 ||
	     EN_req ;

  // register rg_priv
  assign rg_priv$D_IN = req_priv ;
  assign rg_priv$EN = EN_req ;

  // register rg_pte_pa
  assign rg_pte_pa$D_IN =
	     MUX_master_xactor_f_rd_addr$enq_1__SEL_1 ?
	       lev_0_pte_pa__h29583 :
	       lev_1_pte_pa__h28671 ;
  assign rg_pte_pa$EN =
	     WILL_FIRE_RL_rl_ptw_level_1 &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     _theResult____h28937[0] &&
	     !_theResult____h28937[2] &&
	     !_theResult____h28937[3] &&
	     !_theResult____h28937[1] ||
	     WILL_FIRE_RL_rl_start_tlb_refill ;

  // register rg_satp
  assign rg_satp$D_IN = req_satp ;
  assign rg_satp$EN = EN_req ;

  // register rg_sstatus_SUM
  assign rg_sstatus_SUM$D_IN = req_sstatus_SUM ;
  assign rg_sstatus_SUM$EN = EN_req ;

  // register rg_st_amo_val
  assign rg_st_amo_val$D_IN = EN_req ? req_st_value : new_st_val__h25327 ;
  assign rg_st_amo_val$EN =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d920 ||
	     EN_req ;

  // register rg_state
  always@(EN_tlb_flush or
	  EN_req or
	  MUX_rg_state$write_1__VAL_2 or
	  WILL_FIRE_RL_rl_start_reset or
	  WILL_FIRE_RL_rl_io_AMO_read_rsp or
	  MUX_rg_state$write_1__VAL_4 or
	  WILL_FIRE_RL_rl_io_AMO_op_req or
	  WILL_FIRE_RL_rl_io_AMO_SC_req or
	  WILL_FIRE_RL_rl_io_write_req or
	  WILL_FIRE_RL_rl_io_read_rsp or
	  WILL_FIRE_RL_rl_io_read_req or
	  WILL_FIRE_RL_rl_rereq or
	  MUX_rg_state$write_1__SEL_11 or
	  MUX_rg_state$write_1__VAL_11 or
	  WILL_FIRE_RL_rl_start_cache_refill or
	  WILL_FIRE_RL_rl_ptw_level_0 or
	  MUX_rg_state$write_1__VAL_13 or
	  WILL_FIRE_RL_rl_ptw_level_1 or
	  MUX_rg_state$write_1__VAL_14 or
	  WILL_FIRE_RL_rl_start_tlb_refill or
	  MUX_rg_state$write_1__SEL_16 or
	  MUX_rg_state$write_1__VAL_16 or MUX_rg_state$write_1__SEL_17)
  case (1'b1)
    EN_tlb_flush: rg_state$D_IN = 4'd2;
    EN_req: rg_state$D_IN = MUX_rg_state$write_1__VAL_2;
    WILL_FIRE_RL_rl_start_reset: rg_state$D_IN = 4'd1;
    WILL_FIRE_RL_rl_io_AMO_read_rsp:
	rg_state$D_IN = MUX_rg_state$write_1__VAL_4;
    WILL_FIRE_RL_rl_io_AMO_op_req: rg_state$D_IN = 4'd15;
    WILL_FIRE_RL_rl_io_AMO_SC_req || WILL_FIRE_RL_rl_io_write_req:
	rg_state$D_IN = 4'd11;
    WILL_FIRE_RL_rl_io_read_rsp: rg_state$D_IN = MUX_rg_state$write_1__VAL_4;
    WILL_FIRE_RL_rl_io_read_req: rg_state$D_IN = 4'd13;
    WILL_FIRE_RL_rl_rereq: rg_state$D_IN = 4'd3;
    MUX_rg_state$write_1__SEL_11:
	rg_state$D_IN = MUX_rg_state$write_1__VAL_11;
    WILL_FIRE_RL_rl_start_cache_refill: rg_state$D_IN = 4'd9;
    WILL_FIRE_RL_rl_ptw_level_0: rg_state$D_IN = MUX_rg_state$write_1__VAL_13;
    WILL_FIRE_RL_rl_ptw_level_1: rg_state$D_IN = MUX_rg_state$write_1__VAL_14;
    WILL_FIRE_RL_rl_start_tlb_refill: rg_state$D_IN = 4'd6;
    MUX_rg_state$write_1__SEL_16:
	rg_state$D_IN = MUX_rg_state$write_1__VAL_16;
    MUX_rg_state$write_1__SEL_17: rg_state$D_IN = 4'd2;
    default: rg_state$D_IN = 4'b1010 /* unspecified value */ ;
  endcase
  assign rg_state$EN =
	     WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ||
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     rg_cset_cword_in_cache[2:0] == 3'd7 ||
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d435 ||
	     WILL_FIRE_RL_rl_io_read_rsp ||
	     WILL_FIRE_RL_rl_io_AMO_read_rsp ||
	     WILL_FIRE_RL_rl_ptw_level_1 ||
	     WILL_FIRE_RL_rl_ptw_level_0 ||
	     EN_req ||
	     WILL_FIRE_RL_rl_start_reset ||
	     EN_tlb_flush ||
	     WILL_FIRE_RL_rl_rereq ||
	     WILL_FIRE_RL_rl_start_tlb_refill ||
	     WILL_FIRE_RL_rl_start_cache_refill ||
	     WILL_FIRE_RL_rl_io_AMO_SC_req ||
	     WILL_FIRE_RL_rl_io_write_req ||
	     WILL_FIRE_RL_rl_io_read_req ||
	     WILL_FIRE_RL_rl_io_AMO_op_req ;

  // register rg_tohost_addr
  assign rg_tohost_addr$D_IN = set_watch_tohost_tohost_addr ;
  assign rg_tohost_addr$EN = EN_set_watch_tohost ;

  // register rg_tohost_value
  assign rg_tohost_value$D_IN = rg_st_amo_val ;
  assign rg_tohost_value$EN =
	     WILL_FIRE_RL_rl_ST_AMO_response && rg_watch_tohost &&
	     fabric_addr__h36270 == rg_tohost_addr &&
	     rg_st_amo_val != 64'd0 ;

  // register rg_victim_way
  assign rg_victim_way$D_IN = tmp__h30959[0] ;
  assign rg_victim_way$EN = WILL_FIRE_RL_rl_start_cache_refill ;

  // register rg_watch_tohost
  assign rg_watch_tohost$D_IN = set_watch_tohost_watch_tohost ;
  assign rg_watch_tohost$EN = EN_set_watch_tohost ;

  // register rg_wr_rsp_err
  assign rg_wr_rsp_err$D_IN = 1'd1 ;
  assign rg_wr_rsp_err$EN =
	     WILL_FIRE_RL_rl_discard_write_rsp &&
	     master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0 ;

  // submodule f_fabric_write_reqs
  always@(MUX_dw_output_ld_val$wset_1__SEL_2 or
	  MUX_f_fabric_write_reqs$enq_1__VAL_1 or
	  MUX_f_fabric_write_reqs$enq_1__SEL_2 or
	  MUX_f_fabric_write_reqs$enq_1__VAL_2 or
	  WILL_FIRE_RL_rl_writeback_updated_PTE or
	  MUX_f_fabric_write_reqs$enq_1__VAL_3 or
	  WILL_FIRE_RL_rl_io_write_req or
	  MUX_f_fabric_write_reqs$enq_1__VAL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_dw_output_ld_val$wset_1__SEL_2:
	  f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_1;
      MUX_f_fabric_write_reqs$enq_1__SEL_2:
	  f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_2;
      WILL_FIRE_RL_rl_writeback_updated_PTE:
	  f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_3;
      WILL_FIRE_RL_rl_io_write_req:
	  f_fabric_write_reqs$D_IN = MUX_f_fabric_write_reqs$enq_1__VAL_4;
      default: f_fabric_write_reqs$D_IN =
		   101'h0AAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign f_fabric_write_reqs$ENQ =
	     WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d850 ||
	     WILL_FIRE_RL_rl_writeback_updated_PTE ||
	     WILL_FIRE_RL_rl_io_write_req ;
  assign f_fabric_write_reqs$DEQ = CAN_FIRE_RL_rl_fabric_send_write_req ;
  assign f_fabric_write_reqs$CLR = 1'b0 ;

  // submodule f_pte_writebacks
  assign f_pte_writebacks$D_IN = { tlb$lookup[33:0], x1_avValue_pte__h6223 } ;
  assign f_pte_writebacks$ENQ = MUX_tlb$insert_1__SEL_1 ;
  assign f_pte_writebacks$DEQ = WILL_FIRE_RL_rl_writeback_updated_PTE ;
  assign f_pte_writebacks$CLR = 1'b0 ;

  // submodule f_reset_reqs
  assign f_reset_reqs$D_IN = !EN_server_reset_request_put ;
  assign f_reset_reqs$ENQ =
	     EN_server_reset_request_put || EN_server_flush_request_put ;
  assign f_reset_reqs$DEQ =
	     WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ;
  assign f_reset_reqs$CLR = 1'b0 ;

  // submodule f_reset_rsps
  assign f_reset_rsps$D_IN = f_reset_reqs$D_OUT ;
  assign f_reset_rsps$ENQ =
	     WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 ;
  assign f_reset_rsps$DEQ =
	     EN_server_flush_response_get || EN_server_reset_response_get ;
  assign f_reset_rsps$CLR = 1'b0 ;

  // submodule master_xactor_f_rd_addr
  always@(MUX_master_xactor_f_rd_addr$enq_1__SEL_1 or
	  MUX_master_xactor_f_rd_addr$enq_1__VAL_1 or
	  MUX_master_xactor_f_rd_addr$enq_1__SEL_2 or
	  MUX_master_xactor_f_rd_addr$enq_1__VAL_2 or
	  WILL_FIRE_RL_rl_start_tlb_refill or
	  MUX_master_xactor_f_rd_addr$enq_1__VAL_3 or
	  WILL_FIRE_RL_rl_start_cache_refill or
	  MUX_master_xactor_f_rd_addr$enq_1__VAL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_master_xactor_f_rd_addr$enq_1__SEL_1:
	  master_xactor_f_rd_addr$D_IN =
	      MUX_master_xactor_f_rd_addr$enq_1__VAL_1;
      MUX_master_xactor_f_rd_addr$enq_1__SEL_2:
	  master_xactor_f_rd_addr$D_IN =
	      MUX_master_xactor_f_rd_addr$enq_1__VAL_2;
      WILL_FIRE_RL_rl_start_tlb_refill:
	  master_xactor_f_rd_addr$D_IN =
	      MUX_master_xactor_f_rd_addr$enq_1__VAL_3;
      WILL_FIRE_RL_rl_start_cache_refill:
	  master_xactor_f_rd_addr$D_IN =
	      MUX_master_xactor_f_rd_addr$enq_1__VAL_4;
      default: master_xactor_f_rd_addr$D_IN =
		   97'h0AAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign master_xactor_f_rd_addr$ENQ =
	     WILL_FIRE_RL_rl_ptw_level_1 &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     _theResult____h28937[0] &&
	     !_theResult____h28937[2] &&
	     !_theResult____h28937[3] &&
	     !_theResult____h28937[1] ||
	     WILL_FIRE_RL_rl_io_AMO_op_req ||
	     WILL_FIRE_RL_rl_io_read_req ||
	     WILL_FIRE_RL_rl_start_tlb_refill ||
	     WILL_FIRE_RL_rl_start_cache_refill ;
  assign master_xactor_f_rd_addr$DEQ =
	     master_xactor_f_rd_addr$EMPTY_N && mem_master_arready ;
  assign master_xactor_f_rd_addr$CLR =
	     WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;

  // submodule master_xactor_f_rd_data
  assign master_xactor_f_rd_data$D_IN =
	     { mem_master_rid,
	       mem_master_rdata,
	       mem_master_rresp,
	       mem_master_rlast } ;
  assign master_xactor_f_rd_data$ENQ =
	     mem_master_rvalid && master_xactor_f_rd_data$FULL_N ;
  assign master_xactor_f_rd_data$DEQ =
	     WILL_FIRE_RL_rl_io_read_rsp ||
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop ||
	     WILL_FIRE_RL_rl_ptw_level_0 ||
	     WILL_FIRE_RL_rl_ptw_level_1 ||
	     WILL_FIRE_RL_rl_io_AMO_read_rsp ;
  assign master_xactor_f_rd_data$CLR =
	     WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;

  // submodule master_xactor_f_wr_addr
  assign master_xactor_f_wr_addr$D_IN =
	     { 4'd0,
	       mem_req_wr_addr_awaddr__h2978,
	       8'd0,
	       x__h3025,
	       18'd65536 } ;
  assign master_xactor_f_wr_addr$ENQ = CAN_FIRE_RL_rl_fabric_send_write_req ;
  assign master_xactor_f_wr_addr$DEQ =
	     master_xactor_f_wr_addr$EMPTY_N && mem_master_awready ;
  assign master_xactor_f_wr_addr$CLR =
	     WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;

  // submodule master_xactor_f_wr_data
  assign master_xactor_f_wr_data$D_IN =
	     { mem_req_wr_data_wdata__h3204,
	       mem_req_wr_data_wstrb__h3205,
	       1'd1 } ;
  assign master_xactor_f_wr_data$ENQ = CAN_FIRE_RL_rl_fabric_send_write_req ;
  assign master_xactor_f_wr_data$DEQ =
	     master_xactor_f_wr_data$EMPTY_N && mem_master_wready ;
  assign master_xactor_f_wr_data$CLR =
	     WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;

  // submodule master_xactor_f_wr_resp
  assign master_xactor_f_wr_resp$D_IN = { mem_master_bid, mem_master_bresp } ;
  assign master_xactor_f_wr_resp$ENQ =
	     mem_master_bvalid && master_xactor_f_wr_resp$FULL_N ;
  assign master_xactor_f_wr_resp$DEQ = CAN_FIRE_RL_rl_discard_write_rsp ;
  assign master_xactor_f_wr_resp$CLR =
	     WILL_FIRE_RL_rl_start_reset && !f_reset_reqs$D_OUT ;

  // submodule ram_cword_set
  assign ram_cword_set$ADDRA =
	     MUX_ram_cword_set$a_put_1__SEL_1 ?
	       rg_cset_cword_in_cache :
	       rg_addr[11:3] ;
  always@(MUX_ram_cword_set$b_put_1__SEL_1 or
	  req_addr or
	  MUX_ram_cword_set$b_put_1__SEL_2 or
	  MUX_ram_cword_set$b_put_2__VAL_2 or
	  WILL_FIRE_RL_rl_rereq or
	  rg_addr or
	  WILL_FIRE_RL_rl_start_cache_refill or
	  MUX_ram_cword_set$b_put_2__VAL_4)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_ram_cword_set$b_put_1__SEL_1: ram_cword_set$ADDRB = req_addr[11:3];
      MUX_ram_cword_set$b_put_1__SEL_2:
	  ram_cword_set$ADDRB = MUX_ram_cword_set$b_put_2__VAL_2;
      WILL_FIRE_RL_rl_rereq: ram_cword_set$ADDRB = rg_addr[11:3];
      WILL_FIRE_RL_rl_start_cache_refill:
	  ram_cword_set$ADDRB = MUX_ram_cword_set$b_put_2__VAL_4;
      default: ram_cword_set$ADDRB = 9'b010101010 /* unspecified value */ ;
    endcase
  end
  assign ram_cword_set$DIA =
	     MUX_ram_cword_set$a_put_1__SEL_1 ?
	       MUX_ram_cword_set$a_put_3__VAL_1 :
	       MUX_ram_cword_set$a_put_3__VAL_2 ;
  always@(MUX_ram_cword_set$b_put_1__SEL_1 or
	  MUX_ram_cword_set$b_put_1__SEL_2 or
	  WILL_FIRE_RL_rl_rereq or WILL_FIRE_RL_rl_start_cache_refill)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_ram_cword_set$b_put_1__SEL_1:
	  ram_cword_set$DIB =
	      128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
      MUX_ram_cword_set$b_put_1__SEL_2:
	  ram_cword_set$DIB =
	      128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
      WILL_FIRE_RL_rl_rereq:
	  ram_cword_set$DIB =
	      128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
      WILL_FIRE_RL_rl_start_cache_refill:
	  ram_cword_set$DIB =
	      128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
      default: ram_cword_set$DIB =
		   128'hAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign ram_cword_set$WEA = 1'd1 ;
  assign ram_cword_set$WEB = 1'd0 ;
  assign ram_cword_set$ENA =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d719 ;
  assign ram_cword_set$ENB =
	     EN_req &&
	     req_f3_BITS_1_TO_0_393_EQ_0b0_394_OR_req_f3_BI_ETC___d1423 ||
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     rg_cset_cword_in_cache[2:0] != 3'd7 ||
	     WILL_FIRE_RL_rl_rereq ||
	     WILL_FIRE_RL_rl_start_cache_refill ;

  // submodule ram_state_and_ctag_cset
  assign ram_state_and_ctag_cset$ADDRA =
	     MUX_ram_state_and_ctag_cset$a_put_1__SEL_1 ?
	       rg_addr[11:6] :
	       rg_cset_in_cache ;
  assign ram_state_and_ctag_cset$ADDRB =
	     MUX_ram_cword_set$b_put_1__SEL_1 ?
	       req_addr[11:6] :
	       rg_addr[11:6] ;
  assign ram_state_and_ctag_cset$DIA =
	     MUX_ram_state_and_ctag_cset$a_put_1__SEL_1 ?
	       MUX_ram_state_and_ctag_cset$a_put_3__VAL_1 :
	       46'h1555552AAAAA ;
  assign ram_state_and_ctag_cset$DIB =
	     MUX_ram_cword_set$b_put_1__SEL_1 ?
	       46'h2AAAAAAAAAAA /* unspecified value */  :
	       46'h2AAAAAAAAAAA /* unspecified value */  ;
  assign ram_state_and_ctag_cset$WEA = 1'd1 ;
  assign ram_state_and_ctag_cset$WEB = 1'd0 ;
  assign ram_state_and_ctag_cset$ENA =
	     WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	     rg_cset_cword_in_cache[2:0] == 3'd0 &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 ||
	     WILL_FIRE_RL_rl_reset ;
  assign ram_state_and_ctag_cset$ENB =
	     EN_req &&
	     req_f3_BITS_1_TO_0_393_EQ_0b0_394_OR_req_f3_BI_ETC___d1423 ||
	     WILL_FIRE_RL_rl_rereq ;

  // submodule soc_map
  assign soc_map$m_is_IO_addr_addr = 64'h0 ;
  assign soc_map$m_is_mem_addr_addr = { 30'd0, x1_avValue_pa__h6220 } ;
  assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;

  // submodule tlb
  assign tlb$insert_asid = rg_satp[30:22] ;
  always@(MUX_tlb$insert_1__SEL_1 or
	  tlb$lookup or MUX_tlb$insert_1__SEL_2 or MUX_tlb$insert_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_tlb$insert_1__SEL_1: tlb$insert_level = tlb$lookup[35:34];
      MUX_tlb$insert_1__SEL_2: tlb$insert_level = 2'd1;
      MUX_tlb$insert_1__SEL_3: tlb$insert_level = 2'd0;
      default: tlb$insert_level = 2'b10 /* unspecified value */ ;
    endcase
  end
  always@(MUX_tlb$insert_1__SEL_1 or
	  x1_avValue_pte__h6223 or
	  MUX_tlb$insert_1__SEL_2 or
	  _theResult____h28937 or MUX_tlb$insert_1__SEL_3)
  begin
    case (1'b1) // synopsys parallel_case
      MUX_tlb$insert_1__SEL_1: tlb$insert_pte = x1_avValue_pte__h6223;
      MUX_tlb$insert_1__SEL_2: tlb$insert_pte = _theResult____h28937;
      MUX_tlb$insert_1__SEL_3: tlb$insert_pte = _theResult____h28937;
      default: tlb$insert_pte = 32'hAAAAAAAA /* unspecified value */ ;
    endcase
  end
  assign tlb$insert_pte_pa =
	     MUX_tlb$insert_1__SEL_1 ? tlb$lookup[33:0] : rg_pte_pa ;
  assign tlb$insert_vpn = rg_addr[31:12] ;
  assign tlb$lookup_asid = rg_satp[30:22] ;
  assign tlb$lookup_vpn = rg_addr[31:12] ;
  assign tlb$EN_flush = WILL_FIRE_RL_rl_start_reset || EN_tlb_flush ;
  assign tlb$EN_insert =
	     WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	     rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d417 ||
	     WILL_FIRE_RL_rl_ptw_level_1 &&
	     master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d1000 ||
	     WILL_FIRE_RL_rl_ptw_level_0 &&
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     _theResult____h28937[0] &&
	     (_theResult____h28937[1] || !_theResult____h28937[2]) &&
	     (_theResult____h28937[3] || _theResult____h28937[1]) ;

  // remaining internal signals
  assign IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d332 =
	     (x1_avValue_pa__h6220[2:0] == 3'h0) ?
	       CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_15_ETC__q29 :
	       NOT_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_3_ETC___d331 ;
  assign IF_NOT_ram_state_and_ctag_cset_b_read__98_BIT__ETC___d436 =
	     ((!ram_state_and_ctag_cset$DOB[22] ||
	       !ram_state_and_ctag_cset_b_read__98_BITS_21_TO__ETC___d203) &&
	      (!ram_state_and_ctag_cset$DOB[45] ||
	       !ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209)) ?
	       4'd8 :
	       4'd11 ;
  assign IF_NOT_ram_state_and_ctag_cset_b_read__98_BIT__ETC___d774 =
	     (!ram_state_and_ctag_cset$DOB[45] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209) ?
	       n__h22557 :
	       ram_cword_set$DOB[63:0] ;
  assign IF_NOT_ram_state_and_ctag_cset_b_read__98_BIT__ETC___d842 =
	     (!ram_state_and_ctag_cset$DOB[45] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209) ?
	       n__h25491 :
	       ram_cword_set$DOB[63:0] ;
  assign IF_ram_state_and_ctag_cset_b_read__98_BIT_45_0_ETC___d773 =
	     (ram_state_and_ctag_cset$DOB[45] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209) ?
	       n__h22557 :
	       ram_cword_set$DOB[127:64] ;
  assign IF_ram_state_and_ctag_cset_b_read__98_BIT_45_0_ETC___d841 =
	     (ram_state_and_ctag_cset$DOB[45] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209) ?
	       n__h25491 :
	       ram_cword_set$DOB[127:64] ;
  assign IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_1__ETC___d657 =
	     (rg_addr[2:0] == 3'h0) ? 64'd1 : 64'd0 ;
  assign IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_IF_ETC___d1307 =
	     (rg_addr[2:0] == 3'h0) ? ld_val__h34607 : 64'd0 ;
  assign IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_NO_ETC___d253 =
	     (rg_addr[2:0] == 3'h0) ?
	       NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d233 &&
	       NOT_ram_state_and_ctag_cset_b_read__98_BIT_45__ETC___d234 :
	       rg_addr[2:0] != 3'h4 ||
	       NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d233 &&
	       NOT_ram_state_and_ctag_cset_b_read__98_BIT_45__ETC___d234 ;
  assign IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_ra_ETC___d642 =
	     (rg_addr[2:0] == 3'h0) ? word64__h7644 : 64'd0 ;
  assign IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_01_BITS__ETC__q32 =
	     IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_01_BITS__ETC___d649[31:0] ;
  assign IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_rg_st_amo_val_ETC___d779 =
	     (rg_f3 == 3'b010) ?
	       { {32{rg_st_amo_val_BITS_31_TO_0__q33[31]}},
		 rg_st_amo_val_BITS_31_TO_0__q33 } :
	       rg_st_amo_val ;
  assign IF_rg_op_17_EQ_0_18_OR_rg_op_17_EQ_2_20_AND_rg_ETC___d346 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
	       NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d263 :
	       IF_rg_op_17_EQ_1_64_OR_rg_op_17_EQ_2_20_AND_rg_ETC___d345 ;
  assign IF_rg_op_17_EQ_0_18_OR_rg_op_17_EQ_2_20_AND_rg_ETC___d438 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
	       4'd8 :
	       IF_rg_op_17_EQ_1_64_OR_rg_op_17_EQ_2_20_AND_rg_ETC___d437 ;
  assign IF_rg_op_17_EQ_1_64_OR_rg_op_17_EQ_2_20_AND_rg_ETC___d345 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
	       rg_op_17_EQ_2_20_AND_rg_amo_funct7_22_BITS_6_T_ETC___d285 :
	       NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d344 ;
  assign IF_rg_op_17_EQ_1_64_OR_rg_op_17_EQ_2_20_AND_rg_ETC___d437 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
	       4'd11 :
	       IF_NOT_ram_state_and_ctag_cset_b_read__98_BIT__ETC___d436 ;
  assign IF_rg_op_17_EQ_1_64_OR_rg_op_17_EQ_2_20_AND_rg_ETC___d851 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
	       rg_st_amo_val :
	       new_st_val__h25327 ;
  assign IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5__ETC___d440 =
	     rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d157 ?
	       4'd4 :
	       ((dmem_not_imem && !soc_map$m_is_mem_addr) ?
		  4'd12 :
		  IF_rg_op_17_EQ_0_18_OR_rg_op_17_EQ_2_20_AND_rg_ETC___d438) ;
  assign IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5__ETC___d480 =
	     x1_avValue_pa__h6220 == rg_lrsc_pa ;
  assign NOT_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_3_ETC___d321 =
	     x1_avValue_pa__h6220[2:0] != 3'h7 ||
	     CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_15_ETC__q29 ;
  assign NOT_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_3_ETC___d327 =
	     x1_avValue_pa__h6220[2:0] != 3'h6 ||
	     CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_15_ETC__q29 ;
  assign NOT_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_3_ETC___d331 =
	     x1_avValue_pa__h6220[2:0] != 3'h4 ||
	     CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_15_ETC__q29 ;
  assign NOT_IF_rg_pte_pa_40_BIT_2_41_THEN_master_xacto_ETC___d968 =
	     !_theResult____h28937[0] ||
	     !_theResult____h28937[1] && _theResult____h28937[2] ||
	     (_theResult____h28937[3] || _theResult____h28937[1]) &&
	     _theResult____h28937[19:10] != 10'd0 ||
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ;
  assign NOT_cfg_verbosity_read__2_ULE_2_058___d1059 = cfg_verbosity > 4'd2 ;
  assign NOT_cfg_verbosity_read__2_ULT_2_44___d445 = cfg_verbosity >= 4'd2 ;
  assign NOT_dmem_not_imem_32_AND_rg_op_17_EQ_0_18_OR_r_ETC___d380 =
	     !dmem_not_imem &&
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     tlb$lookup[39] ;
  assign NOT_dmem_not_imem_32_OR_NOT_rg_op_17_EQ_0_18_1_ETC___d139 =
	     !dmem_not_imem ||
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ||
	     !tlb_lookup_rg_satp_4_BITS_30_TO_22_00_rg_addr__ETC___d137 ;
  assign NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d474 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     ram_state_and_ctag_cset$DOB[22] &&
	     ram_state_and_ctag_cset_b_read__98_BITS_21_TO__ETC___d203 &&
	     ram_state_and_ctag_cset$DOB[45] &&
	     ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209 ;
  assign NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d670 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     ram_state_and_ctag_cset_b_read__98_BIT_22_99_A_ETC___d668 ;
  assign NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d682 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00010 &&
	     ram_state_and_ctag_cset_b_read__98_BIT_22_99_A_ETC___d668 ;
  assign NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d687 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d685 ;
  assign NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d695 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00010 &&
	     NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d692 ;
  assign NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d704 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     (rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 ||
	      NOT_rg_op_17_EQ_1_64_88_AND_ram_state_and_ctag_ETC___d701) ;
  assign NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d717 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     rg_op_17_EQ_1_64_OR_rg_op_17_EQ_2_20_AND_rg_am_ETC___d715 ;
  assign NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d854 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd1 &&
	     IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5__ETC___d480 &&
	     !cfg_verbosity_read__2_ULE_1___d43 ;
  assign NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d872 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00011 &&
	     !cfg_verbosity_read__2_ULE_1___d43 ;
  assign NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d918 =
	     (!dmem_not_imem || soc_map$m_is_mem_addr) && rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     NOT_rg_op_17_EQ_1_64_88_AND_NOT_rg_op_17_EQ_2__ETC___d714 ;
  assign NOT_master_xactor_f_rd_data_first__36_BITS_2_T_ETC___d961 =
	     master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	     !_theResult____h28937[0] ||
	     !_theResult____h28937[1] && _theResult____h28937[2] ||
	     ((!_theResult____h28937[3] && !_theResult____h28937[1]) ?
		master_xactor_f_rd_addr$FULL_N :
		_theResult____h28937[19:10] != 10'd0 || tlb$RDY_insert) ;
  assign NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d233 =
	     !ram_state_and_ctag_cset$DOB[22] || !rg_priv_1_ULE_0b1___d92 ||
	     !rg_satp[31] ||
	     tlb$RDY_lookup ;
  assign NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d263 =
	     (!ram_state_and_ctag_cset$DOB[22] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_21_TO__ETC___d203) &&
	     (!ram_state_and_ctag_cset$DOB[45] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209) ||
	     rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 ||
	     IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b100_17__ETC___d261 ;
  assign NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d283 =
	     (!ram_state_and_ctag_cset$DOB[22] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_21_TO__ETC___d203) &&
	     (!ram_state_and_ctag_cset$DOB[45] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209) ||
	     (!ram_state_and_ctag_cset$DOB[45] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209 ||
	      IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b1_40_OR_ETC___d277) &&
	     (ram_state_and_ctag_cset$DOB[45] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209 ||
	      IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b1_40_OR_ETC___d277) ;
  assign NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d344 =
	     (!ram_state_and_ctag_cset$DOB[22] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_21_TO__ETC___d203) &&
	     (!ram_state_and_ctag_cset$DOB[45] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209) ||
	     f_fabric_write_reqs$FULL_N &&
	     rg_amo_funct7_22_BITS_6_TO_2_23_EQ_0b1_86_OR_I_ETC___d342 ;
  assign NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d482 =
	     (!ram_state_and_ctag_cset$DOB[22] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_21_TO__ETC___d203) &&
	     (!ram_state_and_ctag_cset$DOB[45] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209) &&
	     rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00010 &&
	     IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5__ETC___d480 ;
  assign NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d685 =
	     (!ram_state_and_ctag_cset$DOB[22] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_21_TO__ETC___d203) &&
	     (!ram_state_and_ctag_cset$DOB[45] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209) &&
	     !cfg_verbosity_read__2_ULE_1___d43 ;
  assign NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d692 =
	     (!ram_state_and_ctag_cset$DOB[22] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_21_TO__ETC___d203) &&
	     (!ram_state_and_ctag_cset$DOB[45] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209) &&
	     IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5__ETC___d480 &&
	     !cfg_verbosity_read__2_ULE_1___d43 ;
  assign NOT_ram_state_and_ctag_cset_b_read__98_BIT_45__ETC___d234 =
	     !ram_state_and_ctag_cset$DOB[45] || !rg_priv_1_ULE_0b1___d92 ||
	     !rg_satp[31] ||
	     tlb$RDY_lookup ;
  assign NOT_req_f3_BITS_1_TO_0_393_EQ_0b0_394_395_AND__ETC___d1414 =
	     req_f3[1:0] != 2'b0 && (req_f3[1:0] != 2'b01 || req_addr[0]) &&
	     (req_f3[1:0] != 2'b10 || req_addr[1:0] != 2'b0) &&
	     (req_f3[1:0] != 2'b11 || req_addr[2:0] != 3'b0) ;
  assign NOT_rg_op_17_EQ_0_18_19_AND_NOT_rg_op_17_EQ_2__ETC___d431 =
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
	      rg_lrsc_valid &&
	      rg_lrsc_pa_68_EQ_IF_rg_priv_1_ULE_0b1_2_AND_rg_ETC___d269) ;
  assign NOT_rg_op_17_EQ_1_64_88_AND_NOT_rg_op_17_EQ_2__ETC___d714 =
	     rg_op != 2'd1 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
	     (ram_state_and_ctag_cset$DOB[22] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_21_TO__ETC___d203 ||
	      ram_state_and_ctag_cset$DOB[45] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209) ;
  assign NOT_rg_op_17_EQ_1_64_88_AND_ram_state_and_ctag_ETC___d701 =
	     rg_op != 2'd1 &&
	     (ram_state_and_ctag_cset$DOB[22] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_21_TO__ETC___d203 ||
	      ram_state_and_ctag_cset$DOB[45] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209) ;
  assign NOT_rg_op_17_EQ_2_20_21_OR_NOT_rg_amo_funct7_2_ETC___d712 =
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
	      rg_lrsc_valid &&
	      rg_lrsc_pa_68_EQ_IF_rg_priv_1_ULE_0b1_2_AND_rg_ETC___d269) &&
	     (ram_state_and_ctag_cset$DOB[22] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_21_TO__ETC___d203 ||
	      ram_state_and_ctag_cset$DOB[45] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209) ;
  assign NOT_rg_op_17_EQ_2_20_21_OR_NOT_rg_amo_funct7_2_ETC___d875 =
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
	      rg_lrsc_valid &&
	      rg_lrsc_pa_68_EQ_IF_rg_priv_1_ULE_0b1_2_AND_rg_ETC___d269) &&
	     ram_state_and_ctag_cset_b_read__98_BIT_22_99_A_ETC___d668 ;
  assign NOT_rg_op_17_EQ_2_20_21_OR_NOT_rg_amo_funct7_2_ETC___d881 =
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
	      rg_lrsc_valid &&
	      rg_lrsc_pa_68_EQ_IF_rg_priv_1_ULE_0b1_2_AND_rg_ETC___d269) &&
	     NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d685 ;
  assign NOT_rg_op_17_EQ_2_20_21_OR_NOT_rg_amo_funct7_2_ETC___d887 =
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
	      rg_lrsc_valid &&
	      rg_lrsc_pa_68_EQ_IF_rg_priv_1_ULE_0b1_2_AND_rg_ETC___d269) &&
	     !cfg_verbosity_read__2_ULE_1___d43 ;
  assign NOT_rg_priv_1_EQ_0b0_07_73_OR_tlb_lookup_rg_sa_ETC___d387 =
	     (rg_priv != 2'b0 || tlb$lookup[40]) &&
	     (rg_priv != 2'b01 || !tlb$lookup[40] || rg_sstatus_SUM) &&
	     (NOT_dmem_not_imem_32_AND_rg_op_17_EQ_0_18_OR_r_ETC___d380 ||
	      dmem_not_imem_AND_rg_op_17_EQ_0_18_OR_rg_op_17_ETC___d382 ||
	      dmem_not_imem && rg_op != 2'd0 &&
	      (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	      tlb$lookup[38]) ;
  assign NOT_rg_priv_1_EQ_0b0_07_73_OR_tlb_lookup_rg_sa_ETC___d410 =
	     (rg_priv != 2'b0 || tlb$lookup[40]) &&
	     (rg_priv != 2'b01 || !tlb$lookup[40] || rg_sstatus_SUM) &&
	     dmem_not_imem &&
	     tlb$lookup[38] ;
  assign NOT_rg_priv_1_EQ_0b0_07_73_OR_tlb_lookup_rg_sa_ETC___d448 =
	     (rg_priv != 2'b0 || tlb$lookup[40]) &&
	     (rg_priv != 2'b01 || !tlb$lookup[40] || rg_sstatus_SUM) &&
	     tlb$lookup[42] &&
	     !pte___2__h6719[7] &&
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ;
  assign NOT_rg_priv_1_EQ_0b0_07_73_OR_tlb_lookup_rg_sa_ETC___d664 =
	     (rg_priv != 2'b0 || tlb$lookup[40]) &&
	     (rg_priv != 2'b01 || !tlb$lookup[40] || rg_sstatus_SUM) &&
	     (!dmem_not_imem && tlb$lookup[39] ||
	      dmem_not_imem &&
	      tlb_lookup_rg_satp_4_BITS_30_TO_22_00_rg_addr__ETC___d137) ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d173 =
	     !rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || !tlb$lookup[68] ||
	     rg_priv_1_EQ_0b0_07_AND_NOT_tlb_lookup_rg_satp_ETC___d161 ||
	     NOT_tlb_lookup_rg_satp_4_BITS_30_TO_22_00_rg_a_ETC___d170 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d348 =
	     (NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d173 ||
	      tlb$RDY_insert && tlb$RDY_lookup && f_pte_writebacks$FULL_N) &&
	     (dmem_not_imem && !soc_map$m_is_mem_addr ||
	      IF_rg_op_17_EQ_0_18_OR_rg_op_17_EQ_2_20_AND_rg_ETC___d346) ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d392 =
	     !rg_priv_1_ULE_0b1___d92 || !rg_satp[31] ||
	     tlb$lookup[68] &&
	     NOT_rg_priv_1_EQ_0b0_07_73_OR_tlb_lookup_rg_sa_ETC___d387 &&
	     tlb_lookup_rg_satp_4_BITS_30_TO_22_00_rg_addr__ETC___d389 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d407 =
	     !rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || !tlb$lookup[68] ||
	     rg_priv_1_EQ_0b0_07_AND_NOT_tlb_lookup_rg_satp_ETC___d161 ||
	     NOT_tlb_lookup_rg_satp_4_BITS_30_TO_22_00_rg_a_ETC___d170 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d459 =
	     !rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || !tlb$lookup[68] ||
	     NOT_rg_priv_1_EQ_0b0_07_73_OR_tlb_lookup_rg_sa_ETC___d387 &&
	     tlb_lookup_rg_satp_4_BITS_30_TO_22_00_rg_addr__ETC___d389 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d460 =
	     (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$lookup[68]) &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d459 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d467 =
	     !rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || !tlb$lookup[68] ||
	     (rg_priv != 2'b0 || tlb$lookup[40]) &&
	     (rg_priv != 2'b01 || !tlb$lookup[40] || rg_sstatus_SUM) &&
	     rg_op_17_EQ_0_18_OR_rg_op_17_EQ_2_20_AND_rg_am_ETC___d463 &&
	     tlb_lookup_rg_satp_4_BITS_30_TO_22_00_rg_addr__ETC___d389 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d470 =
	     (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$lookup[68]) &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d467 &&
	     dmem_not_imem &&
	     !soc_map$m_is_mem_addr &&
	     !cfg_verbosity_read__2_ULE_1___d43 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d476 =
	     (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$lookup[68]) &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d459 &&
	     NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d474 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d497 =
	     (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$lookup[68]) &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d459 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op_17_EQ_0_18_OR_rg_op_17_EQ_2_20_AND_rg_am_ETC___d494 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d503 =
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d459 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     (rg_op_17_EQ_0_18_OR_rg_op_17_EQ_2_20_AND_rg_am_ETC___d498 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 &&
	      lrsc_result__h21768) ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d504 =
	     (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$lookup[68]) &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d503 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d667 =
	     !rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || !tlb$lookup[68] ||
	     NOT_rg_priv_1_EQ_0b0_07_73_OR_tlb_lookup_rg_sa_ETC___d664 &&
	     tlb$lookup[42] ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d672 =
	     (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$lookup[68]) &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d667 &&
	     NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d670 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d678 =
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d667 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op == 2'd2 &&
	     rg_amo_funct7_22_BITS_6_TO_2_23_EQ_0b10_24_AND_ETC___d675 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d684 =
	     (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$lookup[68]) &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d667 &&
	     NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d682 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d689 =
	     (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$lookup[68]) &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d667 &&
	     NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d687 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d697 =
	     (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$lookup[68]) &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d667 &&
	     NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d695 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d700 =
	     !rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || !tlb$lookup[68] ||
	     NOT_rg_priv_1_EQ_0b0_07_73_OR_tlb_lookup_rg_sa_ETC___d410 &&
	     tlb$lookup[42] &&
	     tlb$lookup[43] ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d706 =
	     (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$lookup[68]) &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d700 &&
	     NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d704 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d719 =
	     (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$lookup[68]) &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d700 &&
	     NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d717 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d849 =
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d700 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     (rg_op_17_EQ_1_64_OR_rg_op_17_EQ_2_20_AND_rg_am_ETC___d845 ||
	      NOT_rg_op_17_EQ_1_64_88_AND_NOT_rg_op_17_EQ_2__ETC___d714) ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d850 =
	     (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$lookup[68]) &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d849 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d856 =
	     (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$lookup[68]) &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d700 &&
	     NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d854 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d862 =
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d700 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00011 &&
	     rg_lrsc_valid &&
	     !rg_lrsc_pa_68_EQ_IF_rg_priv_1_ULE_0b1_2_AND_rg_ETC___d269 &&
	     !cfg_verbosity_read__2_ULE_1___d43 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d868 =
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d700 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00011 &&
	     !rg_lrsc_valid &&
	     !cfg_verbosity_read__2_ULE_1___d43 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d874 =
	     (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$lookup[68]) &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d700 &&
	     NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d872 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d879 =
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d700 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
	     NOT_rg_op_17_EQ_2_20_21_OR_NOT_rg_amo_funct7_2_ETC___d875 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d880 =
	     (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$lookup[68]) &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d879 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d885 =
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d700 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
	     NOT_rg_op_17_EQ_2_20_21_OR_NOT_rg_amo_funct7_2_ETC___d881 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d891 =
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d700 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
	     NOT_rg_op_17_EQ_2_20_21_OR_NOT_rg_amo_funct7_2_ETC___d887 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d892 =
	     (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$lookup[68]) &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d891 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d897 =
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d700 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00011 &&
	     lrsc_result__h21768 &&
	     !cfg_verbosity_read__2_ULE_1___d43 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d898 =
	     (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$lookup[68]) &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d897 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d904 =
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d700 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     rg_op != 2'd1 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
	     NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d685 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d909 =
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d700 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     rg_op != 2'd1 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
	     ram_state_and_ctag_cset_b_read__98_BIT_22_99_A_ETC___d668 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d910 =
	     (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$lookup[68]) &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d909 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d915 =
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d700 &&
	     (!dmem_not_imem || soc_map$m_is_mem_addr) &&
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     rg_op != 2'd1 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
	     ram_state_and_ctag_cset_b_read__98_BIT_22_99_A_ETC___d911 ;
  assign NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d920 =
	     (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$lookup[68]) &&
	     NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d700 &&
	     NOT_dmem_not_imem_32_OR_soc_map_m_is_mem_addr__ETC___d918 ;
  assign NOT_tlb_lookup_rg_satp_4_BITS_30_TO_22_00_rg_a_ETC___d154 =
	     !tlb$lookup[42] ||
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     !tlb$lookup[43] ;
  assign NOT_tlb_lookup_rg_satp_4_BITS_30_TO_22_00_rg_a_ETC___d170 =
	     !tlb$lookup[42] || !tlb$lookup[43] || pte___2__h6719[7] ||
	     rg_op == 2'd0 ||
	     rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 ;
  assign _theResult____h28937 =
	     rg_pte_pa[2] ?
	       master_xactor_f_rd_data$D_OUT[66:35] :
	       master_xactor_f_rd_data$D_OUT[34:3] ;
  assign _theResult___fst__h6308 =
	     tlb$lookup[68] ? _theResult___fst__h6380 : pa__h6208 ;
  assign _theResult___fst__h6380 =
	     (rg_priv_1_EQ_0b0_07_AND_NOT_tlb_lookup_rg_satp_ETC___d148 ||
	      NOT_tlb_lookup_rg_satp_4_BITS_30_TO_22_00_rg_a_ETC___d154) ?
	       pa__h6208 :
	       _theResult___fst__h6721 ;
  assign _theResult___snd_fst__h3212 =
	     f_fabric_write_reqs$D_OUT[63:0] << shift_bits__h2992 ;
  assign _theResult___snd_fst__h6310 =
	     tlb$lookup[68] ?
	       _theResult___snd_fst__h6382 :
	       tlb$lookup[67:36] ;
  assign _theResult___snd_fst__h6382 =
	     (rg_priv_1_EQ_0b0_07_AND_NOT_tlb_lookup_rg_satp_ETC___d148 ||
	      NOT_tlb_lookup_rg_satp_4_BITS_30_TO_22_00_rg_a_ETC___d154) ?
	       tlb$lookup[67:36] :
	       _theResult___snd_fst__h6859 ;
  assign _theResult___snd_fst__h6859 =
	     (!pte___2__h6719[7] && rg_op != 2'd0 &&
	      (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010)) ?
	       pte___1__h6936 :
	       pte___2__h6719 ;
  assign access_exc_code__h2760 =
	     dmem_not_imem ?
	       ((rg_op == 2'd0 ||
		 rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
		  4'd5 :
		  4'd7) :
	       4'd1 ;
  assign b__h28572 =
	     CAN_FIRE_RL_rl_fabric_send_write_req ?
	       ctr_wr_rsps_pending_crg$port0__write_1 :
	       ctr_wr_rsps_pending_crg ;
  assign cfg_verbosity_read__2_ULE_1___d43 = cfg_verbosity <= 4'd1 ;
  assign cline_addr__h30818 = { rg_pa[33:6], 6'd0 } ;
  assign cline_fabric_addr__h30819 = { 30'd0, cline_addr__h30818 } ;
  assign dmem_not_imem_AND_rg_op_17_EQ_0_18_OR_rg_op_17_ETC___d382 =
	     dmem_not_imem &&
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     tlb_lookup_rg_satp_4_BITS_30_TO_22_00_rg_addr__ETC___d137 ;
  assign dmem_not_imem_OR_NOT_rg_op_17_EQ_0_18_19_AND_N_ETC___d131 =
	     dmem_not_imem ||
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ||
	     !tlb$lookup[39] ;
  assign exc_code___1__h6621 = x1_avValue_exc_code__h6221 ;
  assign fabric_addr__h36270 = { 30'd0, rg_pa } ;
  assign ld_val4607_BITS_15_TO_0__q38 = ld_val__h34607[15:0] ;
  assign ld_val4607_BITS_15_TO_8__q40 = ld_val__h34607[15:8] ;
  assign ld_val4607_BITS_23_TO_16__q41 = ld_val__h34607[23:16] ;
  assign ld_val4607_BITS_31_TO_0__q39 = ld_val__h34607[31:0] ;
  assign ld_val4607_BITS_31_TO_16__q42 = ld_val__h34607[31:16] ;
  assign ld_val4607_BITS_31_TO_24__q43 = ld_val__h34607[31:24] ;
  assign ld_val4607_BITS_39_TO_32__q44 = ld_val__h34607[39:32] ;
  assign ld_val4607_BITS_47_TO_32__q45 = ld_val__h34607[47:32] ;
  assign ld_val4607_BITS_47_TO_40__q47 = ld_val__h34607[47:40] ;
  assign ld_val4607_BITS_55_TO_48__q48 = ld_val__h34607[55:48] ;
  assign ld_val4607_BITS_63_TO_32__q46 = ld_val__h34607[63:32] ;
  assign ld_val4607_BITS_63_TO_48__q49 = ld_val__h34607[63:48] ;
  assign ld_val4607_BITS_63_TO_56__q50 = ld_val__h34607[63:56] ;
  assign ld_val4607_BITS_7_TO_0__q37 = ld_val__h34607[7:0] ;
  assign lev_0_PTN_pa__h29581 = { _theResult____h28937[31:10], 12'b0 } ;
  assign lev_0_pte_pa__h29583 = lev_0_PTN_pa__h29581 + vpn_0_pa__h29582 ;
  assign lev_0_pte_pa_w64__h29584 = { lev_0_pte_pa__h29583[33:3], 3'b0 } ;
  assign lev_0_pte_pa_w64_fa__h29585 = { 30'd0, lev_0_pte_pa_w64__h29584 } ;
  assign lev_1_pte_pa__h28671 = satp_pa__h1960 + vpn_1_pa__h28670 ;
  assign lev_1_pte_pa_w64__h28672 = { lev_1_pte_pa__h28671[33:3], 3'b0 } ;
  assign lev_1_pte_pa_w64_fa__h28673 = { 30'd0, lev_1_pte_pa_w64__h28672 } ;
  assign lrsc_result__h21768 =
	     !rg_lrsc_valid ||
	     !rg_lrsc_pa_68_EQ_IF_rg_priv_1_ULE_0b1_2_AND_rg_ETC___d269 ;
  assign master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1 =
	     master_xactor_f_rd_data$D_OUT[10:3] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4 =
	     master_xactor_f_rd_data$D_OUT[18:11] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2 =
	     master_xactor_f_rd_data$D_OUT[18:3] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q5 =
	     master_xactor_f_rd_data$D_OUT[26:19] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q6 =
	     master_xactor_f_rd_data$D_OUT[34:19] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q7 =
	     master_xactor_f_rd_data$D_OUT[34:27] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3 =
	     master_xactor_f_rd_data$D_OUT[34:3] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q8 =
	     master_xactor_f_rd_data$D_OUT[42:35] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9 =
	     master_xactor_f_rd_data$D_OUT[50:35] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11 =
	     master_xactor_f_rd_data$D_OUT[50:43] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12 =
	     master_xactor_f_rd_data$D_OUT[58:51] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10 =
	     master_xactor_f_rd_data$D_OUT[66:35] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13 =
	     master_xactor_f_rd_data$D_OUT[66:51] ;
  assign master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14 =
	     master_xactor_f_rd_data$D_OUT[66:59] ;
  assign master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d1000 =
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     _theResult____h28937[0] &&
	     (_theResult____h28937[1] || !_theResult____h28937[2]) &&
	     (_theResult____h28937[3] || _theResult____h28937[1]) &&
	     _theResult____h28937[19:10] == 10'd0 ;
  assign master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d1004 =
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     _theResult____h28937[0] &&
	     (_theResult____h28937[1] || !_theResult____h28937[2]) &&
	     (_theResult____h28937[3] || _theResult____h28937[1]) &&
	     _theResult____h28937[19:10] == 10'd0 &&
	     !cfg_verbosity_read__2_ULE_1___d43 ;
  assign master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d1010 =
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     _theResult____h28937[0] &&
	     (_theResult____h28937[1] || !_theResult____h28937[2]) &&
	     (_theResult____h28937[3] || _theResult____h28937[1]) &&
	     _theResult____h28937[19:10] != 10'd0 &&
	     !cfg_verbosity_read__2_ULE_1___d43 ;
  assign master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d1036 =
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     _theResult____h28937[0] &&
	     (_theResult____h28937[1] || !_theResult____h28937[2]) &&
	     (_theResult____h28937[3] || _theResult____h28937[1]) &&
	     !cfg_verbosity_read__2_ULE_1___d43 ;
  assign master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d977 =
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     (!_theResult____h28937[0] ||
	      !_theResult____h28937[1] && _theResult____h28937[2]) &&
	     !cfg_verbosity_read__2_ULE_1___d43 ;
  assign master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985 =
	     master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	     _theResult____h28937[0] &&
	     !_theResult____h28937[2] &&
	     !_theResult____h28937[3] &&
	     !_theResult____h28937[1] &&
	     !cfg_verbosity_read__2_ULE_1___d43 ;
  assign mem_req_wr_addr_awaddr__h2978 =
	     { 30'd0, f_fabric_write_reqs$D_OUT[97:64] } ;
  assign new_st_val__h25327 =
	     (rg_f3 == 3'b010) ?
	       new_st_val__h25633 :
	       _theResult_____2__h25629 ;
  assign new_st_val__h25633 = { 32'd0, _theResult_____2__h25629[31:0] } ;
  assign new_st_val__h25724 =
	     IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_IF_rg_f3_15_E_ETC___d710 +
	     IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_rg_st_amo_val_ETC___d779 ;
  assign new_st_val__h26704 = w1__h25621 ^ w2__h36853 ;
  assign new_st_val__h26708 = w1__h25621 & w2__h36853 ;
  assign new_st_val__h26712 = w1__h25621 | w2__h36853 ;
  assign new_st_val__h26716 =
	     (w1__h25621 < w2__h36853) ? w1__h25621 : w2__h36853 ;
  assign new_st_val__h26721 =
	     (w1__h25621 <= w2__h36853) ? w2__h36853 : w1__h25621 ;
  assign new_st_val__h26727 =
	     ((IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_IF_rg_f3_15_E_ETC___d710 ^
	       64'h8000000000000000) <
	      (IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_rg_st_amo_val_ETC___d779 ^
	       64'h8000000000000000)) ?
	       w1__h25621 :
	       w2__h36853 ;
  assign new_st_val__h26732 =
	     ((IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_IF_rg_f3_15_E_ETC___d710 ^
	       64'h8000000000000000) <=
	      (IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_rg_st_amo_val_ETC___d779 ^
	       64'h8000000000000000)) ?
	       w2__h36853 :
	       w1__h25621 ;
  assign new_st_val__h36863 = { 32'd0, _theResult_____2__h36859[31:0] } ;
  assign new_st_val__h36954 =
	     new_ld_val__h36813 +
	     IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_rg_st_amo_val_ETC___d779 ;
  assign new_st_val__h38814 = w1__h36851 ^ w2__h36853 ;
  assign new_st_val__h38818 = w1__h36851 & w2__h36853 ;
  assign new_st_val__h38822 = w1__h36851 | w2__h36853 ;
  assign new_st_val__h38826 =
	     (w1__h36851 < w2__h36853) ? w1__h36851 : w2__h36853 ;
  assign new_st_val__h38831 =
	     (w1__h36851 <= w2__h36853) ? w2__h36853 : w1__h36851 ;
  assign new_st_val__h38837 =
	     ((new_ld_val__h36813 ^ 64'h8000000000000000) <
	      (IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_rg_st_amo_val_ETC___d779 ^
	       64'h8000000000000000)) ?
	       w1__h36851 :
	       w2__h36853 ;
  assign new_st_val__h38842 =
	     ((new_ld_val__h36813 ^ 64'h8000000000000000) <=
	      (IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_rg_st_amo_val_ETC___d779 ^
	       64'h8000000000000000)) ?
	       w2__h36853 :
	       w1__h36851 ;
  assign new_value__h24197 =
	     (rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
	       64'd1 :
	       CASE_rg_f3_0b0_IF_rg_addr_01_BITS_2_TO_0_19_EQ_ETC__q53 ;
  assign new_value__h7772 =
	     (rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) ?
	       word64__h7644 :
	       IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_01_BITS__ETC___d649 ;
  assign pa___1__h6727 = { tlb$lookup[67:46], rg_addr[11:0] } ;
  assign pa___1__h6776 = { tlb$lookup[67:56], rg_addr[21:0] } ;
  assign pa__h6208 = { 2'd0, rg_addr } ;
  assign pte___1__h6908 = { tlb$lookup[67:43], 1'd1, tlb$lookup[41:36] } ;
  assign pte___1__h6936 =
	     { pte___2__h6719[31:8], 1'd1, pte___2__h6719[6:0] } ;
  assign pte___2__h6719 =
	     tlb$lookup[42] ? tlb$lookup[67:36] : pte___1__h6908 ;
  assign ram_state_and_ctag_cset_b_read__98_BITS_21_TO__ETC___d203 =
	     ram_state_and_ctag_cset$DOB[21:0] ==
	     x1_avValue_pa__h6220[33:12] ;
  assign ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209 =
	     ram_state_and_ctag_cset$DOB[44:23] ==
	     x1_avValue_pa__h6220[33:12] ;
  assign ram_state_and_ctag_cset_b_read__98_BIT_22_99_A_ETC___d479 =
	     (ram_state_and_ctag_cset$DOB[22] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_21_TO__ETC___d203 ||
	      ram_state_and_ctag_cset$DOB[45] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209) &&
	     rg_op == 2'd2 &&
	     rg_amo_funct7[6:2] == 5'b00010 ;
  assign ram_state_and_ctag_cset_b_read__98_BIT_22_99_A_ETC___d490 =
	     (ram_state_and_ctag_cset$DOB[22] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_21_TO__ETC___d203 ||
	      ram_state_and_ctag_cset$DOB[45] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209) &&
	     IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5__ETC___d480 ;
  assign ram_state_and_ctag_cset_b_read__98_BIT_22_99_A_ETC___d668 =
	     (ram_state_and_ctag_cset$DOB[22] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_21_TO__ETC___d203 ||
	      ram_state_and_ctag_cset$DOB[45] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209) &&
	     !cfg_verbosity_read__2_ULE_1___d43 ;
  assign ram_state_and_ctag_cset_b_read__98_BIT_22_99_A_ETC___d911 =
	     (ram_state_and_ctag_cset$DOB[22] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_21_TO__ETC___d203 ||
	      ram_state_and_ctag_cset$DOB[45] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209) &&
	     IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5__ETC___d480 &&
	     !cfg_verbosity_read__2_ULE_1___d43 ;
  assign req_f3_BITS_1_TO_0_393_EQ_0b0_394_OR_req_f3_BI_ETC___d1423 =
	     req_f3[1:0] == 2'b0 || req_f3[1:0] == 2'b01 && !req_addr[0] ||
	     req_f3[1:0] == 2'b10 && req_addr[1:0] == 2'b0 ||
	     req_f3[1:0] == 2'b11 && req_addr[2:0] == 3'b0 ;
  assign result__h20481 =
	     { {56{word64644_BITS_7_TO_0__q15[7]}},
	       word64644_BITS_7_TO_0__q15 } ;
  assign result__h20509 =
	     { {56{word64644_BITS_15_TO_8__q18[7]}},
	       word64644_BITS_15_TO_8__q18 } ;
  assign result__h20537 =
	     { {56{word64644_BITS_23_TO_16__q19[7]}},
	       word64644_BITS_23_TO_16__q19 } ;
  assign result__h20565 =
	     { {56{word64644_BITS_31_TO_24__q21[7]}},
	       word64644_BITS_31_TO_24__q21 } ;
  assign result__h20593 =
	     { {56{word64644_BITS_39_TO_32__q22[7]}},
	       word64644_BITS_39_TO_32__q22 } ;
  assign result__h20621 =
	     { {56{word64644_BITS_47_TO_40__q25[7]}},
	       word64644_BITS_47_TO_40__q25 } ;
  assign result__h20649 =
	     { {56{word64644_BITS_55_TO_48__q26[7]}},
	       word64644_BITS_55_TO_48__q26 } ;
  assign result__h20677 =
	     { {56{word64644_BITS_63_TO_56__q28[7]}},
	       word64644_BITS_63_TO_56__q28 } ;
  assign result__h20722 = { 56'd0, word64__h7644[7:0] } ;
  assign result__h20750 = { 56'd0, word64__h7644[15:8] } ;
  assign result__h20778 = { 56'd0, word64__h7644[23:16] } ;
  assign result__h20806 = { 56'd0, word64__h7644[31:24] } ;
  assign result__h20834 = { 56'd0, word64__h7644[39:32] } ;
  assign result__h20862 = { 56'd0, word64__h7644[47:40] } ;
  assign result__h20890 = { 56'd0, word64__h7644[55:48] } ;
  assign result__h20918 = { 56'd0, word64__h7644[63:56] } ;
  assign result__h20963 =
	     { {48{word64644_BITS_15_TO_0__q16[15]}},
	       word64644_BITS_15_TO_0__q16 } ;
  assign result__h20991 =
	     { {48{word64644_BITS_31_TO_16__q20[15]}},
	       word64644_BITS_31_TO_16__q20 } ;
  assign result__h21019 =
	     { {48{word64644_BITS_47_TO_32__q23[15]}},
	       word64644_BITS_47_TO_32__q23 } ;
  assign result__h21047 =
	     { {48{word64644_BITS_63_TO_48__q27[15]}},
	       word64644_BITS_63_TO_48__q27 } ;
  assign result__h21088 = { 48'd0, word64__h7644[15:0] } ;
  assign result__h21116 = { 48'd0, word64__h7644[31:16] } ;
  assign result__h21144 = { 48'd0, word64__h7644[47:32] } ;
  assign result__h21172 = { 48'd0, word64__h7644[63:48] } ;
  assign result__h21213 =
	     { {32{word64644_BITS_31_TO_0__q17[31]}},
	       word64644_BITS_31_TO_0__q17 } ;
  assign result__h21241 =
	     { {32{word64644_BITS_63_TO_32__q24[31]}},
	       word64644_BITS_63_TO_32__q24 } ;
  assign result__h21280 = { 32'd0, word64__h7644[31:0] } ;
  assign result__h21308 = { 32'd0, word64__h7644[63:32] } ;
  assign result__h34667 =
	     { {56{master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1[7]}},
	       master_xactor_f_rd_dataD_OUT_BITS_10_TO_3__q1 } ;
  assign result__h34697 =
	     { {56{master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4[7]}},
	       master_xactor_f_rd_dataD_OUT_BITS_18_TO_11__q4 } ;
  assign result__h34724 =
	     { {56{master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q5[7]}},
	       master_xactor_f_rd_dataD_OUT_BITS_26_TO_19__q5 } ;
  assign result__h34751 =
	     { {56{master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q7[7]}},
	       master_xactor_f_rd_dataD_OUT_BITS_34_TO_27__q7 } ;
  assign result__h34778 =
	     { {56{master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q8[7]}},
	       master_xactor_f_rd_dataD_OUT_BITS_42_TO_35__q8 } ;
  assign result__h34805 =
	     { {56{master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11[7]}},
	       master_xactor_f_rd_dataD_OUT_BITS_50_TO_43__q11 } ;
  assign result__h34832 =
	     { {56{master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12[7]}},
	       master_xactor_f_rd_dataD_OUT_BITS_58_TO_51__q12 } ;
  assign result__h34859 =
	     { {56{master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14[7]}},
	       master_xactor_f_rd_dataD_OUT_BITS_66_TO_59__q14 } ;
  assign result__h34903 = { 56'd0, master_xactor_f_rd_data$D_OUT[10:3] } ;
  assign result__h34930 = { 56'd0, master_xactor_f_rd_data$D_OUT[18:11] } ;
  assign result__h34957 = { 56'd0, master_xactor_f_rd_data$D_OUT[26:19] } ;
  assign result__h34984 = { 56'd0, master_xactor_f_rd_data$D_OUT[34:27] } ;
  assign result__h35011 = { 56'd0, master_xactor_f_rd_data$D_OUT[42:35] } ;
  assign result__h35038 = { 56'd0, master_xactor_f_rd_data$D_OUT[50:43] } ;
  assign result__h35065 = { 56'd0, master_xactor_f_rd_data$D_OUT[58:51] } ;
  assign result__h35092 = { 56'd0, master_xactor_f_rd_data$D_OUT[66:59] } ;
  assign result__h35136 =
	     { {48{master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2[15]}},
	       master_xactor_f_rd_dataD_OUT_BITS_18_TO_3__q2 } ;
  assign result__h35163 =
	     { {48{master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q6[15]}},
	       master_xactor_f_rd_dataD_OUT_BITS_34_TO_19__q6 } ;
  assign result__h35190 =
	     { {48{master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9[15]}},
	       master_xactor_f_rd_dataD_OUT_BITS_50_TO_35__q9 } ;
  assign result__h35217 =
	     { {48{master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13[15]}},
	       master_xactor_f_rd_dataD_OUT_BITS_66_TO_51__q13 } ;
  assign result__h35257 = { 48'd0, master_xactor_f_rd_data$D_OUT[18:3] } ;
  assign result__h35284 = { 48'd0, master_xactor_f_rd_data$D_OUT[34:19] } ;
  assign result__h35311 = { 48'd0, master_xactor_f_rd_data$D_OUT[50:35] } ;
  assign result__h35338 = { 48'd0, master_xactor_f_rd_data$D_OUT[66:51] } ;
  assign result__h35378 =
	     { {32{master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3[31]}},
	       master_xactor_f_rd_dataD_OUT_BITS_34_TO_3__q3 } ;
  assign result__h35405 =
	     { {32{master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10[31]}},
	       master_xactor_f_rd_dataD_OUT_BITS_66_TO_35__q10 } ;
  assign result__h35443 = { 32'd0, master_xactor_f_rd_data$D_OUT[34:3] } ;
  assign result__h35470 = { 32'd0, master_xactor_f_rd_data$D_OUT[66:35] } ;
  assign result__h37042 =
	     { {56{ld_val4607_BITS_7_TO_0__q37[7]}},
	       ld_val4607_BITS_7_TO_0__q37 } ;
  assign result__h37950 =
	     { {56{ld_val4607_BITS_15_TO_8__q40[7]}},
	       ld_val4607_BITS_15_TO_8__q40 } ;
  assign result__h37978 =
	     { {56{ld_val4607_BITS_23_TO_16__q41[7]}},
	       ld_val4607_BITS_23_TO_16__q41 } ;
  assign result__h38006 =
	     { {56{ld_val4607_BITS_31_TO_24__q43[7]}},
	       ld_val4607_BITS_31_TO_24__q43 } ;
  assign result__h38034 =
	     { {56{ld_val4607_BITS_39_TO_32__q44[7]}},
	       ld_val4607_BITS_39_TO_32__q44 } ;
  assign result__h38062 =
	     { {56{ld_val4607_BITS_47_TO_40__q47[7]}},
	       ld_val4607_BITS_47_TO_40__q47 } ;
  assign result__h38090 =
	     { {56{ld_val4607_BITS_55_TO_48__q48[7]}},
	       ld_val4607_BITS_55_TO_48__q48 } ;
  assign result__h38118 =
	     { {56{ld_val4607_BITS_63_TO_56__q50[7]}},
	       ld_val4607_BITS_63_TO_56__q50 } ;
  assign result__h38163 = { 56'd0, ld_val__h34607[7:0] } ;
  assign result__h38191 = { 56'd0, ld_val__h34607[15:8] } ;
  assign result__h38219 = { 56'd0, ld_val__h34607[23:16] } ;
  assign result__h38247 = { 56'd0, ld_val__h34607[31:24] } ;
  assign result__h38275 = { 56'd0, ld_val__h34607[39:32] } ;
  assign result__h38303 = { 56'd0, ld_val__h34607[47:40] } ;
  assign result__h38331 = { 56'd0, ld_val__h34607[55:48] } ;
  assign result__h38359 = { 56'd0, ld_val__h34607[63:56] } ;
  assign result__h38404 =
	     { {48{ld_val4607_BITS_15_TO_0__q38[15]}},
	       ld_val4607_BITS_15_TO_0__q38 } ;
  assign result__h38432 =
	     { {48{ld_val4607_BITS_31_TO_16__q42[15]}},
	       ld_val4607_BITS_31_TO_16__q42 } ;
  assign result__h38460 =
	     { {48{ld_val4607_BITS_47_TO_32__q45[15]}},
	       ld_val4607_BITS_47_TO_32__q45 } ;
  assign result__h38488 =
	     { {48{ld_val4607_BITS_63_TO_48__q49[15]}},
	       ld_val4607_BITS_63_TO_48__q49 } ;
  assign result__h38529 = { 48'd0, ld_val__h34607[15:0] } ;
  assign result__h38557 = { 48'd0, ld_val__h34607[31:16] } ;
  assign result__h38585 = { 48'd0, ld_val__h34607[47:32] } ;
  assign result__h38613 = { 48'd0, ld_val__h34607[63:48] } ;
  assign result__h38654 =
	     { {32{ld_val4607_BITS_31_TO_0__q39[31]}},
	       ld_val4607_BITS_31_TO_0__q39 } ;
  assign result__h38682 =
	     { {32{ld_val4607_BITS_63_TO_32__q46[31]}},
	       ld_val4607_BITS_63_TO_32__q46 } ;
  assign result__h38721 = { 32'd0, ld_val__h34607[31:0] } ;
  assign result__h38749 = { 32'd0, ld_val__h34607[63:32] } ;
  assign rg_amo_funct7_22_BITS_6_TO_2_23_EQ_0b10_24_AND_ETC___d675 =
	     rg_amo_funct7[6:2] == 5'b00010 &&
	     (ram_state_and_ctag_cset$DOB[22] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_21_TO__ETC___d203 ||
	      ram_state_and_ctag_cset$DOB[45] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209) ;
  assign rg_amo_funct7_22_BITS_6_TO_2_23_EQ_0b1_86_OR_I_ETC___d342 =
	     IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b100_17__ETC___d261 &&
	     (!ram_state_and_ctag_cset$DOB[45] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209 ||
	      IF_rg_f3_15_EQ_0b0_16_THEN_NOT_rg_priv_1_ULE_0_ETC___d337) &&
	     (ram_state_and_ctag_cset$DOB[45] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209 ||
	      IF_rg_f3_15_EQ_0b0_16_THEN_NOT_rg_priv_1_ULE_0_ETC___d337) ;
  assign rg_lrsc_pa_68_EQ_IF_rg_priv_1_ULE_0b1_2_AND_rg_ETC___d269 =
	     rg_lrsc_pa == x1_avValue_pa__h6220 ;
  assign rg_op_17_EQ_0_18_OR_rg_op_17_EQ_2_20_AND_rg_am_ETC___d426 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     (!ram_state_and_ctag_cset$DOB[22] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_21_TO__ETC___d203) &&
	     (!ram_state_and_ctag_cset$DOB[45] ||
	      !ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209) ;
  assign rg_op_17_EQ_0_18_OR_rg_op_17_EQ_2_20_AND_rg_am_ETC___d463 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     tlb_lookup_rg_satp_4_BITS_30_TO_22_00_rg_addr__ETC___d137 ||
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     tlb$lookup[38] ;
  assign rg_op_17_EQ_0_18_OR_rg_op_17_EQ_2_20_AND_rg_am_ETC___d484 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     (ram_state_and_ctag_cset_b_read__98_BIT_22_99_A_ETC___d479 ||
	      NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d482) ;
  assign rg_op_17_EQ_0_18_OR_rg_op_17_EQ_2_20_AND_rg_am_ETC___d494 =
	     rg_op_17_EQ_0_18_OR_rg_op_17_EQ_2_20_AND_rg_am_ETC___d484 ||
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) &&
	     rg_op_17_EQ_1_64_OR_rg_op_17_EQ_2_20_AND_rg_am_ETC___d492 ;
  assign rg_op_17_EQ_0_18_OR_rg_op_17_EQ_2_20_AND_rg_am_ETC___d498 =
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     (ram_state_and_ctag_cset$DOB[22] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_21_TO__ETC___d203 ||
	      ram_state_and_ctag_cset$DOB[45] &&
	      ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209) ;
  assign rg_op_17_EQ_1_64_OR_rg_op_17_EQ_2_20_AND_rg_am_ETC___d492 =
	     rg_op == 2'd1 &&
	     IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5__ETC___d480 ||
	     rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 ||
	     rg_op != 2'd1 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011) &&
	     ram_state_and_ctag_cset_b_read__98_BIT_22_99_A_ETC___d490 ;
  assign rg_op_17_EQ_1_64_OR_rg_op_17_EQ_2_20_AND_rg_am_ETC___d715 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
	     NOT_rg_op_17_EQ_2_20_21_OR_NOT_rg_amo_funct7_2_ETC___d712 ||
	     NOT_rg_op_17_EQ_1_64_88_AND_NOT_rg_op_17_EQ_2__ETC___d714 ;
  assign rg_op_17_EQ_1_64_OR_rg_op_17_EQ_2_20_AND_rg_am_ETC___d845 =
	     (rg_op == 2'd1 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011) &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00011 ||
	      rg_lrsc_valid &&
	      rg_lrsc_pa_68_EQ_IF_rg_priv_1_ULE_0b1_2_AND_rg_ETC___d269) ;
  assign rg_op_17_EQ_2_20_AND_rg_amo_funct7_22_BITS_6_T_ETC___d285 =
	     rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00011 &&
	     lrsc_result__h21768 ||
	     f_fabric_write_reqs$FULL_N &&
	     NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d283 ;
  assign rg_priv_1_EQ_0b0_07_AND_NOT_tlb_lookup_rg_satp_ETC___d148 =
	     rg_priv == 2'b0 && !tlb$lookup[40] ||
	     rg_priv == 2'b01 && tlb$lookup[40] && !rg_sstatus_SUM ||
	     dmem_not_imem_OR_NOT_rg_op_17_EQ_0_18_19_AND_N_ETC___d131 &&
	     NOT_dmem_not_imem_32_OR_NOT_rg_op_17_EQ_0_18_1_ETC___d139 &&
	     (!dmem_not_imem || rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 ||
	      !tlb$lookup[38]) ;
  assign rg_priv_1_EQ_0b0_07_AND_NOT_tlb_lookup_rg_satp_ETC___d161 =
	     rg_priv == 2'b0 && !tlb$lookup[40] ||
	     rg_priv == 2'b01 && tlb$lookup[40] && !rg_sstatus_SUM ||
	     !dmem_not_imem ||
	     !tlb$lookup[38] ;
  assign rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d157 =
	     rg_priv_1_ULE_0b1___d92 && rg_satp[31] && tlb$lookup[68] &&
	     (rg_priv_1_EQ_0b0_07_AND_NOT_tlb_lookup_rg_satp_ETC___d148 ||
	      NOT_tlb_lookup_rg_satp_4_BITS_30_TO_22_00_rg_a_ETC___d154) ;
  assign rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d350 =
	     rg_priv_1_ULE_0b1___d92 && rg_satp[31] && !tlb$lookup[68] ||
	     (rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d157 ?
		tlb$RDY_lookup :
		NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d348) ;
  assign rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d395 =
	     rg_priv_1_ULE_0b1___d92 && rg_satp[31] &&
	     (rg_priv_1_EQ_0b0_07_AND_NOT_tlb_lookup_rg_satp_ETC___d148 ||
	      NOT_tlb_lookup_rg_satp_4_BITS_30_TO_22_00_rg_a_ETC___d154) &&
	     tlb$lookup[68] ;
  assign rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d417 =
	     rg_priv_1_ULE_0b1___d92 && rg_satp[31] && tlb$lookup[68] &&
	     NOT_rg_priv_1_EQ_0b0_07_73_OR_tlb_lookup_rg_sa_ETC___d410 &&
	     tlb$lookup[42] &&
	     tlb$lookup[43] &&
	     !pte___2__h6719[7] &&
	     rg_op != 2'd0 &&
	     (rg_op != 2'd2 || rg_amo_funct7[6:2] != 5'b00010) ;
  assign rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d434 =
	     rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d157 ||
	     dmem_not_imem && !soc_map$m_is_mem_addr ||
	     rg_op_17_EQ_0_18_OR_rg_op_17_EQ_2_20_AND_rg_am_ETC___d426 ||
	     NOT_rg_op_17_EQ_0_18_19_AND_NOT_rg_op_17_EQ_2__ETC___d431 ;
  assign rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d435 =
	     rg_priv_1_ULE_0b1___d92 && rg_satp[31] && !tlb$lookup[68] ||
	     rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d434 ;
  assign rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d453 =
	     rg_priv_1_ULE_0b1___d92 && rg_satp[31] && tlb$lookup[68] &&
	     NOT_rg_priv_1_EQ_0b0_07_73_OR_tlb_lookup_rg_sa_ETC___d448 &&
	     NOT_cfg_verbosity_read__2_ULT_2_44___d445 &&
	     dmem_not_imem &&
	     tlb$lookup[38] &&
	     tlb$lookup[43] ;
  assign rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d456 =
	     rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d417 &&
	     NOT_cfg_verbosity_read__2_ULT_2_44___d445 &&
	     (!dmem_not_imem || !tlb$lookup[38] || !tlb$lookup[43]) ;
  assign rg_priv_1_ULE_0b1___d92 = rg_priv <= 2'b01 ;
  assign rg_st_amo_val_BITS_31_TO_0__q33 = rg_st_amo_val[31:0] ;
  assign rg_state_5_EQ_12_109_AND_rg_op_17_EQ_0_18_OR_r_ETC___d1111 =
	     rg_state == 4'd12 &&
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) &&
	     b__h28572 == 4'd0 ;
  assign satp_pa__h1960 = { rg_satp[21:0], 12'b0 } ;
  assign shift_bits__h2992 = { f_fabric_write_reqs$D_OUT[66:64], 3'b0 } ;
  assign strobe64__h3142 = 8'b00000001 << f_fabric_write_reqs$D_OUT[66:64] ;
  assign strobe64__h3144 = 8'b00000011 << f_fabric_write_reqs$D_OUT[66:64] ;
  assign strobe64__h3146 = 8'b00001111 << f_fabric_write_reqs$D_OUT[66:64] ;
  assign tlb_lookup_rg_satp_4_BITS_30_TO_22_00_rg_addr__ETC___d137 =
	     tlb$lookup[37] | y__h6547 ;
  assign tlb_lookup_rg_satp_4_BITS_30_TO_22_00_rg_addr__ETC___d389 =
	     tlb$lookup[42] &&
	     (rg_op == 2'd0 ||
	      rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010 ||
	      tlb$lookup[43]) ;
  assign tmp__h30958 = { 1'd0, rg_victim_way } ;
  assign tmp__h30959 = tmp__h30958 + 2'd1 ;
  assign vpn_0_pa__h29582 = { 22'd0, rg_addr[21:12], 2'd0 } ;
  assign vpn_1_pa__h28670 = { 22'd0, rg_addr[31:22], 2'd0 } ;
  assign w16847_BITS_31_TO_0__q52 = w1__h36847[31:0] ;
  assign w1___1__h25692 =
	     { 32'd0,
	       IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_01_BITS__ETC___d649[31:0] } ;
  assign w1___1__h36922 = { 32'd0, w1__h36847[31:0] } ;
  assign w2___1__h36923 = { 32'd0, rg_st_amo_val[31:0] } ;
  assign w2__h36853 = (rg_f3 == 3'b010) ? w2___1__h36923 : rg_st_amo_val ;
  assign word64644_BITS_15_TO_0__q16 = word64__h7644[15:0] ;
  assign word64644_BITS_15_TO_8__q18 = word64__h7644[15:8] ;
  assign word64644_BITS_23_TO_16__q19 = word64__h7644[23:16] ;
  assign word64644_BITS_31_TO_0__q17 = word64__h7644[31:0] ;
  assign word64644_BITS_31_TO_16__q20 = word64__h7644[31:16] ;
  assign word64644_BITS_31_TO_24__q21 = word64__h7644[31:24] ;
  assign word64644_BITS_39_TO_32__q22 = word64__h7644[39:32] ;
  assign word64644_BITS_47_TO_32__q23 = word64__h7644[47:32] ;
  assign word64644_BITS_47_TO_40__q25 = word64__h7644[47:40] ;
  assign word64644_BITS_55_TO_48__q26 = word64__h7644[55:48] ;
  assign word64644_BITS_63_TO_32__q24 = word64__h7644[63:32] ;
  assign word64644_BITS_63_TO_48__q27 = word64__h7644[63:48] ;
  assign word64644_BITS_63_TO_56__q28 = word64__h7644[63:56] ;
  assign word64644_BITS_7_TO_0__q15 = word64__h7644[7:0] ;
  assign word64__h7644 = x__h7795 | y__h7796 ;
  assign x1_avValue_exc_code__h6221 =
	     dmem_not_imem ?
	       ((rg_op == 2'd0 ||
		 rg_op == 2'd2 && rg_amo_funct7[6:2] == 5'b00010) ?
		  4'd13 :
		  4'd15) :
	       4'd12 ;
  assign x1_avValue_pa__h6220 =
	     (rg_priv_1_ULE_0b1___d92 && rg_satp[31]) ?
	       _theResult___fst__h6308 :
	       pa__h6208 ;
  assign x1_avValue_pte__h6223 =
	     (rg_priv_1_ULE_0b1___d92 && rg_satp[31]) ?
	       _theResult___snd_fst__h6310 :
	       tlb$lookup[67:36] ;
  assign x__h21778 = { 63'd0, lrsc_result__h21768 } ;
  assign x__h36842 =
	     (rg_f3 == 3'b010) ?
	       new_st_val__h36863 :
	       _theResult_____2__h36859 ;
  assign x__h3849 = { 32'd0, f_pte_writebacks$D_OUT[31:0] } ;
  assign x__h7795 = ram_cword_set$DOB[63:0] & y__h7810 ;
  assign y__h14125 =
	     {64{ram_state_and_ctag_cset$DOB[45] &&
		 ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209}} ;
  assign y__h6547 = rg_mstatus_MXR & tlb$lookup[39] ;
  assign y__h7796 = ram_cword_set$DOB[127:64] & y__h14125 ;
  assign y__h7810 =
	     {64{ram_state_and_ctag_cset$DOB[22] &&
		 ram_state_and_ctag_cset_b_read__98_BITS_21_TO__ETC___d203}} ;
  always@(f_fabric_write_reqs$D_OUT)
  begin
    case (f_fabric_write_reqs$D_OUT[99:98])
      2'b0: x__h3025 = 3'b0;
      2'b01: x__h3025 = 3'b001;
      2'b10: x__h3025 = 3'b010;
      2'b11: x__h3025 = 3'b011;
    endcase
  end
  always@(rg_f3)
  begin
    case (rg_f3[1:0])
      2'b0: value__h36399 = 3'b0;
      2'b01: value__h36399 = 3'b001;
      2'b10: value__h36399 = 3'b010;
      2'd3: value__h36399 = 3'b011;
    endcase
  end
  always@(tlb$lookup or pa__h6208 or pa___1__h6727 or pa___1__h6776)
  begin
    case (tlb$lookup[35:34])
      2'd0: _theResult___fst__h6721 = pa___1__h6727;
      2'd1: _theResult___fst__h6721 = pa___1__h6776;
      default: _theResult___fst__h6721 = pa__h6208;
    endcase
  end
  always@(f_fabric_write_reqs$D_OUT or
	  strobe64__h3142 or strobe64__h3144 or strobe64__h3146)
  begin
    case (f_fabric_write_reqs$D_OUT[99:98])
      2'b0: mem_req_wr_data_wstrb__h3205 = strobe64__h3142;
      2'b01: mem_req_wr_data_wstrb__h3205 = strobe64__h3144;
      2'b10: mem_req_wr_data_wstrb__h3205 = strobe64__h3146;
      2'b11: mem_req_wr_data_wstrb__h3205 = 8'b11111111;
    endcase
  end
  always@(f_fabric_write_reqs$D_OUT or _theResult___snd_fst__h3212)
  begin
    case (f_fabric_write_reqs$D_OUT[99:98])
      2'b0, 2'b01, 2'b10:
	  mem_req_wr_data_wdata__h3204 = _theResult___snd_fst__h3212;
      2'd3: mem_req_wr_data_wdata__h3204 = f_fabric_write_reqs$D_OUT[63:0];
    endcase
  end
  always@(ram_state_and_ctag_cset$DOB or
	  ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209 or
	  ram_cword_set$DOB)
  begin
    case (ram_state_and_ctag_cset$DOB[45] &&
	  ram_state_and_ctag_cset_b_read__98_BITS_44_TO__ETC___d209)
      1'd0: old_cword__h22546 = ram_cword_set$DOB[63:0];
      1'd1: old_cword__h22546 = ram_cword_set$DOB[127:64];
    endcase
  end
  always@(rg_f3 or
	  NOT_ram_state_and_ctag_cset_b_read__98_BIT_45__ETC___d234 or
	  rg_priv_1_ULE_0b1___d92 or rg_satp or tlb$RDY_lookup)
  begin
    case (rg_f3)
      3'b0, 3'b001, 3'b010:
	  IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b1_40_OR_ETC___d277 =
	      !rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$RDY_lookup;
      default: IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b1_40_OR_ETC___d277 =
		   rg_f3 == 3'b011 ||
		   NOT_ram_state_and_ctag_cset_b_read__98_BIT_45__ETC___d234;
    endcase
  end
  always@(rg_addr or
	  NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d233 or
	  NOT_ram_state_and_ctag_cset_b_read__98_BIT_45__ETC___d234)
  begin
    case (rg_addr[2:0])
      3'h0, 3'h1, 3'h2, 3'h3, 3'h4, 3'h5, 3'h6:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_OR_rg_a_ETC___d239 =
	      NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d233 &&
	      NOT_ram_state_and_ctag_cset_b_read__98_BIT_45__ETC___d234;
      3'd7:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_OR_rg_a_ETC___d239 =
	      rg_addr[2:0] != 3'h7 ||
	      NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d233 &&
	      NOT_ram_state_and_ctag_cset_b_read__98_BIT_45__ETC___d234;
    endcase
  end
  always@(rg_addr or
	  NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d233 or
	  NOT_ram_state_and_ctag_cset_b_read__98_BIT_45__ETC___d234)
  begin
    case (rg_addr[2:0])
      3'h0, 3'h2, 3'h4:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_OR_rg_a_ETC___d247 =
	      NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d233 &&
	      NOT_ram_state_and_ctag_cset_b_read__98_BIT_45__ETC___d234;
      default: IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_OR_rg_a_ETC___d247 =
		   rg_addr[2:0] != 3'h6 ||
		   NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d233 &&
		   NOT_ram_state_and_ctag_cset_b_read__98_BIT_45__ETC___d234;
    endcase
  end
  always@(rg_f3 or
	  rg_addr or
	  NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d233 or
	  NOT_ram_state_and_ctag_cset_b_read__98_BIT_45__ETC___d234 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_OR_rg_a_ETC___d239 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_OR_rg_a_ETC___d247 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_NO_ETC___d253)
  begin
    case (rg_f3)
      3'b0, 3'b100:
	  IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b100_17__ETC___d261 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_OR_rg_a_ETC___d239;
      3'b001, 3'b101:
	  IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b100_17__ETC___d261 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_OR_rg_a_ETC___d247;
      3'b010, 3'b110:
	  IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b100_17__ETC___d261 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_NO_ETC___d253;
      default: IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b100_17__ETC___d261 =
		   rg_f3 != 3'b011 || rg_addr[2:0] != 3'h0 ||
		   NOT_ram_state_and_ctag_cset_b_read__98_BIT_22__ETC___d233 &&
		   NOT_ram_state_and_ctag_cset_b_read__98_BIT_45__ETC___d234;
    endcase
  end
  always@(rg_amo_funct7 or
	  IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b100_17__ETC___d261)
  begin
    case (rg_amo_funct7[6:2])
      5'b0, 5'b00100, 5'b01000, 5'b01100, 5'b10000, 5'b11000, 5'b11100:
	  CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_15_ETC__q29 =
	      IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b100_17__ETC___d261;
      default: CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_15_ETC__q29 =
		   rg_amo_funct7[6:2] != 5'b10100 ||
		   IF_rg_f3_15_EQ_0b0_16_OR_rg_f3_15_EQ_0b100_17__ETC___d261;
    endcase
  end
  always@(x1_avValue_pa__h6220 or
	  NOT_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_3_ETC___d327 or
	  CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_15_ETC__q29)
  begin
    case (x1_avValue_pa__h6220[2:0])
      3'h0, 3'h2, 3'h4:
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d328 =
	      CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_15_ETC__q29;
      default: IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d328 =
		   NOT_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_3_ETC___d327;
    endcase
  end
  always@(x1_avValue_pa__h6220 or
	  NOT_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_3_ETC___d321 or
	  CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_15_ETC__q29)
  begin
    case (x1_avValue_pa__h6220[2:0])
      3'h0, 3'h1, 3'h2, 3'h3, 3'h4, 3'h5, 3'h6:
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d322 =
	      CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_15_ETC__q29;
      3'd7:
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d322 =
	      NOT_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_3_ETC___d321;
    endcase
  end
  always@(rg_f3 or
	  NOT_ram_state_and_ctag_cset_b_read__98_BIT_45__ETC___d234 or
	  rg_priv_1_ULE_0b1___d92 or
	  rg_satp or
	  tlb$RDY_lookup or
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d322 or
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d328 or
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d332 or
	  CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_15_ETC__q29)
  begin
    case (rg_f3)
      3'b0:
	  IF_rg_f3_15_EQ_0b0_16_THEN_NOT_rg_priv_1_ULE_0_ETC___d337 =
	      (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$RDY_lookup) &&
	      IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d322;
      3'b001:
	  IF_rg_f3_15_EQ_0b0_16_THEN_NOT_rg_priv_1_ULE_0_ETC___d337 =
	      (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$RDY_lookup) &&
	      IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d328;
      3'b010:
	  IF_rg_f3_15_EQ_0b0_16_THEN_NOT_rg_priv_1_ULE_0_ETC___d337 =
	      (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$RDY_lookup) &&
	      IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d332;
      3'b011:
	  IF_rg_f3_15_EQ_0b0_16_THEN_NOT_rg_priv_1_ULE_0_ETC___d337 =
	      CASE_rg_amo_funct7_BITS_6_TO_2_0b0_IF_rg_f3_15_ETC__q29;
      default: IF_rg_f3_15_EQ_0b0_16_THEN_NOT_rg_priv_1_ULE_0_ETC___d337 =
		   NOT_ram_state_and_ctag_cset_b_read__98_BIT_45__ETC___d234;
    endcase
  end
  always@(rg_addr or
	  result__h20481 or
	  result__h20509 or
	  result__h20537 or
	  result__h20565 or
	  result__h20593 or
	  result__h20621 or result__h20649 or result__h20677)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d595 =
	      result__h20481;
      3'h1:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d595 =
	      result__h20509;
      3'h2:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d595 =
	      result__h20537;
      3'h3:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d595 =
	      result__h20565;
      3'h4:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d595 =
	      result__h20593;
      3'h5:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d595 =
	      result__h20621;
      3'h6:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d595 =
	      result__h20649;
      3'h7:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d595 =
	      result__h20677;
    endcase
  end
  always@(rg_addr or
	  result__h20722 or
	  result__h20750 or
	  result__h20778 or
	  result__h20806 or
	  result__h20834 or
	  result__h20862 or result__h20890 or result__h20918)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d611 =
	      result__h20722;
      3'h1:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d611 =
	      result__h20750;
      3'h2:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d611 =
	      result__h20778;
      3'h3:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d611 =
	      result__h20806;
      3'h4:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d611 =
	      result__h20834;
      3'h5:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d611 =
	      result__h20862;
      3'h6:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d611 =
	      result__h20890;
      3'h7:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d611 =
	      result__h20918;
    endcase
  end
  always@(rg_addr or
	  result__h20963 or
	  result__h20991 or result__h21019 or result__h21047)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d623 =
	      result__h20963;
      3'h2:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d623 =
	      result__h20991;
      3'h4:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d623 =
	      result__h21019;
      3'h6:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d623 =
	      result__h21047;
      default: IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d623 =
		   64'd0;
    endcase
  end
  always@(rg_addr or
	  result__h21088 or
	  result__h21116 or result__h21144 or result__h21172)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d631 =
	      result__h21088;
      3'h2:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d631 =
	      result__h21116;
      3'h4:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d631 =
	      result__h21144;
      3'h6:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d631 =
	      result__h21172;
      default: IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d631 =
		   64'd0;
    endcase
  end
  always@(rg_addr or result__h21280 or result__h21308)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d641 =
	      result__h21280;
      3'h4:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d641 =
	      result__h21308;
      default: IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d641 =
		   64'd0;
    endcase
  end
  always@(rg_addr or result__h21213 or result__h21241)
  begin
    case (rg_addr[2:0])
      3'h0:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result1213_0x4_re_ETC__q30 =
	      result__h21213;
      3'h4:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result1213_0x4_re_ETC__q30 =
	      result__h21241;
      default: CASE_rg_addr_BITS_2_TO_0_0x0_result1213_0x4_re_ETC__q30 =
		   64'd0;
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d595 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d623 or
	  CASE_rg_addr_BITS_2_TO_0_0x0_result1213_0x4_re_ETC__q30 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_ra_ETC___d642 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d611 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d631 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d641)
  begin
    case (rg_f3)
      3'b0:
	  IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_01_BITS__ETC___d649 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d595;
      3'b001:
	  IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_01_BITS__ETC___d649 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d623;
      3'b010:
	  IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_01_BITS__ETC___d649 =
	      CASE_rg_addr_BITS_2_TO_0_0x0_result1213_0x4_re_ETC__q30;
      3'b011:
	  IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_01_BITS__ETC___d649 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_ra_ETC___d642;
      3'b100:
	  IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_01_BITS__ETC___d649 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d611;
      3'b101:
	  IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_01_BITS__ETC___d649 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d631;
      3'b110:
	  IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_01_BITS__ETC___d649 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d641;
      3'd7: IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_01_BITS__ETC___d649 = 64'd0;
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d595 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d623 or
	  w1___1__h25692 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_ra_ETC___d642 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d611 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d631 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d641)
  begin
    case (rg_f3)
      3'b0:
	  w1__h25621 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d595;
      3'b001:
	  w1__h25621 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d623;
      3'b010: w1__h25621 = w1___1__h25692;
      3'b011:
	  w1__h25621 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_ra_ETC___d642;
      3'b100:
	  w1__h25621 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d611;
      3'b101:
	  w1__h25621 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d631;
      3'b110:
	  w1__h25621 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d641;
      3'd7: w1__h25621 = 64'd0;
    endcase
  end
  always@(x1_avValue_pa__h6220 or old_cword__h22546 or rg_st_amo_val)
  begin
    case (x1_avValue_pa__h6220[2:0])
      3'h0:
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d763 =
	      { old_cword__h22546[63:16], rg_st_amo_val[15:0] };
      3'h2:
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d763 =
	      { old_cword__h22546[63:32],
		rg_st_amo_val[15:0],
		old_cword__h22546[15:0] };
      3'h4:
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d763 =
	      { old_cword__h22546[63:48],
		rg_st_amo_val[15:0],
		old_cword__h22546[31:0] };
      3'h6:
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d763 =
	      { rg_st_amo_val[15:0], old_cword__h22546[47:0] };
      default: IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d763 =
		   old_cword__h22546;
    endcase
  end
  always@(x1_avValue_pa__h6220 or old_cword__h22546 or rg_st_amo_val)
  begin
    case (x1_avValue_pa__h6220[2:0])
      3'h0:
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d754 =
	      { old_cword__h22546[63:8], rg_st_amo_val[7:0] };
      3'h1:
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d754 =
	      { old_cword__h22546[63:16],
		rg_st_amo_val[7:0],
		old_cword__h22546[7:0] };
      3'h2:
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d754 =
	      { old_cword__h22546[63:24],
		rg_st_amo_val[7:0],
		old_cword__h22546[15:0] };
      3'h3:
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d754 =
	      { old_cword__h22546[63:32],
		rg_st_amo_val[7:0],
		old_cword__h22546[23:0] };
      3'h4:
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d754 =
	      { old_cword__h22546[63:40],
		rg_st_amo_val[7:0],
		old_cword__h22546[31:0] };
      3'h5:
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d754 =
	      { old_cword__h22546[63:48],
		rg_st_amo_val[7:0],
		old_cword__h22546[39:0] };
      3'h6:
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d754 =
	      { old_cword__h22546[63:56],
		rg_st_amo_val[7:0],
		old_cword__h22546[47:0] };
      3'h7:
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d754 =
	      { rg_st_amo_val[7:0], old_cword__h22546[55:0] };
    endcase
  end
  always@(x1_avValue_pa__h6220 or old_cword__h22546 or rg_st_amo_val)
  begin
    case (x1_avValue_pa__h6220[2:0])
      3'h0:
	  CASE_x1_avValue_pa220_BITS_2_TO_0_0x0_old_cwor_ETC__q31 =
	      { old_cword__h22546[63:32], rg_st_amo_val[31:0] };
      3'h4:
	  CASE_x1_avValue_pa220_BITS_2_TO_0_0x0_old_cwor_ETC__q31 =
	      { rg_st_amo_val[31:0], old_cword__h22546[31:0] };
      default: CASE_x1_avValue_pa220_BITS_2_TO_0_0x0_old_cwor_ETC__q31 =
		   old_cword__h22546;
    endcase
  end
  always@(rg_f3 or
	  old_cword__h22546 or
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d754 or
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d763 or
	  CASE_x1_avValue_pa220_BITS_2_TO_0_0x0_old_cwor_ETC__q31 or
	  rg_st_amo_val)
  begin
    case (rg_f3)
      3'b0:
	  n__h22557 =
	      IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d754;
      3'b001:
	  n__h22557 =
	      IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d763;
      3'b010:
	  n__h22557 = CASE_x1_avValue_pa220_BITS_2_TO_0_0x0_old_cwor_ETC__q31;
      3'b011: n__h22557 = rg_st_amo_val;
      default: n__h22557 = old_cword__h22546;
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d595 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d623 or
	  IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_01_BITS__ETC__q32 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_ra_ETC___d642 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d611 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d631 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d641)
  begin
    case (rg_f3)
      3'b0:
	  IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_IF_rg_f3_15_E_ETC___d710 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d595;
      3'b001:
	  IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_IF_rg_f3_15_E_ETC___d710 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d623;
      3'b010:
	  IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_IF_rg_f3_15_E_ETC___d710 =
	      { {32{IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_01_BITS__ETC__q32[31]}},
		IF_rg_f3_15_EQ_0b0_16_THEN_IF_rg_addr_01_BITS__ETC__q32 };
      3'b011:
	  IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_IF_rg_f3_15_E_ETC___d710 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_ra_ETC___d642;
      3'b100:
	  IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_IF_rg_f3_15_E_ETC___d710 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d611;
      3'b101:
	  IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_IF_rg_f3_15_E_ETC___d710 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d631;
      3'b110:
	  IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_IF_rg_f3_15_E_ETC___d710 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d641;
      3'd7: IF_rg_f3_15_EQ_0b10_48_THEN_SEXT_IF_rg_f3_15_E_ETC___d710 = 64'd0;
    endcase
  end
  always@(rg_amo_funct7 or
	  new_st_val__h26732 or
	  new_st_val__h25724 or
	  w2__h36853 or
	  new_st_val__h26704 or
	  new_st_val__h26712 or
	  new_st_val__h26708 or
	  new_st_val__h26727 or new_st_val__h26716 or new_st_val__h26721)
  begin
    case (rg_amo_funct7[6:2])
      5'b0: _theResult_____2__h25629 = new_st_val__h25724;
      5'b00001: _theResult_____2__h25629 = w2__h36853;
      5'b00100: _theResult_____2__h25629 = new_st_val__h26704;
      5'b01000: _theResult_____2__h25629 = new_st_val__h26712;
      5'b01100: _theResult_____2__h25629 = new_st_val__h26708;
      5'b10000: _theResult_____2__h25629 = new_st_val__h26727;
      5'b11000: _theResult_____2__h25629 = new_st_val__h26716;
      5'b11100: _theResult_____2__h25629 = new_st_val__h26721;
      default: _theResult_____2__h25629 = new_st_val__h26732;
    endcase
  end
  always@(x1_avValue_pa__h6220 or old_cword__h22546 or new_st_val__h25327)
  begin
    case (x1_avValue_pa__h6220[2:0])
      3'h0:
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d831 =
	      { old_cword__h22546[63:16], new_st_val__h25327[15:0] };
      3'h2:
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d831 =
	      { old_cword__h22546[63:32],
		new_st_val__h25327[15:0],
		old_cword__h22546[15:0] };
      3'h4:
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d831 =
	      { old_cword__h22546[63:48],
		new_st_val__h25327[15:0],
		old_cword__h22546[31:0] };
      3'h6:
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d831 =
	      { new_st_val__h25327[15:0], old_cword__h22546[47:0] };
      default: IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d831 =
		   old_cword__h22546;
    endcase
  end
  always@(x1_avValue_pa__h6220 or old_cword__h22546 or new_st_val__h25327)
  begin
    case (x1_avValue_pa__h6220[2:0])
      3'h0:
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d822 =
	      { old_cword__h22546[63:8], new_st_val__h25327[7:0] };
      3'h1:
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d822 =
	      { old_cword__h22546[63:16],
		new_st_val__h25327[7:0],
		old_cword__h22546[7:0] };
      3'h2:
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d822 =
	      { old_cword__h22546[63:24],
		new_st_val__h25327[7:0],
		old_cword__h22546[15:0] };
      3'h3:
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d822 =
	      { old_cword__h22546[63:32],
		new_st_val__h25327[7:0],
		old_cword__h22546[23:0] };
      3'h4:
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d822 =
	      { old_cword__h22546[63:40],
		new_st_val__h25327[7:0],
		old_cword__h22546[31:0] };
      3'h5:
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d822 =
	      { old_cword__h22546[63:48],
		new_st_val__h25327[7:0],
		old_cword__h22546[39:0] };
      3'h6:
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d822 =
	      { old_cword__h22546[63:56],
		new_st_val__h25327[7:0],
		old_cword__h22546[47:0] };
      3'h7:
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d822 =
	      { new_st_val__h25327[7:0], old_cword__h22546[55:0] };
    endcase
  end
  always@(x1_avValue_pa__h6220 or old_cword__h22546 or new_st_val__h25327)
  begin
    case (x1_avValue_pa__h6220[2:0])
      3'h0:
	  CASE_x1_avValue_pa220_BITS_2_TO_0_0x0_old_cwor_ETC__q34 =
	      { old_cword__h22546[63:32], new_st_val__h25327[31:0] };
      3'h4:
	  CASE_x1_avValue_pa220_BITS_2_TO_0_0x0_old_cwor_ETC__q34 =
	      { new_st_val__h25327[31:0], old_cword__h22546[31:0] };
      default: CASE_x1_avValue_pa220_BITS_2_TO_0_0x0_old_cwor_ETC__q34 =
		   old_cword__h22546;
    endcase
  end
  always@(rg_f3 or
	  old_cword__h22546 or
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d822 or
	  IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d831 or
	  CASE_x1_avValue_pa220_BITS_2_TO_0_0x0_old_cwor_ETC__q34 or
	  new_st_val__h25327)
  begin
    case (rg_f3)
      3'b0:
	  n__h25491 =
	      IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d822;
      3'b001:
	  n__h25491 =
	      IF_IF_rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_ETC___d831;
      3'b010:
	  n__h25491 = CASE_x1_avValue_pa220_BITS_2_TO_0_0x0_old_cwor_ETC__q34;
      3'b011: n__h25491 = new_st_val__h25327;
      default: n__h25491 = old_cword__h22546;
    endcase
  end
  always@(rg_addr or
	  result__h35257 or
	  result__h35284 or result__h35311 or result__h35338)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1189 =
	      result__h35257;
      3'h2:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1189 =
	      result__h35284;
      3'h4:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1189 =
	      result__h35311;
      3'h6:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1189 =
	      result__h35338;
      default: IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1189 =
		   64'd0;
    endcase
  end
  always@(rg_addr or
	  result__h35136 or
	  result__h35163 or result__h35190 or result__h35217)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1181 =
	      result__h35136;
      3'h2:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1181 =
	      result__h35163;
      3'h4:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1181 =
	      result__h35190;
      3'h6:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1181 =
	      result__h35217;
      default: IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1181 =
		   64'd0;
    endcase
  end
  always@(rg_addr or
	  result__h34903 or
	  result__h34930 or
	  result__h34957 or
	  result__h34984 or
	  result__h35011 or
	  result__h35038 or result__h35065 or result__h35092)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1169 =
	      result__h34903;
      3'h1:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1169 =
	      result__h34930;
      3'h2:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1169 =
	      result__h34957;
      3'h3:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1169 =
	      result__h34984;
      3'h4:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1169 =
	      result__h35011;
      3'h5:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1169 =
	      result__h35038;
      3'h6:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1169 =
	      result__h35065;
      3'h7:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1169 =
	      result__h35092;
    endcase
  end
  always@(rg_addr or
	  result__h34667 or
	  result__h34697 or
	  result__h34724 or
	  result__h34751 or
	  result__h34778 or
	  result__h34805 or result__h34832 or result__h34859)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1153 =
	      result__h34667;
      3'h1:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1153 =
	      result__h34697;
      3'h2:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1153 =
	      result__h34724;
      3'h3:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1153 =
	      result__h34751;
      3'h4:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1153 =
	      result__h34778;
      3'h5:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1153 =
	      result__h34805;
      3'h6:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1153 =
	      result__h34832;
      3'h7:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1153 =
	      result__h34859;
    endcase
  end
  always@(rg_addr or result__h35378 or result__h35405)
  begin
    case (rg_addr[2:0])
      3'h0:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result5378_0x4_re_ETC__q35 =
	      result__h35378;
      3'h4:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result5378_0x4_re_ETC__q35 =
	      result__h35405;
      default: CASE_rg_addr_BITS_2_TO_0_0x0_result5378_0x4_re_ETC__q35 =
		   64'd0;
    endcase
  end
  always@(rg_addr or result__h35443 or result__h35470)
  begin
    case (rg_addr[2:0])
      3'h0:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result5443_0x4_re_ETC__q36 =
	      result__h35443;
      3'h4:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result5443_0x4_re_ETC__q36 =
	      result__h35470;
      default: CASE_rg_addr_BITS_2_TO_0_0x0_result5443_0x4_re_ETC__q36 =
		   64'd0;
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1153 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1181 or
	  CASE_rg_addr_BITS_2_TO_0_0x0_result5378_0x4_re_ETC__q35 or
	  rg_addr or
	  master_xactor_f_rd_data$D_OUT or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1169 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1189 or
	  CASE_rg_addr_BITS_2_TO_0_0x0_result5443_0x4_re_ETC__q36)
  begin
    case (rg_f3)
      3'b0:
	  ld_val__h34607 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1153;
      3'b001:
	  ld_val__h34607 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1181;
      3'b010:
	  ld_val__h34607 =
	      CASE_rg_addr_BITS_2_TO_0_0x0_result5378_0x4_re_ETC__q35;
      3'b011:
	  ld_val__h34607 =
	      (rg_addr[2:0] == 3'h0) ?
		master_xactor_f_rd_data$D_OUT[66:3] :
		64'd0;
      3'b100:
	  ld_val__h34607 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1169;
      3'b101:
	  ld_val__h34607 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1189;
      3'b110:
	  ld_val__h34607 =
	      CASE_rg_addr_BITS_2_TO_0_0x0_result5443_0x4_re_ETC__q36;
      3'd7: ld_val__h34607 = 64'd0;
    endcase
  end
  always@(rg_addr or result__h38721 or result__h38749)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1306 =
	      result__h38721;
      3'h4:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1306 =
	      result__h38749;
      default: IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1306 =
		   64'd0;
    endcase
  end
  always@(rg_addr or
	  result__h38529 or
	  result__h38557 or result__h38585 or result__h38613)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1296 =
	      result__h38529;
      3'h2:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1296 =
	      result__h38557;
      3'h4:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1296 =
	      result__h38585;
      3'h6:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1296 =
	      result__h38613;
      default: IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1296 =
		   64'd0;
    endcase
  end
  always@(rg_addr or
	  result__h38404 or
	  result__h38432 or result__h38460 or result__h38488)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1288 =
	      result__h38404;
      3'h2:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1288 =
	      result__h38432;
      3'h4:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1288 =
	      result__h38460;
      3'h6:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1288 =
	      result__h38488;
      default: IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1288 =
		   64'd0;
    endcase
  end
  always@(rg_addr or
	  result__h38163 or
	  result__h38191 or
	  result__h38219 or
	  result__h38247 or
	  result__h38275 or
	  result__h38303 or result__h38331 or result__h38359)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1276 =
	      result__h38163;
      3'h1:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1276 =
	      result__h38191;
      3'h2:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1276 =
	      result__h38219;
      3'h3:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1276 =
	      result__h38247;
      3'h4:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1276 =
	      result__h38275;
      3'h5:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1276 =
	      result__h38303;
      3'h6:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1276 =
	      result__h38331;
      3'h7:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1276 =
	      result__h38359;
    endcase
  end
  always@(rg_addr or
	  result__h37042 or
	  result__h37950 or
	  result__h37978 or
	  result__h38006 or
	  result__h38034 or
	  result__h38062 or result__h38090 or result__h38118)
  begin
    case (rg_addr[2:0])
      3'h0:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1260 =
	      result__h37042;
      3'h1:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1260 =
	      result__h37950;
      3'h2:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1260 =
	      result__h37978;
      3'h3:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1260 =
	      result__h38006;
      3'h4:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1260 =
	      result__h38034;
      3'h5:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1260 =
	      result__h38062;
      3'h6:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1260 =
	      result__h38090;
      3'h7:
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1260 =
	      result__h38118;
    endcase
  end
  always@(rg_addr or result__h38654 or result__h38682)
  begin
    case (rg_addr[2:0])
      3'h0:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result8654_0x4_re_ETC__q51 =
	      result__h38654;
      3'h4:
	  CASE_rg_addr_BITS_2_TO_0_0x0_result8654_0x4_re_ETC__q51 =
	      result__h38682;
      default: CASE_rg_addr_BITS_2_TO_0_0x0_result8654_0x4_re_ETC__q51 =
		   64'd0;
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1260 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1288 or
	  CASE_rg_addr_BITS_2_TO_0_0x0_result8654_0x4_re_ETC__q51 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_IF_ETC___d1307 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1276 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1296 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1306)
  begin
    case (rg_f3)
      3'b0:
	  w1__h36847 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1260;
      3'b001:
	  w1__h36847 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1288;
      3'b010:
	  w1__h36847 =
	      CASE_rg_addr_BITS_2_TO_0_0x0_result8654_0x4_re_ETC__q51;
      3'b011:
	  w1__h36847 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_IF_ETC___d1307;
      3'b100:
	  w1__h36847 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1276;
      3'b101:
	  w1__h36847 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1296;
      3'b110:
	  w1__h36847 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1306;
      3'd7: w1__h36847 = 64'd0;
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1260 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1288 or
	  w1___1__h36922 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_IF_ETC___d1307 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1276 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1296 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1306)
  begin
    case (rg_f3)
      3'b0:
	  w1__h36851 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1260;
      3'b001:
	  w1__h36851 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1288;
      3'b010: w1__h36851 = w1___1__h36922;
      3'b011:
	  w1__h36851 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_IF_ETC___d1307;
      3'b100:
	  w1__h36851 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1276;
      3'b101:
	  w1__h36851 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1296;
      3'b110:
	  w1__h36851 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1306;
      3'd7: w1__h36851 = 64'd0;
    endcase
  end
  always@(rg_f3 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1260 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1288 or
	  w16847_BITS_31_TO_0__q52 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_IF_ETC___d1307 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1276 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1296 or
	  IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1306)
  begin
    case (rg_f3)
      3'b0:
	  new_ld_val__h36813 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1260;
      3'b001:
	  new_ld_val__h36813 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_SE_ETC___d1288;
      3'b010:
	  new_ld_val__h36813 =
	      { {32{w16847_BITS_31_TO_0__q52[31]}},
		w16847_BITS_31_TO_0__q52 };
      3'b011:
	  new_ld_val__h36813 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_IF_ETC___d1307;
      3'b100:
	  new_ld_val__h36813 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1276;
      3'b101:
	  new_ld_val__h36813 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1296;
      3'b110:
	  new_ld_val__h36813 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_0__ETC___d1306;
      3'd7: new_ld_val__h36813 = 64'd0;
    endcase
  end
  always@(rg_amo_funct7 or
	  new_st_val__h38842 or
	  new_st_val__h36954 or
	  w2__h36853 or
	  new_st_val__h38814 or
	  new_st_val__h38822 or
	  new_st_val__h38818 or
	  new_st_val__h38837 or new_st_val__h38826 or new_st_val__h38831)
  begin
    case (rg_amo_funct7[6:2])
      5'b0: _theResult_____2__h36859 = new_st_val__h36954;
      5'b00001: _theResult_____2__h36859 = w2__h36853;
      5'b00100: _theResult_____2__h36859 = new_st_val__h38814;
      5'b01000: _theResult_____2__h36859 = new_st_val__h38822;
      5'b01100: _theResult_____2__h36859 = new_st_val__h38818;
      5'b10000: _theResult_____2__h36859 = new_st_val__h38837;
      5'b11000: _theResult_____2__h36859 = new_st_val__h38826;
      5'b11100: _theResult_____2__h36859 = new_st_val__h38831;
      default: _theResult_____2__h36859 = new_st_val__h38842;
    endcase
  end
  always@(rg_f3 or IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_1__ETC___d657)
  begin
    case (rg_f3)
      3'b0, 3'b001, 3'b010, 3'b011, 3'b100, 3'b101, 3'b110:
	  CASE_rg_f3_0b0_IF_rg_addr_01_BITS_2_TO_0_19_EQ_ETC__q53 =
	      IF_rg_addr_01_BITS_2_TO_0_19_EQ_0x0_20_THEN_1__ETC___d657;
      3'd7: CASE_rg_f3_0b0_IF_rg_addr_01_BITS_2_TO_0_19_EQ_ETC__q53 = 64'd0;
    endcase
  end

  // handling of inlined registers

  always@(posedge CLK)
  begin
    if (RST_N == `BSV_RESET_VALUE)
      begin
        cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
	ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY 4'd0;
	rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY 6'd0;
	rg_ddr4_ready <= `BSV_ASSIGNMENT_DELAY 1'd0;
	rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY 1'd0;
	rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY 1'd0;
	rg_state <= `BSV_ASSIGNMENT_DELAY 4'd0;
	rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY 64'h0000000080001000;
	rg_tohost_value <= `BSV_ASSIGNMENT_DELAY 64'd0;
	rg_watch_tohost <= `BSV_ASSIGNMENT_DELAY 1'd0;
	rg_wr_rsp_err <= `BSV_ASSIGNMENT_DELAY 1'd0;
      end
    else
      begin
        if (cfg_verbosity$EN)
	  cfg_verbosity <= `BSV_ASSIGNMENT_DELAY cfg_verbosity$D_IN;
	if (ctr_wr_rsps_pending_crg$EN)
	  ctr_wr_rsps_pending_crg <= `BSV_ASSIGNMENT_DELAY
	      ctr_wr_rsps_pending_crg$D_IN;
	if (rg_cset_in_cache$EN)
	  rg_cset_in_cache <= `BSV_ASSIGNMENT_DELAY rg_cset_in_cache$D_IN;
	if (rg_ddr4_ready$EN)
	  rg_ddr4_ready <= `BSV_ASSIGNMENT_DELAY rg_ddr4_ready$D_IN;
	if (rg_lower_word32_full$EN)
	  rg_lower_word32_full <= `BSV_ASSIGNMENT_DELAY
	      rg_lower_word32_full$D_IN;
	if (rg_lrsc_valid$EN)
	  rg_lrsc_valid <= `BSV_ASSIGNMENT_DELAY rg_lrsc_valid$D_IN;
	if (rg_state$EN) rg_state <= `BSV_ASSIGNMENT_DELAY rg_state$D_IN;
	if (rg_tohost_addr$EN)
	  rg_tohost_addr <= `BSV_ASSIGNMENT_DELAY rg_tohost_addr$D_IN;
	if (rg_tohost_value$EN)
	  rg_tohost_value <= `BSV_ASSIGNMENT_DELAY rg_tohost_value$D_IN;
	if (rg_watch_tohost$EN)
	  rg_watch_tohost <= `BSV_ASSIGNMENT_DELAY rg_watch_tohost$D_IN;
	if (rg_wr_rsp_err$EN)
	  rg_wr_rsp_err <= `BSV_ASSIGNMENT_DELAY rg_wr_rsp_err$D_IN;
      end
    if (rg_addr$EN) rg_addr <= `BSV_ASSIGNMENT_DELAY rg_addr$D_IN;
    if (rg_amo_funct7$EN)
      rg_amo_funct7 <= `BSV_ASSIGNMENT_DELAY rg_amo_funct7$D_IN;
    if (rg_cset_cword_in_cache$EN)
      rg_cset_cword_in_cache <= `BSV_ASSIGNMENT_DELAY
	  rg_cset_cword_in_cache$D_IN;
    if (rg_error_during_refill$EN)
      rg_error_during_refill <= `BSV_ASSIGNMENT_DELAY
	  rg_error_during_refill$D_IN;
    if (rg_exc_code$EN) rg_exc_code <= `BSV_ASSIGNMENT_DELAY rg_exc_code$D_IN;
    if (rg_f3$EN) rg_f3 <= `BSV_ASSIGNMENT_DELAY rg_f3$D_IN;
    if (rg_ld_val$EN) rg_ld_val <= `BSV_ASSIGNMENT_DELAY rg_ld_val$D_IN;
    if (rg_lower_word32$EN)
      rg_lower_word32 <= `BSV_ASSIGNMENT_DELAY rg_lower_word32$D_IN;
    if (rg_lrsc_pa$EN) rg_lrsc_pa <= `BSV_ASSIGNMENT_DELAY rg_lrsc_pa$D_IN;
    if (rg_mstatus_MXR$EN)
      rg_mstatus_MXR <= `BSV_ASSIGNMENT_DELAY rg_mstatus_MXR$D_IN;
    if (rg_op$EN) rg_op <= `BSV_ASSIGNMENT_DELAY rg_op$D_IN;
    if (rg_pa$EN) rg_pa <= `BSV_ASSIGNMENT_DELAY rg_pa$D_IN;
    if (rg_priv$EN) rg_priv <= `BSV_ASSIGNMENT_DELAY rg_priv$D_IN;
    if (rg_pte_pa$EN) rg_pte_pa <= `BSV_ASSIGNMENT_DELAY rg_pte_pa$D_IN;
    if (rg_satp$EN) rg_satp <= `BSV_ASSIGNMENT_DELAY rg_satp$D_IN;
    if (rg_sstatus_SUM$EN)
      rg_sstatus_SUM <= `BSV_ASSIGNMENT_DELAY rg_sstatus_SUM$D_IN;
    if (rg_st_amo_val$EN)
      rg_st_amo_val <= `BSV_ASSIGNMENT_DELAY rg_st_amo_val$D_IN;
    if (rg_victim_way$EN)
      rg_victim_way <= `BSV_ASSIGNMENT_DELAY rg_victim_way$D_IN;
  end

  // synopsys translate_off
  `ifdef BSV_NO_INITIAL_BLOCKS
  `else // not BSV_NO_INITIAL_BLOCKS
  initial
  begin
    cfg_verbosity = 4'hA;
    ctr_wr_rsps_pending_crg = 4'hA;
    rg_addr = 32'hAAAAAAAA;
    rg_amo_funct7 = 7'h2A;
    rg_cset_cword_in_cache = 9'h0AA;
    rg_cset_in_cache = 6'h2A;
    rg_ddr4_ready = 1'h0;
    rg_error_during_refill = 1'h0;
    rg_exc_code = 4'hA;
    rg_f3 = 3'h2;
    rg_ld_val = 64'hAAAAAAAAAAAAAAAA;
    rg_lower_word32 = 32'hAAAAAAAA;
    rg_lower_word32_full = 1'h0;
    rg_lrsc_pa = 34'h2AAAAAAAA;
    rg_lrsc_valid = 1'h0;
    rg_mstatus_MXR = 1'h0;
    rg_op = 2'h2;
    rg_pa = 34'h2AAAAAAAA;
    rg_priv = 2'h2;
    rg_pte_pa = 34'h2AAAAAAAA;
    rg_satp = 32'hAAAAAAAA;
    rg_sstatus_SUM = 1'h0;
    rg_st_amo_val = 64'hAAAAAAAAAAAAAAAA;
    rg_state = 4'hA;
    rg_tohost_addr = 64'hAAAAAAAAAAAAAAAA;
    rg_tohost_value = 64'hAAAAAAAAAAAAAAAA;
    rg_victim_way = 1'h0;
    rg_watch_tohost = 1'h0;
    rg_wr_rsp_err = 1'h0;
  end
  `endif // BSV_NO_INITIAL_BLOCKS
  // synopsys translate_on

  // handling of system tasks

  // synopsys translate_off
  always@(negedge CLK)
  begin
    #0;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("            To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("AXI4_Wr_Addr { ", "awid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "awaddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", mem_req_wr_addr_awaddr__h2978);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "awlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "awsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", x__h3025);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "awburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "awlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "awcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "awprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "awqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "awregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "awuser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("                       ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("AXI4_Wr_Data { ", "wdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", mem_req_wr_data_wdata__h3204);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "wstrb: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", mem_req_wr_data_wstrb__h3205);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "wlast: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "wuser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_fabric_send_write_req &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
	  cfg_verbosity != 4'd0 &&
	  !f_reset_reqs$D_OUT)
	begin
	  v__h4706 = $stime;
	  #0;
	end
    v__h4700 = v__h4706 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
	  cfg_verbosity != 4'd0 &&
	  !f_reset_reqs$D_OUT)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY",
		   v__h4700,
		   "D_MMU_Cache",
		   $signed(32'd64),
		   $signed(32'd2));
	else
	  $display("%0d: %s.rl_reset: %0d sets x %0d ways: all tag states reset to CTAG_EMPTY",
		   v__h4700,
		   "I_MMU_Cache",
		   $signed(32'd64),
		   $signed(32'd2));
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
	  !cfg_verbosity_read__2_ULE_1___d43 &&
	  f_reset_reqs$D_OUT)
	begin
	  v__h4805 = $stime;
	  #0;
	end
    v__h4799 = v__h4805 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_reset && rg_cset_in_cache == 6'd63 &&
	  !cfg_verbosity_read__2_ULE_1___d43 &&
	  f_reset_reqs$D_OUT)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_reset: Flushed", v__h4799, "D_MMU_Cache");
	else
	  $display("%0d: %s.rl_reset: Flushed", v__h4799, "I_MMU_Cache");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	begin
	  v__h4955 = $stime;
	  #0;
	end
    v__h4949 = v__h4955 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	if (dmem_not_imem)
	  $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h",
		   v__h4949,
		   "D_MMU_Cache",
		   rg_addr);
	else
	  $display("%0d: %s: rl_probe_and_immed_rsp; eaddr %0h",
		   v__h4949,
		   "I_MMU_Cache",
		   rg_addr);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43 &&
	  rg_satp[31])
	$display("        Priv:%0d  SATP:{mode %0d asid %0h pa %0h}  VA:%0h.%0h.%0h",
		 rg_priv,
		 rg_satp[31],
		 rg_satp[30:22],
		 satp_pa__h1960,
		 rg_addr[31:22],
		 rg_addr[21:12],
		 rg_addr[11:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$display("        eaddr = {CTag 0x%0h  CSet 0x%0h  Word64 0x%0h  Byte 0x%0h}",
		 { 2'd0, rg_addr[31:12] },
		 rg_addr[11:6],
		 rg_addr[5:3],
		 rg_addr[2:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("        CSet 0x%0x: (state, tag):", rg_addr[11:6]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(" (");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43 &&
	  ram_state_and_ctag_cset$DOB[22])
	$write("CTAG_CLEAN");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43 &&
	  !ram_state_and_ctag_cset$DOB[22])
	$write("CTAG_EMPTY");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43 &&
	  ram_state_and_ctag_cset$DOB[22])
	$write(", 0x%0x", ram_state_and_ctag_cset$DOB[21:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43 &&
	  !ram_state_and_ctag_cset$DOB[22])
	$write(", --");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(")");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(" (");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43 &&
	  ram_state_and_ctag_cset$DOB[45])
	$write("CTAG_CLEAN");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43 &&
	  !ram_state_and_ctag_cset$DOB[45])
	$write("CTAG_EMPTY");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43 &&
	  ram_state_and_ctag_cset$DOB[45])
	$write(", 0x%0x", ram_state_and_ctag_cset$DOB[44:23]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43 &&
	  !ram_state_and_ctag_cset$DOB[45])
	$write(", --");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(")");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("        CSet 0x%0x, CWord 0x%0x: ",
	       rg_addr[11:6],
	       rg_addr[5:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(" 0x%0x", ram_cword_set$DOB[63:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(" 0x%0x", ram_cword_set$DOB[127:64]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("    TLB result: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("VM_Xlate_Result { ", "outcome: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43 &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d392)
	$write("VM_XLATE_OK");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43 &&
	  rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d395)
	$write("VM_XLATE_EXCEPTION");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43 &&
	  rg_priv_1_ULE_0b1___d92 &&
	  rg_satp[31] &&
	  !tlb$lookup[68])
	$write("VM_XLATE_TLB_MISS");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "pa: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", x1_avValue_pa__h6220);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "exc_code: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", x1_avValue_exc_code__h6221);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "pte_modified: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43 &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d407)
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43 &&
	  rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d417)
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "pte: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", x1_avValue_pte__h6223, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d417 &&
	  NOT_cfg_verbosity_read__2_ULT_2_44___d445)
	$display("    fa_record_pte_A_D_updates:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d417 &&
	  NOT_cfg_verbosity_read__2_ULT_2_44___d445)
	$write("      ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d417 &&
	  NOT_cfg_verbosity_read__2_ULT_2_44___d445)
	$write("TLB_Lookup_Result { ", "hit: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d417 &&
	  NOT_cfg_verbosity_read__2_ULT_2_44___d445)
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d417 &&
	  NOT_cfg_verbosity_read__2_ULT_2_44___d445)
	$write(", ", "pte: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d417 &&
	  NOT_cfg_verbosity_read__2_ULT_2_44___d445)
	$write("'h%h", tlb$lookup[67:36]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d417 &&
	  NOT_cfg_verbosity_read__2_ULT_2_44___d445)
	$write(", ", "pte_level: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d417 &&
	  NOT_cfg_verbosity_read__2_ULT_2_44___d445)
	$write("'h%h", tlb$lookup[35:34]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d417 &&
	  NOT_cfg_verbosity_read__2_ULT_2_44___d445)
	$write(", ", "pte_pa: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d417 &&
	  NOT_cfg_verbosity_read__2_ULT_2_44___d445)
	$write("'h%h", tlb$lookup[33:0], " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d417 &&
	  NOT_cfg_verbosity_read__2_ULT_2_44___d445)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d417 &&
	  NOT_cfg_verbosity_read__2_ULT_2_44___d445)
	$write("      ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d417 &&
	  NOT_cfg_verbosity_read__2_ULT_2_44___d445)
	$write("VM_Xlate_Result { ", "outcome: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d453)
	$write("VM_XLATE_OK");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d456)
	$write("VM_XLATE_EXCEPTION");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d417 &&
	  NOT_cfg_verbosity_read__2_ULT_2_44___d445)
	$write(", ", "pa: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d417 &&
	  NOT_cfg_verbosity_read__2_ULT_2_44___d445)
	$write("'h%h", x1_avValue_pa__h6220);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d417 &&
	  NOT_cfg_verbosity_read__2_ULT_2_44___d445)
	$write(", ", "exc_code: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d417 &&
	  NOT_cfg_verbosity_read__2_ULT_2_44___d445)
	$write("'h%h", x1_avValue_exc_code__h6221);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d417 &&
	  NOT_cfg_verbosity_read__2_ULT_2_44___d445)
	$write(", ", "pte_modified: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d456)
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d453)
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d417 &&
	  NOT_cfg_verbosity_read__2_ULT_2_44___d445)
	$write(", ", "pte: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d417 &&
	  NOT_cfg_verbosity_read__2_ULT_2_44___d445)
	$write("'h%h", x1_avValue_pte__h6223, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  rg_priv_1_ULE_0b1_2_AND_rg_satp_4_BIT_31_5_9_A_ETC___d417 &&
	  NOT_cfg_verbosity_read__2_ULT_2_44___d445)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d470)
	$display("    => IO_REQ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d476)
	$display("        ASSERTION ERROR: fn_test_cache_hit_or_miss: multiple hits in set at [%0d] and [%0d]",
		 $signed(32'd1),
		 1'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d672)
	begin
	  v__h21391 = $stime;
	  #0;
	end
    v__h21385 = v__h21391 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d672)
	if (dmem_not_imem)
	  $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
		   v__h21385,
		   "D_MMU_Cache",
		   rg_addr,
		   word64__h7644,
		   64'd0);
	else
	  $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
		   v__h21385,
		   "I_MMU_Cache",
		   rg_addr,
		   word64__h7644,
		   64'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d684)
	$display("        AMO LR: reserving PA 0x%0h", x1_avValue_pa__h6220);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d672)
	$display("        Read-hit: addr 0x%0h word64 0x%0h",
		 rg_addr,
		 word64__h7644);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d689)
	$display("        Read Miss: -> CACHE_START_REFILL.");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d697)
	$display("        AMO LR: cache refill: cancelling LR/SC reservation for PA 0x%0h",
		 rg_lrsc_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d856)
	$display("        ST: cancelling LR/SC reservation for PA",
		 x1_avValue_pa__h6220);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$lookup[68]) &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d862)
	$display("        AMO SC: fail: reserved addr 0x%0h, this address 0x%0h",
		 rg_lrsc_pa,
		 x1_avValue_pa__h6220);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$lookup[68]) &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d868)
	$display("        AMO SC: fail due to invalid LR/SC reservation");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d874)
	$display("        AMO SC result = %0d", lrsc_result__h21768);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d880)
	$display("        Write-Cache-Hit: pa 0x%0h word64 0x%0h",
		 x1_avValue_pa__h6220,
		 rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d880)
	$write("        New Word64_Set:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d880)
	$write("        CSet 0x%0x, CWord 0x%0x: ",
	       rg_addr[11:6],
	       rg_addr[5:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d880)
	$write(" 0x%0x",
	       IF_NOT_ram_state_and_ctag_cset_b_read__98_BIT__ETC___d774);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d880)
	$write(" 0x%0x",
	       IF_ram_state_and_ctag_cset_b_read__98_BIT_45_0_ETC___d773);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d880)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$lookup[68]) &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d885)
	$display("        Write-Cache-Miss: pa 0x%0h word64 0x%0h",
		 x1_avValue_pa__h6220,
		 rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d892)
	$display("        Write-Cache-Hit/Miss: eaddr 0x%0h word64 0x%0h",
		 rg_addr,
		 rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d892)
	$display("        => rl_write_response");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d898)
	begin
	  v__h25107 = $stime;
	  #0;
	end
    v__h25101 = v__h25107 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d898)
	if (dmem_not_imem)
	  $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
		   v__h25101,
		   "D_MMU_Cache",
		   rg_addr,
		   64'd1,
		   64'd0);
	else
	  $display("%0d: %s.drive_mem_rsp: addr 0x%0h ld_val 0x%0h st_amo_val 0x%0h",
		   v__h25101,
		   "I_MMU_Cache",
		   rg_addr,
		   64'd1,
		   64'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d898)
	$display("        AMO SC: Fail response for addr 0x%0h", rg_addr);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$lookup[68]) &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d904)
	$display("        AMO Miss: -> CACHE_START_REFILL.");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d910)
	$display("        AMO: addr 0x%0h amo_f7 0x%0h f3 %0d rs2_val 0x%0h",
		 rg_addr,
		 rg_amo_funct7,
		 rg_f3,
		 rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d910)
	$display("          PA 0x%0h ", x1_avValue_pa__h6220);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d910)
	$display("          Cache word64 0x%0h, load-result 0x%0h",
		 word64__h7644,
		 word64__h7644);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d910)
	$display("          0x%0h  op  0x%0h -> 0x%0h",
		 word64__h7644,
		 word64__h7644,
		 new_st_val__h25327);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d910)
	$write("          New Word64_Set:");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d910)
	$write("        CSet 0x%0x, CWord 0x%0x: ",
	       rg_addr[11:6],
	       rg_addr[5:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d910)
	$write(" 0x%0x",
	       IF_NOT_ram_state_and_ctag_cset_b_read__98_BIT__ETC___d842);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d910)
	$write(" 0x%0x",
	       IF_ram_state_and_ctag_cset_b_read__98_BIT_45_0_ETC___d841);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d910)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_probe_and_immed_rsp &&
	  (!rg_priv_1_ULE_0b1___d92 || !rg_satp[31] || tlb$lookup[68]) &&
	  NOT_rg_priv_1_ULE_0b1_2_3_OR_NOT_rg_satp_4_BIT_ETC___d915)
	$display("        AMO_op: cancelling LR/SC reservation for PA",
		 x1_avValue_pa__h6220);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_ma_ddr4_ready)
	begin
	  v__h41747 = $stime;
	  #0;
	end
    v__h41741 = v__h41747 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_ma_ddr4_ready)
	$display("%0d: %m.ma_ddr4_ready: Enabling MMU_Cache", v__h41741);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	begin
	  v__h28618 = $stime;
	  #0;
	end
    v__h28612 = v__h28618 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_start_tlb_refill for eaddr 0x%0h; req for level 1 PTE",
		   v__h28612,
		   "D_MMU_Cache",
		   rg_addr);
	else
	  $display("%0d: %s.rl_start_tlb_refill for eaddr 0x%0h; req for level 1 PTE",
		   v__h28612,
		   "I_MMU_Cache",
		   rg_addr);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("            To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("AXI4_Rd_Addr { ", "arid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "araddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", lev_1_pte_pa_w64_fa__h28673);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 3'b010);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "aruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_tlb_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d977)
	begin
	  v__h29551 = $stime;
	  #0;
	end
    v__h29545 = v__h29551 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d977)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
		   v__h29545,
		   "D_MMU_Cache",
		   rg_addr,
		   _theResult____h28937,
		   rg_pte_pa,
		   exc_code___1__h6621);
	else
	  $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
		   v__h29545,
		   "I_MMU_Cache",
		   rg_addr,
		   _theResult____h28937,
		   rg_pte_pa,
		   exc_code___1__h6621);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	begin
	  v__h29309 = $stime;
	  #0;
	end
    v__h29303 = v__h29309 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 0",
		   v__h29303,
		   "D_MMU_Cache",
		   rg_addr,
		   _theResult____h28937,
		   rg_pte_pa);
	else
	  $display("%0d: %s.rl_rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: continue to level 0",
		   v__h29303,
		   "I_MMU_Cache",
		   rg_addr,
		   _theResult____h28937,
		   rg_pte_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	$display("    Req for level 0 PTE");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	$write("            To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	$write("AXI4_Rd_Addr { ", "arid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	$write(", ", "araddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	$write("'h%h", lev_0_pte_pa_w64_fa__h29585);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	$write(", ", "arlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	$write("'h%h", 8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	$write(", ", "arsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	$write("'h%h", 3'b010);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	$write(", ", "arburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	$write(", ", "arlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	$write(", ", "arcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	$write(", ", "arprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	$write(", ", "arqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	$write(", ", "arregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	$write(", ", "aruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d1004)
	begin
	  v__h29949 = $stime;
	  #0;
	end
    v__h29943 = v__h29949 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d1004)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for megapage",
		   v__h29943,
		   "D_MMU_Cache",
		   rg_addr,
		   _theResult____h28937,
		   rg_pte_pa);
	else
	  $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE for megapage",
		   v__h29943,
		   "I_MMU_Cache",
		   rg_addr,
		   _theResult____h28937,
		   rg_pte_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d1004)
	$display("    Addr Space megapage pa: 0x%0h", lev_0_PTN_pa__h29581);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d1010)
	begin
	  v__h29837 = $stime;
	  #0;
	end
    v__h29831 = v__h29837 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d1010)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: megapage pte 0x%0h @ 0x%0h",
		   v__h29831,
		   "D_MMU_Cache",
		   rg_addr,
		   _theResult____h28937,
		   rg_pte_pa);
	else
	  $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: megapage pte 0x%0h @ 0x%0h",
		   v__h29831,
		   "I_MMU_Cache",
		   rg_addr,
		   _theResult____h28937,
		   rg_pte_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  _theResult____h28937[0] &&
	  (_theResult____h28937[1] || !_theResult____h28937[2]) &&
	  (_theResult____h28937[3] || _theResult____h28937[1]) &&
	  _theResult____h28937[19:10] != 10'd0)
	$display("    Invalid PTE: PPN [0] is not zero; page fault %0d",
		 exc_code___1__h6621);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	begin
	  v__h29480 = $stime;
	  #0;
	end
    v__h29474 = v__h29480 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_1 &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
		   v__h29474,
		   "D_MMU_Cache",
		   rg_addr,
		   rg_pte_pa,
		   access_exc_code__h2760);
	else
	  $display("%0d: %s.rl_ptw_level_1: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
		   v__h29474,
		   "I_MMU_Cache",
		   rg_addr,
		   rg_pte_pa,
		   access_exc_code__h2760);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d977)
	begin
	  v__h30488 = $stime;
	  #0;
	end
    v__h30482 = v__h30488 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d977)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
		   v__h30482,
		   "D_MMU_Cache",
		   rg_addr,
		   _theResult____h28937,
		   rg_pte_pa,
		   exc_code___1__h6621);
	else
	  $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: Invalid PTE; page fault %0d",
		   v__h30482,
		   "I_MMU_Cache",
		   rg_addr,
		   _theResult____h28937,
		   rg_pte_pa,
		   exc_code___1__h6621);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	begin
	  v__h30559 = $stime;
	  #0;
	end
    v__h30553 = v__h30559 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d985)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x50h: Not a leaf PTE; page fault %0d",
		   v__h30553,
		   "D_MMU_Cache",
		   rg_addr,
		   _theResult____h28937,
		   rg_pte_pa,
		   exc_code___1__h6621);
	else
	  $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x50h: Not a leaf PTE; page fault %0d",
		   v__h30553,
		   "I_MMU_Cache",
		   rg_addr,
		   _theResult____h28937,
		   rg_pte_pa,
		   exc_code___1__h6621);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d1036)
	begin
	  v__h30641 = $stime;
	  #0;
	end
    v__h30635 = v__h30641 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d1036)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE",
		   v__h30635,
		   "D_MMU_Cache",
		   rg_addr,
		   _theResult____h28937,
		   rg_pte_pa);
	else
	  $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte 0x%0h @ 0x%0h: leaf PTE",
		   v__h30635,
		   "I_MMU_Cache",
		   rg_addr,
		   _theResult____h28937,
		   rg_pte_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 &&
	  master_xactor_f_rd_data_first__36_BITS_2_TO_1__ETC___d1036)
	$display("    Addr Space page pa: 0x%0h", lev_0_PTN_pa__h29581);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	begin
	  v__h30417 = $stime;
	  #0;
	end
    v__h30411 = v__h30417 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_ptw_level_0 &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
		   v__h30411,
		   "D_MMU_Cache",
		   rg_addr,
		   rg_pte_pa,
		   access_exc_code__h2760);
	else
	  $display("%0d: %s.rl_ptw_level_0: for eaddr 0x%0h: pte_pa 0x%0h: FABRIC_RSP_ERR: access exception %0d",
		   v__h30411,
		   "I_MMU_Cache",
		   rg_addr,
		   rg_pte_pa,
		   access_exc_code__h2760);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	begin
	  v__h30766 = $stime;
	  #0;
	end
    v__h30760 = v__h30766 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_start_cache_refill: ",
		   v__h30760,
		   "D_MMU_Cache");
	else
	  $display("%0d: %s.rl_start_cache_refill: ",
		   v__h30760,
		   "I_MMU_Cache");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("    To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("AXI4_Rd_Addr { ", "arid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "araddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", cline_fabric_addr__h30819);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 8'd7);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 3'b011);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "aruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_cache_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$display("    Victim way %0d; => CACHE_REFILL", tmp__h30959[0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__2_ULE_2_058___d1059)
	begin
	  v__h31457 = $stime;
	  #0;
	end
    v__h31451 = v__h31457 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__2_ULE_2_058___d1059)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_cache_refill_rsps_loop:",
		   v__h31451,
		   "D_MMU_Cache");
	else
	  $display("%0d: %s.rl_cache_refill_rsps_loop:",
		   v__h31451,
		   "I_MMU_Cache");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__2_ULE_2_058___d1059)
	$write("        ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__2_ULE_2_058___d1059)
	$write("AXI4_Rd_Data { ", "rid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__2_ULE_2_058___d1059)
	$write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__2_ULE_2_058___d1059)
	$write(", ", "rdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__2_ULE_2_058___d1059)
	$write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__2_ULE_2_058___d1059)
	$write(", ", "rresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__2_ULE_2_058___d1059)
	$write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__2_ULE_2_058___d1059)
	$write(", ", "rlast: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__2_ULE_2_058___d1059 &&
	  master_xactor_f_rd_data$D_OUT[0])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__2_ULE_2_058___d1059 &&
	  !master_xactor_f_rd_data$D_OUT[0])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__2_ULE_2_058___d1059)
	$write(", ", "ruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__2_ULE_2_058___d1059)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__2_ULE_2_058___d1059)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	begin
	  v__h31679 = $stime;
	  #0;
	end
    v__h31673 = v__h31679 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d",
		   v__h31673,
		   "D_MMU_Cache",
		   access_exc_code__h2760);
	else
	  $display("%0d: %s.rl_cache_refill_rsps_loop: FABRIC_RSP_ERR: raising access exception %0d",
		   v__h31673,
		   "I_MMU_Cache",
		   access_exc_code__h2760);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  rg_cset_cword_in_cache[2:0] == 3'd7 &&
	  (master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 ||
	   rg_error_during_refill) &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$display("    => MODULE_EXCEPTION_RSP");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  rg_cset_cword_in_cache[2:0] == 3'd7 &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  !rg_error_during_refill &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$display("    => CACHE_REREQ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__2_ULE_2_058___d1059)
	$display("        Updating Cache cword_set 0x%0h, cword_in_cline %0d) old => new",
		 rg_cset_cword_in_cache,
		 rg_cset_cword_in_cache[2:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__2_ULE_2_058___d1059)
	$write("        CSet 0x%0x, CWord 0x%0x: ",
	       rg_addr[11:6],
	       rg_cset_cword_in_cache[2:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__2_ULE_2_058___d1059)
	$write(" 0x%0x", ram_cword_set$DOB[63:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__2_ULE_2_058___d1059)
	$write(" 0x%0x", ram_cword_set$DOB[127:64]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__2_ULE_2_058___d1059)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__2_ULE_2_058___d1059)
	$write("        CSet 0x%0x, CWord 0x%0x: ",
	       rg_addr[11:6],
	       rg_cset_cword_in_cache[2:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__2_ULE_2_058___d1059)
	$write(" 0x%0x",
	       rg_victim_way ?
		 ram_cword_set$DOB[63:0] :
		 master_xactor_f_rd_data$D_OUT[66:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__2_ULE_2_058___d1059)
	$write(" 0x%0x",
	       rg_victim_way ?
		 master_xactor_f_rd_data$D_OUT[66:3] :
		 ram_cword_set$DOB[127:64]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_cache_refill_rsps_loop &&
	  NOT_cfg_verbosity_read__2_ULE_2_058___d1059)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_rereq && !cfg_verbosity_read__2_ULE_1___d43)
	$display("    fa_req_ram_B tagCSet [0x%0x] cword_set [0x%0d]",
		 rg_addr[11:6],
		 rg_addr[11:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_set_watch_tohost)
	begin
	  v__h41679 = $stime;
	  #0;
	end
    v__h41673 = v__h41679 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_set_watch_tohost)
	$display("%0d: %m.set_watch_tohost: watch %0d, addr %0h",
		 v__h41673,
		 set_watch_tohost_watch_tohost,
		 set_watch_tohost_tohost_addr);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__2_ULE_1___d43)
	begin
	  v__h34148 = $stime;
	  #0;
	end
    v__h34142 = v__h34148 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__2_ULE_1___d43)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h  paddr %0h",
		   v__h34142,
		   "D_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa);
	else
	  $display("%0d: %s.rl_io_read_req; f3 0x%0h vaddr %0h  paddr %0h",
		   v__h34142,
		   "I_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("            To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("AXI4_Rd_Addr { ", "arid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "araddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", fabric_addr__h36270);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", value__h36399);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "aruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__2_ULE_1___d43)
	begin
	  v__h34498 = $stime;
	  #0;
	end
    v__h34492 = v__h34498 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__2_ULE_1___d43)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h  paddr 0x%0h",
		   v__h34492,
		   "D_MMU_Cache",
		   rg_addr,
		   rg_pa);
	else
	  $display("%0d: %s.rl_io_read_rsp: vaddr 0x%0h  paddr 0x%0h",
		   v__h34492,
		   "I_MMU_Cache",
		   rg_addr,
		   rg_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__2_ULE_1___d43)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__2_ULE_1___d43)
	$write("AXI4_Rd_Data { ", "rid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "rdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "rresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "rlast: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__2_ULE_1___d43 &&
	  master_xactor_f_rd_data$D_OUT[0])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__2_ULE_1___d43 &&
	  !master_xactor_f_rd_data$D_OUT[0])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "ruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp && !cfg_verbosity_read__2_ULE_1___d43)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	begin
	  v__h35598 = $stime;
	  #0;
	end
    v__h35592 = v__h35598 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	if (dmem_not_imem)
	  $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
		   v__h35592,
		   "D_MMU_Cache",
		   rg_addr,
		   ld_val__h34607);
	else
	  $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
		   v__h35592,
		   "I_MMU_Cache",
		   rg_addr,
		   ld_val__h34607);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	begin
	  v__h35705 = $stime;
	  #0;
	end
    v__h35699 = v__h35705 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT",
		   v__h35699,
		   "D_MMU_Cache");
	else
	  $display("%0d: %s.rl_io_read_rsp: FABRIC_RSP_ERR: raising trap LOAD_ACCESS_FAULT",
		   v__h35699,
		   "I_MMU_Cache");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_maintain_io_read_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	begin
	  v__h35810 = $stime;
	  #0;
	end
    v__h35804 = v__h35810 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_maintain_io_read_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	if (dmem_not_imem)
	  $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
		   v__h35804,
		   "D_MMU_Cache",
		   rg_addr,
		   rg_ld_val);
	else
	  $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
		   v__h35804,
		   "I_MMU_Cache",
		   rg_addr,
		   rg_ld_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__2_ULE_1___d43)
	begin
	  v__h35890 = $stime;
	  #0;
	end
    v__h35884 = v__h35890 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__2_ULE_1___d43)
	if (dmem_not_imem)
	  $display("%0d: %s: rl_io_write_req; f3 0x%0h  vaddr %0h  paddr %0h  word64 0x%0h",
		   v__h35884,
		   "D_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa,
		   rg_st_amo_val);
	else
	  $display("%0d: %s: rl_io_write_req; f3 0x%0h  vaddr %0h  paddr %0h  word64 0x%0h",
		   v__h35884,
		   "I_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa,
		   rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_write_req && !cfg_verbosity_read__2_ULE_1___d43)
	$display("    => rl_ST_AMO_response");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__2_ULE_1___d43)
	begin
	  v__h36100 = $stime;
	  #0;
	end
    v__h36094 = v__h36100 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__2_ULE_1___d43)
	if (dmem_not_imem)
	  $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h  vaddr %0h  paddr %0h  word64 0x%0h",
		   v__h36094,
		   "D_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa,
		   rg_st_amo_val);
	else
	  $display("%0d: %s: rl_io_AMO_SC_req; f3 0x%0h  vaddr %0h  paddr %0h  word64 0x%0h",
		   v__h36094,
		   "I_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa,
		   rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__2_ULE_1___d43)
	$display("    FAIL due to I/O address.");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_SC_req && !cfg_verbosity_read__2_ULE_1___d43)
	$display("    => rl_ST_AMO_response");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__2_ULE_1___d43)
	begin
	  v__h36218 = $stime;
	  #0;
	end
    v__h36212 = v__h36218 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__2_ULE_1___d43)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h  paddr %0h",
		   v__h36212,
		   "D_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa);
	else
	  $display("%0d: %s.rl_io_AMO_op_req; f3 0x%0h vaddr %0h  paddr %0h",
		   v__h36212,
		   "I_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("            To fabric: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("AXI4_Rd_Addr { ", "arid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "araddr: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", fabric_addr__h36270);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arlen: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 8'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arsize: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", value__h36399);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arburst: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 2'b01);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arlock: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 1'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arcache: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 4'b0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arprot: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 3'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arqos: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "arregion: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 4'd0);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "aruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 1'h0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_op_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	begin
	  v__h36512 = $stime;
	  #0;
	end
    v__h36506 = v__h36512 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h  paddr 0x%0h",
		   v__h36506,
		   "D_MMU_Cache",
		   rg_addr,
		   rg_pa);
	else
	  $display("%0d: %s.rl_io_AMO_read_rsp: vaddr 0x%0h  paddr 0x%0h",
		   v__h36506,
		   "I_MMU_Cache",
		   rg_addr,
		   rg_pa);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("AXI4_Rd_Data { ", "rid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", master_xactor_f_rd_data$D_OUT[70:67]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "rdata: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", master_xactor_f_rd_data$D_OUT[66:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "rresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", master_xactor_f_rd_data$D_OUT[2:1]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "rlast: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43 &&
	  master_xactor_f_rd_data$D_OUT[0])
	$write("True");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43 &&
	  !master_xactor_f_rd_data$D_OUT[0])
	$write("False");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "ruser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	begin
	  v__h36687 = $stime;
	  #0;
	end
    v__h36681 = v__h36687 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	if (dmem_not_imem)
	  $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h  vaddr %0h  paddr %0h  word64 0x%0h",
		   v__h36681,
		   "D_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa,
		   rg_st_amo_val);
	else
	  $display("%0d: %s: rl_io_AMO_read_rsp; f3 0x%0h  vaddr %0h  paddr %0h  word64 0x%0h",
		   v__h36681,
		   "I_MMU_Cache",
		   rg_f3,
		   rg_addr,
		   rg_pa,
		   rg_st_amo_val);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	begin
	  v__h38946 = $stime;
	  #0;
	end
    v__h38940 = v__h38946 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	if (dmem_not_imem)
	  $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
		   v__h38940,
		   "D_MMU_Cache",
		   rg_addr,
		   new_ld_val__h36813);
	else
	  $display("%0d: %s.drive_IO_read_rsp: addr 0x%0h ld_val 0x%0h",
		   v__h38940,
		   "I_MMU_Cache",
		   rg_addr,
		   new_ld_val__h36813);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] == 2'b0 &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$display("    => rl_ST_AMO_response");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	begin
	  v__h36783 = $stime;
	  #0;
	end
    v__h36777 = v__h36783 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_io_AMO_read_rsp &&
	  master_xactor_f_rd_data$D_OUT[2:1] != 2'b0 &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT",
		   v__h36777,
		   "D_MMU_Cache");
	else
	  $display("%0d: %s.rl_io_AMO_read_rsp: FABRIC_RSP_ERR: raising trap STORE_AMO_ACCESS_FAULT",
		   v__h36777,
		   "I_MMU_Cache");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	begin
	  v__h39524 = $stime;
	  #0;
	end
    v__h39518 = v__h39524 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	if (dmem_not_imem)
	  $write("%0d: %s.rl_discard_write_rsp: pending %0d ",
		 v__h39518,
		 "D_MMU_Cache",
		 $unsigned(b__h28572));
	else
	  $write("%0d: %s.rl_discard_write_rsp: pending %0d ",
		 v__h39518,
		 "I_MMU_Cache",
		 $unsigned(b__h28572));
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("AXI4_Wr_Resp { ", "bid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", master_xactor_f_wr_resp$D_OUT[5:2]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "bresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", master_xactor_f_wr_resp$D_OUT[1:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write(", ", "buser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] == 2'b0 &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	begin
	  v__h39566 = $stime;
	  #0;
	end
    v__h39560 = v__h39566 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	if (dmem_not_imem)
	  $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit",
		   v__h39560,
		   "D_MMU_Cache");
	else
	  $display("%0d: %s.rl_discard_write_rsp: fabric response error: exit",
		   v__h39560,
		   "I_MMU_Cache");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	$write("    ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	$write("AXI4_Wr_Resp { ", "bid: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	$write("'h%h", master_xactor_f_wr_resp$D_OUT[5:2]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	$write(", ", "bresp: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	$write("'h%h", master_xactor_f_wr_resp$D_OUT[1:0]);
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	$write(", ", "buser: ");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	$write("'h%h", 1'd0, " }");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_discard_write_rsp &&
	  master_xactor_f_wr_resp$D_OUT[1:0] != 2'b0)
	$write("\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_reset)
	begin
	  v__h4238 = $stime;
	  #0;
	end
    v__h4232 = v__h4238 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (WILL_FIRE_RL_rl_start_reset)
	if (dmem_not_imem)
	  $display("%0d: %s: cache size %0d KB, associativity %0d, line size %0d bytes (= %0d XLEN words)",
		   v__h4232,
		   "D_MMU_Cache",
		   $signed(32'd8),
		   $signed(32'd2),
		   $signed(32'd64),
		   $signed(32'd16));
	else
	  $display("%0d: %s: cache size %0d KB, associativity %0d, line size %0d bytes (= %0d XLEN words)",
		   v__h4232,
		   "I_MMU_Cache",
		   $signed(32'd8),
		   $signed(32'd2),
		   $signed(32'd64),
		   $signed(32'd16));
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__2_ULE_1___d43)
	begin
	  v__h39935 = $stime;
	  #0;
	end
    v__h39929 = v__h39935 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write("%0d: %m.req: op:", v__h39929);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__2_ULE_1___d43 && req_op == 2'd0)
	$write("CACHE_LD");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__2_ULE_1___d43 && req_op == 2'd1)
	$write("CACHE_ST");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__2_ULE_1___d43 && req_op != 2'd0 &&
	  req_op != 2'd1)
	$write("CACHE_AMO");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write(" f3:%0d addr:0x%0h st_value:0x%0h",
	       req_f3,
	       req_addr,
	       req_st_value,
	       "\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__2_ULE_1___d43) $write("    priv:");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__2_ULE_1___d43 && req_priv == 2'b0)
	$write("U");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__2_ULE_1___d43 && req_priv == 2'b01)
	$write("S");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__2_ULE_1___d43 && req_priv == 2'b11)
	$write("M");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__2_ULE_1___d43 && req_priv != 2'b0 &&
	  req_priv != 2'b01 &&
	  req_priv != 2'b11)
	$write("RESERVED");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__2_ULE_1___d43)
	$write(" sstatus_SUM:%0d mstatus_MXR:%0d satp:0x%0h",
	       req_sstatus_SUM,
	       req_mstatus_MXR,
	       req_satp,
	       "\n");
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req && !cfg_verbosity_read__2_ULE_1___d43)
	$display("    amo_funct7 = 0x%0h", req_amo_funct7);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_req &&
	  req_f3_BITS_1_TO_0_393_EQ_0b0_394_OR_req_f3_BI_ETC___d1423 &&
	  !cfg_verbosity_read__2_ULE_1___d43)
	$display("    fa_req_ram_B tagCSet [0x%0x] cword_set [0x%0d]",
		 req_addr[11:6],
		 req_addr[11:3]);
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_tlb_flush && !cfg_verbosity_read__2_ULE_1___d43)
	begin
	  v__h41310 = $stime;
	  #0;
	end
    v__h41304 = v__h41310 / 32'd10;
    if (RST_N != `BSV_RESET_VALUE)
      if (EN_tlb_flush && !cfg_verbosity_read__2_ULE_1___d43)
	if (dmem_not_imem)
	  $display("%0d: %s.tlb_flush", v__h41304, "D_MMU_Cache");
	else
	  $display("%0d: %s.tlb_flush", v__h41304, "I_MMU_Cache");
  end
  // synopsys translate_on
endmodule  // mkMMU_Cache

